2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req *our_req(struct usb_request *req)
40 return container_of(req, struct dwc2_hsotg_req, req);
43 static inline struct dwc2_hsotg_ep *our_ep(struct usb_ep *ep)
45 return container_of(ep, struct dwc2_hsotg_ep, ep);
48 static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget)
50 return container_of(gadget, struct dwc2_hsotg, gadget);
53 static inline void __orr32(void __iomem *ptr, u32 val)
55 dwc2_writel(dwc2_readl(ptr) | val, ptr);
58 static inline void __bic32(void __iomem *ptr, u32 val)
60 dwc2_writel(dwc2_readl(ptr) & ~val, ptr);
63 static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg,
64 u32 ep_index, u32 dir_in)
67 return hsotg->eps_in[ep_index];
69 return hsotg->eps_out[ep_index];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg *hsotg)
96 return hsotg->g_using_dma;
100 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
101 * @hs_ep: The endpoint
102 * @increment: The value to increment by
104 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
105 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
107 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep)
109 hs_ep->target_frame += hs_ep->interval;
110 if (hs_ep->target_frame > DSTS_SOFFN_LIMIT) {
111 hs_ep->frame_overrun = 1;
112 hs_ep->target_frame &= DSTS_SOFFN_LIMIT;
114 hs_ep->frame_overrun = 0;
119 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
120 * @hsotg: The device state
121 * @ints: A bitmask of the interrupts to enable
123 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints)
125 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
128 new_gsintmsk = gsintmsk | ints;
130 if (new_gsintmsk != gsintmsk) {
131 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
132 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
137 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
138 * @hsotg: The device state
139 * @ints: A bitmask of the interrupts to enable
141 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints)
143 u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
146 new_gsintmsk = gsintmsk & ~ints;
148 if (new_gsintmsk != gsintmsk)
149 dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
153 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
154 * @hsotg: The device state
155 * @ep: The endpoint index
156 * @dir_in: True if direction is in.
157 * @en: The enable value, true to enable
159 * Set or clear the mask for an individual endpoint's interrupt
162 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg,
163 unsigned int ep, unsigned int dir_in,
173 local_irq_save(flags);
174 daint = dwc2_readl(hsotg->regs + DAINTMSK);
179 dwc2_writel(daint, hsotg->regs + DAINTMSK);
180 local_irq_restore(flags);
184 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
185 * @hsotg: The device instance.
187 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg)
194 /* Reset fifo map if not correctly cleared during previous session */
195 WARN_ON(hsotg->fifo_map);
198 /* set RX/NPTX FIFO sizes */
199 dwc2_writel(hsotg->g_rx_fifo_sz, hsotg->regs + GRXFSIZ);
200 dwc2_writel((hsotg->g_rx_fifo_sz << FIFOSIZE_STARTADDR_SHIFT) |
201 (hsotg->g_np_g_tx_fifo_sz << FIFOSIZE_DEPTH_SHIFT),
202 hsotg->regs + GNPTXFSIZ);
205 * arange all the rest of the TX FIFOs, as some versions of this
206 * block have overlapping default addresses. This also ensures
207 * that if the settings have been changed, then they are set to
211 /* start at the end of the GNPTXFSIZ, rounded up */
212 addr = hsotg->g_rx_fifo_sz + hsotg->g_np_g_tx_fifo_sz;
215 * Configure fifos sizes from provided configuration and assign
216 * them to endpoints dynamically according to maxpacket size value of
219 for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
220 if (!hsotg->g_tx_fifo_sz[ep])
223 val |= hsotg->g_tx_fifo_sz[ep] << FIFOSIZE_DEPTH_SHIFT;
224 WARN_ONCE(addr + hsotg->g_tx_fifo_sz[ep] > hsotg->fifo_mem,
225 "insufficient fifo memory");
226 addr += hsotg->g_tx_fifo_sz[ep];
228 dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
232 * according to p428 of the design guide, we need to ensure that
233 * all fifos are flushed before continuing
236 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH |
237 GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
239 /* wait until the fifos are both flushed */
242 val = dwc2_readl(hsotg->regs + GRSTCTL);
244 if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0)
247 if (--timeout == 0) {
249 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
257 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
261 * @ep: USB endpoint to allocate request for.
262 * @flags: Allocation flags
264 * Allocate a new USB request structure appropriate for the specified endpoint
266 static struct usb_request *dwc2_hsotg_ep_alloc_request(struct usb_ep *ep,
269 struct dwc2_hsotg_req *req;
271 req = kzalloc(sizeof(struct dwc2_hsotg_req), flags);
275 INIT_LIST_HEAD(&req->queue);
281 * is_ep_periodic - return true if the endpoint is in periodic mode.
282 * @hs_ep: The endpoint to query.
284 * Returns true if the endpoint is in periodic mode, meaning it is being
285 * used for an Interrupt or ISO transfer.
287 static inline int is_ep_periodic(struct dwc2_hsotg_ep *hs_ep)
289 return hs_ep->periodic;
293 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
294 * @hsotg: The device state.
295 * @hs_ep: The endpoint for the request
296 * @hs_req: The request being processed.
298 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
299 * of a request to ensure the buffer is ready for access by the caller.
301 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg *hsotg,
302 struct dwc2_hsotg_ep *hs_ep,
303 struct dwc2_hsotg_req *hs_req)
305 struct usb_request *req = &hs_req->req;
307 /* ignore this if we're not moving any data */
308 if (hs_req->req.length == 0)
311 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
315 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
316 * @hsotg: The controller state.
317 * @hs_ep: The endpoint we're going to write for.
318 * @hs_req: The request to write data for.
320 * This is called when the TxFIFO has some space in it to hold a new
321 * transmission and we have something to give it. The actual setup of
322 * the data size is done elsewhere, so all we have to do is to actually
325 * The return value is zero if there is more space (or nothing was done)
326 * otherwise -ENOSPC is returned if the FIFO space was used up.
328 * This routine is only needed for PIO
330 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg,
331 struct dwc2_hsotg_ep *hs_ep,
332 struct dwc2_hsotg_req *hs_req)
334 bool periodic = is_ep_periodic(hs_ep);
335 u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
336 int buf_pos = hs_req->req.actual;
337 int to_write = hs_ep->size_loaded;
343 to_write -= (buf_pos - hs_ep->last_load);
345 /* if there's nothing to write, get out early */
349 if (periodic && !hsotg->dedicated_fifos) {
350 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
355 * work out how much data was loaded so we can calculate
356 * how much data is left in the fifo.
359 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
362 * if shared fifo, we cannot write anything until the
363 * previous data has been completely sent.
365 if (hs_ep->fifo_load != 0) {
366 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
370 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
372 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
374 /* how much of the data has moved */
375 size_done = hs_ep->size_loaded - size_left;
377 /* how much data is left in the fifo */
378 can_write = hs_ep->fifo_load - size_done;
379 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
380 __func__, can_write);
382 can_write = hs_ep->fifo_size - can_write;
383 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
384 __func__, can_write);
386 if (can_write <= 0) {
387 dwc2_hsotg_en_gsint(hsotg, GINTSTS_PTXFEMP);
390 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
391 can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index));
396 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts) == 0) {
398 "%s: no queue slots available (0x%08x)\n",
401 dwc2_hsotg_en_gsint(hsotg, GINTSTS_NPTXFEMP);
405 can_write = GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts);
406 can_write *= 4; /* fifo size is in 32bit quantities. */
409 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
411 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
412 __func__, gnptxsts, can_write, to_write, max_transfer);
415 * limit to 512 bytes of data, it seems at least on the non-periodic
416 * FIFO, requests of >512 cause the endpoint to get stuck with a
417 * fragment of the end of the transfer in it.
419 if (can_write > 512 && !periodic)
423 * limit the write to one max-packet size worth of data, but allow
424 * the transfer to return that it did not run out of fifo space
427 if (to_write > max_transfer) {
428 to_write = max_transfer;
430 /* it's needed only when we do not use dedicated fifos */
431 if (!hsotg->dedicated_fifos)
432 dwc2_hsotg_en_gsint(hsotg,
433 periodic ? GINTSTS_PTXFEMP :
437 /* see if we can write data */
439 if (to_write > can_write) {
440 to_write = can_write;
441 pkt_round = to_write % max_transfer;
444 * Round the write down to an
445 * exact number of packets.
447 * Note, we do not currently check to see if we can ever
448 * write a full packet or not to the FIFO.
452 to_write -= pkt_round;
455 * enable correct FIFO interrupt to alert us when there
459 /* it's needed only when we do not use dedicated fifos */
460 if (!hsotg->dedicated_fifos)
461 dwc2_hsotg_en_gsint(hsotg,
462 periodic ? GINTSTS_PTXFEMP :
466 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
467 to_write, hs_req->req.length, can_write, buf_pos);
472 hs_req->req.actual = buf_pos + to_write;
473 hs_ep->total_data += to_write;
476 hs_ep->fifo_load += to_write;
478 to_write = DIV_ROUND_UP(to_write, 4);
479 data = hs_req->req.buf + buf_pos;
481 iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
483 return (to_write >= can_write) ? -ENOSPC : 0;
487 * get_ep_limit - get the maximum data legnth for this endpoint
488 * @hs_ep: The endpoint
490 * Return the maximum data that can be queued in one go on a given endpoint
491 * so that transfers that are too long can be split.
493 static unsigned get_ep_limit(struct dwc2_hsotg_ep *hs_ep)
495 int index = hs_ep->index;
500 maxsize = DXEPTSIZ_XFERSIZE_LIMIT + 1;
501 maxpkt = DXEPTSIZ_PKTCNT_LIMIT + 1;
505 maxpkt = DIEPTSIZ0_PKTCNT_LIMIT + 1;
510 /* we made the constant loading easier above by using +1 */
515 * constrain by packet count if maxpkts*pktsize is greater
516 * than the length register size.
519 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
520 maxsize = maxpkt * hs_ep->ep.maxpacket;
526 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
527 * @hsotg: The controller state.
528 * @hs_ep: The endpoint to process a request for
529 * @hs_req: The request to start.
530 * @continuing: True if we are doing more for the current request.
532 * Start the given request running by setting the endpoint registers
533 * appropriately, and writing any data to the FIFOs.
535 static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg,
536 struct dwc2_hsotg_ep *hs_ep,
537 struct dwc2_hsotg_req *hs_req,
540 struct usb_request *ureq = &hs_req->req;
541 int index = hs_ep->index;
542 int dir_in = hs_ep->dir_in;
552 if (hs_ep->req && !continuing) {
553 dev_err(hsotg->dev, "%s: active request\n", __func__);
556 } else if (hs_ep->req != hs_req && continuing) {
558 "%s: continue different req\n", __func__);
564 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
565 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
567 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
568 __func__, dwc2_readl(hsotg->regs + epctrl_reg), index,
569 hs_ep->dir_in ? "in" : "out");
571 /* If endpoint is stalled, we will restart request later */
572 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
574 if (index && ctrl & DXEPCTL_STALL) {
575 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
579 length = ureq->length - ureq->actual;
580 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
581 ureq->length, ureq->actual);
583 maxreq = get_ep_limit(hs_ep);
584 if (length > maxreq) {
585 int round = maxreq % hs_ep->ep.maxpacket;
587 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
588 __func__, length, maxreq, round);
590 /* round down to multiple of packets */
598 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
600 packets = 1; /* send one packet if length is zero. */
602 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
603 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
607 if (dir_in && index != 0)
608 if (hs_ep->isochronous)
609 epsize = DXEPTSIZ_MC(packets);
611 epsize = DXEPTSIZ_MC(1);
616 * zero length packet should be programmed on its own and should not
617 * be counted in DIEPTSIZ.PktCnt with other packets.
619 if (dir_in && ureq->zero && !continuing) {
620 /* Test if zlp is actually required. */
621 if ((ureq->length >= hs_ep->ep.maxpacket) &&
622 !(ureq->length % hs_ep->ep.maxpacket))
626 epsize |= DXEPTSIZ_PKTCNT(packets);
627 epsize |= DXEPTSIZ_XFERSIZE(length);
629 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
630 __func__, packets, length, ureq->length, epsize, epsize_reg);
632 /* store the request as the current one we're doing */
635 /* write size / packets */
636 dwc2_writel(epsize, hsotg->regs + epsize_reg);
638 if (using_dma(hsotg) && !continuing) {
639 unsigned int dma_reg;
642 * write DMA address to control register, buffer already
643 * synced by dwc2_hsotg_ep_queue().
646 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
647 dwc2_writel(ureq->dma, hsotg->regs + dma_reg);
649 dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n",
650 __func__, &ureq->dma, dma_reg);
653 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
655 dev_dbg(hsotg->dev, "ep0 state:%d\n", hsotg->ep0_state);
657 /* For Setup request do not clear NAK */
658 if (!(index == 0 && hsotg->ep0_state == DWC2_EP0_SETUP))
659 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
661 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
662 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
665 * set these, it seems that DMA support increments past the end
666 * of the packet buffer so we need to calculate the length from
669 hs_ep->size_loaded = length;
670 hs_ep->last_load = ureq->actual;
672 if (dir_in && !using_dma(hsotg)) {
673 /* set these anyway, we may need them for non-periodic in */
674 hs_ep->fifo_load = 0;
676 dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
680 * Note, trying to clear the NAK here causes problems with transmit
681 * on the S3C6400 ending up with the TXFIFO becoming full.
684 /* check ep is enabled */
685 if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA))
687 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
688 index, dwc2_readl(hsotg->regs + epctrl_reg));
690 dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n",
691 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
693 /* enable ep interrupts */
694 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
698 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
699 * @hsotg: The device state.
700 * @hs_ep: The endpoint the request is on.
701 * @req: The request being processed.
703 * We've been asked to queue a request, so ensure that the memory buffer
704 * is correctly setup for DMA. If we've been passed an extant DMA address
705 * then ensure the buffer has been synced to memory. If our buffer has no
706 * DMA memory, then we map the memory and mark our request to allow us to
707 * cleanup on completion.
709 static int dwc2_hsotg_map_dma(struct dwc2_hsotg *hsotg,
710 struct dwc2_hsotg_ep *hs_ep,
711 struct usb_request *req)
713 struct dwc2_hsotg_req *hs_req = our_req(req);
716 /* if the length is zero, ignore the DMA data */
717 if (hs_req->req.length == 0)
720 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
727 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
728 __func__, req->buf, req->length);
733 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg *hsotg,
734 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
736 void *req_buf = hs_req->req.buf;
738 /* If dma is not being used or buffer is aligned */
739 if (!using_dma(hsotg) || !((long)req_buf & 3))
742 WARN_ON(hs_req->saved_req_buf);
744 dev_dbg(hsotg->dev, "%s: %s: buf=%p length=%d\n", __func__,
745 hs_ep->ep.name, req_buf, hs_req->req.length);
747 hs_req->req.buf = kmalloc(hs_req->req.length, GFP_ATOMIC);
748 if (!hs_req->req.buf) {
749 hs_req->req.buf = req_buf;
751 "%s: unable to allocate memory for bounce buffer\n",
756 /* Save actual buffer */
757 hs_req->saved_req_buf = req_buf;
760 memcpy(hs_req->req.buf, req_buf, hs_req->req.length);
764 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg *hsotg,
765 struct dwc2_hsotg_ep *hs_ep, struct dwc2_hsotg_req *hs_req)
767 /* If dma is not being used or buffer was aligned */
768 if (!using_dma(hsotg) || !hs_req->saved_req_buf)
771 dev_dbg(hsotg->dev, "%s: %s: status=%d actual-length=%d\n", __func__,
772 hs_ep->ep.name, hs_req->req.status, hs_req->req.actual);
774 /* Copy data from bounce buffer on successful out transfer */
775 if (!hs_ep->dir_in && !hs_req->req.status)
776 memcpy(hs_req->saved_req_buf, hs_req->req.buf,
779 /* Free bounce buffer */
780 kfree(hs_req->req.buf);
782 hs_req->req.buf = hs_req->saved_req_buf;
783 hs_req->saved_req_buf = NULL;
786 static int dwc2_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
789 struct dwc2_hsotg_req *hs_req = our_req(req);
790 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
791 struct dwc2_hsotg *hs = hs_ep->parent;
795 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
796 ep->name, req, req->length, req->buf, req->no_interrupt,
797 req->zero, req->short_not_ok);
799 /* Prevent new request submission when controller is suspended */
800 if (hs->lx_state == DWC2_L2) {
801 dev_dbg(hs->dev, "%s: don't submit request while suspended\n",
806 /* initialise status of the request */
807 INIT_LIST_HEAD(&hs_req->queue);
809 req->status = -EINPROGRESS;
811 ret = dwc2_hsotg_handle_unaligned_buf_start(hs, hs_ep, hs_req);
815 /* if we're using DMA, sync the buffers as necessary */
817 ret = dwc2_hsotg_map_dma(hs, hs_ep, req);
822 first = list_empty(&hs_ep->queue);
823 list_add_tail(&hs_req->queue, &hs_ep->queue);
826 dwc2_hsotg_start_req(hs, hs_ep, hs_req, false);
831 static int dwc2_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
834 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
835 struct dwc2_hsotg *hs = hs_ep->parent;
836 unsigned long flags = 0;
839 spin_lock_irqsave(&hs->lock, flags);
840 ret = dwc2_hsotg_ep_queue(ep, req, gfp_flags);
841 spin_unlock_irqrestore(&hs->lock, flags);
846 static void dwc2_hsotg_ep_free_request(struct usb_ep *ep,
847 struct usb_request *req)
849 struct dwc2_hsotg_req *hs_req = our_req(req);
855 * dwc2_hsotg_complete_oursetup - setup completion callback
856 * @ep: The endpoint the request was on.
857 * @req: The request completed.
859 * Called on completion of any requests the driver itself
860 * submitted that need cleaning up.
862 static void dwc2_hsotg_complete_oursetup(struct usb_ep *ep,
863 struct usb_request *req)
865 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
866 struct dwc2_hsotg *hsotg = hs_ep->parent;
868 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
870 dwc2_hsotg_ep_free_request(ep, req);
874 * ep_from_windex - convert control wIndex value to endpoint
875 * @hsotg: The driver state.
876 * @windex: The control request wIndex field (in host order).
878 * Convert the given wIndex into a pointer to an driver endpoint
879 * structure, or return NULL if it is not a valid endpoint.
881 static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg,
884 struct dwc2_hsotg_ep *ep;
885 int dir = (windex & USB_DIR_IN) ? 1 : 0;
886 int idx = windex & 0x7F;
891 if (idx > hsotg->num_of_eps)
894 ep = index_to_ep(hsotg, idx, dir);
896 if (idx && ep->dir_in != dir)
903 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
904 * @hsotg: The driver state.
905 * @testmode: requested usb test mode
906 * Enable usb Test Mode requested by the Host.
908 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode)
910 int dctl = dwc2_readl(hsotg->regs + DCTL);
912 dctl &= ~DCTL_TSTCTL_MASK;
919 dctl |= testmode << DCTL_TSTCTL_SHIFT;
924 dwc2_writel(dctl, hsotg->regs + DCTL);
929 * dwc2_hsotg_send_reply - send reply to control request
930 * @hsotg: The device state
932 * @buff: Buffer for request
933 * @length: Length of reply.
935 * Create a request and queue it on the given endpoint. This is useful as
936 * an internal method of sending replies to certain control requests, etc.
938 static int dwc2_hsotg_send_reply(struct dwc2_hsotg *hsotg,
939 struct dwc2_hsotg_ep *ep,
943 struct usb_request *req;
946 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
948 req = dwc2_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
949 hsotg->ep0_reply = req;
951 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
955 req->buf = hsotg->ep0_buff;
956 req->length = length;
958 * zero flag is for sending zlp in DATA IN stage. It has no impact on
962 req->complete = dwc2_hsotg_complete_oursetup;
965 memcpy(req->buf, buff, length);
967 ret = dwc2_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
969 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
977 * dwc2_hsotg_process_req_status - process request GET_STATUS
978 * @hsotg: The device state
979 * @ctrl: USB control request
981 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg *hsotg,
982 struct usb_ctrlrequest *ctrl)
984 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
985 struct dwc2_hsotg_ep *ep;
989 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
992 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
996 switch (ctrl->bRequestType & USB_RECIP_MASK) {
997 case USB_RECIP_DEVICE:
998 reply = cpu_to_le16(0); /* bit 0 => self powered,
999 * bit 1 => remote wakeup */
1002 case USB_RECIP_INTERFACE:
1003 /* currently, the data result should be zero */
1004 reply = cpu_to_le16(0);
1007 case USB_RECIP_ENDPOINT:
1008 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1012 reply = cpu_to_le16(ep->halted ? 1 : 0);
1019 if (le16_to_cpu(ctrl->wLength) != 2)
1022 ret = dwc2_hsotg_send_reply(hsotg, ep0, &reply, 2);
1024 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1031 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now);
1034 * get_ep_head - return the first request on the endpoint
1035 * @hs_ep: The controller endpoint to get
1037 * Get the first request on the endpoint.
1039 static struct dwc2_hsotg_req *get_ep_head(struct dwc2_hsotg_ep *hs_ep)
1041 if (list_empty(&hs_ep->queue))
1044 return list_first_entry(&hs_ep->queue, struct dwc2_hsotg_req, queue);
1048 * dwc2_gadget_start_next_request - Starts next request from ep queue
1049 * @hs_ep: Endpoint structure
1051 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1052 * in its handler. Hence we need to unmask it here to be able to do
1053 * resynchronization.
1055 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep)
1058 struct dwc2_hsotg *hsotg = hs_ep->parent;
1059 int dir_in = hs_ep->dir_in;
1060 struct dwc2_hsotg_req *hs_req;
1061 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1063 if (!list_empty(&hs_ep->queue)) {
1064 hs_req = get_ep_head(hs_ep);
1065 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1068 if (!hs_ep->isochronous)
1072 dev_dbg(hsotg->dev, "%s: No more ISOC-IN requests\n",
1075 dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n",
1077 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1078 mask |= DOEPMSK_OUTTKNEPDISMSK;
1079 dwc2_writel(mask, hsotg->regs + epmsk_reg);
1084 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1085 * @hsotg: The device state
1086 * @ctrl: USB control request
1088 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg *hsotg,
1089 struct usb_ctrlrequest *ctrl)
1091 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1092 struct dwc2_hsotg_req *hs_req;
1093 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1094 struct dwc2_hsotg_ep *ep;
1101 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1102 __func__, set ? "SET" : "CLEAR");
1104 wValue = le16_to_cpu(ctrl->wValue);
1105 wIndex = le16_to_cpu(ctrl->wIndex);
1106 recip = ctrl->bRequestType & USB_RECIP_MASK;
1109 case USB_RECIP_DEVICE:
1111 case USB_DEVICE_TEST_MODE:
1112 if ((wIndex & 0xff) != 0)
1117 hsotg->test_mode = wIndex >> 8;
1118 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1121 "%s: failed to send reply\n", __func__);
1130 case USB_RECIP_ENDPOINT:
1131 ep = ep_from_windex(hsotg, wIndex);
1133 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1139 case USB_ENDPOINT_HALT:
1140 halted = ep->halted;
1142 dwc2_hsotg_ep_sethalt(&ep->ep, set, true);
1144 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1147 "%s: failed to send reply\n", __func__);
1152 * we have to complete all requests for ep if it was
1153 * halted, and the halt was cleared by CLEAR_FEATURE
1156 if (!set && halted) {
1158 * If we have request in progress,
1164 list_del_init(&hs_req->queue);
1165 if (hs_req->req.complete) {
1166 spin_unlock(&hsotg->lock);
1167 usb_gadget_giveback_request(
1168 &ep->ep, &hs_req->req);
1169 spin_lock(&hsotg->lock);
1173 /* If we have pending request, then start it */
1175 dwc2_gadget_start_next_request(ep);
1191 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg);
1194 * dwc2_hsotg_stall_ep0 - stall ep0
1195 * @hsotg: The device state
1197 * Set stall for ep0 as response for setup request.
1199 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg)
1201 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1205 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1206 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1209 * DxEPCTL_Stall will be cleared by EP once it has
1210 * taken effect, so no need to clear later.
1213 ctrl = dwc2_readl(hsotg->regs + reg);
1214 ctrl |= DXEPCTL_STALL;
1215 ctrl |= DXEPCTL_CNAK;
1216 dwc2_writel(ctrl, hsotg->regs + reg);
1219 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1220 ctrl, reg, dwc2_readl(hsotg->regs + reg));
1223 * complete won't be called, so we enqueue
1224 * setup request here
1226 dwc2_hsotg_enqueue_setup(hsotg);
1230 * dwc2_hsotg_process_control - process a control request
1231 * @hsotg: The device state
1232 * @ctrl: The control request received
1234 * The controller has received the SETUP phase of a control request, and
1235 * needs to work out what to do next (and whether to pass it on to the
1238 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg,
1239 struct usb_ctrlrequest *ctrl)
1241 struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
1246 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1247 ctrl->bRequestType, ctrl->bRequest, ctrl->wValue,
1248 ctrl->wIndex, ctrl->wLength);
1250 if (ctrl->wLength == 0) {
1252 hsotg->ep0_state = DWC2_EP0_STATUS_IN;
1253 } else if (ctrl->bRequestType & USB_DIR_IN) {
1255 hsotg->ep0_state = DWC2_EP0_DATA_IN;
1258 hsotg->ep0_state = DWC2_EP0_DATA_OUT;
1261 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1262 switch (ctrl->bRequest) {
1263 case USB_REQ_SET_ADDRESS:
1264 hsotg->connected = 1;
1265 dcfg = dwc2_readl(hsotg->regs + DCFG);
1266 dcfg &= ~DCFG_DEVADDR_MASK;
1267 dcfg |= (le16_to_cpu(ctrl->wValue) <<
1268 DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
1269 dwc2_writel(dcfg, hsotg->regs + DCFG);
1271 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1273 ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
1276 case USB_REQ_GET_STATUS:
1277 ret = dwc2_hsotg_process_req_status(hsotg, ctrl);
1280 case USB_REQ_CLEAR_FEATURE:
1281 case USB_REQ_SET_FEATURE:
1282 ret = dwc2_hsotg_process_req_feature(hsotg, ctrl);
1287 /* as a fallback, try delivering it to the driver to deal with */
1289 if (ret == 0 && hsotg->driver) {
1290 spin_unlock(&hsotg->lock);
1291 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1292 spin_lock(&hsotg->lock);
1294 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1298 * the request is either unhandlable, or is not formatted correctly
1299 * so respond with a STALL for the status stage to indicate failure.
1303 dwc2_hsotg_stall_ep0(hsotg);
1307 * dwc2_hsotg_complete_setup - completion of a setup transfer
1308 * @ep: The endpoint the request was on.
1309 * @req: The request completed.
1311 * Called on completion of any requests the driver itself submitted for
1314 static void dwc2_hsotg_complete_setup(struct usb_ep *ep,
1315 struct usb_request *req)
1317 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
1318 struct dwc2_hsotg *hsotg = hs_ep->parent;
1320 if (req->status < 0) {
1321 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1325 spin_lock(&hsotg->lock);
1326 if (req->actual == 0)
1327 dwc2_hsotg_enqueue_setup(hsotg);
1329 dwc2_hsotg_process_control(hsotg, req->buf);
1330 spin_unlock(&hsotg->lock);
1334 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1335 * @hsotg: The device state.
1337 * Enqueue a request on EP0 if necessary to received any SETUP packets
1338 * received from the host.
1340 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg *hsotg)
1342 struct usb_request *req = hsotg->ctrl_req;
1343 struct dwc2_hsotg_req *hs_req = our_req(req);
1346 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1350 req->buf = hsotg->ctrl_buff;
1351 req->complete = dwc2_hsotg_complete_setup;
1353 if (!list_empty(&hs_req->queue)) {
1354 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1358 hsotg->eps_out[0]->dir_in = 0;
1359 hsotg->eps_out[0]->send_zlp = 0;
1360 hsotg->ep0_state = DWC2_EP0_SETUP;
1362 ret = dwc2_hsotg_ep_queue(&hsotg->eps_out[0]->ep, req, GFP_ATOMIC);
1364 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1366 * Don't think there's much we can do other than watch the
1372 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg,
1373 struct dwc2_hsotg_ep *hs_ep)
1376 u8 index = hs_ep->index;
1377 u32 epctl_reg = hs_ep->dir_in ? DIEPCTL(index) : DOEPCTL(index);
1378 u32 epsiz_reg = hs_ep->dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
1381 dev_dbg(hsotg->dev, "Sending zero-length packet on ep%d\n",
1384 dev_dbg(hsotg->dev, "Receiving zero-length packet on ep%d\n",
1387 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1388 DXEPTSIZ_XFERSIZE(0), hsotg->regs +
1391 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1392 ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */
1393 ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */
1394 ctrl |= DXEPCTL_USBACTEP;
1395 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1399 * dwc2_hsotg_complete_request - complete a request given to us
1400 * @hsotg: The device state.
1401 * @hs_ep: The endpoint the request was on.
1402 * @hs_req: The request to complete.
1403 * @result: The result code (0 => Ok, otherwise errno)
1405 * The given request has finished, so call the necessary completion
1406 * if it has one and then look to see if we can start a new request
1409 * Note, expects the ep to already be locked as appropriate.
1411 static void dwc2_hsotg_complete_request(struct dwc2_hsotg *hsotg,
1412 struct dwc2_hsotg_ep *hs_ep,
1413 struct dwc2_hsotg_req *hs_req,
1418 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1422 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1423 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1426 * only replace the status if we've not already set an error
1427 * from a previous transaction
1430 if (hs_req->req.status == -EINPROGRESS)
1431 hs_req->req.status = result;
1433 if (using_dma(hsotg))
1434 dwc2_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1436 dwc2_hsotg_handle_unaligned_buf_complete(hsotg, hs_ep, hs_req);
1439 list_del_init(&hs_req->queue);
1442 * call the complete request with the locks off, just in case the
1443 * request tries to queue more work for this endpoint.
1446 if (hs_req->req.complete) {
1447 spin_unlock(&hsotg->lock);
1448 usb_gadget_giveback_request(&hs_ep->ep, &hs_req->req);
1449 spin_lock(&hsotg->lock);
1453 * Look to see if there is anything else to do. Note, the completion
1454 * of the previous request may have caused a new request to be started
1455 * so be careful when doing this.
1458 if (!hs_ep->req && result >= 0) {
1459 dwc2_gadget_start_next_request(hs_ep);
1464 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1465 * @hsotg: The device state.
1466 * @ep_idx: The endpoint index for the data
1467 * @size: The size of data in the fifo, in bytes
1469 * The FIFO status shows there is data to read from the FIFO for a given
1470 * endpoint, so sort out whether we need to read the data into a request
1471 * that has been made for that endpoint.
1473 static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size)
1475 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx];
1476 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1477 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1484 u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx));
1488 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1489 __func__, size, ep_idx, epctl);
1491 /* dump the data from the FIFO, we've nothing we can do */
1492 for (ptr = 0; ptr < size; ptr += 4)
1493 (void)dwc2_readl(fifo);
1499 read_ptr = hs_req->req.actual;
1500 max_req = hs_req->req.length - read_ptr;
1502 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1503 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1505 if (to_read > max_req) {
1507 * more data appeared than we where willing
1508 * to deal with in this request.
1511 /* currently we don't deal this */
1515 hs_ep->total_data += to_read;
1516 hs_req->req.actual += to_read;
1517 to_read = DIV_ROUND_UP(to_read, 4);
1520 * note, we might over-write the buffer end by 3 bytes depending on
1521 * alignment of the data.
1523 ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read);
1527 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1528 * @hsotg: The device instance
1529 * @dir_in: If IN zlp
1531 * Generate a zero-length IN packet request for terminating a SETUP
1534 * Note, since we don't write any data to the TxFIFO, then it is
1535 * currently believed that we do not need to wait for any space in
1538 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg *hsotg, bool dir_in)
1540 /* eps_out[0] is used in both directions */
1541 hsotg->eps_out[0]->dir_in = dir_in;
1542 hsotg->ep0_state = dir_in ? DWC2_EP0_STATUS_IN : DWC2_EP0_STATUS_OUT;
1544 dwc2_hsotg_program_zlp(hsotg, hsotg->eps_out[0]);
1547 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg,
1552 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
1553 if (ctrl & DXEPCTL_EOFRNUM)
1554 ctrl |= DXEPCTL_SETEVENFR;
1556 ctrl |= DXEPCTL_SETODDFR;
1557 dwc2_writel(ctrl, hsotg->regs + epctl_reg);
1561 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1562 * @hsotg: The device instance
1563 * @epnum: The endpoint received from
1565 * The RXFIFO has delivered an OutDone event, which means that the data
1566 * transfer for an OUT endpoint has been completed, either by a short
1567 * packet or by the finish of a transfer.
1569 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum)
1571 u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum));
1572 struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum];
1573 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1574 struct usb_request *req = &hs_req->req;
1575 unsigned size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1579 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1583 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_OUT) {
1584 dev_dbg(hsotg->dev, "zlp packet received\n");
1585 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1586 dwc2_hsotg_enqueue_setup(hsotg);
1590 if (using_dma(hsotg)) {
1594 * Calculate the size of the transfer by checking how much
1595 * is left in the endpoint size register and then working it
1596 * out from the amount we loaded for the transfer.
1598 * We need to do this as DMA pointers are always 32bit aligned
1599 * so may overshoot/undershoot the transfer.
1602 size_done = hs_ep->size_loaded - size_left;
1603 size_done += hs_ep->last_load;
1605 req->actual = size_done;
1608 /* if there is more request to do, schedule new transfer */
1609 if (req->actual < req->length && size_left == 0) {
1610 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1614 if (req->actual < req->length && req->short_not_ok) {
1615 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1616 __func__, req->actual, req->length);
1619 * todo - what should we return here? there's no one else
1620 * even bothering to check the status.
1624 if (epnum == 0 && hsotg->ep0_state == DWC2_EP0_DATA_OUT) {
1625 /* Move to STATUS IN */
1626 dwc2_hsotg_ep0_zlp(hsotg, true);
1631 * Slave mode OUT transfers do not go through XferComplete so
1632 * adjust the ISOC parity here.
1634 if (!using_dma(hsotg)) {
1635 hs_ep->has_correct_parity = 1;
1636 if (hs_ep->isochronous && hs_ep->interval == 1)
1637 dwc2_hsotg_change_ep_iso_parity(hsotg, DOEPCTL(epnum));
1640 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1644 * dwc2_hsotg_read_frameno - read current frame number
1645 * @hsotg: The device instance
1647 * Return the current frame number
1649 static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg)
1653 dsts = dwc2_readl(hsotg->regs + DSTS);
1654 dsts &= DSTS_SOFFN_MASK;
1655 dsts >>= DSTS_SOFFN_SHIFT;
1661 * dwc2_hsotg_handle_rx - RX FIFO has data
1662 * @hsotg: The device instance
1664 * The IRQ handler has detected that the RX FIFO has some data in it
1665 * that requires processing, so find out what is in there and do the
1668 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1669 * chunks, so if you have x packets received on an endpoint you'll get x
1670 * FIFO events delivered, each with a packet's worth of data in it.
1672 * When using DMA, we should not be processing events from the RXFIFO
1673 * as the actual data should be sent to the memory directly and we turn
1674 * on the completion interrupts to get notifications of transfer completion.
1676 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg)
1678 u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP);
1679 u32 epnum, status, size;
1681 WARN_ON(using_dma(hsotg));
1683 epnum = grxstsr & GRXSTS_EPNUM_MASK;
1684 status = grxstsr & GRXSTS_PKTSTS_MASK;
1686 size = grxstsr & GRXSTS_BYTECNT_MASK;
1687 size >>= GRXSTS_BYTECNT_SHIFT;
1689 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1690 __func__, grxstsr, size, epnum);
1692 switch ((status & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT) {
1693 case GRXSTS_PKTSTS_GLOBALOUTNAK:
1694 dev_dbg(hsotg->dev, "GLOBALOUTNAK\n");
1697 case GRXSTS_PKTSTS_OUTDONE:
1698 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1699 dwc2_hsotg_read_frameno(hsotg));
1701 if (!using_dma(hsotg))
1702 dwc2_hsotg_handle_outdone(hsotg, epnum);
1705 case GRXSTS_PKTSTS_SETUPDONE:
1707 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1708 dwc2_hsotg_read_frameno(hsotg),
1709 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1711 * Call dwc2_hsotg_handle_outdone here if it was not called from
1712 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1713 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1715 if (hsotg->ep0_state == DWC2_EP0_SETUP)
1716 dwc2_hsotg_handle_outdone(hsotg, epnum);
1719 case GRXSTS_PKTSTS_OUTRX:
1720 dwc2_hsotg_rx_data(hsotg, epnum, size);
1723 case GRXSTS_PKTSTS_SETUPRX:
1725 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1726 dwc2_hsotg_read_frameno(hsotg),
1727 dwc2_readl(hsotg->regs + DOEPCTL(0)));
1729 WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP);
1731 dwc2_hsotg_rx_data(hsotg, epnum, size);
1735 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1738 dwc2_hsotg_dump(hsotg);
1744 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1745 * @mps: The maximum packet size in bytes.
1747 static u32 dwc2_hsotg_ep0_mps(unsigned int mps)
1751 return D0EPCTL_MPS_64;
1753 return D0EPCTL_MPS_32;
1755 return D0EPCTL_MPS_16;
1757 return D0EPCTL_MPS_8;
1760 /* bad max packet size, warn and return invalid result */
1766 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1767 * @hsotg: The driver state.
1768 * @ep: The index number of the endpoint
1769 * @mps: The maximum packet size in bytes
1771 * Configure the maximum packet size for the given endpoint, updating
1772 * the hardware control registers to reflect this.
1774 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg,
1775 unsigned int ep, unsigned int mps, unsigned int dir_in)
1777 struct dwc2_hsotg_ep *hs_ep;
1778 void __iomem *regs = hsotg->regs;
1783 hs_ep = index_to_ep(hsotg, ep, dir_in);
1788 /* EP0 is a special case */
1789 mpsval = dwc2_hsotg_ep0_mps(mps);
1792 hs_ep->ep.maxpacket = mps;
1795 mpsval = mps & DXEPCTL_MPS_MASK;
1798 mcval = ((mps >> 11) & 0x3) + 1;
1802 hs_ep->ep.maxpacket = mpsval;
1806 reg = dwc2_readl(regs + DIEPCTL(ep));
1807 reg &= ~DXEPCTL_MPS_MASK;
1809 dwc2_writel(reg, regs + DIEPCTL(ep));
1811 reg = dwc2_readl(regs + DOEPCTL(ep));
1812 reg &= ~DXEPCTL_MPS_MASK;
1814 dwc2_writel(reg, regs + DOEPCTL(ep));
1820 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1824 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1825 * @hsotg: The driver state
1826 * @idx: The index for the endpoint (0..15)
1828 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx)
1833 dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH,
1834 hsotg->regs + GRSTCTL);
1836 /* wait until the fifo is flushed */
1840 val = dwc2_readl(hsotg->regs + GRSTCTL);
1842 if ((val & (GRSTCTL_TXFFLSH)) == 0)
1845 if (--timeout == 0) {
1847 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1857 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1858 * @hsotg: The driver state
1859 * @hs_ep: The driver endpoint to check.
1861 * Check to see if there is a request that has data to send, and if so
1862 * make an attempt to write data into the FIFO.
1864 static int dwc2_hsotg_trytx(struct dwc2_hsotg *hsotg,
1865 struct dwc2_hsotg_ep *hs_ep)
1867 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1869 if (!hs_ep->dir_in || !hs_req) {
1871 * if request is not enqueued, we disable interrupts
1872 * for endpoints, excepting ep0
1874 if (hs_ep->index != 0)
1875 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index,
1880 if (hs_req->req.actual < hs_req->req.length) {
1881 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1883 return dwc2_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1890 * dwc2_hsotg_complete_in - complete IN transfer
1891 * @hsotg: The device state.
1892 * @hs_ep: The endpoint that has just completed.
1894 * An IN transfer has been completed, update the transfer's state and then
1895 * call the relevant completion routines.
1897 static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg,
1898 struct dwc2_hsotg_ep *hs_ep)
1900 struct dwc2_hsotg_req *hs_req = hs_ep->req;
1901 u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1902 int size_left, size_done;
1905 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1909 /* Finish ZLP handling for IN EP0 transactions */
1910 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_STATUS_IN) {
1911 dev_dbg(hsotg->dev, "zlp packet sent\n");
1912 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1913 if (hsotg->test_mode) {
1916 ret = dwc2_hsotg_set_test_mode(hsotg, hsotg->test_mode);
1918 dev_dbg(hsotg->dev, "Invalid Test #%d\n",
1920 dwc2_hsotg_stall_ep0(hsotg);
1924 dwc2_hsotg_enqueue_setup(hsotg);
1929 * Calculate the size of the transfer by checking how much is left
1930 * in the endpoint size register and then working it out from
1931 * the amount we loaded for the transfer.
1933 * We do this even for DMA, as the transfer may have incremented
1934 * past the end of the buffer (DMA transfers are always 32bit
1938 size_left = DXEPTSIZ_XFERSIZE_GET(epsize);
1940 size_done = hs_ep->size_loaded - size_left;
1941 size_done += hs_ep->last_load;
1943 if (hs_req->req.actual != size_done)
1944 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1945 __func__, hs_req->req.actual, size_done);
1947 hs_req->req.actual = size_done;
1948 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1949 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1951 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1952 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1953 dwc2_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1957 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
1958 if (hs_ep->send_zlp) {
1959 dwc2_hsotg_program_zlp(hsotg, hs_ep);
1960 hs_ep->send_zlp = 0;
1961 /* transfer will be completed on next complete interrupt */
1965 if (hs_ep->index == 0 && hsotg->ep0_state == DWC2_EP0_DATA_IN) {
1966 /* Move to STATUS OUT */
1967 dwc2_hsotg_ep0_zlp(hsotg, false);
1971 dwc2_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1975 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
1976 * @hsotg: The device state.
1977 * @idx: Index of ep.
1978 * @dir_in: Endpoint direction 1-in 0-out.
1980 * Reads for endpoint with given index and direction, by masking
1981 * epint_reg with coresponding mask.
1983 static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg,
1984 unsigned int idx, int dir_in)
1986 u32 epmsk_reg = dir_in ? DIEPMSK : DOEPMSK;
1987 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1992 mask = dwc2_readl(hsotg->regs + epmsk_reg);
1993 diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK);
1994 mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0;
1995 mask |= DXEPINT_SETUP_RCVD;
1997 ints = dwc2_readl(hsotg->regs + epint_reg);
2003 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2004 * @hs_ep: The endpoint on which interrupt is asserted.
2006 * This is starting point for ISOC-OUT transfer, synchronization done with
2007 * first out token received from host while corresponding EP is disabled.
2009 * Device does not know initial frame in which out token will come. For this
2010 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2011 * getting this interrupt SW starts calculation for next transfer frame.
2013 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep)
2015 struct dwc2_hsotg *hsotg = ep->parent;
2016 int dir_in = ep->dir_in;
2019 if (dir_in || !ep->isochronous)
2022 dwc2_hsotg_complete_request(hsotg, ep, get_ep_head(ep), -ENODATA);
2024 if (ep->interval > 1 &&
2025 ep->target_frame == TARGET_FRAME_INITIAL) {
2029 dsts = dwc2_readl(hsotg->regs + DSTS);
2030 ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2031 dwc2_gadget_incr_frame_num(ep);
2033 ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index));
2034 if (ep->target_frame & 0x1)
2035 ctrl |= DXEPCTL_SETODDFR;
2037 ctrl |= DXEPCTL_SETEVENFR;
2039 dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index));
2042 dwc2_gadget_start_next_request(ep);
2043 doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
2044 doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK;
2045 dwc2_writel(doepmsk, hsotg->regs + DOEPMSK);
2049 * dwc2_gadget_handle_nak - handle NAK interrupt
2050 * @hs_ep: The endpoint on which interrupt is asserted.
2052 * This is starting point for ISOC-IN transfer, synchronization done with
2053 * first IN token received from host while corresponding EP is disabled.
2055 * Device does not know when first one token will arrive from host. On first
2056 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2057 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2058 * sent in response to that as there was no data in FIFO. SW is basing on this
2059 * interrupt to obtain frame in which token has come and then based on the
2060 * interval calculates next frame for transfer.
2062 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep)
2064 struct dwc2_hsotg *hsotg = hs_ep->parent;
2065 int dir_in = hs_ep->dir_in;
2067 if (!dir_in || !hs_ep->isochronous)
2070 if (hs_ep->target_frame == TARGET_FRAME_INITIAL) {
2071 hs_ep->target_frame = dwc2_hsotg_read_frameno(hsotg);
2072 if (hs_ep->interval > 1) {
2073 u32 ctrl = dwc2_readl(hsotg->regs +
2074 DIEPCTL(hs_ep->index));
2075 if (hs_ep->target_frame & 0x1)
2076 ctrl |= DXEPCTL_SETODDFR;
2078 ctrl |= DXEPCTL_SETEVENFR;
2080 dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index));
2083 dwc2_hsotg_complete_request(hsotg, hs_ep,
2084 get_ep_head(hs_ep), 0);
2087 dwc2_gadget_incr_frame_num(hs_ep);
2091 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2092 * @hsotg: The driver state
2093 * @idx: The index for the endpoint (0..15)
2094 * @dir_in: Set if this is an IN endpoint
2096 * Process and clear any interrupt pending for an individual endpoint
2098 static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx,
2101 struct dwc2_hsotg_ep *hs_ep = index_to_ep(hsotg, idx, dir_in);
2102 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
2103 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
2104 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
2108 ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in);
2109 ctrl = dwc2_readl(hsotg->regs + epctl_reg);
2111 /* Clear endpoint interrupts */
2112 dwc2_writel(ints, hsotg->regs + epint_reg);
2115 dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n",
2116 __func__, idx, dir_in ? "in" : "out");
2120 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2121 __func__, idx, dir_in ? "in" : "out", ints);
2123 /* Don't process XferCompl interrupt if it is a setup packet */
2124 if (idx == 0 && (ints & (DXEPINT_SETUP | DXEPINT_SETUP_RCVD)))
2125 ints &= ~DXEPINT_XFERCOMPL;
2127 if (ints & DXEPINT_XFERCOMPL) {
2128 hs_ep->has_correct_parity = 1;
2129 if (hs_ep->isochronous && hs_ep->interval == 1)
2130 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2133 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2134 __func__, dwc2_readl(hsotg->regs + epctl_reg),
2135 dwc2_readl(hsotg->regs + epsiz_reg));
2138 * we get OutDone from the FIFO, so we only need to look
2139 * at completing IN requests here
2142 dwc2_hsotg_complete_in(hsotg, hs_ep);
2144 if (idx == 0 && !hs_ep->req)
2145 dwc2_hsotg_enqueue_setup(hsotg);
2146 } else if (using_dma(hsotg)) {
2148 * We're using DMA, we need to fire an OutDone here
2149 * as we ignore the RXFIFO.
2152 dwc2_hsotg_handle_outdone(hsotg, idx);
2156 if (ints & DXEPINT_EPDISBLD) {
2157 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
2160 int epctl = dwc2_readl(hsotg->regs + epctl_reg);
2162 dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index);
2164 if ((epctl & DXEPCTL_STALL) &&
2165 (epctl & DXEPCTL_EPTYPE_BULK)) {
2166 int dctl = dwc2_readl(hsotg->regs + DCTL);
2168 dctl |= DCTL_CGNPINNAK;
2169 dwc2_writel(dctl, hsotg->regs + DCTL);
2174 if (ints & DXEPINT_OUTTKNEPDIS)
2175 dwc2_gadget_handle_out_token_ep_disabled(hs_ep);
2177 if (ints & DXEPINT_NAKINTRPT)
2178 dwc2_gadget_handle_nak(hs_ep);
2180 if (ints & DXEPINT_AHBERR)
2181 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2183 if (ints & DXEPINT_SETUP) { /* Setup or Timeout */
2184 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2186 if (using_dma(hsotg) && idx == 0) {
2188 * this is the notification we've received a
2189 * setup packet. In non-DMA mode we'd get this
2190 * from the RXFIFO, instead we need to process
2197 dwc2_hsotg_handle_outdone(hsotg, 0);
2201 if (ints & DXEPINT_BACK2BACKSETUP)
2202 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2204 if (dir_in && !hs_ep->isochronous) {
2205 /* not sure if this is important, but we'll clear it anyway */
2206 if (ints & DXEPINT_INTKNTXFEMP) {
2207 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2211 /* this probably means something bad is happening */
2212 if (ints & DXEPINT_INTKNEPMIS) {
2213 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2217 /* FIFO has space or is empty (see GAHBCFG) */
2218 if (hsotg->dedicated_fifos &&
2219 ints & DXEPINT_TXFEMP) {
2220 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2222 if (!using_dma(hsotg))
2223 dwc2_hsotg_trytx(hsotg, hs_ep);
2229 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2230 * @hsotg: The device state.
2232 * Handle updating the device settings after the enumeration phase has
2235 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg)
2237 u32 dsts = dwc2_readl(hsotg->regs + DSTS);
2238 int ep0_mps = 0, ep_mps = 8;
2241 * This should signal the finish of the enumeration phase
2242 * of the USB handshaking, so we should now know what rate
2246 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2249 * note, since we're limited by the size of transfer on EP0, and
2250 * it seems IN transfers must be a even number of packets we do
2251 * not advertise a 64byte MPS on EP0.
2254 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2255 switch ((dsts & DSTS_ENUMSPD_MASK) >> DSTS_ENUMSPD_SHIFT) {
2256 case DSTS_ENUMSPD_FS:
2257 case DSTS_ENUMSPD_FS48:
2258 hsotg->gadget.speed = USB_SPEED_FULL;
2259 ep0_mps = EP0_MPS_LIMIT;
2263 case DSTS_ENUMSPD_HS:
2264 hsotg->gadget.speed = USB_SPEED_HIGH;
2265 ep0_mps = EP0_MPS_LIMIT;
2269 case DSTS_ENUMSPD_LS:
2270 hsotg->gadget.speed = USB_SPEED_LOW;
2272 * note, we don't actually support LS in this driver at the
2273 * moment, and the documentation seems to imply that it isn't
2274 * supported by the PHYs on some of the devices.
2278 dev_info(hsotg->dev, "new device is %s\n",
2279 usb_speed_string(hsotg->gadget.speed));
2282 * we should now know the maximum packet size for an
2283 * endpoint, so set the endpoints to a default value.
2288 /* Initialize ep0 for both in and out directions */
2289 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 1);
2290 dwc2_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps, 0);
2291 for (i = 1; i < hsotg->num_of_eps; i++) {
2292 if (hsotg->eps_in[i])
2293 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 1);
2294 if (hsotg->eps_out[i])
2295 dwc2_hsotg_set_ep_maxpacket(hsotg, i, ep_mps, 0);
2299 /* ensure after enumeration our EP0 is active */
2301 dwc2_hsotg_enqueue_setup(hsotg);
2303 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2304 dwc2_readl(hsotg->regs + DIEPCTL0),
2305 dwc2_readl(hsotg->regs + DOEPCTL0));
2309 * kill_all_requests - remove all requests from the endpoint's queue
2310 * @hsotg: The device state.
2311 * @ep: The endpoint the requests may be on.
2312 * @result: The result code to use.
2314 * Go through the requests on the given endpoint and mark them
2315 * completed with the given result code.
2317 static void kill_all_requests(struct dwc2_hsotg *hsotg,
2318 struct dwc2_hsotg_ep *ep,
2321 struct dwc2_hsotg_req *req, *treq;
2326 list_for_each_entry_safe(req, treq, &ep->queue, queue)
2327 dwc2_hsotg_complete_request(hsotg, ep, req,
2330 if (!hsotg->dedicated_fifos)
2332 size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4;
2333 if (size < ep->fifo_size)
2334 dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index);
2338 * dwc2_hsotg_disconnect - disconnect service
2339 * @hsotg: The device state.
2341 * The device has been disconnected. Remove all current
2342 * transactions and signal the gadget driver that this
2345 void dwc2_hsotg_disconnect(struct dwc2_hsotg *hsotg)
2349 if (!hsotg->connected)
2352 hsotg->connected = 0;
2353 hsotg->test_mode = 0;
2355 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
2356 if (hsotg->eps_in[ep])
2357 kill_all_requests(hsotg, hsotg->eps_in[ep],
2359 if (hsotg->eps_out[ep])
2360 kill_all_requests(hsotg, hsotg->eps_out[ep],
2364 call_gadget(hsotg, disconnect);
2365 hsotg->lx_state = DWC2_L3;
2369 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2370 * @hsotg: The device state:
2371 * @periodic: True if this is a periodic FIFO interrupt
2373 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg *hsotg, bool periodic)
2375 struct dwc2_hsotg_ep *ep;
2378 /* look through for any more data to transmit */
2379 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2380 ep = index_to_ep(hsotg, epno, 1);
2388 if ((periodic && !ep->periodic) ||
2389 (!periodic && ep->periodic))
2392 ret = dwc2_hsotg_trytx(hsotg, ep);
2398 /* IRQ flags which will trigger a retry around the IRQ loop */
2399 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2404 * dwc2_hsotg_core_init - issue softreset to the core
2405 * @hsotg: The device state
2407 * Issue a soft reset to the core, and await the core finishing it.
2409 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
2416 /* Kill any ep0 requests as controller will be reinitialized */
2417 kill_all_requests(hsotg, hsotg->eps_out[0], -ECONNRESET);
2420 if (dwc2_core_reset(hsotg))
2424 * we must now enable ep0 ready for host detection and then
2425 * set configuration.
2428 /* keep other bits untouched (so e.g. forced modes are not lost) */
2429 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2430 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
2433 /* set the PLL on, remove the HNP/SRP and set the PHY */
2434 val = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
2435 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
2436 (val << GUSBCFG_USBTRDTIM_SHIFT);
2437 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2439 dwc2_hsotg_init_fifo(hsotg);
2442 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2444 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS, hsotg->regs + DCFG);
2446 /* Clear any pending OTG interrupts */
2447 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
2449 /* Clear any pending interrupts */
2450 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
2451 intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT |
2452 GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF |
2453 GINTSTS_USBRST | GINTSTS_RESETDET |
2454 GINTSTS_ENUMDONE | GINTSTS_OTGINT |
2455 GINTSTS_USBSUSP | GINTSTS_WKUPINT |
2456 GINTSTS_INCOMPL_SOIN | GINTSTS_INCOMPL_SOOUT;
2458 if (hsotg->core_params->external_id_pin_ctl <= 0)
2459 intmsk |= GINTSTS_CONIDSTSCHNG;
2461 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
2463 if (using_dma(hsotg))
2464 dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN |
2465 (GAHBCFG_HBSTLEN_INCR4 << GAHBCFG_HBSTLEN_SHIFT),
2466 hsotg->regs + GAHBCFG);
2468 dwc2_writel(((hsotg->dedicated_fifos) ?
2469 (GAHBCFG_NP_TXF_EMP_LVL |
2470 GAHBCFG_P_TXF_EMP_LVL) : 0) |
2471 GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG);
2474 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2475 * when we have no data to transfer. Otherwise we get being flooded by
2479 dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ?
2480 DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) |
2481 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK |
2482 DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
2483 DIEPMSK_INTKNEPMISMSK,
2484 hsotg->regs + DIEPMSK);
2487 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2488 * DMA mode we may need this.
2490 dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK |
2491 DIEPMSK_TIMEOUTMSK) : 0) |
2492 DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK |
2494 hsotg->regs + DOEPMSK);
2496 dwc2_writel(0, hsotg->regs + DAINTMSK);
2498 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2499 dwc2_readl(hsotg->regs + DIEPCTL0),
2500 dwc2_readl(hsotg->regs + DOEPCTL0));
2502 /* enable in and out endpoint interrupts */
2503 dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT);
2506 * Enable the RXFIFO when in slave mode, as this is how we collect
2507 * the data. In DMA mode, we get events from the FIFO but also
2508 * things we cannot process, so do not use it.
2510 if (!using_dma(hsotg))
2511 dwc2_hsotg_en_gsint(hsotg, GINTSTS_RXFLVL);
2513 /* Enable interrupts for EP0 in and out */
2514 dwc2_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2515 dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2517 if (!is_usb_reset) {
2518 __orr32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2519 udelay(10); /* see openiboot */
2520 __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE);
2523 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL));
2526 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2527 * writing to the EPCTL register..
2530 /* set to read 1 8byte packet */
2531 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2532 DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0);
2534 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2535 DXEPCTL_CNAK | DXEPCTL_EPENA |
2537 hsotg->regs + DOEPCTL0);
2539 /* enable, but don't activate EP0in */
2540 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) |
2541 DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0);
2543 dwc2_hsotg_enqueue_setup(hsotg);
2545 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2546 dwc2_readl(hsotg->regs + DIEPCTL0),
2547 dwc2_readl(hsotg->regs + DOEPCTL0));
2549 /* clear global NAKs */
2550 val = DCTL_CGOUTNAK | DCTL_CGNPINNAK;
2552 val |= DCTL_SFTDISCON;
2553 __orr32(hsotg->regs + DCTL, val);
2555 /* must be at-least 3ms to allow bus to see disconnect */
2558 hsotg->lx_state = DWC2_L0;
2561 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg)
2563 /* set the soft-disconnect bit */
2564 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2567 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg)
2569 /* remove the soft-disconnect and let's go */
2570 __bic32(hsotg->regs + DCTL, DCTL_SFTDISCON);
2574 * dwc2_hsotg_irq - handle device interrupt
2575 * @irq: The IRQ number triggered
2576 * @pw: The pw value when registered the handler.
2578 static irqreturn_t dwc2_hsotg_irq(int irq, void *pw)
2580 struct dwc2_hsotg *hsotg = pw;
2581 int retry_count = 8;
2585 if (!dwc2_is_device_mode(hsotg))
2588 spin_lock(&hsotg->lock);
2590 gintsts = dwc2_readl(hsotg->regs + GINTSTS);
2591 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
2593 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2594 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2598 if (gintsts & GINTSTS_RESETDET) {
2599 dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__);
2601 dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS);
2603 /* This event must be used only if controller is suspended */
2604 if (hsotg->lx_state == DWC2_L2) {
2605 dwc2_exit_hibernation(hsotg, true);
2606 hsotg->lx_state = DWC2_L0;
2610 if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) {
2612 u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL);
2613 u32 connected = hsotg->connected;
2615 dev_dbg(hsotg->dev, "%s: USBRst\n", __func__);
2616 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2617 dwc2_readl(hsotg->regs + GNPTXSTS));
2619 dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS);
2621 /* Report disconnection if it is not already done. */
2622 dwc2_hsotg_disconnect(hsotg);
2624 if (usb_status & GOTGCTL_BSESVLD && connected)
2625 dwc2_hsotg_core_init_disconnected(hsotg, true);
2628 if (gintsts & GINTSTS_ENUMDONE) {
2629 dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS);
2631 dwc2_hsotg_irq_enumdone(hsotg);
2634 if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) {
2635 u32 daint = dwc2_readl(hsotg->regs + DAINT);
2636 u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
2637 u32 daint_out, daint_in;
2641 daint_out = daint >> DAINT_OUTEP_SHIFT;
2642 daint_in = daint & ~(daint_out << DAINT_OUTEP_SHIFT);
2644 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2646 for (ep = 0; ep < hsotg->num_of_eps && daint_out;
2647 ep++, daint_out >>= 1) {
2649 dwc2_hsotg_epint(hsotg, ep, 0);
2652 for (ep = 0; ep < hsotg->num_of_eps && daint_in;
2653 ep++, daint_in >>= 1) {
2655 dwc2_hsotg_epint(hsotg, ep, 1);
2659 /* check both FIFOs */
2661 if (gintsts & GINTSTS_NPTXFEMP) {
2662 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2665 * Disable the interrupt to stop it happening again
2666 * unless one of these endpoint routines decides that
2667 * it needs re-enabling
2670 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_NPTXFEMP);
2671 dwc2_hsotg_irq_fifoempty(hsotg, false);
2674 if (gintsts & GINTSTS_PTXFEMP) {
2675 dev_dbg(hsotg->dev, "PTxFEmp\n");
2677 /* See note in GINTSTS_NPTxFEmp */
2679 dwc2_hsotg_disable_gsint(hsotg, GINTSTS_PTXFEMP);
2680 dwc2_hsotg_irq_fifoempty(hsotg, true);
2683 if (gintsts & GINTSTS_RXFLVL) {
2685 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2686 * we need to retry dwc2_hsotg_handle_rx if this is still
2690 dwc2_hsotg_handle_rx(hsotg);
2693 if (gintsts & GINTSTS_ERLYSUSP) {
2694 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2695 dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS);
2699 * these next two seem to crop-up occasionally causing the core
2700 * to shutdown the USB transfer, so try clearing them and logging
2704 if (gintsts & GINTSTS_GOUTNAKEFF) {
2705 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2707 __orr32(hsotg->regs + DCTL, DCTL_CGOUTNAK);
2709 dwc2_hsotg_dump(hsotg);
2712 if (gintsts & GINTSTS_GINNAKEFF) {
2713 dev_info(hsotg->dev, "GINNakEff triggered\n");
2715 __orr32(hsotg->regs + DCTL, DCTL_CGNPINNAK);
2717 dwc2_hsotg_dump(hsotg);
2720 if (gintsts & GINTSTS_INCOMPL_SOIN) {
2722 struct dwc2_hsotg_ep *hs_ep;
2724 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOIN\n", __func__);
2725 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2726 hs_ep = hsotg->eps_in[idx];
2728 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2731 epctl_reg = DIEPCTL(idx);
2732 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2734 dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS);
2737 if (gintsts & GINTSTS_INCOMPL_SOOUT) {
2739 struct dwc2_hsotg_ep *hs_ep;
2741 dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__);
2742 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
2743 hs_ep = hsotg->eps_out[idx];
2745 if (!hs_ep->isochronous || hs_ep->has_correct_parity)
2748 epctl_reg = DOEPCTL(idx);
2749 dwc2_hsotg_change_ep_iso_parity(hsotg, epctl_reg);
2751 dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS);
2755 * if we've had fifo events, we should try and go around the
2756 * loop again to see if there's any point in returning yet.
2759 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2762 spin_unlock(&hsotg->lock);
2768 * dwc2_hsotg_ep_enable - enable the given endpoint
2769 * @ep: The USB endpint to configure
2770 * @desc: The USB endpoint descriptor to configure with.
2772 * This is called from the USB gadget code's usb_ep_enable().
2774 static int dwc2_hsotg_ep_enable(struct usb_ep *ep,
2775 const struct usb_endpoint_descriptor *desc)
2777 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2778 struct dwc2_hsotg *hsotg = hs_ep->parent;
2779 unsigned long flags;
2780 unsigned int index = hs_ep->index;
2784 unsigned int dir_in;
2785 unsigned int i, val, size;
2789 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2790 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2791 desc->wMaxPacketSize, desc->bInterval);
2793 /* not to be called for EP0 */
2795 dev_err(hsotg->dev, "%s: called for EP 0\n", __func__);
2799 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2800 if (dir_in != hs_ep->dir_in) {
2801 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2805 mps = usb_endpoint_maxp(desc);
2807 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2809 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2810 epctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2812 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2813 __func__, epctrl, epctrl_reg);
2815 spin_lock_irqsave(&hsotg->lock, flags);
2817 epctrl &= ~(DXEPCTL_EPTYPE_MASK | DXEPCTL_MPS_MASK);
2818 epctrl |= DXEPCTL_MPS(mps);
2821 * mark the endpoint as active, otherwise the core may ignore
2822 * transactions entirely for this endpoint
2824 epctrl |= DXEPCTL_USBACTEP;
2827 * set the NAK status on the endpoint, otherwise we might try and
2828 * do something with data that we've yet got a request to process
2829 * since the RXFIFO will take data for an endpoint even if the
2830 * size register hasn't been set.
2833 epctrl |= DXEPCTL_SNAK;
2835 /* update the endpoint state */
2836 dwc2_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps, dir_in);
2838 /* default, set to non-periodic */
2839 hs_ep->isochronous = 0;
2840 hs_ep->periodic = 0;
2842 hs_ep->interval = desc->bInterval;
2844 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2845 case USB_ENDPOINT_XFER_ISOC:
2846 epctrl |= DXEPCTL_EPTYPE_ISO;
2847 epctrl |= DXEPCTL_SETEVENFR;
2848 hs_ep->isochronous = 1;
2849 hs_ep->interval = 1 << (desc->bInterval - 1);
2851 hs_ep->periodic = 1;
2854 case USB_ENDPOINT_XFER_BULK:
2855 epctrl |= DXEPCTL_EPTYPE_BULK;
2858 case USB_ENDPOINT_XFER_INT:
2860 hs_ep->periodic = 1;
2862 if (hsotg->gadget.speed == USB_SPEED_HIGH)
2863 hs_ep->interval = 1 << (desc->bInterval - 1);
2865 epctrl |= DXEPCTL_EPTYPE_INTERRUPT;
2868 case USB_ENDPOINT_XFER_CONTROL:
2869 epctrl |= DXEPCTL_EPTYPE_CONTROL;
2873 /* If fifo is already allocated for this ep */
2874 if (hs_ep->fifo_index) {
2875 size = hs_ep->ep.maxpacket * hs_ep->mc;
2876 /* If bigger fifo is required deallocate current one */
2877 if (size > hs_ep->fifo_size) {
2878 hsotg->fifo_map &= ~(1 << hs_ep->fifo_index);
2879 hs_ep->fifo_index = 0;
2880 hs_ep->fifo_size = 0;
2885 * if the hardware has dedicated fifos, we must give each IN EP
2886 * a unique tx-fifo even if it is non-periodic.
2888 if (dir_in && hsotg->dedicated_fifos && !hs_ep->fifo_index) {
2890 u32 fifo_size = UINT_MAX;
2891 size = hs_ep->ep.maxpacket*hs_ep->mc;
2892 for (i = 1; i < hsotg->num_of_eps; ++i) {
2893 if (hsotg->fifo_map & (1<<i))
2895 val = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
2896 val = (val >> FIFOSIZE_DEPTH_SHIFT)*4;
2899 /* Search for smallest acceptable fifo */
2900 if (val < fifo_size) {
2907 "%s: No suitable fifo found\n", __func__);
2911 hsotg->fifo_map |= 1 << fifo_index;
2912 epctrl |= DXEPCTL_TXFNUM(fifo_index);
2913 hs_ep->fifo_index = fifo_index;
2914 hs_ep->fifo_size = fifo_size;
2917 /* for non control endpoints, set PID to D0 */
2919 epctrl |= DXEPCTL_SETD0PID;
2921 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2924 dwc2_writel(epctrl, hsotg->regs + epctrl_reg);
2925 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2926 __func__, dwc2_readl(hsotg->regs + epctrl_reg));
2928 /* enable the endpoint interrupt */
2929 dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2932 spin_unlock_irqrestore(&hsotg->lock, flags);
2937 * dwc2_hsotg_ep_disable - disable given endpoint
2938 * @ep: The endpoint to disable.
2940 static int dwc2_hsotg_ep_disable(struct usb_ep *ep)
2942 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
2943 struct dwc2_hsotg *hsotg = hs_ep->parent;
2944 int dir_in = hs_ep->dir_in;
2945 int index = hs_ep->index;
2946 unsigned long flags;
2950 dev_dbg(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2952 if (ep == &hsotg->eps_out[0]->ep) {
2953 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2957 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2959 spin_lock_irqsave(&hsotg->lock, flags);
2961 hsotg->fifo_map &= ~(1<<hs_ep->fifo_index);
2962 hs_ep->fifo_index = 0;
2963 hs_ep->fifo_size = 0;
2965 ctrl = dwc2_readl(hsotg->regs + epctrl_reg);
2966 ctrl &= ~DXEPCTL_EPENA;
2967 ctrl &= ~DXEPCTL_USBACTEP;
2968 ctrl |= DXEPCTL_SNAK;
2970 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2971 dwc2_writel(ctrl, hsotg->regs + epctrl_reg);
2973 /* disable endpoint interrupts */
2974 dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2976 /* terminate all requests with shutdown */
2977 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN);
2979 spin_unlock_irqrestore(&hsotg->lock, flags);
2984 * on_list - check request is on the given endpoint
2985 * @ep: The endpoint to check.
2986 * @test: The request to test if it is on the endpoint.
2988 static bool on_list(struct dwc2_hsotg_ep *ep, struct dwc2_hsotg_req *test)
2990 struct dwc2_hsotg_req *req, *treq;
2992 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
3000 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hs_otg, u32 reg,
3001 u32 bit, u32 timeout)
3005 for (i = 0; i < timeout; i++) {
3006 if (dwc2_readl(hs_otg->regs + reg) & bit)
3014 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg,
3015 struct dwc2_hsotg_ep *hs_ep)
3020 epctrl_reg = hs_ep->dir_in ? DIEPCTL(hs_ep->index) :
3021 DOEPCTL(hs_ep->index);
3022 epint_reg = hs_ep->dir_in ? DIEPINT(hs_ep->index) :
3023 DOEPINT(hs_ep->index);
3025 dev_dbg(hsotg->dev, "%s: stopping transfer on %s\n", __func__,
3027 if (hs_ep->dir_in) {
3028 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_SNAK);
3029 /* Wait for Nak effect */
3030 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg,
3031 DXEPINT_INEPNAKEFF, 100))
3032 dev_warn(hsotg->dev,
3033 "%s: timeout DIEPINT.NAKEFF\n", __func__);
3035 if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF))
3036 __orr32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3038 /* Wait for global nak to take effect */
3039 if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS,
3040 GINTSTS_GOUTNAKEFF, 100))
3041 dev_warn(hsotg->dev,
3042 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__);
3046 __orr32(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK);
3048 /* Wait for ep to be disabled */
3049 if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100))
3050 dev_warn(hsotg->dev,
3051 "%s: timeout DOEPCTL.EPDisable\n", __func__);
3053 if (hs_ep->dir_in) {
3054 if (hsotg->dedicated_fifos) {
3055 dwc2_writel(GRSTCTL_TXFNUM(hs_ep->fifo_index) |
3056 GRSTCTL_TXFFLSH, hsotg->regs + GRSTCTL);
3057 /* Wait for fifo flush */
3058 if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
3059 GRSTCTL_TXFFLSH, 100))
3060 dev_warn(hsotg->dev,
3061 "%s: timeout flushing fifos\n",
3064 /* TODO: Flush shared tx fifo */
3066 /* Remove global NAKs */
3067 __bic32(hsotg->regs + DCTL, DCTL_SGOUTNAK);
3072 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
3073 * @ep: The endpoint to dequeue.
3074 * @req: The request to be removed from a queue.
3076 static int dwc2_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
3078 struct dwc2_hsotg_req *hs_req = our_req(req);
3079 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3080 struct dwc2_hsotg *hs = hs_ep->parent;
3081 unsigned long flags;
3083 dev_dbg(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
3085 spin_lock_irqsave(&hs->lock, flags);
3087 if (!on_list(hs_ep, hs_req)) {
3088 spin_unlock_irqrestore(&hs->lock, flags);
3092 /* Dequeue already started request */
3093 if (req == &hs_ep->req->req)
3094 dwc2_hsotg_ep_stop_xfr(hs, hs_ep);
3096 dwc2_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
3097 spin_unlock_irqrestore(&hs->lock, flags);
3103 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
3104 * @ep: The endpoint to set halt.
3105 * @value: Set or unset the halt.
3106 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
3107 * the endpoint is busy processing requests.
3109 * We need to stall the endpoint immediately if request comes from set_feature
3110 * protocol command handler.
3112 static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now)
3114 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3115 struct dwc2_hsotg *hs = hs_ep->parent;
3116 int index = hs_ep->index;
3121 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
3125 dwc2_hsotg_stall_ep0(hs);
3128 "%s: can't clear halt on ep0\n", __func__);
3132 if (hs_ep->isochronous) {
3133 dev_err(hs->dev, "%s is Isochronous Endpoint\n", ep->name);
3137 if (!now && value && !list_empty(&hs_ep->queue)) {
3138 dev_dbg(hs->dev, "%s request is pending, cannot halt\n",
3143 if (hs_ep->dir_in) {
3144 epreg = DIEPCTL(index);
3145 epctl = dwc2_readl(hs->regs + epreg);
3148 epctl |= DXEPCTL_STALL | DXEPCTL_SNAK;
3149 if (epctl & DXEPCTL_EPENA)
3150 epctl |= DXEPCTL_EPDIS;
3152 epctl &= ~DXEPCTL_STALL;
3153 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
3154 if (xfertype == DXEPCTL_EPTYPE_BULK ||
3155 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
3156 epctl |= DXEPCTL_SETD0PID;
3158 dwc2_writel(epctl, hs->regs + epreg);
3161 epreg = DOEPCTL(index);
3162 epctl = dwc2_readl(hs->regs + epreg);
3165 epctl |= DXEPCTL_STALL;
3167 epctl &= ~DXEPCTL_STALL;
3168 xfertype = epctl & DXEPCTL_EPTYPE_MASK;
3169 if (xfertype == DXEPCTL_EPTYPE_BULK ||
3170 xfertype == DXEPCTL_EPTYPE_INTERRUPT)
3171 epctl |= DXEPCTL_SETD0PID;
3173 dwc2_writel(epctl, hs->regs + epreg);
3176 hs_ep->halted = value;
3182 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3183 * @ep: The endpoint to set halt.
3184 * @value: Set or unset the halt.
3186 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
3188 struct dwc2_hsotg_ep *hs_ep = our_ep(ep);
3189 struct dwc2_hsotg *hs = hs_ep->parent;
3190 unsigned long flags = 0;
3193 spin_lock_irqsave(&hs->lock, flags);
3194 ret = dwc2_hsotg_ep_sethalt(ep, value, false);
3195 spin_unlock_irqrestore(&hs->lock, flags);
3200 static struct usb_ep_ops dwc2_hsotg_ep_ops = {
3201 .enable = dwc2_hsotg_ep_enable,
3202 .disable = dwc2_hsotg_ep_disable,
3203 .alloc_request = dwc2_hsotg_ep_alloc_request,
3204 .free_request = dwc2_hsotg_ep_free_request,
3205 .queue = dwc2_hsotg_ep_queue_lock,
3206 .dequeue = dwc2_hsotg_ep_dequeue,
3207 .set_halt = dwc2_hsotg_ep_sethalt_lock,
3208 /* note, don't believe we have any call for the fifo routines */
3212 * dwc2_hsotg_init - initalize the usb core
3213 * @hsotg: The driver state
3215 static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg)
3219 /* unmask subset of endpoint interrupts */
3221 dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK |
3222 DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK,
3223 hsotg->regs + DIEPMSK);
3225 dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK |
3226 DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK,
3227 hsotg->regs + DOEPMSK);
3229 dwc2_writel(0, hsotg->regs + DAINTMSK);
3231 /* Be in disconnected state until gadget is registered */
3232 __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON);
3236 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3237 dwc2_readl(hsotg->regs + GRXFSIZ),
3238 dwc2_readl(hsotg->regs + GNPTXFSIZ));
3240 dwc2_hsotg_init_fifo(hsotg);
3242 /* keep other bits untouched (so e.g. forced modes are not lost) */
3243 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3244 usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP |
3247 /* set the PLL on, remove the HNP/SRP and set the PHY */
3248 trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5;
3249 usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) |
3250 (trdtim << GUSBCFG_USBTRDTIM_SHIFT);
3251 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
3253 if (using_dma(hsotg))
3254 __orr32(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN);
3258 * dwc2_hsotg_udc_start - prepare the udc for work
3259 * @gadget: The usb gadget state
3260 * @driver: The usb gadget driver
3262 * Perform initialization to prepare udc device and driver
3265 static int dwc2_hsotg_udc_start(struct usb_gadget *gadget,
3266 struct usb_gadget_driver *driver)
3268 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3269 unsigned long flags;
3273 pr_err("%s: called with no device\n", __func__);
3278 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3282 if (driver->max_speed < USB_SPEED_FULL)
3283 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3285 if (!driver->setup) {
3286 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3290 WARN_ON(hsotg->driver);
3292 driver->driver.bus = NULL;
3293 hsotg->driver = driver;
3294 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3295 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3297 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
3298 ret = dwc2_lowlevel_hw_enable(hsotg);
3303 if (!IS_ERR_OR_NULL(hsotg->uphy))
3304 otg_set_peripheral(hsotg->uphy->otg, &hsotg->gadget);
3306 spin_lock_irqsave(&hsotg->lock, flags);
3307 dwc2_hsotg_init(hsotg);
3308 dwc2_hsotg_core_init_disconnected(hsotg, false);
3310 spin_unlock_irqrestore(&hsotg->lock, flags);
3312 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3317 hsotg->driver = NULL;
3322 * dwc2_hsotg_udc_stop - stop the udc
3323 * @gadget: The usb gadget state
3324 * @driver: The usb gadget driver
3326 * Stop udc hw block and stay tunned for future transmissions
3328 static int dwc2_hsotg_udc_stop(struct usb_gadget *gadget)
3330 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3331 unsigned long flags = 0;
3337 /* all endpoints should be shutdown */
3338 for (ep = 1; ep < hsotg->num_of_eps; ep++) {
3339 if (hsotg->eps_in[ep])
3340 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3341 if (hsotg->eps_out[ep])
3342 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3345 spin_lock_irqsave(&hsotg->lock, flags);
3347 hsotg->driver = NULL;
3348 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3351 spin_unlock_irqrestore(&hsotg->lock, flags);
3353 if (!IS_ERR_OR_NULL(hsotg->uphy))
3354 otg_set_peripheral(hsotg->uphy->otg, NULL);
3356 if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3357 dwc2_lowlevel_hw_disable(hsotg);
3363 * dwc2_hsotg_gadget_getframe - read the frame number
3364 * @gadget: The usb gadget state
3366 * Read the {micro} frame number
3368 static int dwc2_hsotg_gadget_getframe(struct usb_gadget *gadget)
3370 return dwc2_hsotg_read_frameno(to_hsotg(gadget));
3374 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3375 * @gadget: The usb gadget state
3376 * @is_on: Current state of the USB PHY
3378 * Connect/Disconnect the USB PHY pullup
3380 static int dwc2_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3382 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3383 unsigned long flags = 0;
3385 dev_dbg(hsotg->dev, "%s: is_on: %d op_state: %d\n", __func__, is_on,
3388 /* Don't modify pullup state while in host mode */
3389 if (hsotg->op_state != OTG_STATE_B_PERIPHERAL) {
3390 hsotg->enabled = is_on;
3394 spin_lock_irqsave(&hsotg->lock, flags);
3397 dwc2_hsotg_core_init_disconnected(hsotg, false);
3398 dwc2_hsotg_core_connect(hsotg);
3400 dwc2_hsotg_core_disconnect(hsotg);
3401 dwc2_hsotg_disconnect(hsotg);
3405 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3406 spin_unlock_irqrestore(&hsotg->lock, flags);
3411 static int dwc2_hsotg_vbus_session(struct usb_gadget *gadget, int is_active)
3413 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3414 unsigned long flags;
3416 dev_dbg(hsotg->dev, "%s: is_active: %d\n", __func__, is_active);
3417 spin_lock_irqsave(&hsotg->lock, flags);
3420 * If controller is hibernated, it must exit from hibernation
3421 * before being initialized / de-initialized
3423 if (hsotg->lx_state == DWC2_L2)
3424 dwc2_exit_hibernation(hsotg, false);
3427 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3429 dwc2_hsotg_core_init_disconnected(hsotg, false);
3431 dwc2_hsotg_core_connect(hsotg);
3433 dwc2_hsotg_core_disconnect(hsotg);
3434 dwc2_hsotg_disconnect(hsotg);
3437 spin_unlock_irqrestore(&hsotg->lock, flags);
3442 * dwc2_hsotg_vbus_draw - report bMaxPower field
3443 * @gadget: The usb gadget state
3444 * @mA: Amount of current
3446 * Report how much power the device may consume to the phy.
3448 static int dwc2_hsotg_vbus_draw(struct usb_gadget *gadget, unsigned mA)
3450 struct dwc2_hsotg *hsotg = to_hsotg(gadget);
3452 if (IS_ERR_OR_NULL(hsotg->uphy))
3454 return usb_phy_set_power(hsotg->uphy, mA);
3457 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops = {
3458 .get_frame = dwc2_hsotg_gadget_getframe,
3459 .udc_start = dwc2_hsotg_udc_start,
3460 .udc_stop = dwc2_hsotg_udc_stop,
3461 .pullup = dwc2_hsotg_pullup,
3462 .vbus_session = dwc2_hsotg_vbus_session,
3463 .vbus_draw = dwc2_hsotg_vbus_draw,
3467 * dwc2_hsotg_initep - initialise a single endpoint
3468 * @hsotg: The device state.
3469 * @hs_ep: The endpoint to be initialised.
3470 * @epnum: The endpoint number
3472 * Initialise the given endpoint (as part of the probe and device state
3473 * creation) to give to the gadget driver. Setup the endpoint name, any
3474 * direction information and other state that may be required.
3476 static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg,
3477 struct dwc2_hsotg_ep *hs_ep,
3490 hs_ep->dir_in = dir_in;
3491 hs_ep->index = epnum;
3493 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3495 INIT_LIST_HEAD(&hs_ep->queue);
3496 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3498 /* add to the list of endpoints known by the gadget driver */
3500 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3502 hs_ep->parent = hsotg;
3503 hs_ep->ep.name = hs_ep->name;
3504 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3505 hs_ep->ep.ops = &dwc2_hsotg_ep_ops;
3508 hs_ep->ep.caps.type_control = true;
3510 hs_ep->ep.caps.type_iso = true;
3511 hs_ep->ep.caps.type_bulk = true;
3512 hs_ep->ep.caps.type_int = true;
3516 hs_ep->ep.caps.dir_in = true;
3518 hs_ep->ep.caps.dir_out = true;
3521 * if we're using dma, we need to set the next-endpoint pointer
3522 * to be something valid.
3525 if (using_dma(hsotg)) {
3526 u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15);
3528 dwc2_writel(next, hsotg->regs + DIEPCTL(epnum));
3530 dwc2_writel(next, hsotg->regs + DOEPCTL(epnum));
3535 * dwc2_hsotg_hw_cfg - read HW configuration registers
3536 * @param: The device state
3538 * Read the USB core HW configuration registers
3540 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg *hsotg)
3546 /* check hardware configuration */
3548 hsotg->num_of_eps = hsotg->hw_params.num_dev_ep;
3551 hsotg->num_of_eps++;
3553 hsotg->eps_in[0] = devm_kzalloc(hsotg->dev, sizeof(struct dwc2_hsotg_ep),
3555 if (!hsotg->eps_in[0])
3557 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3558 hsotg->eps_out[0] = hsotg->eps_in[0];
3560 cfg = hsotg->hw_params.dev_ep_dirs;
3561 for (i = 1, cfg >>= 2; i < hsotg->num_of_eps; i++, cfg >>= 2) {
3563 /* Direction in or both */
3564 if (!(ep_type & 2)) {
3565 hsotg->eps_in[i] = devm_kzalloc(hsotg->dev,
3566 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3567 if (!hsotg->eps_in[i])
3570 /* Direction out or both */
3571 if (!(ep_type & 1)) {
3572 hsotg->eps_out[i] = devm_kzalloc(hsotg->dev,
3573 sizeof(struct dwc2_hsotg_ep), GFP_KERNEL);
3574 if (!hsotg->eps_out[i])
3579 hsotg->fifo_mem = hsotg->hw_params.total_fifo_size;
3580 hsotg->dedicated_fifos = hsotg->hw_params.en_multiple_tx_fifo;
3582 dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3584 hsotg->dedicated_fifos ? "dedicated" : "shared",
3590 * dwc2_hsotg_dump - dump state of the udc
3591 * @param: The device state
3593 static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg)
3596 struct device *dev = hsotg->dev;
3597 void __iomem *regs = hsotg->regs;
3601 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3602 dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL),
3603 dwc2_readl(regs + DIEPMSK));
3605 dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3606 dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1));
3608 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3609 dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ));
3611 /* show periodic fifo settings */
3613 for (idx = 1; idx < hsotg->num_of_eps; idx++) {
3614 val = dwc2_readl(regs + DPTXFSIZN(idx));
3615 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3616 val >> FIFOSIZE_DEPTH_SHIFT,
3617 val & FIFOSIZE_STARTADDR_MASK);
3620 for (idx = 0; idx < hsotg->num_of_eps; idx++) {
3622 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3623 dwc2_readl(regs + DIEPCTL(idx)),
3624 dwc2_readl(regs + DIEPTSIZ(idx)),
3625 dwc2_readl(regs + DIEPDMA(idx)));
3627 val = dwc2_readl(regs + DOEPCTL(idx));
3629 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3630 idx, dwc2_readl(regs + DOEPCTL(idx)),
3631 dwc2_readl(regs + DOEPTSIZ(idx)),
3632 dwc2_readl(regs + DOEPDMA(idx)));
3636 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3637 dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE));
3642 static void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg)
3644 struct device_node *np = hsotg->dev->of_node;
3648 /* Enable dma if requested in device tree */
3649 hsotg->g_using_dma = of_property_read_bool(np, "g-use-dma");
3652 * Register TX periodic fifo size per endpoint.
3653 * EP0 is excluded since it has no fifo configuration.
3655 if (!of_find_property(np, "g-tx-fifo-size", &len))
3660 /* Read tx fifo sizes other than ep0 */
3661 if (of_property_read_u32_array(np, "g-tx-fifo-size",
3662 &hsotg->g_tx_fifo_sz[1], len))
3668 /* Make remaining TX fifos unavailable */
3669 if (len < MAX_EPS_CHANNELS) {
3670 for (i = len; i < MAX_EPS_CHANNELS; i++)
3671 hsotg->g_tx_fifo_sz[i] = 0;
3675 /* Register RX fifo size */
3676 of_property_read_u32(np, "g-rx-fifo-size", &hsotg->g_rx_fifo_sz);
3678 /* Register NPTX fifo size */
3679 of_property_read_u32(np, "g-np-tx-fifo-size",
3680 &hsotg->g_np_g_tx_fifo_sz);
3683 static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg *hsotg) { }
3687 * dwc2_gadget_init - init function for gadget
3688 * @dwc2: The data structure for the DWC2 driver.
3689 * @irq: The IRQ number for the controller.
3691 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
3693 struct device *dev = hsotg->dev;
3697 u32 p_tx_fifo[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE;
3699 /* Initialize to legacy fifo configuration values */
3700 hsotg->g_rx_fifo_sz = 2048;
3701 hsotg->g_np_g_tx_fifo_sz = 1024;
3702 memcpy(&hsotg->g_tx_fifo_sz[1], p_tx_fifo, sizeof(p_tx_fifo));
3703 /* Device tree specific probe */
3704 dwc2_hsotg_of_probe(hsotg);
3706 /* Check against largest possible value. */
3707 if (hsotg->g_np_g_tx_fifo_sz >
3708 hsotg->hw_params.dev_nperio_tx_fifo_size) {
3709 dev_warn(dev, "Specified GNPTXFDEP=%d > %d\n",
3710 hsotg->g_np_g_tx_fifo_sz,
3711 hsotg->hw_params.dev_nperio_tx_fifo_size);
3712 hsotg->g_np_g_tx_fifo_sz =
3713 hsotg->hw_params.dev_nperio_tx_fifo_size;
3716 /* Dump fifo information */
3717 dev_dbg(dev, "NonPeriodic TXFIFO size: %d\n",
3718 hsotg->g_np_g_tx_fifo_sz);
3719 dev_dbg(dev, "RXFIFO size: %d\n", hsotg->g_rx_fifo_sz);
3720 for (i = 0; i < MAX_EPS_CHANNELS; i++)
3721 dev_dbg(dev, "Periodic TXFIFO%2d size: %d\n", i,
3722 hsotg->g_tx_fifo_sz[i]);
3724 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3725 hsotg->gadget.ops = &dwc2_hsotg_gadget_ops;
3726 hsotg->gadget.name = dev_name(dev);
3727 if (hsotg->dr_mode == USB_DR_MODE_OTG)
3728 hsotg->gadget.is_otg = 1;
3729 else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
3730 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3732 ret = dwc2_hsotg_hw_cfg(hsotg);
3734 dev_err(hsotg->dev, "Hardware configuration failed: %d\n", ret);
3738 hsotg->ctrl_buff = devm_kzalloc(hsotg->dev,
3739 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3740 if (!hsotg->ctrl_buff) {
3741 dev_err(dev, "failed to allocate ctrl request buff\n");
3745 hsotg->ep0_buff = devm_kzalloc(hsotg->dev,
3746 DWC2_CTRL_BUFF_SIZE, GFP_KERNEL);
3747 if (!hsotg->ep0_buff) {
3748 dev_err(dev, "failed to allocate ctrl reply buff\n");
3752 ret = devm_request_irq(hsotg->dev, irq, dwc2_hsotg_irq, IRQF_SHARED,
3753 dev_name(hsotg->dev), hsotg);
3755 dev_err(dev, "cannot claim IRQ for gadget\n");
3759 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3761 if (hsotg->num_of_eps == 0) {
3762 dev_err(dev, "wrong number of EPs (zero)\n");
3766 /* setup endpoint information */
3768 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3769 hsotg->gadget.ep0 = &hsotg->eps_out[0]->ep;
3771 /* allocate EP0 request */
3773 hsotg->ctrl_req = dwc2_hsotg_ep_alloc_request(&hsotg->eps_out[0]->ep,
3775 if (!hsotg->ctrl_req) {
3776 dev_err(dev, "failed to allocate ctrl req\n");
3780 /* initialise the endpoints now the core has been initialised */
3781 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++) {
3782 if (hsotg->eps_in[epnum])
3783 dwc2_hsotg_initep(hsotg, hsotg->eps_in[epnum],
3785 if (hsotg->eps_out[epnum])
3786 dwc2_hsotg_initep(hsotg, hsotg->eps_out[epnum],
3790 ret = usb_add_gadget_udc(dev, &hsotg->gadget);
3794 dwc2_hsotg_dump(hsotg);
3800 * dwc2_hsotg_remove - remove function for hsotg driver
3801 * @pdev: The platform information for the driver
3803 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg)
3805 usb_del_gadget_udc(&hsotg->gadget);
3810 int dwc2_hsotg_suspend(struct dwc2_hsotg *hsotg)
3812 unsigned long flags;
3814 if (hsotg->lx_state != DWC2_L0)
3817 if (hsotg->driver) {
3820 dev_info(hsotg->dev, "suspending usb gadget %s\n",
3821 hsotg->driver->driver.name);
3823 spin_lock_irqsave(&hsotg->lock, flags);
3825 dwc2_hsotg_core_disconnect(hsotg);
3826 dwc2_hsotg_disconnect(hsotg);
3827 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3828 spin_unlock_irqrestore(&hsotg->lock, flags);
3830 for (ep = 0; ep < hsotg->num_of_eps; ep++) {
3831 if (hsotg->eps_in[ep])
3832 dwc2_hsotg_ep_disable(&hsotg->eps_in[ep]->ep);
3833 if (hsotg->eps_out[ep])
3834 dwc2_hsotg_ep_disable(&hsotg->eps_out[ep]->ep);
3841 int dwc2_hsotg_resume(struct dwc2_hsotg *hsotg)
3843 unsigned long flags;
3845 if (hsotg->lx_state == DWC2_L2)
3848 if (hsotg->driver) {
3849 dev_info(hsotg->dev, "resuming usb gadget %s\n",
3850 hsotg->driver->driver.name);
3852 spin_lock_irqsave(&hsotg->lock, flags);
3853 dwc2_hsotg_core_init_disconnected(hsotg, false);
3855 dwc2_hsotg_core_connect(hsotg);
3856 spin_unlock_irqrestore(&hsotg->lock, flags);
3863 * dwc2_backup_device_registers() - Backup controller device registers.
3864 * When suspending usb bus, registers needs to be backuped
3865 * if controller power is disabled once suspended.
3867 * @hsotg: Programming view of the DWC_otg controller
3869 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
3871 struct dwc2_dregs_backup *dr;
3874 dev_dbg(hsotg->dev, "%s\n", __func__);
3876 /* Backup dev regs */
3877 dr = &hsotg->dr_backup;
3879 dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
3880 dr->dctl = dwc2_readl(hsotg->regs + DCTL);
3881 dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
3882 dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
3883 dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
3885 for (i = 0; i < hsotg->num_of_eps; i++) {
3887 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
3889 /* Ensure DATA PID is correctly configured */
3890 if (dr->diepctl[i] & DXEPCTL_DPID)
3891 dr->diepctl[i] |= DXEPCTL_SETD1PID;
3893 dr->diepctl[i] |= DXEPCTL_SETD0PID;
3895 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
3896 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
3898 /* Backup OUT EPs */
3899 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
3901 /* Ensure DATA PID is correctly configured */
3902 if (dr->doepctl[i] & DXEPCTL_DPID)
3903 dr->doepctl[i] |= DXEPCTL_SETD1PID;
3905 dr->doepctl[i] |= DXEPCTL_SETD0PID;
3907 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
3908 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
3915 * dwc2_restore_device_registers() - Restore controller device registers.
3916 * When resuming usb bus, device registers needs to be restored
3917 * if controller power were disabled.
3919 * @hsotg: Programming view of the DWC_otg controller
3921 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
3923 struct dwc2_dregs_backup *dr;
3927 dev_dbg(hsotg->dev, "%s\n", __func__);
3929 /* Restore dev regs */
3930 dr = &hsotg->dr_backup;
3932 dev_err(hsotg->dev, "%s: no device registers to restore\n",
3938 dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
3939 dwc2_writel(dr->dctl, hsotg->regs + DCTL);
3940 dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
3941 dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
3942 dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
3944 for (i = 0; i < hsotg->num_of_eps; i++) {
3945 /* Restore IN EPs */
3946 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
3947 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
3948 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
3950 /* Restore OUT EPs */
3951 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
3952 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
3953 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
3956 /* Set the Power-On Programming done bit */
3957 dctl = dwc2_readl(hsotg->regs + DCTL);
3958 dctl |= DCTL_PWRONPRGDONE;
3959 dwc2_writel(dctl, hsotg->regs + DCTL);