drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = &dwc->ep0_trb[dep->trb_enqueue];
  74
  75         if (chain)
  76                 dep->trb_enqueue++;
  77
  78         trb->bpl = lower_32_bits(buf_dma);
  79         trb->bph = upper_32_bits(buf_dma);
  80         trb->size = len;
  81         trb->ctrl = type;
  82
  83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  84                         | DWC3_TRB_CTRL_ISP_IMI);
  85
  86         if (chain)
  87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  88         else
  89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  90                                 | DWC3_TRB_CTRL_LST);
  91
  92         if (chain)
  93                 return 0;
  94
  95         memset(&params, 0, sizeof(params));
  96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  98
  99         trace_dwc3_prepare_trb(dep, trb);
 100
 101         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
 102         if (ret < 0) {
 103                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 104                                 dep->name);
 105                 return ret;
 106         }
 107
 108         dep->flags |= DWC3_EP_BUSY;
 109         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 110         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 111
 112         return 0;
 113 }
 114
 115 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 116                 struct dwc3_request *req)
 117 {
 118         struct dwc3             *dwc = dep->dwc;
 119
 120         req->request.actual     = 0;
 121         req->request.status     = -EINPROGRESS;
 122         req->epnum              = dep->number;
 123
 124         list_add_tail(&req->list, &dep->pending_list);
 125
 126         /*
 127          * Gadget driver might not be quick enough to queue a request
 128          * before we get a Transfer Not Ready event on this endpoint.
 129          *
 130          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 131          * flag is set, it's telling us that as soon as Gadget queues the
 132          * required request, we should kick the transfer here because the
 133          * IRQ we were waiting for is long gone.
 134          */
 135         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 136                 unsigned        direction;
 137
 138                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 139
 140                 if (dwc->ep0state != EP0_DATA_PHASE) {
 141                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 142                         return 0;
 143                 }
 144
 145                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 146
 147                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 148                                 DWC3_EP0_DIR_IN);
 149
 150                 return 0;
 151         }
 152
 153         /*
 154          * In case gadget driver asked us to delay the STATUS phase,
 155          * handle it here.
 156          */
 157         if (dwc->delayed_status) {
 158                 unsigned        direction;
 159
 160                 direction = !dwc->ep0_expect_in;
 161                 dwc->delayed_status = false;
 162                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 163
 164                 if (dwc->ep0state == EP0_STATUS_PHASE)
 165                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 166                 else
 167                         dwc3_trace(trace_dwc3_ep0,
 168                                         "too early for delayed status");
 169
 170                 return 0;
 171         }
 172
 173         /*
 174          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 175          *
 176          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 177          * come before issueing Start Transfer command, but if we do, we will
 178          * miss situations where the host starts another SETUP phase instead of
 179          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 180          * Layer Compliance Suite.
 181          *
 182          * The problem surfaces due to the fact that in case of back-to-back
 183          * SETUP packets there will be no XferNotReady(DATA) generated and we
 184          * will be stuck waiting for XferNotReady(DATA) forever.
 185          *
 186          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 187          * it tells us to start Data Phase right away. It also mentions that if
 188          * we receive a SETUP phase instead of the DATA phase, core will issue
 189          * XferComplete for the DATA phase, before actually initiating it in
 190          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 191          * can only be used to print some debugging logs, as the core expects
 192          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 193          * just so it completes right away, without transferring anything and,
 194          * only then, we can go back to the SETUP phase.
 195          *
 196          * Because of this scenario, SNPS decided to change the programming
 197          * model of control transfers and support on-demand transfers only for
 198          * the STATUS phase. To fix the issue we have now, we will always wait
 199          * for gadget driver to queue the DATA phase's struct usb_request, then
 200          * start it right away.
 201          *
 202          * If we're actually in a 2-stage transfer, we will wait for
 203          * XferNotReady(STATUS).
 204          */
 205         if (dwc->three_stage_setup) {
 206                 unsigned        direction;
 207
 208                 direction = dwc->ep0_expect_in;
 209                 dwc->ep0state = EP0_DATA_PHASE;
 210
 211                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 212
 213                 dep->flags &= ~DWC3_EP0_DIR_IN;
 214         }
 215
 216         return 0;
 217 }
 218
 219 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 220                 gfp_t gfp_flags)
 221 {
 222         struct dwc3_request             *req = to_dwc3_request(request);
 223         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 224         struct dwc3                     *dwc = dep->dwc;
 225
 226         unsigned long                   flags;
 227
 228         int                             ret;
 229
 230         spin_lock_irqsave(&dwc->lock, flags);
 231         if (!dep->endpoint.desc) {
 232                 dwc3_trace(trace_dwc3_ep0,
 233                                 "trying to queue request %p to disabled %s",
 234                                 request, dep->name);
 235                 ret = -ESHUTDOWN;
 236                 goto out;
 237         }
 238
 239         /* we share one TRB for ep0/1 */
 240         if (!list_empty(&dep->pending_list)) {
 241                 ret = -EBUSY;
 242                 goto out;
 243         }
 244
 245         dwc3_trace(trace_dwc3_ep0,
 246                         "queueing request %p to %s length %d state '%s'",
 247                         request, dep->name, request->length,
 248                         dwc3_ep0_state_string(dwc->ep0state));
 249
 250         ret = __dwc3_gadget_ep0_queue(dep, req);
 251
 252 out:
 253         spin_unlock_irqrestore(&dwc->lock, flags);
 254
 255         return ret;
 256 }
 257
 258 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 259 {
 260         struct dwc3_ep          *dep;
 261
 262         /* reinitialize physical ep1 */
 263         dep = dwc->eps[1];
 264         dep->flags = DWC3_EP_ENABLED;
 265
 266         /* stall is always issued on EP0 */
 267         dep = dwc->eps[0];
 268         __dwc3_gadget_ep_set_halt(dep, 1, false);
 269         dep->flags = DWC3_EP_ENABLED;
 270         dwc->delayed_status = false;
 271
 272         if (!list_empty(&dep->pending_list)) {
 273                 struct dwc3_request     *req;
 274
 275                 req = next_request(&dep->pending_list);
 276                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 277         }
 278
 279         dwc->ep0state = EP0_SETUP_PHASE;
 280         dwc3_ep0_out_start(dwc);
 281 }
 282
 283 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 284 {
 285         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 286         struct dwc3                     *dwc = dep->dwc;
 287
 288         dwc3_ep0_stall_and_restart(dwc);
 289
 290         return 0;
 291 }
 292
 293 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 294 {
 295         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 296         struct dwc3                     *dwc = dep->dwc;
 297         unsigned long                   flags;
 298         int                             ret;
 299
 300         spin_lock_irqsave(&dwc->lock, flags);
 301         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 302         spin_unlock_irqrestore(&dwc->lock, flags);
 303
 304         return ret;
 305 }
 306
 307 void dwc3_ep0_out_start(struct dwc3 *dwc)
 308 {
 309         int                             ret;
 310
 311         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 312                         DWC3_TRBCTL_CONTROL_SETUP, false);
 313         WARN_ON(ret < 0);
 314 }
 315
 316 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 317 {
 318         struct dwc3_ep          *dep;
 319         u32                     windex = le16_to_cpu(wIndex_le);
 320         u32                     epnum;
 321
 322         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 323         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 324                 epnum |= 1;
 325
 326         dep = dwc->eps[epnum];
 327         if (dep->flags & DWC3_EP_ENABLED)
 328                 return dep;
 329
 330         return NULL;
 331 }
 332
 333 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 334 {
 335 }
 336 /*
 337  * ch 9.4.5
 338  */
 339 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 340                 struct usb_ctrlrequest *ctrl)
 341 {
 342         struct dwc3_ep          *dep;
 343         u32                     recip;
 344         u32                     reg;
 345         u16                     usb_status = 0;
 346         __le16                  *response_pkt;
 347
 348         recip = ctrl->bRequestType & USB_RECIP_MASK;
 349         switch (recip) {
 350         case USB_RECIP_DEVICE:
 351                 /*
 352                  * LTM will be set once we know how to set this in HW.
 353                  */
 354                 usb_status |= dwc->gadget.is_selfpowered;
 355
 356                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 357                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 358                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 359                         if (reg & DWC3_DCTL_INITU1ENA)
 360                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 361                         if (reg & DWC3_DCTL_INITU2ENA)
 362                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 363                 }
 364
 365                 break;
 366
 367         case USB_RECIP_INTERFACE:
 368                 /*
 369                  * Function Remote Wake Capable D0
 370                  * Function Remote Wakeup       D1
 371                  */
 372                 break;
 373
 374         case USB_RECIP_ENDPOINT:
 375                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 376                 if (!dep)
 377                         return -EINVAL;
 378
 379                 if (dep->flags & DWC3_EP_STALL)
 380                         usb_status = 1 << USB_ENDPOINT_HALT;
 381                 break;
 382         default:
 383                 return -EINVAL;
 384         }
 385
 386         response_pkt = (__le16 *) dwc->setup_buf;
 387         *response_pkt = cpu_to_le16(usb_status);
 388
 389         dep = dwc->eps[0];
 390         dwc->ep0_usb_req.dep = dep;
 391         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 392         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 393         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 394
 395         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 396 }
 397
 398 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 399                 struct usb_ctrlrequest *ctrl, int set)
 400 {
 401         struct dwc3_ep          *dep;
 402         u32                     recip;
 403         u32                     wValue;
 404         u32                     wIndex;
 405         u32                     reg;
 406         int                     ret;
 407         enum usb_device_state   state;
 408
 409         wValue = le16_to_cpu(ctrl->wValue);
 410         wIndex = le16_to_cpu(ctrl->wIndex);
 411         recip = ctrl->bRequestType & USB_RECIP_MASK;
 412         state = dwc->gadget.state;
 413
 414         switch (recip) {
 415         case USB_RECIP_DEVICE:
 416
 417                 switch (wValue) {
 418                 case USB_DEVICE_REMOTE_WAKEUP:
 419                         break;
 420                 /*
 421                  * 9.4.1 says only only for SS, in AddressState only for
 422                  * default control pipe
 423                  */
 424                 case USB_DEVICE_U1_ENABLE:
 425                         if (state != USB_STATE_CONFIGURED)
 426                                 return -EINVAL;
 427                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 428                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 429                                 return -EINVAL;
 430
 431                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 432                         if (set)
 433                                 reg |= DWC3_DCTL_INITU1ENA;
 434                         else
 435                                 reg &= ~DWC3_DCTL_INITU1ENA;
 436                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 437                         break;
 438
 439                 case USB_DEVICE_U2_ENABLE:
 440                         if (state != USB_STATE_CONFIGURED)
 441                                 return -EINVAL;
 442                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 443                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 444                                 return -EINVAL;
 445
 446                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 447                         if (set)
 448                                 reg |= DWC3_DCTL_INITU2ENA;
 449                         else
 450                                 reg &= ~DWC3_DCTL_INITU2ENA;
 451                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 452                         break;
 453
 454                 case USB_DEVICE_LTM_ENABLE:
 455                         return -EINVAL;
 456
 457                 case USB_DEVICE_TEST_MODE:
 458                         if ((wIndex & 0xff) != 0)
 459                                 return -EINVAL;
 460                         if (!set)
 461                                 return -EINVAL;
 462
 463                         switch (wIndex >> 8) {
 464                         case TEST_J:
 465                         case TEST_K:
 466                         case TEST_SE0_NAK:
 467                         case TEST_PACKET:
 468                         case TEST_FORCE_EN:
 469                                 dwc->test_mode_nr = wIndex >> 8;
 470                                 dwc->test_mode = true;
 471                                 break;
 472                         default:
 473                                 return -EINVAL;
 474                         }
 475                         break;
 476                 default:
 477                         return -EINVAL;
 478                 }
 479                 break;
 480
 481         case USB_RECIP_INTERFACE:
 482                 switch (wValue) {
 483                 case USB_INTRF_FUNC_SUSPEND:
 484                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 485                                 /* XXX enable Low power suspend */
 486                                 ;
 487                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 488                                 /* XXX enable remote wakeup */
 489                                 ;
 490                         break;
 491                 default:
 492                         return -EINVAL;
 493                 }
 494                 break;
 495
 496         case USB_RECIP_ENDPOINT:
 497                 switch (wValue) {
 498                 case USB_ENDPOINT_HALT:
 499                         dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 500                         if (!dep)
 501                                 return -EINVAL;
 502                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 503                                 break;
 504                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 505                         if (ret)
 506                                 return -EINVAL;
 507                         break;
 508                 default:
 509                         return -EINVAL;
 510                 }
 511                 break;
 512
 513         default:
 514                 return -EINVAL;
 515         }
 516
 517         return 0;
 518 }
 519
 520 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 521 {
 522         enum usb_device_state state = dwc->gadget.state;
 523         u32 addr;
 524         u32 reg;
 525
 526         addr = le16_to_cpu(ctrl->wValue);
 527         if (addr > 127) {
 528                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 529                 return -EINVAL;
 530         }
 531
 532         if (state == USB_STATE_CONFIGURED) {
 533                 dwc3_trace(trace_dwc3_ep0,
 534                                 "trying to set address when configured");
 535                 return -EINVAL;
 536         }
 537
 538         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 539         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 540         reg |= DWC3_DCFG_DEVADDR(addr);
 541         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 542
 543         if (addr)
 544                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 545         else
 546                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 547
 548         return 0;
 549 }
 550
 551 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 552 {
 553         int ret;
 554
 555         spin_unlock(&dwc->lock);
 556         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 557         spin_lock(&dwc->lock);
 558         return ret;
 559 }
 560
 561 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 562 {
 563         enum usb_device_state state = dwc->gadget.state;
 564         u32 cfg;
 565         int ret;
 566         u32 reg;
 567
 568         cfg = le16_to_cpu(ctrl->wValue);
 569
 570         switch (state) {
 571         case USB_STATE_DEFAULT:
 572                 return -EINVAL;
 573
 574         case USB_STATE_ADDRESS:
 575                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 576                 /* if the cfg matches and the cfg is non zero */
 577                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 578
 579                         /*
 580                          * only change state if set_config has already
 581                          * been processed. If gadget driver returns
 582                          * USB_GADGET_DELAYED_STATUS, we will wait
 583                          * to change the state on the next usb_ep_queue()
 584                          */
 585                         if (ret == 0)
 586                                 usb_gadget_set_state(&dwc->gadget,
 587                                                 USB_STATE_CONFIGURED);
 588
 589                         /*
 590                          * Enable transition to U1/U2 state when
 591                          * nothing is pending from application.
 592                          */
 593                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 594                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 595                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 596                 }
 597                 break;
 598
 599         case USB_STATE_CONFIGURED:
 600                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 601                 if (!cfg && !ret)
 602                         usb_gadget_set_state(&dwc->gadget,
 603                                         USB_STATE_ADDRESS);
 604                 break;
 605         default:
 606                 ret = -EINVAL;
 607         }
 608         return ret;
 609 }
 610
 611 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 612 {
 613         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 614         struct dwc3     *dwc = dep->dwc;
 615
 616         u32             param = 0;
 617         u32             reg;
 618
 619         struct timing {
 620                 u8      u1sel;
 621                 u8      u1pel;
 622                 __le16  u2sel;
 623                 __le16  u2pel;
 624         } __packed timing;
 625
 626         int             ret;
 627
 628         memcpy(&timing, req->buf, sizeof(timing));
 629
 630         dwc->u1sel = timing.u1sel;
 631         dwc->u1pel = timing.u1pel;
 632         dwc->u2sel = le16_to_cpu(timing.u2sel);
 633         dwc->u2pel = le16_to_cpu(timing.u2pel);
 634
 635         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 636         if (reg & DWC3_DCTL_INITU2ENA)
 637                 param = dwc->u2pel;
 638         if (reg & DWC3_DCTL_INITU1ENA)
 639                 param = dwc->u1pel;
 640
 641         /*
 642          * According to Synopsys Databook, if parameter is
 643          * greater than 125, a value of zero should be
 644          * programmed in the register.
 645          */
 646         if (param > 125)
 647                 param = 0;
 648
 649         /* now that we have the time, issue DGCMD Set Sel */
 650         ret = dwc3_send_gadget_generic_command(dwc,
 651                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 652         WARN_ON(ret < 0);
 653 }
 654
 655 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 656 {
 657         struct dwc3_ep  *dep;
 658         enum usb_device_state state = dwc->gadget.state;
 659         u16             wLength;
 660         u16             wValue;
 661
 662         if (state == USB_STATE_DEFAULT)
 663                 return -EINVAL;
 664
 665         wValue = le16_to_cpu(ctrl->wValue);
 666         wLength = le16_to_cpu(ctrl->wLength);
 667
 668         if (wLength != 6) {
 669                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 670                                 wLength);
 671                 return -EINVAL;
 672         }
 673
 674         /*
 675          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 676          * queue a usb_request for 6 bytes.
 677          *
 678          * Remember, though, this controller can't handle non-wMaxPacketSize
 679          * aligned transfers on the OUT direction, so we queue a request for
 680          * wMaxPacketSize instead.
 681          */
 682         dep = dwc->eps[0];
 683         dwc->ep0_usb_req.dep = dep;
 684         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 685         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 686         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 687
 688         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 689 }
 690
 691 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 692 {
 693         u16             wLength;
 694         u16             wValue;
 695         u16             wIndex;
 696
 697         wValue = le16_to_cpu(ctrl->wValue);
 698         wLength = le16_to_cpu(ctrl->wLength);
 699         wIndex = le16_to_cpu(ctrl->wIndex);
 700
 701         if (wIndex || wLength)
 702                 return -EINVAL;
 703
 704         /*
 705          * REVISIT It's unclear from Databook what to do with this
 706          * value. For now, just cache it.
 707          */
 708         dwc->isoch_delay = wValue;
 709
 710         return 0;
 711 }
 712
 713 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 714 {
 715         int ret;
 716
 717         switch (ctrl->bRequest) {
 718         case USB_REQ_GET_STATUS:
 719                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 720                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 721                 break;
 722         case USB_REQ_CLEAR_FEATURE:
 723                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 724                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 725                 break;
 726         case USB_REQ_SET_FEATURE:
 727                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 728                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 729                 break;
 730         case USB_REQ_SET_ADDRESS:
 731                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 732                 ret = dwc3_ep0_set_address(dwc, ctrl);
 733                 break;
 734         case USB_REQ_SET_CONFIGURATION:
 735                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 736                 ret = dwc3_ep0_set_config(dwc, ctrl);
 737                 break;
 738         case USB_REQ_SET_SEL:
 739                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 740                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 741                 break;
 742         case USB_REQ_SET_ISOCH_DELAY:
 743                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 744                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 745                 break;
 746         default:
 747                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 748                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 749                 break;
 750         }
 751
 752         return ret;
 753 }
 754
 755 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 756                 const struct dwc3_event_depevt *event)
 757 {
 758         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 759         int ret = -EINVAL;
 760         u32 len;
 761
 762         if (!dwc->gadget_driver)
 763                 goto out;
 764
 765         trace_dwc3_ctrl_req(ctrl);
 766
 767         len = le16_to_cpu(ctrl->wLength);
 768         if (!len) {
 769                 dwc->three_stage_setup = false;
 770                 dwc->ep0_expect_in = false;
 771                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 772         } else {
 773                 dwc->three_stage_setup = true;
 774                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 775                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 776         }
 777
 778         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 779                 ret = dwc3_ep0_std_request(dwc, ctrl);
 780         else
 781                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 782
 783         if (ret == USB_GADGET_DELAYED_STATUS)
 784                 dwc->delayed_status = true;
 785
 786 out:
 787         if (ret < 0)
 788                 dwc3_ep0_stall_and_restart(dwc);
 789 }
 790
 791 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 792                 const struct dwc3_event_depevt *event)
 793 {
 794         struct dwc3_request     *r = NULL;
 795         struct usb_request      *ur;
 796         struct dwc3_trb         *trb;
 797         struct dwc3_ep          *ep0;
 798         unsigned                transfer_size = 0;
 799         unsigned                maxp;
 800         unsigned                remaining_ur_length;
 801         void                    *buf;
 802         u32                     transferred = 0;
 803         u32                     status;
 804         u32                     length;
 805         u8                      epnum;
 806
 807         epnum = event->endpoint_number;
 808         ep0 = dwc->eps[0];
 809
 810         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 811
 812         trb = dwc->ep0_trb;
 813
 814         trace_dwc3_complete_trb(ep0, trb);
 815
 816         r = next_request(&ep0->pending_list);
 817         if (!r)
 818                 return;
 819
 820         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 821         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 822                 dwc->setup_packet_pending = true;
 823
 824                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 825
 826                 if (r)
 827                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 828
 829                 return;
 830         }
 831
 832         ur = &r->request;
 833         buf = ur->buf;
 834         remaining_ur_length = ur->length;
 835
 836         length = trb->size & DWC3_TRB_SIZE_MASK;
 837
 838         maxp = ep0->endpoint.maxpacket;
 839
 840         if (dwc->ep0_bounced) {
 841                 /*
 842                  * Handle the first TRB before handling the bounce buffer if
 843                  * the request length is greater than the bounce buffer size
 844                  */
 845                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 846                         transfer_size = ALIGN(ur->length - maxp, maxp);
 847                         transferred = transfer_size - length;
 848                         buf = (u8 *)buf + transferred;
 849                         ur->actual += transferred;
 850                         remaining_ur_length -= transferred;
 851
 852                         trb++;
 853                         length = trb->size & DWC3_TRB_SIZE_MASK;
 854
 855                         ep0->trb_enqueue = 0;
 856                 }
 857
 858                 transfer_size = roundup((ur->length - transfer_size),
 859                                         maxp);
 860
 861                 transferred = min_t(u32, remaining_ur_length,
 862                                     transfer_size - length);
 863                 memcpy(buf, dwc->ep0_bounce, transferred);
 864         } else {
 865                 transferred = ur->length - length;
 866         }
 867
 868         ur->actual += transferred;
 869
 870         if ((epnum & 1) && ur->actual < ur->length) {
 871                 /* for some reason we did not get everything out */
 872
 873                 dwc3_ep0_stall_and_restart(dwc);
 874         } else {
 875                 dwc3_gadget_giveback(ep0, r, 0);
 876
 877                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 878                                 ur->length && ur->zero) {
 879                         int ret;
 880
 881                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 882
 883                         ret = dwc3_ep0_start_trans(dwc, epnum,
 884                                         dwc->ctrl_req_addr, 0,
 885                                         DWC3_TRBCTL_CONTROL_DATA, false);
 886                         WARN_ON(ret < 0);
 887                 }
 888         }
 889 }
 890
 891 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 892                 const struct dwc3_event_depevt *event)
 893 {
 894         struct dwc3_request     *r;
 895         struct dwc3_ep          *dep;
 896         struct dwc3_trb         *trb;
 897         u32                     status;
 898
 899         dep = dwc->eps[0];
 900         trb = dwc->ep0_trb;
 901
 902         trace_dwc3_complete_trb(dep, trb);
 903
 904         if (!list_empty(&dep->pending_list)) {
 905                 r = next_request(&dep->pending_list);
 906
 907                 dwc3_gadget_giveback(dep, r, 0);
 908         }
 909
 910         if (dwc->test_mode) {
 911                 int ret;
 912
 913                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 914                 if (ret < 0) {
 915                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 916                                         dwc->test_mode_nr);
 917                         dwc3_ep0_stall_and_restart(dwc);
 918                         return;
 919                 }
 920         }
 921
 922         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 923         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 924                 dwc->setup_packet_pending = true;
 925                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 926         }
 927
 928         dwc->ep0state = EP0_SETUP_PHASE;
 929         dwc3_ep0_out_start(dwc);
 930 }
 931
 932 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 933                         const struct dwc3_event_depevt *event)
 934 {
 935         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 936
 937         dep->flags &= ~DWC3_EP_BUSY;
 938         dep->resource_index = 0;
 939         dwc->setup_packet_pending = false;
 940
 941         switch (dwc->ep0state) {
 942         case EP0_SETUP_PHASE:
 943                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 944                 dwc3_ep0_inspect_setup(dwc, event);
 945                 break;
 946
 947         case EP0_DATA_PHASE:
 948                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 949                 dwc3_ep0_complete_data(dwc, event);
 950                 break;
 951
 952         case EP0_STATUS_PHASE:
 953                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 954                 dwc3_ep0_complete_status(dwc, event);
 955                 break;
 956         default:
 957                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 958         }
 959 }
 960
 961 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 962                 struct dwc3_ep *dep, struct dwc3_request *req)
 963 {
 964         int                     ret;
 965
 966         req->direction = !!dep->number;
 967
 968         if (req->request.length == 0) {
 969                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 970                                 dwc->ctrl_req_addr, 0,
 971                                 DWC3_TRBCTL_CONTROL_DATA, false);
 972         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 973                         && (dep->number == 0)) {
 974                 u32     transfer_size = 0;
 975                 u32     maxpacket;
 976
 977                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 978                                 dep->number);
 979                 if (ret) {
 980                         dwc3_trace(trace_dwc3_ep0, "failed to map request");
 981                         return;
 982                 }
 983
 984                 maxpacket = dep->endpoint.maxpacket;
 985
 986                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 987                         transfer_size = ALIGN(req->request.length - maxpacket,
 988                                               maxpacket);
 989                         ret = dwc3_ep0_start_trans(dwc, dep->number,
 990                                                    req->request.dma,
 991                                                    transfer_size,
 992                                                    DWC3_TRBCTL_CONTROL_DATA,
 993                                                    true);
 994                 }
 995
 996                 transfer_size = roundup((req->request.length - transfer_size),
 997                                         maxpacket);
 998
 999                 dwc->ep0_bounced = true;
1000
1001                 ret = dwc3_ep0_start_trans(dwc, dep->number,
1002                                 dwc->ep0_bounce_addr, transfer_size,
1003                                 DWC3_TRBCTL_CONTROL_DATA, false);
1004         } else {
1005                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1006                                 dep->number);
1007                 if (ret) {
1008                         dwc3_trace(trace_dwc3_ep0, "failed to map request");
1009                         return;
1010                 }
1011
1012                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1013                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1014                                 false);
1015         }
1016
1017         WARN_ON(ret < 0);
1018 }
1019
1020 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1021 {
1022         struct dwc3             *dwc = dep->dwc;
1023         u32                     type;
1024
1025         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1026                 : DWC3_TRBCTL_CONTROL_STATUS2;
1027
1028         return dwc3_ep0_start_trans(dwc, dep->number,
1029                         dwc->ctrl_req_addr, 0, type, false);
1030 }
1031
1032 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1033 {
1034         WARN_ON(dwc3_ep0_start_control_status(dep));
1035 }
1036
1037 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1038                 const struct dwc3_event_depevt *event)
1039 {
1040         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1041
1042         __dwc3_ep0_do_control_status(dwc, dep);
1043 }
1044
1045 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1046 {
1047         struct dwc3_gadget_ep_cmd_params params;
1048         u32                     cmd;
1049         int                     ret;
1050
1051         if (!dep->resource_index)
1052                 return;
1053
1054         cmd = DWC3_DEPCMD_ENDTRANSFER;
1055         cmd |= DWC3_DEPCMD_CMDIOC;
1056         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1057         memset(&params, 0, sizeof(params));
1058         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1059         WARN_ON_ONCE(ret);
1060         dep->resource_index = 0;
1061 }
1062
1063 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1064                 const struct dwc3_event_depevt *event)
1065 {
1066         switch (event->status) {
1067         case DEPEVT_STATUS_CONTROL_DATA:
1068                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1069
1070                 /*
1071                  * We already have a DATA transfer in the controller's cache,
1072                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1073                  * it's for the wrong direction.
1074                  *
1075                  * In that case, we must issue END_TRANSFER command to the Data
1076                  * Phase we already have started and issue SetStall on the
1077                  * control endpoint.
1078                  */
1079                 if (dwc->ep0_expect_in != event->endpoint_number) {
1080                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1081
1082                         dwc3_trace(trace_dwc3_ep0,
1083                                         "Wrong direction for Data phase");
1084                         dwc3_ep0_end_control_data(dwc, dep);
1085                         dwc3_ep0_stall_and_restart(dwc);
1086                         return;
1087                 }
1088
1089                 break;
1090
1091         case DEPEVT_STATUS_CONTROL_STATUS:
1092                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1093                         return;
1094
1095                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1096
1097                 dwc->ep0state = EP0_STATUS_PHASE;
1098
1099                 if (dwc->delayed_status) {
1100                         WARN_ON_ONCE(event->endpoint_number != 1);
1101                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1102                         return;
1103                 }
1104
1105                 dwc3_ep0_do_control_status(dwc, event);
1106         }
1107 }
1108
1109 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1110                 const struct dwc3_event_depevt *event)
1111 {
1112         dwc3_trace(trace_dwc3_ep0, "%s: state '%s'",
1113                         dwc3_ep_event_string(event),
1114                         dwc3_ep0_state_string(dwc->ep0state));
1115
1116         switch (event->endpoint_event) {
1117         case DWC3_DEPEVT_XFERCOMPLETE:
1118                 dwc3_ep0_xfer_complete(dwc, event);
1119                 break;
1120
1121         case DWC3_DEPEVT_XFERNOTREADY:
1122                 dwc3_ep0_xfernotready(dwc, event);
1123                 break;
1124
1125         case DWC3_DEPEVT_XFERINPROGRESS:
1126         case DWC3_DEPEVT_RXTXFIFOEVT:
1127         case DWC3_DEPEVT_STREAMEVT:
1128         case DWC3_DEPEVT_EPCMDCMPLT:
1129                 break;
1130         }
1131 }