drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = &dwc->ep0_trb[dep->free_slot];
  74
  75         if (chain)
  76                 dep->free_slot++;
  77
  78         trb->bpl = lower_32_bits(buf_dma);
  79         trb->bph = upper_32_bits(buf_dma);
  80         trb->size = len;
  81         trb->ctrl = type;
  82
  83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  84                         | DWC3_TRB_CTRL_ISP_IMI);
  85
  86         if (chain)
  87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  88         else
  89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  90                                 | DWC3_TRB_CTRL_LST);
  91
  92         if (chain)
  93                 return 0;
  94
  95         memset(&params, 0, sizeof(params));
  96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  98
  99         trace_dwc3_prepare_trb(dep, trb);
 100
 101         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
 102                         DWC3_DEPCMD_STARTTRANSFER, &params);
 103         if (ret < 0) {
 104                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 105                                 dep->name);
 106                 return ret;
 107         }
 108
 109         dep->flags |= DWC3_EP_BUSY;
 110         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
 111                         dep->number);
 112
 113         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 114
 115         return 0;
 116 }
 117
 118 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 119                 struct dwc3_request *req)
 120 {
 121         struct dwc3             *dwc = dep->dwc;
 122
 123         req->request.actual     = 0;
 124         req->request.status     = -EINPROGRESS;
 125         req->epnum              = dep->number;
 126
 127         list_add_tail(&req->list, &dep->request_list);
 128
 129         /*
 130          * Gadget driver might not be quick enough to queue a request
 131          * before we get a Transfer Not Ready event on this endpoint.
 132          *
 133          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 134          * flag is set, it's telling us that as soon as Gadget queues the
 135          * required request, we should kick the transfer here because the
 136          * IRQ we were waiting for is long gone.
 137          */
 138         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 139                 unsigned        direction;
 140
 141                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 142
 143                 if (dwc->ep0state != EP0_DATA_PHASE) {
 144                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 145                         return 0;
 146                 }
 147
 148                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 149
 150                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 151                                 DWC3_EP0_DIR_IN);
 152
 153                 return 0;
 154         }
 155
 156         /*
 157          * In case gadget driver asked us to delay the STATUS phase,
 158          * handle it here.
 159          */
 160         if (dwc->delayed_status) {
 161                 unsigned        direction;
 162
 163                 direction = !dwc->ep0_expect_in;
 164                 dwc->delayed_status = false;
 165                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 166
 167                 if (dwc->ep0state == EP0_STATUS_PHASE)
 168                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 169                 else
 170                         dwc3_trace(trace_dwc3_ep0,
 171                                         "too early for delayed status");
 172
 173                 return 0;
 174         }
 175
 176         /*
 177          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 178          *
 179          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 180          * come before issueing Start Transfer command, but if we do, we will
 181          * miss situations where the host starts another SETUP phase instead of
 182          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 183          * Layer Compliance Suite.
 184          *
 185          * The problem surfaces due to the fact that in case of back-to-back
 186          * SETUP packets there will be no XferNotReady(DATA) generated and we
 187          * will be stuck waiting for XferNotReady(DATA) forever.
 188          *
 189          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 190          * it tells us to start Data Phase right away. It also mentions that if
 191          * we receive a SETUP phase instead of the DATA phase, core will issue
 192          * XferComplete for the DATA phase, before actually initiating it in
 193          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 194          * can only be used to print some debugging logs, as the core expects
 195          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 196          * just so it completes right away, without transferring anything and,
 197          * only then, we can go back to the SETUP phase.
 198          *
 199          * Because of this scenario, SNPS decided to change the programming
 200          * model of control transfers and support on-demand transfers only for
 201          * the STATUS phase. To fix the issue we have now, we will always wait
 202          * for gadget driver to queue the DATA phase's struct usb_request, then
 203          * start it right away.
 204          *
 205          * If we're actually in a 2-stage transfer, we will wait for
 206          * XferNotReady(STATUS).
 207          */
 208         if (dwc->three_stage_setup) {
 209                 unsigned        direction;
 210
 211                 direction = dwc->ep0_expect_in;
 212                 dwc->ep0state = EP0_DATA_PHASE;
 213
 214                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 215
 216                 dep->flags &= ~DWC3_EP0_DIR_IN;
 217         }
 218
 219         return 0;
 220 }
 221
 222 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 223                 gfp_t gfp_flags)
 224 {
 225         struct dwc3_request             *req = to_dwc3_request(request);
 226         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 227         struct dwc3                     *dwc = dep->dwc;
 228
 229         unsigned long                   flags;
 230
 231         int                             ret;
 232
 233         spin_lock_irqsave(&dwc->lock, flags);
 234         if (!dep->endpoint.desc) {
 235                 dwc3_trace(trace_dwc3_ep0,
 236                                 "trying to queue request %p to disabled %s",
 237                                 request, dep->name);
 238                 ret = -ESHUTDOWN;
 239                 goto out;
 240         }
 241
 242         /* we share one TRB for ep0/1 */
 243         if (!list_empty(&dep->request_list)) {
 244                 ret = -EBUSY;
 245                 goto out;
 246         }
 247
 248         dwc3_trace(trace_dwc3_ep0,
 249                         "queueing request %p to %s length %d state '%s'",
 250                         request, dep->name, request->length,
 251                         dwc3_ep0_state_string(dwc->ep0state));
 252
 253         ret = __dwc3_gadget_ep0_queue(dep, req);
 254
 255 out:
 256         spin_unlock_irqrestore(&dwc->lock, flags);
 257
 258         return ret;
 259 }
 260
 261 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 262 {
 263         struct dwc3_ep          *dep;
 264
 265         /* reinitialize physical ep1 */
 266         dep = dwc->eps[1];
 267         dep->flags = DWC3_EP_ENABLED;
 268
 269         /* stall is always issued on EP0 */
 270         dep = dwc->eps[0];
 271         __dwc3_gadget_ep_set_halt(dep, 1, false);
 272         dep->flags = DWC3_EP_ENABLED;
 273         dwc->delayed_status = false;
 274
 275         if (!list_empty(&dep->request_list)) {
 276                 struct dwc3_request     *req;
 277
 278                 req = next_request(&dep->request_list);
 279                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 280         }
 281
 282         dwc->ep0state = EP0_SETUP_PHASE;
 283         dwc3_ep0_out_start(dwc);
 284 }
 285
 286 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 287 {
 288         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 289         struct dwc3                     *dwc = dep->dwc;
 290
 291         dwc3_ep0_stall_and_restart(dwc);
 292
 293         return 0;
 294 }
 295
 296 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 297 {
 298         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 299         struct dwc3                     *dwc = dep->dwc;
 300         unsigned long                   flags;
 301         int                             ret;
 302
 303         spin_lock_irqsave(&dwc->lock, flags);
 304         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 305         spin_unlock_irqrestore(&dwc->lock, flags);
 306
 307         return ret;
 308 }
 309
 310 void dwc3_ep0_out_start(struct dwc3 *dwc)
 311 {
 312         int                             ret;
 313
 314         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 315                         DWC3_TRBCTL_CONTROL_SETUP, false);
 316         WARN_ON(ret < 0);
 317 }
 318
 319 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 320 {
 321         struct dwc3_ep          *dep;
 322         u32                     windex = le16_to_cpu(wIndex_le);
 323         u32                     epnum;
 324
 325         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 326         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 327                 epnum |= 1;
 328
 329         dep = dwc->eps[epnum];
 330         if (dep->flags & DWC3_EP_ENABLED)
 331                 return dep;
 332
 333         return NULL;
 334 }
 335
 336 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 337 {
 338 }
 339 /*
 340  * ch 9.4.5
 341  */
 342 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 343                 struct usb_ctrlrequest *ctrl)
 344 {
 345         struct dwc3_ep          *dep;
 346         u32                     recip;
 347         u32                     reg;
 348         u16                     usb_status = 0;
 349         __le16                  *response_pkt;
 350
 351         recip = ctrl->bRequestType & USB_RECIP_MASK;
 352         switch (recip) {
 353         case USB_RECIP_DEVICE:
 354                 /*
 355                  * LTM will be set once we know how to set this in HW.
 356                  */
 357                 usb_status |= dwc->gadget.is_selfpowered;
 358
 359                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 360                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 361                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 362                         if (reg & DWC3_DCTL_INITU1ENA)
 363                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 364                         if (reg & DWC3_DCTL_INITU2ENA)
 365                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 366                 }
 367
 368                 break;
 369
 370         case USB_RECIP_INTERFACE:
 371                 /*
 372                  * Function Remote Wake Capable D0
 373                  * Function Remote Wakeup       D1
 374                  */
 375                 break;
 376
 377         case USB_RECIP_ENDPOINT:
 378                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 379                 if (!dep)
 380                         return -EINVAL;
 381
 382                 if (dep->flags & DWC3_EP_STALL)
 383                         usb_status = 1 << USB_ENDPOINT_HALT;
 384                 break;
 385         default:
 386                 return -EINVAL;
 387         }
 388
 389         response_pkt = (__le16 *) dwc->setup_buf;
 390         *response_pkt = cpu_to_le16(usb_status);
 391
 392         dep = dwc->eps[0];
 393         dwc->ep0_usb_req.dep = dep;
 394         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 395         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 396         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 397
 398         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 399 }
 400
 401 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 402                 struct usb_ctrlrequest *ctrl, int set)
 403 {
 404         struct dwc3_ep          *dep;
 405         u32                     recip;
 406         u32                     wValue;
 407         u32                     wIndex;
 408         u32                     reg;
 409         int                     ret;
 410         enum usb_device_state   state;
 411
 412         wValue = le16_to_cpu(ctrl->wValue);
 413         wIndex = le16_to_cpu(ctrl->wIndex);
 414         recip = ctrl->bRequestType & USB_RECIP_MASK;
 415         state = dwc->gadget.state;
 416
 417         switch (recip) {
 418         case USB_RECIP_DEVICE:
 419
 420                 switch (wValue) {
 421                 case USB_DEVICE_REMOTE_WAKEUP:
 422                         break;
 423                 /*
 424                  * 9.4.1 says only only for SS, in AddressState only for
 425                  * default control pipe
 426                  */
 427                 case USB_DEVICE_U1_ENABLE:
 428                         if (state != USB_STATE_CONFIGURED)
 429                                 return -EINVAL;
 430                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 431                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 432                                 return -EINVAL;
 433
 434                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 435                         if (set)
 436                                 reg |= DWC3_DCTL_INITU1ENA;
 437                         else
 438                                 reg &= ~DWC3_DCTL_INITU1ENA;
 439                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 440                         break;
 441
 442                 case USB_DEVICE_U2_ENABLE:
 443                         if (state != USB_STATE_CONFIGURED)
 444                                 return -EINVAL;
 445                         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 446                             (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 447                                 return -EINVAL;
 448
 449                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 450                         if (set)
 451                                 reg |= DWC3_DCTL_INITU2ENA;
 452                         else
 453                                 reg &= ~DWC3_DCTL_INITU2ENA;
 454                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 455                         break;
 456
 457                 case USB_DEVICE_LTM_ENABLE:
 458                         return -EINVAL;
 459
 460                 case USB_DEVICE_TEST_MODE:
 461                         if ((wIndex & 0xff) != 0)
 462                                 return -EINVAL;
 463                         if (!set)
 464                                 return -EINVAL;
 465
 466                         dwc->test_mode_nr = wIndex >> 8;
 467                         dwc->test_mode = true;
 468                         break;
 469                 default:
 470                         return -EINVAL;
 471                 }
 472                 break;
 473
 474         case USB_RECIP_INTERFACE:
 475                 switch (wValue) {
 476                 case USB_INTRF_FUNC_SUSPEND:
 477                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 478                                 /* XXX enable Low power suspend */
 479                                 ;
 480                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 481                                 /* XXX enable remote wakeup */
 482                                 ;
 483                         break;
 484                 default:
 485                         return -EINVAL;
 486                 }
 487                 break;
 488
 489         case USB_RECIP_ENDPOINT:
 490                 switch (wValue) {
 491                 case USB_ENDPOINT_HALT:
 492                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 493                         if (!dep)
 494                                 return -EINVAL;
 495                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 496                                 break;
 497                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 498                         if (ret)
 499                                 return -EINVAL;
 500                         break;
 501                 default:
 502                         return -EINVAL;
 503                 }
 504                 break;
 505
 506         default:
 507                 return -EINVAL;
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 514 {
 515         enum usb_device_state state = dwc->gadget.state;
 516         u32 addr;
 517         u32 reg;
 518
 519         addr = le16_to_cpu(ctrl->wValue);
 520         if (addr > 127) {
 521                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 522                 return -EINVAL;
 523         }
 524
 525         if (state == USB_STATE_CONFIGURED) {
 526                 dwc3_trace(trace_dwc3_ep0,
 527                                 "trying to set address when configured");
 528                 return -EINVAL;
 529         }
 530
 531         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 532         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 533         reg |= DWC3_DCFG_DEVADDR(addr);
 534         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 535
 536         if (addr)
 537                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 538         else
 539                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 540
 541         return 0;
 542 }
 543
 544 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 545 {
 546         int ret;
 547
 548         spin_unlock(&dwc->lock);
 549         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 550         spin_lock(&dwc->lock);
 551         return ret;
 552 }
 553
 554 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 555 {
 556         enum usb_device_state state = dwc->gadget.state;
 557         u32 cfg;
 558         int ret;
 559         u32 reg;
 560
 561         cfg = le16_to_cpu(ctrl->wValue);
 562
 563         switch (state) {
 564         case USB_STATE_DEFAULT:
 565                 return -EINVAL;
 566
 567         case USB_STATE_ADDRESS:
 568                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 569                 /* if the cfg matches and the cfg is non zero */
 570                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 571
 572                         /*
 573                          * only change state if set_config has already
 574                          * been processed. If gadget driver returns
 575                          * USB_GADGET_DELAYED_STATUS, we will wait
 576                          * to change the state on the next usb_ep_queue()
 577                          */
 578                         if (ret == 0)
 579                                 usb_gadget_set_state(&dwc->gadget,
 580                                                 USB_STATE_CONFIGURED);
 581
 582                         /*
 583                          * Enable transition to U1/U2 state when
 584                          * nothing is pending from application.
 585                          */
 586                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 587                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 588                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 589
 590                         dwc->resize_fifos = true;
 591                         dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
 592                 }
 593                 break;
 594
 595         case USB_STATE_CONFIGURED:
 596                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 597                 if (!cfg && !ret)
 598                         usb_gadget_set_state(&dwc->gadget,
 599                                         USB_STATE_ADDRESS);
 600                 break;
 601         default:
 602                 ret = -EINVAL;
 603         }
 604         return ret;
 605 }
 606
 607 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 608 {
 609         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 610         struct dwc3     *dwc = dep->dwc;
 611
 612         u32             param = 0;
 613         u32             reg;
 614
 615         struct timing {
 616                 u8      u1sel;
 617                 u8      u1pel;
 618                 u16     u2sel;
 619                 u16     u2pel;
 620         } __packed timing;
 621
 622         int             ret;
 623
 624         memcpy(&timing, req->buf, sizeof(timing));
 625
 626         dwc->u1sel = timing.u1sel;
 627         dwc->u1pel = timing.u1pel;
 628         dwc->u2sel = le16_to_cpu(timing.u2sel);
 629         dwc->u2pel = le16_to_cpu(timing.u2pel);
 630
 631         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 632         if (reg & DWC3_DCTL_INITU2ENA)
 633                 param = dwc->u2pel;
 634         if (reg & DWC3_DCTL_INITU1ENA)
 635                 param = dwc->u1pel;
 636
 637         /*
 638          * According to Synopsys Databook, if parameter is
 639          * greater than 125, a value of zero should be
 640          * programmed in the register.
 641          */
 642         if (param > 125)
 643                 param = 0;
 644
 645         /* now that we have the time, issue DGCMD Set Sel */
 646         ret = dwc3_send_gadget_generic_command(dwc,
 647                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 648         WARN_ON(ret < 0);
 649 }
 650
 651 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 652 {
 653         struct dwc3_ep  *dep;
 654         enum usb_device_state state = dwc->gadget.state;
 655         u16             wLength;
 656         u16             wValue;
 657
 658         if (state == USB_STATE_DEFAULT)
 659                 return -EINVAL;
 660
 661         wValue = le16_to_cpu(ctrl->wValue);
 662         wLength = le16_to_cpu(ctrl->wLength);
 663
 664         if (wLength != 6) {
 665                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 666                                 wLength);
 667                 return -EINVAL;
 668         }
 669
 670         /*
 671          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 672          * queue a usb_request for 6 bytes.
 673          *
 674          * Remember, though, this controller can't handle non-wMaxPacketSize
 675          * aligned transfers on the OUT direction, so we queue a request for
 676          * wMaxPacketSize instead.
 677          */
 678         dep = dwc->eps[0];
 679         dwc->ep0_usb_req.dep = dep;
 680         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 681         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 682         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 683
 684         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 685 }
 686
 687 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 688 {
 689         u16             wLength;
 690         u16             wValue;
 691         u16             wIndex;
 692
 693         wValue = le16_to_cpu(ctrl->wValue);
 694         wLength = le16_to_cpu(ctrl->wLength);
 695         wIndex = le16_to_cpu(ctrl->wIndex);
 696
 697         if (wIndex || wLength)
 698                 return -EINVAL;
 699
 700         /*
 701          * REVISIT It's unclear from Databook what to do with this
 702          * value. For now, just cache it.
 703          */
 704         dwc->isoch_delay = wValue;
 705
 706         return 0;
 707 }
 708
 709 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 710 {
 711         int ret;
 712
 713         switch (ctrl->bRequest) {
 714         case USB_REQ_GET_STATUS:
 715                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 716                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 717                 break;
 718         case USB_REQ_CLEAR_FEATURE:
 719                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 720                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 721                 break;
 722         case USB_REQ_SET_FEATURE:
 723                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 724                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 725                 break;
 726         case USB_REQ_SET_ADDRESS:
 727                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 728                 ret = dwc3_ep0_set_address(dwc, ctrl);
 729                 break;
 730         case USB_REQ_SET_CONFIGURATION:
 731                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 732                 ret = dwc3_ep0_set_config(dwc, ctrl);
 733                 break;
 734         case USB_REQ_SET_SEL:
 735                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 736                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 737                 break;
 738         case USB_REQ_SET_ISOCH_DELAY:
 739                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 740                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 741                 break;
 742         default:
 743                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 744                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 745                 break;
 746         }
 747
 748         return ret;
 749 }
 750
 751 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 752                 const struct dwc3_event_depevt *event)
 753 {
 754         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 755         int ret = -EINVAL;
 756         u32 len;
 757
 758         if (!dwc->gadget_driver)
 759                 goto out;
 760
 761         trace_dwc3_ctrl_req(ctrl);
 762
 763         len = le16_to_cpu(ctrl->wLength);
 764         if (!len) {
 765                 dwc->three_stage_setup = false;
 766                 dwc->ep0_expect_in = false;
 767                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 768         } else {
 769                 dwc->three_stage_setup = true;
 770                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 771                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 772         }
 773
 774         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 775                 ret = dwc3_ep0_std_request(dwc, ctrl);
 776         else
 777                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 778
 779         if (ret == USB_GADGET_DELAYED_STATUS)
 780                 dwc->delayed_status = true;
 781
 782 out:
 783         if (ret < 0)
 784                 dwc3_ep0_stall_and_restart(dwc);
 785 }
 786
 787 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 788                 const struct dwc3_event_depevt *event)
 789 {
 790         struct dwc3_request     *r = NULL;
 791         struct usb_request      *ur;
 792         struct dwc3_trb         *trb;
 793         struct dwc3_ep          *ep0;
 794         unsigned                transfer_size = 0;
 795         unsigned                maxp;
 796         unsigned                remaining_ur_length;
 797         void                    *buf;
 798         u32                     transferred = 0;
 799         u32                     status;
 800         u32                     length;
 801         u8                      epnum;
 802
 803         epnum = event->endpoint_number;
 804         ep0 = dwc->eps[0];
 805
 806         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 807
 808         trb = dwc->ep0_trb;
 809
 810         trace_dwc3_complete_trb(ep0, trb);
 811
 812         r = next_request(&ep0->request_list);
 813         if (!r)
 814                 return;
 815
 816         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 817         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 818                 dwc->setup_packet_pending = true;
 819
 820                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 821
 822                 if (r)
 823                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 824
 825                 return;
 826         }
 827
 828         ur = &r->request;
 829         buf = ur->buf;
 830         remaining_ur_length = ur->length;
 831
 832         length = trb->size & DWC3_TRB_SIZE_MASK;
 833
 834         maxp = ep0->endpoint.maxpacket;
 835
 836         if (dwc->ep0_bounced) {
 837                 /*
 838                  * Handle the first TRB before handling the bounce buffer if
 839                  * the request length is greater than the bounce buffer size
 840                  */
 841                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 842                         transfer_size = ALIGN(ur->length - maxp, maxp);
 843                         transferred = transfer_size - length;
 844                         buf = (u8 *)buf + transferred;
 845                         ur->actual += transferred;
 846                         remaining_ur_length -= transferred;
 847
 848                         trb++;
 849                         length = trb->size & DWC3_TRB_SIZE_MASK;
 850
 851                         ep0->free_slot = 0;
 852                 }
 853
 854                 transfer_size = roundup((ur->length - transfer_size),
 855                                         maxp);
 856
 857                 transferred = min_t(u32, remaining_ur_length,
 858                                     transfer_size - length);
 859                 memcpy(buf, dwc->ep0_bounce, transferred);
 860         } else {
 861                 transferred = ur->length - length;
 862         }
 863
 864         ur->actual += transferred;
 865
 866         if ((epnum & 1) && ur->actual < ur->length) {
 867                 /* for some reason we did not get everything out */
 868
 869                 dwc3_ep0_stall_and_restart(dwc);
 870         } else {
 871                 dwc3_gadget_giveback(ep0, r, 0);
 872
 873                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 874                                 ur->length && ur->zero) {
 875                         int ret;
 876
 877                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 878
 879                         ret = dwc3_ep0_start_trans(dwc, epnum,
 880                                         dwc->ctrl_req_addr, 0,
 881                                         DWC3_TRBCTL_CONTROL_DATA, false);
 882                         WARN_ON(ret < 0);
 883                 }
 884         }
 885 }
 886
 887 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 888                 const struct dwc3_event_depevt *event)
 889 {
 890         struct dwc3_request     *r;
 891         struct dwc3_ep          *dep;
 892         struct dwc3_trb         *trb;
 893         u32                     status;
 894
 895         dep = dwc->eps[0];
 896         trb = dwc->ep0_trb;
 897
 898         trace_dwc3_complete_trb(dep, trb);
 899
 900         if (!list_empty(&dep->request_list)) {
 901                 r = next_request(&dep->request_list);
 902
 903                 dwc3_gadget_giveback(dep, r, 0);
 904         }
 905
 906         if (dwc->test_mode) {
 907                 int ret;
 908
 909                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 910                 if (ret < 0) {
 911                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 912                                         dwc->test_mode_nr);
 913                         dwc3_ep0_stall_and_restart(dwc);
 914                         return;
 915                 }
 916         }
 917
 918         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 919         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 920                 dwc->setup_packet_pending = true;
 921                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 922         }
 923
 924         dwc->ep0state = EP0_SETUP_PHASE;
 925         dwc3_ep0_out_start(dwc);
 926 }
 927
 928 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 929                         const struct dwc3_event_depevt *event)
 930 {
 931         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 932
 933         dep->flags &= ~DWC3_EP_BUSY;
 934         dep->resource_index = 0;
 935         dwc->setup_packet_pending = false;
 936
 937         switch (dwc->ep0state) {
 938         case EP0_SETUP_PHASE:
 939                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 940                 dwc3_ep0_inspect_setup(dwc, event);
 941                 break;
 942
 943         case EP0_DATA_PHASE:
 944                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 945                 dwc3_ep0_complete_data(dwc, event);
 946                 break;
 947
 948         case EP0_STATUS_PHASE:
 949                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 950                 dwc3_ep0_complete_status(dwc, event);
 951                 break;
 952         default:
 953                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 954         }
 955 }
 956
 957 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 958                 struct dwc3_ep *dep, struct dwc3_request *req)
 959 {
 960         int                     ret;
 961
 962         req->direction = !!dep->number;
 963
 964         if (req->request.length == 0) {
 965                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 966                                 dwc->ctrl_req_addr, 0,
 967                                 DWC3_TRBCTL_CONTROL_DATA, false);
 968         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 969                         && (dep->number == 0)) {
 970                 u32     transfer_size = 0;
 971                 u32     maxpacket;
 972
 973                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 974                                 dep->number);
 975                 if (ret) {
 976                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
 977                         return;
 978                 }
 979
 980                 maxpacket = dep->endpoint.maxpacket;
 981
 982                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 983                         transfer_size = ALIGN(req->request.length - maxpacket,
 984                                               maxpacket);
 985                         ret = dwc3_ep0_start_trans(dwc, dep->number,
 986                                                    req->request.dma,
 987                                                    transfer_size,
 988                                                    DWC3_TRBCTL_CONTROL_DATA,
 989                                                    true);
 990                 }
 991
 992                 transfer_size = roundup((req->request.length - transfer_size),
 993                                         maxpacket);
 994
 995                 dwc->ep0_bounced = true;
 996
 997                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 998                                 dwc->ep0_bounce_addr, transfer_size,
 999                                 DWC3_TRBCTL_CONTROL_DATA, false);
1000         } else {
1001                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1002                                 dep->number);
1003                 if (ret) {
1004                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1005                         return;
1006                 }
1007
1008                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1009                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1010                                 false);
1011         }
1012
1013         WARN_ON(ret < 0);
1014 }
1015
1016 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1017 {
1018         struct dwc3             *dwc = dep->dwc;
1019         u32                     type;
1020
1021         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1022                 : DWC3_TRBCTL_CONTROL_STATUS2;
1023
1024         return dwc3_ep0_start_trans(dwc, dep->number,
1025                         dwc->ctrl_req_addr, 0, type, false);
1026 }
1027
1028 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1029 {
1030         if (dwc->resize_fifos) {
1031                 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
1032                 dwc3_gadget_resize_tx_fifos(dwc);
1033                 dwc->resize_fifos = 0;
1034         }
1035
1036         WARN_ON(dwc3_ep0_start_control_status(dep));
1037 }
1038
1039 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1040                 const struct dwc3_event_depevt *event)
1041 {
1042         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1043
1044         __dwc3_ep0_do_control_status(dwc, dep);
1045 }
1046
1047 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1048 {
1049         struct dwc3_gadget_ep_cmd_params params;
1050         u32                     cmd;
1051         int                     ret;
1052
1053         if (!dep->resource_index)
1054                 return;
1055
1056         cmd = DWC3_DEPCMD_ENDTRANSFER;
1057         cmd |= DWC3_DEPCMD_CMDIOC;
1058         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1059         memset(&params, 0, sizeof(params));
1060         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1061         WARN_ON_ONCE(ret);
1062         dep->resource_index = 0;
1063 }
1064
1065 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1066                 const struct dwc3_event_depevt *event)
1067 {
1068         switch (event->status) {
1069         case DEPEVT_STATUS_CONTROL_DATA:
1070                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1071
1072                 /*
1073                  * We already have a DATA transfer in the controller's cache,
1074                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1075                  * it's for the wrong direction.
1076                  *
1077                  * In that case, we must issue END_TRANSFER command to the Data
1078                  * Phase we already have started and issue SetStall on the
1079                  * control endpoint.
1080                  */
1081                 if (dwc->ep0_expect_in != event->endpoint_number) {
1082                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1083
1084                         dwc3_trace(trace_dwc3_ep0,
1085                                         "Wrong direction for Data phase");
1086                         dwc3_ep0_end_control_data(dwc, dep);
1087                         dwc3_ep0_stall_and_restart(dwc);
1088                         return;
1089                 }
1090
1091                 break;
1092
1093         case DEPEVT_STATUS_CONTROL_STATUS:
1094                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1095                         return;
1096
1097                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1098
1099                 dwc->ep0state = EP0_STATUS_PHASE;
1100
1101                 if (dwc->delayed_status) {
1102                         WARN_ON_ONCE(event->endpoint_number != 1);
1103                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1104                         return;
1105                 }
1106
1107                 dwc3_ep0_do_control_status(dwc, event);
1108         }
1109 }
1110
1111 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1112                 const struct dwc3_event_depevt *event)
1113 {
1114         u8                      epnum = event->endpoint_number;
1115
1116         dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1117                         dwc3_ep_event_string(event->endpoint_event),
1118                         epnum >> 1, (epnum & 1) ? "in" : "out",
1119                         dwc3_ep0_state_string(dwc->ep0state));
1120
1121         switch (event->endpoint_event) {
1122         case DWC3_DEPEVT_XFERCOMPLETE:
1123                 dwc3_ep0_xfer_complete(dwc, event);
1124                 break;
1125
1126         case DWC3_DEPEVT_XFERNOTREADY:
1127                 dwc3_ep0_xfernotready(dwc, event);
1128                 break;
1129
1130         case DWC3_DEPEVT_XFERINPROGRESS:
1131         case DWC3_DEPEVT_RXTXFIFOEVT:
1132         case DWC3_DEPEVT_STREAMEVT:
1133         case DWC3_DEPEVT_EPCMDCMPLT:
1134                 break;
1135         }
1136 }