drivers/usb/gadget/fsl_udc_core.c

   1 /*
   2  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
   3  * All rights reserved.
   4  *
   5  * Author: Li Yang <leoli@freescale.com>
   6  *         Jiang Bo <tanya.jiang@freescale.com>
   7  *
   8  * Description:
   9  * Freescale high-speed USB SOC DR module device controller driver.
  10  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  11  * The driver is previously named as mpc_udc.  Based on bare board
  12  * code from Dave Liu and Shlomi Gridish.
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under  the terms of  the GNU General  Public License as published by the
  16  * Free Software Foundation;  either version 2 of the  License, or (at your
  17  * option) any later version.
  18  */
  19
  20 #undef VERBOSE
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/ioport.h>
  25 #include <linux/types.h>
  26 #include <linux/errno.h>
  27 #include <linux/slab.h>
  28 #include <linux/init.h>
  29 #include <linux/list.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/proc_fs.h>
  32 #include <linux/mm.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include <linux/usb/ch9.h>
  36 #include <linux/usb/gadget.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/fsl_devices.h>
  41 #include <linux/dmapool.h>
  42 #include <linux/delay.h>
  43
  44 #include <asm/byteorder.h>
  45 #include <asm/io.h>
  46 #include <asm/unaligned.h>
  47 #include <asm/dma.h>
  48
  49 #include "fsl_usb2_udc.h"
  50
  51 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  52 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  53 #define DRIVER_VERSION  "Apr 20, 2007"
  54
  55 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  56
  57 static const char driver_name[] = "fsl-usb2-udc";
  58 static const char driver_desc[] = DRIVER_DESC;
  59
  60 static struct usb_dr_device *dr_regs;
  61
  62 static struct usb_sys_interface *usb_sys_regs;
  63
  64 /* it is initialized in probe()  */
  65 static struct fsl_udc *udc_controller = NULL;
  66
  67 static const struct usb_endpoint_descriptor
  68 fsl_ep0_desc = {
  69         .bLength =              USB_DT_ENDPOINT_SIZE,
  70         .bDescriptorType =      USB_DT_ENDPOINT,
  71         .bEndpointAddress =     0,
  72         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  73         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  74 };
  75
  76 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  77
  78 #ifdef CONFIG_PPC32
  79 /*
  80  * On some SoCs, the USB controller registers can be big or little endian,
  81  * depending on the version of the chip. In order to be able to run the
  82  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  83  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  84  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  85  * call through those pointers. Platform code for SoCs that have BE USB
  86  * registers should set pdata->big_endian_mmio flag.
  87  *
  88  * This also applies to controller-to-cpu accessors for the USB descriptors,
  89  * since their endianness is also SoC dependant. Platform code for SoCs that
  90  * have BE USB descriptors should set pdata->big_endian_desc flag.
  91  */
  92 static u32 _fsl_readl_be(const unsigned __iomem *p)
  93 {
  94         return in_be32(p);
  95 }
  96
  97 static u32 _fsl_readl_le(const unsigned __iomem *p)
  98 {
  99         return in_le32(p);
 100 }
 101
 102 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 103 {
 104         out_be32(p, v);
 105 }
 106
 107 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 108 {
 109         out_le32(p, v);
 110 }
 111
 112 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 113 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 114
 115 #define fsl_readl(p)            (*_fsl_readl)((p))
 116 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 117
 118 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 119 {
 120         if (pdata->big_endian_mmio) {
 121                 _fsl_readl = _fsl_readl_be;
 122                 _fsl_writel = _fsl_writel_be;
 123         } else {
 124                 _fsl_readl = _fsl_readl_le;
 125                 _fsl_writel = _fsl_writel_le;
 126         }
 127 }
 128
 129 static inline u32 cpu_to_hc32(const u32 x)
 130 {
 131         return udc_controller->pdata->big_endian_desc
 132                 ? (__force u32)cpu_to_be32(x)
 133                 : (__force u32)cpu_to_le32(x);
 134 }
 135
 136 static inline u32 hc32_to_cpu(const u32 x)
 137 {
 138         return udc_controller->pdata->big_endian_desc
 139                 ? be32_to_cpu((__force __be32)x)
 140                 : le32_to_cpu((__force __le32)x);
 141 }
 142 #else /* !CONFIG_PPC32 */
 143 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 144
 145 #define fsl_readl(addr)         readl(addr)
 146 #define fsl_writel(val32, addr) writel(val32, addr)
 147 #define cpu_to_hc32(x)          cpu_to_le32(x)
 148 #define hc32_to_cpu(x)          le32_to_cpu(x)
 149 #endif /* CONFIG_PPC32 */
 150
 151 /********************************************************************
 152  *      Internal Used Function
 153 ********************************************************************/
 154 /*-----------------------------------------------------------------
 155  * done() - retire a request; caller blocked irqs
 156  * @status : request status to be set, only works when
 157  *      request is still in progress.
 158  *--------------------------------------------------------------*/
 159 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 160 {
 161         struct fsl_udc *udc = NULL;
 162         unsigned char stopped = ep->stopped;
 163         struct ep_td_struct *curr_td, *next_td;
 164         int j;
 165
 166         udc = (struct fsl_udc *)ep->udc;
 167         /* Removed the req from fsl_ep->queue */
 168         list_del_init(&req->queue);
 169
 170         /* req.status should be set as -EINPROGRESS in ep_queue() */
 171         if (req->req.status == -EINPROGRESS)
 172                 req->req.status = status;
 173         else
 174                 status = req->req.status;
 175
 176         /* Free dtd for the request */
 177         next_td = req->head;
 178         for (j = 0; j < req->dtd_count; j++) {
 179                 curr_td = next_td;
 180                 if (j != req->dtd_count - 1) {
 181                         next_td = curr_td->next_td_virt;
 182                 }
 183                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 184         }
 185
 186         if (req->mapped) {
 187                 dma_unmap_single(ep->udc->gadget.dev.parent,
 188                         req->req.dma, req->req.length,
 189                         ep_is_in(ep)
 190                                 ? DMA_TO_DEVICE
 191                                 : DMA_FROM_DEVICE);
 192                 req->req.dma = DMA_ADDR_INVALID;
 193                 req->mapped = 0;
 194         } else
 195                 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
 196                         req->req.dma, req->req.length,
 197                         ep_is_in(ep)
 198                                 ? DMA_TO_DEVICE
 199                                 : DMA_FROM_DEVICE);
 200
 201         if (status && (status != -ESHUTDOWN))
 202                 VDBG("complete %s req %p stat %d len %u/%u",
 203                         ep->ep.name, &req->req, status,
 204                         req->req.actual, req->req.length);
 205
 206         ep->stopped = 1;
 207
 208         spin_unlock(&ep->udc->lock);
 209         /* complete() is from gadget layer,
 210          * eg fsg->bulk_in_complete() */
 211         if (req->req.complete)
 212                 req->req.complete(&ep->ep, &req->req);
 213
 214         spin_lock(&ep->udc->lock);
 215         ep->stopped = stopped;
 216 }
 217
 218 /*-----------------------------------------------------------------
 219  * nuke(): delete all requests related to this ep
 220  * called with spinlock held
 221  *--------------------------------------------------------------*/
 222 static void nuke(struct fsl_ep *ep, int status)
 223 {
 224         ep->stopped = 1;
 225
 226         /* Flush fifo */
 227         fsl_ep_fifo_flush(&ep->ep);
 228
 229         /* Whether this eq has request linked */
 230         while (!list_empty(&ep->queue)) {
 231                 struct fsl_req *req = NULL;
 232
 233                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 234                 done(ep, req, status);
 235         }
 236 }
 237
 238 /*------------------------------------------------------------------
 239         Internal Hardware related function
 240  ------------------------------------------------------------------*/
 241
 242 static int dr_controller_setup(struct fsl_udc *udc)
 243 {
 244         unsigned int tmp, portctrl, ep_num;
 245         unsigned int max_no_of_ep;
 246         unsigned int ctrl;
 247         unsigned long timeout;
 248
 249 #define FSL_UDC_RESET_TIMEOUT 1000
 250
 251         /* Config PHY interface */
 252         portctrl = fsl_readl(&dr_regs->portsc1);
 253         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 254         switch (udc->phy_mode) {
 255         case FSL_USB2_PHY_ULPI:
 256                 if (udc->pdata->have_sysif_regs) {
 257                         if (udc->pdata->controller_ver) {
 258                                 /* controller version 1.6 or above */
 259                                 ctrl = __raw_readl(&usb_sys_regs->control);
 260                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
 261                                 ctrl |= USB_CTRL_USB_EN;
 262                                 __raw_writel(ctrl, &usb_sys_regs->control);
 263                         }
 264                 }
 265                 portctrl |= PORTSCX_PTS_ULPI;
 266                 break;
 267         case FSL_USB2_PHY_UTMI_WIDE:
 268                 portctrl |= PORTSCX_PTW_16BIT;
 269                 /* fall through */
 270         case FSL_USB2_PHY_UTMI:
 271                 if (udc->pdata->have_sysif_regs) {
 272                         if (udc->pdata->controller_ver) {
 273                                 /* controller version 1.6 or above */
 274                                 ctrl = __raw_readl(&usb_sys_regs->control);
 275                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
 276                                         USB_CTRL_USB_EN);
 277                                 __raw_writel(ctrl, &usb_sys_regs->control);
 278                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
 279                                         PHY CLK to become stable - 10ms*/
 280                         }
 281                 }
 282                 portctrl |= PORTSCX_PTS_UTMI;
 283                 break;
 284         case FSL_USB2_PHY_SERIAL:
 285                 portctrl |= PORTSCX_PTS_FSLS;
 286                 break;
 287         default:
 288                 return -EINVAL;
 289         }
 290         fsl_writel(portctrl, &dr_regs->portsc1);
 291
 292         /* Stop and reset the usb controller */
 293         tmp = fsl_readl(&dr_regs->usbcmd);
 294         tmp &= ~USB_CMD_RUN_STOP;
 295         fsl_writel(tmp, &dr_regs->usbcmd);
 296
 297         tmp = fsl_readl(&dr_regs->usbcmd);
 298         tmp |= USB_CMD_CTRL_RESET;
 299         fsl_writel(tmp, &dr_regs->usbcmd);
 300
 301         /* Wait for reset to complete */
 302         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 303         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 304                 if (time_after(jiffies, timeout)) {
 305                         ERR("udc reset timeout!\n");
 306                         return -ETIMEDOUT;
 307                 }
 308                 cpu_relax();
 309         }
 310
 311         /* Set the controller as device mode */
 312         tmp = fsl_readl(&dr_regs->usbmode);
 313         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 314         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 315         /* Disable Setup Lockout */
 316         tmp |= USB_MODE_SETUP_LOCK_OFF;
 317         if (udc->pdata->es)
 318                 tmp |= USB_MODE_ES;
 319         fsl_writel(tmp, &dr_regs->usbmode);
 320
 321         /* Clear the setup status */
 322         fsl_writel(0, &dr_regs->usbsts);
 323
 324         tmp = udc->ep_qh_dma;
 325         tmp &= USB_EP_LIST_ADDRESS_MASK;
 326         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 327
 328         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 329                 udc->ep_qh, (int)tmp,
 330                 fsl_readl(&dr_regs->endpointlistaddr));
 331
 332         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 333         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 334                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 335                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 336                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 337                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 338                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 339         }
 340         /* Config control enable i/o output, cpu endian register */
 341 #ifndef CONFIG_ARCH_MXC
 342         if (udc->pdata->have_sysif_regs) {
 343                 ctrl = __raw_readl(&usb_sys_regs->control);
 344                 ctrl |= USB_CTRL_IOENB;
 345                 __raw_writel(ctrl, &usb_sys_regs->control);
 346         }
 347 #endif
 348
 349 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 350         /* Turn on cache snooping hardware, since some PowerPC platforms
 351          * wholly rely on hardware to deal with cache coherent. */
 352
 353         if (udc->pdata->have_sysif_regs) {
 354                 /* Setup Snooping for all the 4GB space */
 355                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 356                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 357                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 358                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 359         }
 360 #endif
 361
 362         return 0;
 363 }
 364
 365 /* Enable DR irq and set controller to run state */
 366 static void dr_controller_run(struct fsl_udc *udc)
 367 {
 368         u32 temp;
 369
 370         /* Enable DR irq reg */
 371         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 372                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 373                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 374
 375         fsl_writel(temp, &dr_regs->usbintr);
 376
 377         /* Clear stopped bit */
 378         udc->stopped = 0;
 379
 380         /* Set the controller as device mode */
 381         temp = fsl_readl(&dr_regs->usbmode);
 382         temp |= USB_MODE_CTRL_MODE_DEVICE;
 383         fsl_writel(temp, &dr_regs->usbmode);
 384
 385         /* Set controller to Run */
 386         temp = fsl_readl(&dr_regs->usbcmd);
 387         temp |= USB_CMD_RUN_STOP;
 388         fsl_writel(temp, &dr_regs->usbcmd);
 389 }
 390
 391 static void dr_controller_stop(struct fsl_udc *udc)
 392 {
 393         unsigned int tmp;
 394
 395         pr_debug("%s\n", __func__);
 396
 397         /* if we're in OTG mode, and the Host is currently using the port,
 398          * stop now and don't rip the controller out from under the
 399          * ehci driver
 400          */
 401         if (udc->gadget.is_otg) {
 402                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 403                         pr_debug("udc: Leaving early\n");
 404                         return;
 405                 }
 406         }
 407
 408         /* disable all INTR */
 409         fsl_writel(0, &dr_regs->usbintr);
 410
 411         /* Set stopped bit for isr */
 412         udc->stopped = 1;
 413
 414         /* disable IO output */
 415 /*      usb_sys_regs->control = 0; */
 416
 417         /* set controller to Stop */
 418         tmp = fsl_readl(&dr_regs->usbcmd);
 419         tmp &= ~USB_CMD_RUN_STOP;
 420         fsl_writel(tmp, &dr_regs->usbcmd);
 421 }
 422
 423 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 424                         unsigned char ep_type)
 425 {
 426         unsigned int tmp_epctrl = 0;
 427
 428         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 429         if (dir) {
 430                 if (ep_num)
 431                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 432                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 433                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 434                 tmp_epctrl |= ((unsigned int)(ep_type)
 435                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 436         } else {
 437                 if (ep_num)
 438                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 439                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 440                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 441                 tmp_epctrl |= ((unsigned int)(ep_type)
 442                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 443         }
 444
 445         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 446 }
 447
 448 static void
 449 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 450 {
 451         u32 tmp_epctrl = 0;
 452
 453         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 454
 455         if (value) {
 456                 /* set the stall bit */
 457                 if (dir)
 458                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 459                 else
 460                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 461         } else {
 462                 /* clear the stall bit and reset data toggle */
 463                 if (dir) {
 464                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 465                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 466                 } else {
 467                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 468                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 469                 }
 470         }
 471         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 472 }
 473
 474 /* Get stall status of a specific ep
 475    Return: 0: not stalled; 1:stalled */
 476 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 477 {
 478         u32 epctrl;
 479
 480         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 481         if (dir)
 482                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 483         else
 484                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 485 }
 486
 487 /********************************************************************
 488         Internal Structure Build up functions
 489 ********************************************************************/
 490
 491 /*------------------------------------------------------------------
 492 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 493  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 494  * @mult: Mult field
 495  ------------------------------------------------------------------*/
 496 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 497                 unsigned char dir, unsigned char ep_type,
 498                 unsigned int max_pkt_len,
 499                 unsigned int zlt, unsigned char mult)
 500 {
 501         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 502         unsigned int tmp = 0;
 503
 504         /* set the Endpoint Capabilites in QH */
 505         switch (ep_type) {
 506         case USB_ENDPOINT_XFER_CONTROL:
 507                 /* Interrupt On Setup (IOS). for control ep  */
 508                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 509                         | EP_QUEUE_HEAD_IOS;
 510                 break;
 511         case USB_ENDPOINT_XFER_ISOC:
 512                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 513                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 514                 break;
 515         case USB_ENDPOINT_XFER_BULK:
 516         case USB_ENDPOINT_XFER_INT:
 517                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 518                 break;
 519         default:
 520                 VDBG("error ep type is %d", ep_type);
 521                 return;
 522         }
 523         if (zlt)
 524                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 525
 526         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 527         p_QH->next_dtd_ptr = 1;
 528         p_QH->size_ioc_int_sts = 0;
 529 }
 530
 531 /* Setup qh structure and ep register for ep0. */
 532 static void ep0_setup(struct fsl_udc *udc)
 533 {
 534         /* the intialization of an ep includes: fields in QH, Regs,
 535          * fsl_ep struct */
 536         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 537                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 538         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 539                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 540         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 541         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 542
 543         return;
 544
 545 }
 546
 547 /***********************************************************************
 548                 Endpoint Management Functions
 549 ***********************************************************************/
 550
 551 /*-------------------------------------------------------------------------
 552  * when configurations are set, or when interface settings change
 553  * for example the do_set_interface() in gadget layer,
 554  * the driver will enable or disable the relevant endpoints
 555  * ep0 doesn't use this routine. It is always enabled.
 556 -------------------------------------------------------------------------*/
 557 static int fsl_ep_enable(struct usb_ep *_ep,
 558                 const struct usb_endpoint_descriptor *desc)
 559 {
 560         struct fsl_udc *udc = NULL;
 561         struct fsl_ep *ep = NULL;
 562         unsigned short max = 0;
 563         unsigned char mult = 0, zlt;
 564         int retval = -EINVAL;
 565         unsigned long flags = 0;
 566
 567         ep = container_of(_ep, struct fsl_ep, ep);
 568
 569         /* catch various bogus parameters */
 570         if (!_ep || !desc || ep->ep.desc
 571                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 572                 return -EINVAL;
 573
 574         udc = ep->udc;
 575
 576         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 577                 return -ESHUTDOWN;
 578
 579         max = usb_endpoint_maxp(desc);
 580
 581         /* Disable automatic zlp generation.  Driver is responsible to indicate
 582          * explicitly through req->req.zero.  This is needed to enable multi-td
 583          * request. */
 584         zlt = 1;
 585
 586         /* Assume the max packet size from gadget is always correct */
 587         switch (desc->bmAttributes & 0x03) {
 588         case USB_ENDPOINT_XFER_CONTROL:
 589         case USB_ENDPOINT_XFER_BULK:
 590         case USB_ENDPOINT_XFER_INT:
 591                 /* mult = 0.  Execute N Transactions as demonstrated by
 592                  * the USB variable length packet protocol where N is
 593                  * computed using the Maximum Packet Length (dQH) and
 594                  * the Total Bytes field (dTD) */
 595                 mult = 0;
 596                 break;
 597         case USB_ENDPOINT_XFER_ISOC:
 598                 /* Calculate transactions needed for high bandwidth iso */
 599                 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
 600                 max = max & 0x7ff;      /* bit 0~10 */
 601                 /* 3 transactions at most */
 602                 if (mult > 3)
 603                         goto en_done;
 604                 break;
 605         default:
 606                 goto en_done;
 607         }
 608
 609         spin_lock_irqsave(&udc->lock, flags);
 610         ep->ep.maxpacket = max;
 611         ep->ep.desc = desc;
 612         ep->stopped = 0;
 613
 614         /* Controller related setup */
 615         /* Init EPx Queue Head (Ep Capabilites field in QH
 616          * according to max, zlt, mult) */
 617         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 618                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 619                                         ?  USB_SEND : USB_RECV),
 620                         (unsigned char) (desc->bmAttributes
 621                                         & USB_ENDPOINT_XFERTYPE_MASK),
 622                         max, zlt, mult);
 623
 624         /* Init endpoint ctrl register */
 625         dr_ep_setup((unsigned char) ep_index(ep),
 626                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 627                                         ? USB_SEND : USB_RECV),
 628                         (unsigned char) (desc->bmAttributes
 629                                         & USB_ENDPOINT_XFERTYPE_MASK));
 630
 631         spin_unlock_irqrestore(&udc->lock, flags);
 632         retval = 0;
 633
 634         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 635                         ep->ep.desc->bEndpointAddress & 0x0f,
 636                         (desc->bEndpointAddress & USB_DIR_IN)
 637                                 ? "in" : "out", max);
 638 en_done:
 639         return retval;
 640 }
 641
 642 /*---------------------------------------------------------------------
 643  * @ep : the ep being unconfigured. May not be ep0
 644  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 645 *---------------------------------------------------------------------*/
 646 static int fsl_ep_disable(struct usb_ep *_ep)
 647 {
 648         struct fsl_udc *udc = NULL;
 649         struct fsl_ep *ep = NULL;
 650         unsigned long flags = 0;
 651         u32 epctrl;
 652         int ep_num;
 653
 654         ep = container_of(_ep, struct fsl_ep, ep);
 655         if (!_ep || !ep->ep.desc) {
 656                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 657                 return -EINVAL;
 658         }
 659
 660         /* disable ep on controller */
 661         ep_num = ep_index(ep);
 662         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 663         if (ep_is_in(ep)) {
 664                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 665                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 666         } else {
 667                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 668                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 669         }
 670         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 671
 672         udc = (struct fsl_udc *)ep->udc;
 673         spin_lock_irqsave(&udc->lock, flags);
 674
 675         /* nuke all pending requests (does flush) */
 676         nuke(ep, -ESHUTDOWN);
 677
 678         ep->ep.desc = NULL;
 679         ep->stopped = 1;
 680         spin_unlock_irqrestore(&udc->lock, flags);
 681
 682         VDBG("disabled %s OK", _ep->name);
 683         return 0;
 684 }
 685
 686 /*---------------------------------------------------------------------
 687  * allocate a request object used by this endpoint
 688  * the main operation is to insert the req->queue to the eq->queue
 689  * Returns the request, or null if one could not be allocated
 690 *---------------------------------------------------------------------*/
 691 static struct usb_request *
 692 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 693 {
 694         struct fsl_req *req = NULL;
 695
 696         req = kzalloc(sizeof *req, gfp_flags);
 697         if (!req)
 698                 return NULL;
 699
 700         req->req.dma = DMA_ADDR_INVALID;
 701         INIT_LIST_HEAD(&req->queue);
 702
 703         return &req->req;
 704 }
 705
 706 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 707 {
 708         struct fsl_req *req = NULL;
 709
 710         req = container_of(_req, struct fsl_req, req);
 711
 712         if (_req)
 713                 kfree(req);
 714 }
 715
 716 /* Actually add a dTD chain to an empty dQH and let go */
 717 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 718 {
 719         struct ep_queue_head *qh = get_qh_by_ep(ep);
 720
 721         /* Write dQH next pointer and terminate bit to 0 */
 722         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 723                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 724
 725         /* Clear active and halt bit */
 726         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 727                                         | EP_QUEUE_HEAD_STATUS_HALT));
 728
 729         /* Ensure that updates to the QH will occur before priming. */
 730         wmb();
 731
 732         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 733         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 734                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 735 }
 736
 737 /* Add dTD chain to the dQH of an EP */
 738 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 739 {
 740         u32 temp, bitmask, tmp_stat;
 741
 742         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 743         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 744
 745         bitmask = ep_is_in(ep)
 746                 ? (1 << (ep_index(ep) + 16))
 747                 : (1 << (ep_index(ep)));
 748
 749         /* check if the pipe is empty */
 750         if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
 751                 /* Add td to the end */
 752                 struct fsl_req *lastreq;
 753                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 754                 lastreq->tail->next_td_ptr =
 755                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 756                 /* Ensure dTD's next dtd pointer to be updated */
 757                 wmb();
 758                 /* Read prime bit, if 1 goto done */
 759                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 760                         return;
 761
 762                 do {
 763                         /* Set ATDTW bit in USBCMD */
 764                         temp = fsl_readl(&dr_regs->usbcmd);
 765                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 766
 767                         /* Read correct status bit */
 768                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 769
 770                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 771
 772                 /* Write ATDTW bit to 0 */
 773                 temp = fsl_readl(&dr_regs->usbcmd);
 774                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 775
 776                 if (tmp_stat)
 777                         return;
 778         }
 779
 780         fsl_prime_ep(ep, req->head);
 781 }
 782
 783 /* Fill in the dTD structure
 784  * @req: request that the transfer belongs to
 785  * @length: return actually data length of the dTD
 786  * @dma: return dma address of the dTD
 787  * @is_last: return flag if it is the last dTD of the request
 788  * return: pointer to the built dTD */
 789 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 790                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 791 {
 792         u32 swap_temp;
 793         struct ep_td_struct *dtd;
 794
 795         /* how big will this transfer be? */
 796         *length = min(req->req.length - req->req.actual,
 797                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 798
 799         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 800         if (dtd == NULL)
 801                 return dtd;
 802
 803         dtd->td_dma = *dma;
 804         /* Clear reserved field */
 805         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 806         swap_temp &= ~DTD_RESERVED_FIELDS;
 807         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 808
 809         /* Init all of buffer page pointers */
 810         swap_temp = (u32) (req->req.dma + req->req.actual);
 811         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 812         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 813         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 814         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 815         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 816
 817         req->req.actual += *length;
 818
 819         /* zlp is needed if req->req.zero is set */
 820         if (req->req.zero) {
 821                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 822                         *is_last = 1;
 823                 else
 824                         *is_last = 0;
 825         } else if (req->req.length == req->req.actual)
 826                 *is_last = 1;
 827         else
 828                 *is_last = 0;
 829
 830         if ((*is_last) == 0)
 831                 VDBG("multi-dtd request!");
 832         /* Fill in the transfer size; set active bit */
 833         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 834
 835         /* Enable interrupt for the last dtd of a request */
 836         if (*is_last && !req->req.no_interrupt)
 837                 swap_temp |= DTD_IOC;
 838
 839         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 840
 841         mb();
 842
 843         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 844
 845         return dtd;
 846 }
 847
 848 /* Generate dtd chain for a request */
 849 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 850 {
 851         unsigned        count;
 852         int             is_last;
 853         int             is_first =1;
 854         struct ep_td_struct     *last_dtd = NULL, *dtd;
 855         dma_addr_t dma;
 856
 857         do {
 858                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 859                 if (dtd == NULL)
 860                         return -ENOMEM;
 861
 862                 if (is_first) {
 863                         is_first = 0;
 864                         req->head = dtd;
 865                 } else {
 866                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 867                         last_dtd->next_td_virt = dtd;
 868                 }
 869                 last_dtd = dtd;
 870
 871                 req->dtd_count++;
 872         } while (!is_last);
 873
 874         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 875
 876         req->tail = dtd;
 877
 878         return 0;
 879 }
 880
 881 /* queues (submits) an I/O request to an endpoint */
 882 static int
 883 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 884 {
 885         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 886         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 887         struct fsl_udc *udc;
 888         unsigned long flags;
 889
 890         /* catch various bogus parameters */
 891         if (!_req || !req->req.complete || !req->req.buf
 892                         || !list_empty(&req->queue)) {
 893                 VDBG("%s, bad params", __func__);
 894                 return -EINVAL;
 895         }
 896         if (unlikely(!_ep || !ep->ep.desc)) {
 897                 VDBG("%s, bad ep", __func__);
 898                 return -EINVAL;
 899         }
 900         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
 901                 if (req->req.length > ep->ep.maxpacket)
 902                         return -EMSGSIZE;
 903         }
 904
 905         udc = ep->udc;
 906         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 907                 return -ESHUTDOWN;
 908
 909         req->ep = ep;
 910
 911         /* map virtual address to hardware */
 912         if (req->req.dma == DMA_ADDR_INVALID) {
 913                 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
 914                                         req->req.buf,
 915                                         req->req.length, ep_is_in(ep)
 916                                                 ? DMA_TO_DEVICE
 917                                                 : DMA_FROM_DEVICE);
 918                 req->mapped = 1;
 919         } else {
 920                 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
 921                                         req->req.dma, req->req.length,
 922                                         ep_is_in(ep)
 923                                                 ? DMA_TO_DEVICE
 924                                                 : DMA_FROM_DEVICE);
 925                 req->mapped = 0;
 926         }
 927
 928         req->req.status = -EINPROGRESS;
 929         req->req.actual = 0;
 930         req->dtd_count = 0;
 931
 932         /* build dtds and push them to device queue */
 933         if (!fsl_req_to_dtd(req, gfp_flags)) {
 934                 spin_lock_irqsave(&udc->lock, flags);
 935                 fsl_queue_td(ep, req);
 936         } else {
 937                 return -ENOMEM;
 938         }
 939
 940         /* irq handler advances the queue */
 941         if (req != NULL)
 942                 list_add_tail(&req->queue, &ep->queue);
 943         spin_unlock_irqrestore(&udc->lock, flags);
 944
 945         return 0;
 946 }
 947
 948 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 949 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 950 {
 951         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 952         struct fsl_req *req;
 953         unsigned long flags;
 954         int ep_num, stopped, ret = 0;
 955         u32 epctrl;
 956
 957         if (!_ep || !_req)
 958                 return -EINVAL;
 959
 960         spin_lock_irqsave(&ep->udc->lock, flags);
 961         stopped = ep->stopped;
 962
 963         /* Stop the ep before we deal with the queue */
 964         ep->stopped = 1;
 965         ep_num = ep_index(ep);
 966         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 967         if (ep_is_in(ep))
 968                 epctrl &= ~EPCTRL_TX_ENABLE;
 969         else
 970                 epctrl &= ~EPCTRL_RX_ENABLE;
 971         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 972
 973         /* make sure it's actually queued on this endpoint */
 974         list_for_each_entry(req, &ep->queue, queue) {
 975                 if (&req->req == _req)
 976                         break;
 977         }
 978         if (&req->req != _req) {
 979                 ret = -EINVAL;
 980                 goto out;
 981         }
 982
 983         /* The request is in progress, or completed but not dequeued */
 984         if (ep->queue.next == &req->queue) {
 985                 _req->status = -ECONNRESET;
 986                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 987
 988                 /* The request isn't the last request in this ep queue */
 989                 if (req->queue.next != &ep->queue) {
 990                         struct fsl_req *next_req;
 991
 992                         next_req = list_entry(req->queue.next, struct fsl_req,
 993                                         queue);
 994
 995                         /* prime with dTD of next request */
 996                         fsl_prime_ep(ep, next_req->head);
 997                 }
 998         /* The request hasn't been processed, patch up the TD chain */
 999         } else {
1000                 struct fsl_req *prev_req;
1001
1002                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
1003                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
1004         }
1005
1006         done(ep, req, -ECONNRESET);
1007
1008         /* Enable EP */
1009 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
1010         if (ep_is_in(ep))
1011                 epctrl |= EPCTRL_TX_ENABLE;
1012         else
1013                 epctrl |= EPCTRL_RX_ENABLE;
1014         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
1015         ep->stopped = stopped;
1016
1017         spin_unlock_irqrestore(&ep->udc->lock, flags);
1018         return ret;
1019 }
1020
1021 /*-------------------------------------------------------------------------*/
1022
1023 /*-----------------------------------------------------------------
1024  * modify the endpoint halt feature
1025  * @ep: the non-isochronous endpoint being stalled
1026  * @value: 1--set halt  0--clear halt
1027  * Returns zero, or a negative error code.
1028 *----------------------------------------------------------------*/
1029 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1030 {
1031         struct fsl_ep *ep = NULL;
1032         unsigned long flags = 0;
1033         int status = -EOPNOTSUPP;       /* operation not supported */
1034         unsigned char ep_dir = 0, ep_num = 0;
1035         struct fsl_udc *udc = NULL;
1036
1037         ep = container_of(_ep, struct fsl_ep, ep);
1038         udc = ep->udc;
1039         if (!_ep || !ep->ep.desc) {
1040                 status = -EINVAL;
1041                 goto out;
1042         }
1043
1044         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1045                 status = -EOPNOTSUPP;
1046                 goto out;
1047         }
1048
1049         /* Attempt to halt IN ep will fail if any transfer requests
1050          * are still queue */
1051         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1052                 status = -EAGAIN;
1053                 goto out;
1054         }
1055
1056         status = 0;
1057         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1058         ep_num = (unsigned char)(ep_index(ep));
1059         spin_lock_irqsave(&ep->udc->lock, flags);
1060         dr_ep_change_stall(ep_num, ep_dir, value);
1061         spin_unlock_irqrestore(&ep->udc->lock, flags);
1062
1063         if (ep_index(ep) == 0) {
1064                 udc->ep0_state = WAIT_FOR_SETUP;
1065                 udc->ep0_dir = 0;
1066         }
1067 out:
1068         VDBG(" %s %s halt stat %d", ep->ep.name,
1069                         value ?  "set" : "clear", status);
1070
1071         return status;
1072 }
1073
1074 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1075 {
1076         struct fsl_ep *ep;
1077         struct fsl_udc *udc;
1078         int size = 0;
1079         u32 bitmask;
1080         struct ep_queue_head *qh;
1081
1082         ep = container_of(_ep, struct fsl_ep, ep);
1083         if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
1084                 return -ENODEV;
1085
1086         udc = (struct fsl_udc *)ep->udc;
1087
1088         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1089                 return -ESHUTDOWN;
1090
1091         qh = get_qh_by_ep(ep);
1092
1093         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1094             (1 << (ep_index(ep)));
1095
1096         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1097                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1098                     >> DTD_LENGTH_BIT_POS;
1099
1100         pr_debug("%s %u\n", __func__, size);
1101         return size;
1102 }
1103
1104 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1105 {
1106         struct fsl_ep *ep;
1107         int ep_num, ep_dir;
1108         u32 bits;
1109         unsigned long timeout;
1110 #define FSL_UDC_FLUSH_TIMEOUT 1000
1111
1112         if (!_ep) {
1113                 return;
1114         } else {
1115                 ep = container_of(_ep, struct fsl_ep, ep);
1116                 if (!ep->ep.desc)
1117                         return;
1118         }
1119         ep_num = ep_index(ep);
1120         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1121
1122         if (ep_num == 0)
1123                 bits = (1 << 16) | 1;
1124         else if (ep_dir == USB_SEND)
1125                 bits = 1 << (16 + ep_num);
1126         else
1127                 bits = 1 << ep_num;
1128
1129         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1130         do {
1131                 fsl_writel(bits, &dr_regs->endptflush);
1132
1133                 /* Wait until flush complete */
1134                 while (fsl_readl(&dr_regs->endptflush)) {
1135                         if (time_after(jiffies, timeout)) {
1136                                 ERR("ep flush timeout\n");
1137                                 return;
1138                         }
1139                         cpu_relax();
1140                 }
1141                 /* See if we need to flush again */
1142         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1143 }
1144
1145 static struct usb_ep_ops fsl_ep_ops = {
1146         .enable = fsl_ep_enable,
1147         .disable = fsl_ep_disable,
1148
1149         .alloc_request = fsl_alloc_request,
1150         .free_request = fsl_free_request,
1151
1152         .queue = fsl_ep_queue,
1153         .dequeue = fsl_ep_dequeue,
1154
1155         .set_halt = fsl_ep_set_halt,
1156         .fifo_status = fsl_ep_fifo_status,
1157         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1158 };
1159
1160 /*-------------------------------------------------------------------------
1161                 Gadget Driver Layer Operations
1162 -------------------------------------------------------------------------*/
1163
1164 /*----------------------------------------------------------------------
1165  * Get the current frame number (from DR frame_index Reg )
1166  *----------------------------------------------------------------------*/
1167 static int fsl_get_frame(struct usb_gadget *gadget)
1168 {
1169         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1170 }
1171
1172 /*-----------------------------------------------------------------------
1173  * Tries to wake up the host connected to this gadget
1174  -----------------------------------------------------------------------*/
1175 static int fsl_wakeup(struct usb_gadget *gadget)
1176 {
1177         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1178         u32 portsc;
1179
1180         /* Remote wakeup feature not enabled by host */
1181         if (!udc->remote_wakeup)
1182                 return -ENOTSUPP;
1183
1184         portsc = fsl_readl(&dr_regs->portsc1);
1185         /* not suspended? */
1186         if (!(portsc & PORTSCX_PORT_SUSPEND))
1187                 return 0;
1188         /* trigger force resume */
1189         portsc |= PORTSCX_PORT_FORCE_RESUME;
1190         fsl_writel(portsc, &dr_regs->portsc1);
1191         return 0;
1192 }
1193
1194 static int can_pullup(struct fsl_udc *udc)
1195 {
1196         return udc->driver && udc->softconnect && udc->vbus_active;
1197 }
1198
1199 /* Notify controller that VBUS is powered, Called by whatever
1200    detects VBUS sessions */
1201 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1202 {
1203         struct fsl_udc  *udc;
1204         unsigned long   flags;
1205
1206         udc = container_of(gadget, struct fsl_udc, gadget);
1207         spin_lock_irqsave(&udc->lock, flags);
1208         VDBG("VBUS %s", is_active ? "on" : "off");
1209         udc->vbus_active = (is_active != 0);
1210         if (can_pullup(udc))
1211                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1212                                 &dr_regs->usbcmd);
1213         else
1214                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1215                                 &dr_regs->usbcmd);
1216         spin_unlock_irqrestore(&udc->lock, flags);
1217         return 0;
1218 }
1219
1220 /* constrain controller's VBUS power usage
1221  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1222  * reporting how much power the device may consume.  For example, this
1223  * could affect how quickly batteries are recharged.
1224  *
1225  * Returns zero on success, else negative errno.
1226  */
1227 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1228 {
1229         struct fsl_udc *udc;
1230
1231         udc = container_of(gadget, struct fsl_udc, gadget);
1232         if (udc->transceiver)
1233                 return usb_phy_set_power(udc->transceiver, mA);
1234         return -ENOTSUPP;
1235 }
1236
1237 /* Change Data+ pullup status
1238  * this func is used by usb_gadget_connect/disconnet
1239  */
1240 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1241 {
1242         struct fsl_udc *udc;
1243
1244         udc = container_of(gadget, struct fsl_udc, gadget);
1245         udc->softconnect = (is_on != 0);
1246         if (can_pullup(udc))
1247                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1248                                 &dr_regs->usbcmd);
1249         else
1250                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1251                                 &dr_regs->usbcmd);
1252
1253         return 0;
1254 }
1255
1256 static int fsl_start(struct usb_gadget_driver *driver,
1257                 int (*bind)(struct usb_gadget *));
1258 static int fsl_stop(struct usb_gadget_driver *driver);
1259 /* defined in gadget.h */
1260 static struct usb_gadget_ops fsl_gadget_ops = {
1261         .get_frame = fsl_get_frame,
1262         .wakeup = fsl_wakeup,
1263 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1264         .vbus_session = fsl_vbus_session,
1265         .vbus_draw = fsl_vbus_draw,
1266         .pullup = fsl_pullup,
1267         .start = fsl_start,
1268         .stop = fsl_stop,
1269 };
1270
1271 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1272    on new transaction */
1273 static void ep0stall(struct fsl_udc *udc)
1274 {
1275         u32 tmp;
1276
1277         /* must set tx and rx to stall at the same time */
1278         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1279         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1280         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1281         udc->ep0_state = WAIT_FOR_SETUP;
1282         udc->ep0_dir = 0;
1283 }
1284
1285 /* Prime a status phase for ep0 */
1286 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1287 {
1288         struct fsl_req *req = udc->status_req;
1289         struct fsl_ep *ep;
1290
1291         if (direction == EP_DIR_IN)
1292                 udc->ep0_dir = USB_DIR_IN;
1293         else
1294                 udc->ep0_dir = USB_DIR_OUT;
1295
1296         ep = &udc->eps[0];
1297         if (udc->ep0_state != DATA_STATE_XMIT)
1298                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1299
1300         req->ep = ep;
1301         req->req.length = 0;
1302         req->req.status = -EINPROGRESS;
1303         req->req.actual = 0;
1304         req->req.complete = NULL;
1305         req->dtd_count = 0;
1306
1307         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1308                         req->req.buf, req->req.length,
1309                         ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1310         req->mapped = 1;
1311
1312         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1313                 fsl_queue_td(ep, req);
1314         else
1315                 return -ENOMEM;
1316
1317         list_add_tail(&req->queue, &ep->queue);
1318
1319         return 0;
1320 }
1321
1322 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1323 {
1324         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1325
1326         if (ep->name)
1327                 nuke(ep, -ESHUTDOWN);
1328 }
1329
1330 /*
1331  * ch9 Set address
1332  */
1333 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1334 {
1335         /* Save the new address to device struct */
1336         udc->device_address = (u8) value;
1337         /* Update usb state */
1338         udc->usb_state = USB_STATE_ADDRESS;
1339         /* Status phase */
1340         if (ep0_prime_status(udc, EP_DIR_IN))
1341                 ep0stall(udc);
1342 }
1343
1344 /*
1345  * ch9 Get status
1346  */
1347 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1348                 u16 index, u16 length)
1349 {
1350         u16 tmp = 0;            /* Status, cpu endian */
1351         struct fsl_req *req;
1352         struct fsl_ep *ep;
1353
1354         ep = &udc->eps[0];
1355
1356         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1357                 /* Get device status */
1358                 tmp = 1 << USB_DEVICE_SELF_POWERED;
1359                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1360         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1361                 /* Get interface status */
1362                 /* We don't have interface information in udc driver */
1363                 tmp = 0;
1364         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1365                 /* Get endpoint status */
1366                 struct fsl_ep *target_ep;
1367
1368                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1369
1370                 /* stall if endpoint doesn't exist */
1371                 if (!target_ep->ep.desc)
1372                         goto stall;
1373                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1374                                 << USB_ENDPOINT_HALT;
1375         }
1376
1377         udc->ep0_dir = USB_DIR_IN;
1378         /* Borrow the per device status_req */
1379         req = udc->status_req;
1380         /* Fill in the reqest structure */
1381         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1382
1383         req->ep = ep;
1384         req->req.length = 2;
1385         req->req.status = -EINPROGRESS;
1386         req->req.actual = 0;
1387         req->req.complete = NULL;
1388         req->dtd_count = 0;
1389
1390         req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
1391                                 req->req.buf, req->req.length,
1392                                 ep_is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1393         req->mapped = 1;
1394
1395         /* prime the data phase */
1396         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1397                 fsl_queue_td(ep, req);
1398         else                    /* no mem */
1399                 goto stall;
1400
1401         list_add_tail(&req->queue, &ep->queue);
1402         udc->ep0_state = DATA_STATE_XMIT;
1403         if (ep0_prime_status(udc, EP_DIR_OUT))
1404                 ep0stall(udc);
1405
1406         return;
1407 stall:
1408         ep0stall(udc);
1409 }
1410
1411 static void setup_received_irq(struct fsl_udc *udc,
1412                 struct usb_ctrlrequest *setup)
1413 {
1414         u16 wValue = le16_to_cpu(setup->wValue);
1415         u16 wIndex = le16_to_cpu(setup->wIndex);
1416         u16 wLength = le16_to_cpu(setup->wLength);
1417
1418         udc_reset_ep_queue(udc, 0);
1419
1420         /* We process some stardard setup requests here */
1421         switch (setup->bRequest) {
1422         case USB_REQ_GET_STATUS:
1423                 /* Data+Status phase from udc */
1424                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1425                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1426                         break;
1427                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1428                 return;
1429
1430         case USB_REQ_SET_ADDRESS:
1431                 /* Status phase from udc */
1432                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1433                                                 | USB_RECIP_DEVICE))
1434                         break;
1435                 ch9setaddress(udc, wValue, wIndex, wLength);
1436                 return;
1437
1438         case USB_REQ_CLEAR_FEATURE:
1439         case USB_REQ_SET_FEATURE:
1440                 /* Status phase from udc */
1441         {
1442                 int rc = -EOPNOTSUPP;
1443                 u16 ptc = 0;
1444
1445                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1446                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1447                         int pipe = get_pipe_by_windex(wIndex);
1448                         struct fsl_ep *ep;
1449
1450                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1451                                 break;
1452                         ep = get_ep_by_pipe(udc, pipe);
1453
1454                         spin_unlock(&udc->lock);
1455                         rc = fsl_ep_set_halt(&ep->ep,
1456                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1457                                                 ? 1 : 0);
1458                         spin_lock(&udc->lock);
1459
1460                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1461                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1462                                 | USB_TYPE_STANDARD)) {
1463                         /* Note: The driver has not include OTG support yet.
1464                          * This will be set when OTG support is added */
1465                         if (wValue == USB_DEVICE_TEST_MODE)
1466                                 ptc = wIndex >> 8;
1467                         else if (gadget_is_otg(&udc->gadget)) {
1468                                 if (setup->bRequest ==
1469                                     USB_DEVICE_B_HNP_ENABLE)
1470                                         udc->gadget.b_hnp_enable = 1;
1471                                 else if (setup->bRequest ==
1472                                          USB_DEVICE_A_HNP_SUPPORT)
1473                                         udc->gadget.a_hnp_support = 1;
1474                                 else if (setup->bRequest ==
1475                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1476                                         udc->gadget.a_alt_hnp_support = 1;
1477                         }
1478                         rc = 0;
1479                 } else
1480                         break;
1481
1482                 if (rc == 0) {
1483                         if (ep0_prime_status(udc, EP_DIR_IN))
1484                                 ep0stall(udc);
1485                 }
1486                 if (ptc) {
1487                         u32 tmp;
1488
1489                         mdelay(10);
1490                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1491                         fsl_writel(tmp, &dr_regs->portsc1);
1492                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1493                 }
1494
1495                 return;
1496         }
1497
1498         default:
1499                 break;
1500         }
1501
1502         /* Requests handled by gadget */
1503         if (wLength) {
1504                 /* Data phase from gadget, status phase from udc */
1505                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1506                                 ?  USB_DIR_IN : USB_DIR_OUT;
1507                 spin_unlock(&udc->lock);
1508                 if (udc->driver->setup(&udc->gadget,
1509                                 &udc->local_setup_buff) < 0)
1510                         ep0stall(udc);
1511                 spin_lock(&udc->lock);
1512                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1513                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1514                 /*
1515                  * If the data stage is IN, send status prime immediately.
1516                  * See 2.0 Spec chapter 8.5.3.3 for detail.
1517                  */
1518                 if (udc->ep0_state == DATA_STATE_XMIT)
1519                         if (ep0_prime_status(udc, EP_DIR_OUT))
1520                                 ep0stall(udc);
1521
1522         } else {
1523                 /* No data phase, IN status from gadget */
1524                 udc->ep0_dir = USB_DIR_IN;
1525                 spin_unlock(&udc->lock);
1526                 if (udc->driver->setup(&udc->gadget,
1527                                 &udc->local_setup_buff) < 0)
1528                         ep0stall(udc);
1529                 spin_lock(&udc->lock);
1530                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1531         }
1532 }
1533
1534 /* Process request for Data or Status phase of ep0
1535  * prime status phase if needed */
1536 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1537                 struct fsl_req *req)
1538 {
1539         if (udc->usb_state == USB_STATE_ADDRESS) {
1540                 /* Set the new address */
1541                 u32 new_address = (u32) udc->device_address;
1542                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1543                                 &dr_regs->deviceaddr);
1544         }
1545
1546         done(ep0, req, 0);
1547
1548         switch (udc->ep0_state) {
1549         case DATA_STATE_XMIT:
1550                 /* already primed at setup_received_irq */
1551                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1552                 break;
1553         case DATA_STATE_RECV:
1554                 /* send status phase */
1555                 if (ep0_prime_status(udc, EP_DIR_IN))
1556                         ep0stall(udc);
1557                 break;
1558         case WAIT_FOR_OUT_STATUS:
1559                 udc->ep0_state = WAIT_FOR_SETUP;
1560                 break;
1561         case WAIT_FOR_SETUP:
1562                 ERR("Unexpect ep0 packets\n");
1563                 break;
1564         default:
1565                 ep0stall(udc);
1566                 break;
1567         }
1568 }
1569
1570 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1571  * being corrupted by another incoming setup packet */
1572 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1573 {
1574         u32 temp;
1575         struct ep_queue_head *qh;
1576         struct fsl_usb2_platform_data *pdata = udc->pdata;
1577
1578         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1579
1580         /* Clear bit in ENDPTSETUPSTAT */
1581         temp = fsl_readl(&dr_regs->endptsetupstat);
1582         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1583
1584         /* while a hazard exists when setup package arrives */
1585         do {
1586                 /* Set Setup Tripwire */
1587                 temp = fsl_readl(&dr_regs->usbcmd);
1588                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1589
1590                 /* Copy the setup packet to local buffer */
1591                 if (pdata->le_setup_buf) {
1592                         u32 *p = (u32 *)buffer_ptr;
1593                         u32 *s = (u32 *)qh->setup_buffer;
1594
1595                         /* Convert little endian setup buffer to CPU endian */
1596                         *p++ = le32_to_cpu(*s++);
1597                         *p = le32_to_cpu(*s);
1598                 } else {
1599                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1600                 }
1601         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1602
1603         /* Clear Setup Tripwire */
1604         temp = fsl_readl(&dr_regs->usbcmd);
1605         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1606 }
1607
1608 /* process-ep_req(): free the completed Tds for this req */
1609 static int process_ep_req(struct fsl_udc *udc, int pipe,
1610                 struct fsl_req *curr_req)
1611 {
1612         struct ep_td_struct *curr_td;
1613         int     td_complete, actual, remaining_length, j, tmp;
1614         int     status = 0;
1615         int     errors = 0;
1616         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1617         int direction = pipe % 2;
1618
1619         curr_td = curr_req->head;
1620         td_complete = 0;
1621         actual = curr_req->req.length;
1622
1623         for (j = 0; j < curr_req->dtd_count; j++) {
1624                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1625                                         & DTD_PACKET_SIZE)
1626                                 >> DTD_LENGTH_BIT_POS;
1627                 actual -= remaining_length;
1628
1629                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1630                 if (errors & DTD_ERROR_MASK) {
1631                         if (errors & DTD_STATUS_HALTED) {
1632                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1633                                 /* Clear the errors and Halt condition */
1634                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1635                                 tmp &= ~errors;
1636                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1637                                 status = -EPIPE;
1638                                 /* FIXME: continue with next queued TD? */
1639
1640                                 break;
1641                         }
1642                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1643                                 VDBG("Transfer overflow");
1644                                 status = -EPROTO;
1645                                 break;
1646                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1647                                 VDBG("ISO error");
1648                                 status = -EILSEQ;
1649                                 break;
1650                         } else
1651                                 ERR("Unknown error has occurred (0x%x)!\n",
1652                                         errors);
1653
1654                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1655                                 & DTD_STATUS_ACTIVE) {
1656                         VDBG("Request not complete");
1657                         status = REQ_UNCOMPLETE;
1658                         return status;
1659                 } else if (remaining_length) {
1660                         if (direction) {
1661                                 VDBG("Transmit dTD remaining length not zero");
1662                                 status = -EPROTO;
1663                                 break;
1664                         } else {
1665                                 td_complete++;
1666                                 break;
1667                         }
1668                 } else {
1669                         td_complete++;
1670                         VDBG("dTD transmitted successful");
1671                 }
1672
1673                 if (j != curr_req->dtd_count - 1)
1674                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1675         }
1676
1677         if (status)
1678                 return status;
1679
1680         curr_req->req.actual = actual;
1681
1682         return 0;
1683 }
1684
1685 /* Process a DTD completion interrupt */
1686 static void dtd_complete_irq(struct fsl_udc *udc)
1687 {
1688         u32 bit_pos;
1689         int i, ep_num, direction, bit_mask, status;
1690         struct fsl_ep *curr_ep;
1691         struct fsl_req *curr_req, *temp_req;
1692
1693         /* Clear the bits in the register */
1694         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1695         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1696
1697         if (!bit_pos)
1698                 return;
1699
1700         for (i = 0; i < udc->max_ep; i++) {
1701                 ep_num = i >> 1;
1702                 direction = i % 2;
1703
1704                 bit_mask = 1 << (ep_num + 16 * direction);
1705
1706                 if (!(bit_pos & bit_mask))
1707                         continue;
1708
1709                 curr_ep = get_ep_by_pipe(udc, i);
1710
1711                 /* If the ep is configured */
1712                 if (curr_ep->name == NULL) {
1713                         WARNING("Invalid EP?");
1714                         continue;
1715                 }
1716
1717                 /* process the req queue until an uncomplete request */
1718                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1719                                 queue) {
1720                         status = process_ep_req(udc, i, curr_req);
1721
1722                         VDBG("status of process_ep_req= %d, ep = %d",
1723                                         status, ep_num);
1724                         if (status == REQ_UNCOMPLETE)
1725                                 break;
1726                         /* write back status to req */
1727                         curr_req->req.status = status;
1728
1729                         if (ep_num == 0) {
1730                                 ep0_req_complete(udc, curr_ep, curr_req);
1731                                 break;
1732                         } else
1733                                 done(curr_ep, curr_req, status);
1734                 }
1735         }
1736 }
1737
1738 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1739 {
1740         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1741         case PORTSCX_PORT_SPEED_HIGH:
1742                 return USB_SPEED_HIGH;
1743         case PORTSCX_PORT_SPEED_FULL:
1744                 return USB_SPEED_FULL;
1745         case PORTSCX_PORT_SPEED_LOW:
1746                 return USB_SPEED_LOW;
1747         default:
1748                 return USB_SPEED_UNKNOWN;
1749         }
1750 }
1751
1752 /* Process a port change interrupt */
1753 static void port_change_irq(struct fsl_udc *udc)
1754 {
1755         if (udc->bus_reset)
1756                 udc->bus_reset = 0;
1757
1758         /* Bus resetting is finished */
1759         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1760                 /* Get the speed */
1761                 udc->gadget.speed =
1762                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1763
1764         /* Update USB state */
1765         if (!udc->resume_state)
1766                 udc->usb_state = USB_STATE_DEFAULT;
1767 }
1768
1769 /* Process suspend interrupt */
1770 static void suspend_irq(struct fsl_udc *udc)
1771 {
1772         udc->resume_state = udc->usb_state;
1773         udc->usb_state = USB_STATE_SUSPENDED;
1774
1775         /* report suspend to the driver, serial.c does not support this */
1776         if (udc->driver->suspend)
1777                 udc->driver->suspend(&udc->gadget);
1778 }
1779
1780 static void bus_resume(struct fsl_udc *udc)
1781 {
1782         udc->usb_state = udc->resume_state;
1783         udc->resume_state = 0;
1784
1785         /* report resume to the driver, serial.c does not support this */
1786         if (udc->driver->resume)
1787                 udc->driver->resume(&udc->gadget);
1788 }
1789
1790 /* Clear up all ep queues */
1791 static int reset_queues(struct fsl_udc *udc)
1792 {
1793         u8 pipe;
1794
1795         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1796                 udc_reset_ep_queue(udc, pipe);
1797
1798         /* report disconnect; the driver is already quiesced */
1799         spin_unlock(&udc->lock);
1800         udc->driver->disconnect(&udc->gadget);
1801         spin_lock(&udc->lock);
1802
1803         return 0;
1804 }
1805
1806 /* Process reset interrupt */
1807 static void reset_irq(struct fsl_udc *udc)
1808 {
1809         u32 temp;
1810         unsigned long timeout;
1811
1812         /* Clear the device address */
1813         temp = fsl_readl(&dr_regs->deviceaddr);
1814         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1815
1816         udc->device_address = 0;
1817
1818         /* Clear usb state */
1819         udc->resume_state = 0;
1820         udc->ep0_dir = 0;
1821         udc->ep0_state = WAIT_FOR_SETUP;
1822         udc->remote_wakeup = 0; /* default to 0 on reset */
1823         udc->gadget.b_hnp_enable = 0;
1824         udc->gadget.a_hnp_support = 0;
1825         udc->gadget.a_alt_hnp_support = 0;
1826
1827         /* Clear all the setup token semaphores */
1828         temp = fsl_readl(&dr_regs->endptsetupstat);
1829         fsl_writel(temp, &dr_regs->endptsetupstat);
1830
1831         /* Clear all the endpoint complete status bits */
1832         temp = fsl_readl(&dr_regs->endptcomplete);
1833         fsl_writel(temp, &dr_regs->endptcomplete);
1834
1835         timeout = jiffies + 100;
1836         while (fsl_readl(&dr_regs->endpointprime)) {
1837                 /* Wait until all endptprime bits cleared */
1838                 if (time_after(jiffies, timeout)) {
1839                         ERR("Timeout for reset\n");
1840                         break;
1841                 }
1842                 cpu_relax();
1843         }
1844
1845         /* Write 1s to the flush register */
1846         fsl_writel(0xffffffff, &dr_regs->endptflush);
1847
1848         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1849                 VDBG("Bus reset");
1850                 /* Bus is reseting */
1851                 udc->bus_reset = 1;
1852                 /* Reset all the queues, include XD, dTD, EP queue
1853                  * head and TR Queue */
1854                 reset_queues(udc);
1855                 udc->usb_state = USB_STATE_DEFAULT;
1856         } else {
1857                 VDBG("Controller reset");
1858                 /* initialize usb hw reg except for regs for EP, not
1859                  * touch usbintr reg */
1860                 dr_controller_setup(udc);
1861
1862                 /* Reset all internal used Queues */
1863                 reset_queues(udc);
1864
1865                 ep0_setup(udc);
1866
1867                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1868                 dr_controller_run(udc);
1869                 udc->usb_state = USB_STATE_ATTACHED;
1870         }
1871 }
1872
1873 /*
1874  * USB device controller interrupt handler
1875  */
1876 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1877 {
1878         struct fsl_udc *udc = _udc;
1879         u32 irq_src;
1880         irqreturn_t status = IRQ_NONE;
1881         unsigned long flags;
1882
1883         /* Disable ISR for OTG host mode */
1884         if (udc->stopped)
1885                 return IRQ_NONE;
1886         spin_lock_irqsave(&udc->lock, flags);
1887         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1888         /* Clear notification bits */
1889         fsl_writel(irq_src, &dr_regs->usbsts);
1890
1891         /* VDBG("irq_src [0x%8x]", irq_src); */
1892
1893         /* Need to resume? */
1894         if (udc->usb_state == USB_STATE_SUSPENDED)
1895                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1896                         bus_resume(udc);
1897
1898         /* USB Interrupt */
1899         if (irq_src & USB_STS_INT) {
1900                 VDBG("Packet int");
1901                 /* Setup package, we only support ep0 as control ep */
1902                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1903                         tripwire_handler(udc, 0,
1904                                         (u8 *) (&udc->local_setup_buff));
1905                         setup_received_irq(udc, &udc->local_setup_buff);
1906                         status = IRQ_HANDLED;
1907                 }
1908
1909                 /* completion of dtd */
1910                 if (fsl_readl(&dr_regs->endptcomplete)) {
1911                         dtd_complete_irq(udc);
1912                         status = IRQ_HANDLED;
1913                 }
1914         }
1915
1916         /* SOF (for ISO transfer) */
1917         if (irq_src & USB_STS_SOF) {
1918                 status = IRQ_HANDLED;
1919         }
1920
1921         /* Port Change */
1922         if (irq_src & USB_STS_PORT_CHANGE) {
1923                 port_change_irq(udc);
1924                 status = IRQ_HANDLED;
1925         }
1926
1927         /* Reset Received */
1928         if (irq_src & USB_STS_RESET) {
1929                 VDBG("reset int");
1930                 reset_irq(udc);
1931                 status = IRQ_HANDLED;
1932         }
1933
1934         /* Sleep Enable (Suspend) */
1935         if (irq_src & USB_STS_SUSPEND) {
1936                 suspend_irq(udc);
1937                 status = IRQ_HANDLED;
1938         }
1939
1940         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1941                 VDBG("Error IRQ %x", irq_src);
1942         }
1943
1944         spin_unlock_irqrestore(&udc->lock, flags);
1945         return status;
1946 }
1947
1948 /*----------------------------------------------------------------*
1949  * Hook to gadget drivers
1950  * Called by initialization code of gadget drivers
1951 *----------------------------------------------------------------*/
1952 static int fsl_start(struct usb_gadget_driver *driver,
1953                 int (*bind)(struct usb_gadget *))
1954 {
1955         int retval = -ENODEV;
1956         unsigned long flags = 0;
1957
1958         if (!udc_controller)
1959                 return -ENODEV;
1960
1961         if (!driver || driver->max_speed < USB_SPEED_FULL
1962                         || !bind || !driver->disconnect || !driver->setup)
1963                 return -EINVAL;
1964
1965         if (udc_controller->driver)
1966                 return -EBUSY;
1967
1968         /* lock is needed but whether should use this lock or another */
1969         spin_lock_irqsave(&udc_controller->lock, flags);
1970
1971         driver->driver.bus = NULL;
1972         /* hook up the driver */
1973         udc_controller->driver = driver;
1974         udc_controller->gadget.dev.driver = &driver->driver;
1975         spin_unlock_irqrestore(&udc_controller->lock, flags);
1976
1977         /* bind udc driver to gadget driver */
1978         retval = bind(&udc_controller->gadget);
1979         if (retval) {
1980                 VDBG("bind to %s --> %d", driver->driver.name, retval);
1981                 udc_controller->gadget.dev.driver = NULL;
1982                 udc_controller->driver = NULL;
1983                 goto out;
1984         }
1985
1986         if (udc_controller->transceiver) {
1987                 /* Suspend the controller until OTG enable it */
1988                 udc_controller->stopped = 1;
1989                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1990
1991                 /* connect to bus through transceiver */
1992                 if (udc_controller->transceiver) {
1993                         retval = otg_set_peripheral(
1994                                         udc_controller->transceiver->otg,
1995                                                     &udc_controller->gadget);
1996                         if (retval < 0) {
1997                                 ERR("can't bind to transceiver\n");
1998                                 driver->unbind(&udc_controller->gadget);
1999                                 udc_controller->gadget.dev.driver = 0;
2000                                 udc_controller->driver = 0;
2001                                 return retval;
2002                         }
2003                 }
2004         } else {
2005                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
2006                 dr_controller_run(udc_controller);
2007                 udc_controller->usb_state = USB_STATE_ATTACHED;
2008                 udc_controller->ep0_state = WAIT_FOR_SETUP;
2009                 udc_controller->ep0_dir = 0;
2010         }
2011         printk(KERN_INFO "%s: bind to driver %s\n",
2012                         udc_controller->gadget.name, driver->driver.name);
2013
2014 out:
2015         if (retval)
2016                 printk(KERN_WARNING "gadget driver register failed %d\n",
2017                        retval);
2018         return retval;
2019 }
2020
2021 /* Disconnect from gadget driver */
2022 static int fsl_stop(struct usb_gadget_driver *driver)
2023 {
2024         struct fsl_ep *loop_ep;
2025         unsigned long flags;
2026
2027         if (!udc_controller)
2028                 return -ENODEV;
2029
2030         if (!driver || driver != udc_controller->driver || !driver->unbind)
2031                 return -EINVAL;
2032
2033         if (udc_controller->transceiver)
2034                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
2035
2036         /* stop DR, disable intr */
2037         dr_controller_stop(udc_controller);
2038
2039         /* in fact, no needed */
2040         udc_controller->usb_state = USB_STATE_ATTACHED;
2041         udc_controller->ep0_state = WAIT_FOR_SETUP;
2042         udc_controller->ep0_dir = 0;
2043
2044         /* stand operation */
2045         spin_lock_irqsave(&udc_controller->lock, flags);
2046         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2047         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2048         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2049                         ep.ep_list)
2050                 nuke(loop_ep, -ESHUTDOWN);
2051         spin_unlock_irqrestore(&udc_controller->lock, flags);
2052
2053         /* report disconnect; the controller is already quiesced */
2054         driver->disconnect(&udc_controller->gadget);
2055
2056         /* unbind gadget and unhook driver. */
2057         driver->unbind(&udc_controller->gadget);
2058         udc_controller->gadget.dev.driver = NULL;
2059         udc_controller->driver = NULL;
2060
2061         printk(KERN_WARNING "unregistered gadget driver '%s'\n",
2062                driver->driver.name);
2063         return 0;
2064 }
2065
2066 /*-------------------------------------------------------------------------
2067                 PROC File System Support
2068 -------------------------------------------------------------------------*/
2069 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2070
2071 #include <linux/seq_file.h>
2072
2073 static const char proc_filename[] = "driver/fsl_usb2_udc";
2074
2075 static int fsl_proc_read(char *page, char **start, off_t off, int count,
2076                 int *eof, void *_dev)
2077 {
2078         char *buf = page;
2079         char *next = buf;
2080         unsigned size = count;
2081         unsigned long flags;
2082         int t, i;
2083         u32 tmp_reg;
2084         struct fsl_ep *ep = NULL;
2085         struct fsl_req *req;
2086
2087         struct fsl_udc *udc = udc_controller;
2088         if (off != 0)
2089                 return 0;
2090
2091         spin_lock_irqsave(&udc->lock, flags);
2092
2093         /* ------basic driver information ---- */
2094         t = scnprintf(next, size,
2095                         DRIVER_DESC "\n"
2096                         "%s version: %s\n"
2097                         "Gadget driver: %s\n\n",
2098                         driver_name, DRIVER_VERSION,
2099                         udc->driver ? udc->driver->driver.name : "(none)");
2100         size -= t;
2101         next += t;
2102
2103         /* ------ DR Registers ----- */
2104         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2105         t = scnprintf(next, size,
2106                         "USBCMD reg:\n"
2107                         "SetupTW: %d\n"
2108                         "Run/Stop: %s\n\n",
2109                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2110                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2111         size -= t;
2112         next += t;
2113
2114         tmp_reg = fsl_readl(&dr_regs->usbsts);
2115         t = scnprintf(next, size,
2116                         "USB Status Reg:\n"
2117                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2118                         "USB Error Interrupt: %s\n\n",
2119                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2120                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2121                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2122                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2123         size -= t;
2124         next += t;
2125
2126         tmp_reg = fsl_readl(&dr_regs->usbintr);
2127         t = scnprintf(next, size,
2128                         "USB Intrrupt Enable Reg:\n"
2129                         "Sleep Enable: %d SOF Received Enable: %d "
2130                         "Reset Enable: %d\n"
2131                         "System Error Enable: %d "
2132                         "Port Change Dectected Enable: %d\n"
2133                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2134                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2135                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2136                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2137                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2138                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2139                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2140                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2141         size -= t;
2142         next += t;
2143
2144         tmp_reg = fsl_readl(&dr_regs->frindex);
2145         t = scnprintf(next, size,
2146                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2147                         (tmp_reg & USB_FRINDEX_MASKS));
2148         size -= t;
2149         next += t;
2150
2151         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2152         t = scnprintf(next, size,
2153                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2154                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2155         size -= t;
2156         next += t;
2157
2158         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2159         t = scnprintf(next, size,
2160                         "USB Endpoint List Address Reg: "
2161                         "Device Addr is 0x%x\n\n",
2162                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2163         size -= t;
2164         next += t;
2165
2166         tmp_reg = fsl_readl(&dr_regs->portsc1);
2167         t = scnprintf(next, size,
2168                 "USB Port Status&Control Reg:\n"
2169                 "Port Transceiver Type : %s Port Speed: %s\n"
2170                 "PHY Low Power Suspend: %s Port Reset: %s "
2171                 "Port Suspend Mode: %s\n"
2172                 "Over-current Change: %s "
2173                 "Port Enable/Disable Change: %s\n"
2174                 "Port Enabled/Disabled: %s "
2175                 "Current Connect Status: %s\n\n", ( {
2176                         char *s;
2177                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2178                         case PORTSCX_PTS_UTMI:
2179                                 s = "UTMI"; break;
2180                         case PORTSCX_PTS_ULPI:
2181                                 s = "ULPI "; break;
2182                         case PORTSCX_PTS_FSLS:
2183                                 s = "FS/LS Serial"; break;
2184                         default:
2185                                 s = "None"; break;
2186                         }
2187                         s;} ),
2188                 usb_speed_string(portscx_device_speed(tmp_reg)),
2189                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2190                 "Normal PHY mode" : "Low power mode",
2191                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2192                 "Not in Reset",
2193                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2194                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2195                 "No",
2196                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2197                 "Not change",
2198                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2199                 "Not correct",
2200                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2201                 "Attached" : "Not-Att");
2202         size -= t;
2203         next += t;
2204
2205         tmp_reg = fsl_readl(&dr_regs->usbmode);
2206         t = scnprintf(next, size,
2207                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2208                                 char *s;
2209                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2210                                 case USB_MODE_CTRL_MODE_IDLE:
2211                                         s = "Idle"; break;
2212                                 case USB_MODE_CTRL_MODE_DEVICE:
2213                                         s = "Device Controller"; break;
2214                                 case USB_MODE_CTRL_MODE_HOST:
2215                                         s = "Host Controller"; break;
2216                                 default:
2217                                         s = "None"; break;
2218                                 }
2219                                 s;
2220                         } ));
2221         size -= t;
2222         next += t;
2223
2224         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2225         t = scnprintf(next, size,
2226                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2227                         (tmp_reg & EP_SETUP_STATUS_MASK));
2228         size -= t;
2229         next += t;
2230
2231         for (i = 0; i < udc->max_ep / 2; i++) {
2232                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2233                 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2234                                 i, tmp_reg);
2235                 size -= t;
2236                 next += t;
2237         }
2238         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2239         t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2240         size -= t;
2241         next += t;
2242
2243 #ifndef CONFIG_ARCH_MXC
2244         if (udc->pdata->have_sysif_regs) {
2245                 tmp_reg = usb_sys_regs->snoop1;
2246                 t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2247                 size -= t;
2248                 next += t;
2249
2250                 tmp_reg = usb_sys_regs->control;
2251                 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2252                                 tmp_reg);
2253                 size -= t;
2254                 next += t;
2255         }
2256 #endif
2257
2258         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2259         ep = &udc->eps[0];
2260         t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2261                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2262         size -= t;
2263         next += t;
2264
2265         if (list_empty(&ep->queue)) {
2266                 t = scnprintf(next, size, "its req queue is empty\n\n");
2267                 size -= t;
2268                 next += t;
2269         } else {
2270                 list_for_each_entry(req, &ep->queue, queue) {
2271                         t = scnprintf(next, size,
2272                                 "req %p actual 0x%x length 0x%x buf %p\n",
2273                                 &req->req, req->req.actual,
2274                                 req->req.length, req->req.buf);
2275                         size -= t;
2276                         next += t;
2277                 }
2278         }
2279         /* other gadget->eplist ep */
2280         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2281                 if (ep->ep.desc) {
2282                         t = scnprintf(next, size,
2283                                         "\nFor %s Maxpkt is 0x%x "
2284                                         "index is 0x%x\n",
2285                                         ep->ep.name, ep_maxpacket(ep),
2286                                         ep_index(ep));
2287                         size -= t;
2288                         next += t;
2289
2290                         if (list_empty(&ep->queue)) {
2291                                 t = scnprintf(next, size,
2292                                                 "its req queue is empty\n\n");
2293                                 size -= t;
2294                                 next += t;
2295                         } else {
2296                                 list_for_each_entry(req, &ep->queue, queue) {
2297                                         t = scnprintf(next, size,
2298                                                 "req %p actual 0x%x length "
2299                                                 "0x%x  buf %p\n",
2300                                                 &req->req, req->req.actual,
2301                                                 req->req.length, req->req.buf);
2302                                         size -= t;
2303                                         next += t;
2304                                         }       /* end for each_entry of ep req */
2305                                 }       /* end for else */
2306                         }       /* end for if(ep->queue) */
2307                 }               /* end (ep->desc) */
2308
2309         spin_unlock_irqrestore(&udc->lock, flags);
2310
2311         *eof = 1;
2312         return count - size;
2313 }
2314
2315 #define create_proc_file()      create_proc_read_entry(proc_filename, \
2316                                 0, NULL, fsl_proc_read, NULL)
2317
2318 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2319
2320 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2321
2322 #define create_proc_file()      do {} while (0)
2323 #define remove_proc_file()      do {} while (0)
2324
2325 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2326
2327 /*-------------------------------------------------------------------------*/
2328
2329 /* Release udc structures */
2330 static void fsl_udc_release(struct device *dev)
2331 {
2332         complete(udc_controller->done);
2333         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2334                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2335         kfree(udc_controller);
2336 }
2337
2338 /******************************************************************
2339         Internal structure setup functions
2340 *******************************************************************/
2341 /*------------------------------------------------------------------
2342  * init resource for globle controller
2343  * Return the udc handle on success or NULL on failure
2344  ------------------------------------------------------------------*/
2345 static int __init struct_udc_setup(struct fsl_udc *udc,
2346                 struct platform_device *pdev)
2347 {
2348         struct fsl_usb2_platform_data *pdata;
2349         size_t size;
2350
2351         pdata = pdev->dev.platform_data;
2352         udc->phy_mode = pdata->phy_mode;
2353
2354         udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2355         if (!udc->eps) {
2356                 ERR("malloc fsl_ep failed\n");
2357                 return -1;
2358         }
2359
2360         /* initialized QHs, take care of alignment */
2361         size = udc->max_ep * sizeof(struct ep_queue_head);
2362         if (size < QH_ALIGNMENT)
2363                 size = QH_ALIGNMENT;
2364         else if ((size % QH_ALIGNMENT) != 0) {
2365                 size += QH_ALIGNMENT + 1;
2366                 size &= ~(QH_ALIGNMENT - 1);
2367         }
2368         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2369                                         &udc->ep_qh_dma, GFP_KERNEL);
2370         if (!udc->ep_qh) {
2371                 ERR("malloc QHs for udc failed\n");
2372                 kfree(udc->eps);
2373                 return -1;
2374         }
2375
2376         udc->ep_qh_size = size;
2377
2378         /* Initialize ep0 status request structure */
2379         /* FIXME: fsl_alloc_request() ignores ep argument */
2380         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2381                         struct fsl_req, req);
2382         /* allocate a small amount of memory to get valid address */
2383         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2384
2385         udc->resume_state = USB_STATE_NOTATTACHED;
2386         udc->usb_state = USB_STATE_POWERED;
2387         udc->ep0_dir = 0;
2388         udc->remote_wakeup = 0; /* default to 0 on reset */
2389
2390         return 0;
2391 }
2392
2393 /*----------------------------------------------------------------
2394  * Setup the fsl_ep struct for eps
2395  * Link fsl_ep->ep to gadget->ep_list
2396  * ep0out is not used so do nothing here
2397  * ep0in should be taken care
2398  *--------------------------------------------------------------*/
2399 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2400                 char *name, int link)
2401 {
2402         struct fsl_ep *ep = &udc->eps[index];
2403
2404         ep->udc = udc;
2405         strcpy(ep->name, name);
2406         ep->ep.name = ep->name;
2407
2408         ep->ep.ops = &fsl_ep_ops;
2409         ep->stopped = 0;
2410
2411         /* for ep0: maxP defined in desc
2412          * for other eps, maxP is set by epautoconfig() called by gadget layer
2413          */
2414         ep->ep.maxpacket = (unsigned short) ~0;
2415
2416         /* the queue lists any req for this ep */
2417         INIT_LIST_HEAD(&ep->queue);
2418
2419         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2420         if (link)
2421                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2422         ep->gadget = &udc->gadget;
2423         ep->qh = &udc->ep_qh[index];
2424
2425         return 0;
2426 }
2427
2428 /* Driver probe function
2429  * all intialization operations implemented here except enabling usb_intr reg
2430  * board setup should have been done in the platform code
2431  */
2432 static int __init fsl_udc_probe(struct platform_device *pdev)
2433 {
2434         struct fsl_usb2_platform_data *pdata;
2435         struct resource *res;
2436         int ret = -ENODEV;
2437         unsigned int i;
2438         u32 dccparams;
2439
2440         if (strcmp(pdev->name, driver_name)) {
2441                 VDBG("Wrong device");
2442                 return -ENODEV;
2443         }
2444
2445         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2446         if (udc_controller == NULL) {
2447                 ERR("malloc udc failed\n");
2448                 return -ENOMEM;
2449         }
2450
2451         pdata = pdev->dev.platform_data;
2452         udc_controller->pdata = pdata;
2453         spin_lock_init(&udc_controller->lock);
2454         udc_controller->stopped = 1;
2455
2456 #ifdef CONFIG_USB_OTG
2457         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2458                 udc_controller->transceiver = usb_get_transceiver();
2459                 if (!udc_controller->transceiver) {
2460                         ERR("Can't find OTG driver!\n");
2461                         ret = -ENODEV;
2462                         goto err_kfree;
2463                 }
2464         }
2465 #endif
2466
2467         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2468         if (!res) {
2469                 ret = -ENXIO;
2470                 goto err_kfree;
2471         }
2472
2473         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2474                 if (!request_mem_region(res->start, resource_size(res),
2475                                         driver_name)) {
2476                         ERR("request mem region for %s failed\n", pdev->name);
2477                         ret = -EBUSY;
2478                         goto err_kfree;
2479                 }
2480         }
2481
2482         dr_regs = ioremap(res->start, resource_size(res));
2483         if (!dr_regs) {
2484                 ret = -ENOMEM;
2485                 goto err_release_mem_region;
2486         }
2487
2488         pdata->regs = (void *)dr_regs;
2489
2490         /*
2491          * do platform specific init: check the clock, grab/config pins, etc.
2492          */
2493         if (pdata->init && pdata->init(pdev)) {
2494                 ret = -ENODEV;
2495                 goto err_iounmap_noclk;
2496         }
2497
2498         /* Set accessors only after pdata->init() ! */
2499         fsl_set_accessors(pdata);
2500
2501 #ifndef CONFIG_ARCH_MXC
2502         if (pdata->have_sysif_regs)
2503                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2504 #endif
2505
2506         /* Initialize USB clocks */
2507         ret = fsl_udc_clk_init(pdev);
2508         if (ret < 0)
2509                 goto err_iounmap_noclk;
2510
2511         /* Read Device Controller Capability Parameters register */
2512         dccparams = fsl_readl(&dr_regs->dccparams);
2513         if (!(dccparams & DCCPARAMS_DC)) {
2514                 ERR("This SOC doesn't support device role\n");
2515                 ret = -ENODEV;
2516                 goto err_iounmap;
2517         }
2518         /* Get max device endpoints */
2519         /* DEN is bidirectional ep number, max_ep doubles the number */
2520         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2521
2522         udc_controller->irq = platform_get_irq(pdev, 0);
2523         if (!udc_controller->irq) {
2524                 ret = -ENODEV;
2525                 goto err_iounmap;
2526         }
2527
2528         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2529                         driver_name, udc_controller);
2530         if (ret != 0) {
2531                 ERR("cannot request irq %d err %d\n",
2532                                 udc_controller->irq, ret);
2533                 goto err_iounmap;
2534         }
2535
2536         /* Initialize the udc structure including QH member and other member */
2537         if (struct_udc_setup(udc_controller, pdev)) {
2538                 ERR("Can't initialize udc data structure\n");
2539                 ret = -ENOMEM;
2540                 goto err_free_irq;
2541         }
2542
2543         if (!udc_controller->transceiver) {
2544                 /* initialize usb hw reg except for regs for EP,
2545                  * leave usbintr reg untouched */
2546                 dr_controller_setup(udc_controller);
2547         }
2548
2549         fsl_udc_clk_finalize(pdev);
2550
2551         /* Setup gadget structure */
2552         udc_controller->gadget.ops = &fsl_gadget_ops;
2553         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2554         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2555         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2556         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2557         udc_controller->gadget.name = driver_name;
2558
2559         /* Setup gadget.dev and register with kernel */
2560         dev_set_name(&udc_controller->gadget.dev, "gadget");
2561         udc_controller->gadget.dev.release = fsl_udc_release;
2562         udc_controller->gadget.dev.parent = &pdev->dev;
2563         ret = device_register(&udc_controller->gadget.dev);
2564         if (ret < 0)
2565                 goto err_free_irq;
2566
2567         if (udc_controller->transceiver)
2568                 udc_controller->gadget.is_otg = 1;
2569
2570         /* setup QH and epctrl for ep0 */
2571         ep0_setup(udc_controller);
2572
2573         /* setup udc->eps[] for ep0 */
2574         struct_ep_setup(udc_controller, 0, "ep0", 0);
2575         /* for ep0: the desc defined here;
2576          * for other eps, gadget layer called ep_enable with defined desc
2577          */
2578         udc_controller->eps[0].desc = &fsl_ep0_desc;
2579         udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2580
2581         /* setup the udc->eps[] for non-control endpoints and link
2582          * to gadget.ep_list */
2583         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2584                 char name[14];
2585
2586                 sprintf(name, "ep%dout", i);
2587                 struct_ep_setup(udc_controller, i * 2, name, 1);
2588                 sprintf(name, "ep%din", i);
2589                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2590         }
2591
2592         /* use dma_pool for TD management */
2593         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2594                         sizeof(struct ep_td_struct),
2595                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2596         if (udc_controller->td_pool == NULL) {
2597                 ret = -ENOMEM;
2598                 goto err_unregister;
2599         }
2600
2601         ret = usb_add_gadget_udc(&pdev->dev, &udc_controller->gadget);
2602         if (ret)
2603                 goto err_del_udc;
2604
2605         create_proc_file();
2606         return 0;
2607
2608 err_del_udc:
2609         dma_pool_destroy(udc_controller->td_pool);
2610 err_unregister:
2611         device_unregister(&udc_controller->gadget.dev);
2612 err_free_irq:
2613         free_irq(udc_controller->irq, udc_controller);
2614 err_iounmap:
2615         if (pdata->exit)
2616                 pdata->exit(pdev);
2617         fsl_udc_clk_release();
2618 err_iounmap_noclk:
2619         iounmap(dr_regs);
2620 err_release_mem_region:
2621         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2622                 release_mem_region(res->start, resource_size(res));
2623 err_kfree:
2624         kfree(udc_controller);
2625         udc_controller = NULL;
2626         return ret;
2627 }
2628
2629 /* Driver removal function
2630  * Free resources and finish pending transactions
2631  */
2632 static int __exit fsl_udc_remove(struct platform_device *pdev)
2633 {
2634         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2635         struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
2636
2637         DECLARE_COMPLETION(done);
2638
2639         if (!udc_controller)
2640                 return -ENODEV;
2641
2642         usb_del_gadget_udc(&udc_controller->gadget);
2643         udc_controller->done = &done;
2644
2645         fsl_udc_clk_release();
2646
2647         /* DR has been stopped in usb_gadget_unregister_driver() */
2648         remove_proc_file();
2649
2650         /* Free allocated memory */
2651         kfree(udc_controller->status_req->req.buf);
2652         kfree(udc_controller->status_req);
2653         kfree(udc_controller->eps);
2654
2655         dma_pool_destroy(udc_controller->td_pool);
2656         free_irq(udc_controller->irq, udc_controller);
2657         iounmap(dr_regs);
2658         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2659                 release_mem_region(res->start, resource_size(res));
2660
2661         device_unregister(&udc_controller->gadget.dev);
2662         /* free udc --wait for the release() finished */
2663         wait_for_completion(&done);
2664
2665         /*
2666          * do platform specific un-initialization:
2667          * release iomux pins, etc.
2668          */
2669         if (pdata->exit)
2670                 pdata->exit(pdev);
2671
2672         return 0;
2673 }
2674
2675 /*-----------------------------------------------------------------
2676  * Modify Power management attributes
2677  * Used by OTG statemachine to disable gadget temporarily
2678  -----------------------------------------------------------------*/
2679 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2680 {
2681         dr_controller_stop(udc_controller);
2682         return 0;
2683 }
2684
2685 /*-----------------------------------------------------------------
2686  * Invoked on USB resume. May be called in_interrupt.
2687  * Here we start the DR controller and enable the irq
2688  *-----------------------------------------------------------------*/
2689 static int fsl_udc_resume(struct platform_device *pdev)
2690 {
2691         /* Enable DR irq reg and set controller Run */
2692         if (udc_controller->stopped) {
2693                 dr_controller_setup(udc_controller);
2694                 dr_controller_run(udc_controller);
2695         }
2696         udc_controller->usb_state = USB_STATE_ATTACHED;
2697         udc_controller->ep0_state = WAIT_FOR_SETUP;
2698         udc_controller->ep0_dir = 0;
2699         return 0;
2700 }
2701
2702 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2703 {
2704         struct fsl_udc *udc = udc_controller;
2705         u32 mode, usbcmd;
2706
2707         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2708
2709         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2710
2711         /*
2712          * If the controller is already stopped, then this must be a
2713          * PM suspend.  Remember this fact, so that we will leave the
2714          * controller stopped at PM resume time.
2715          */
2716         if (udc->stopped) {
2717                 pr_debug("gadget already stopped, leaving early\n");
2718                 udc->already_stopped = 1;
2719                 return 0;
2720         }
2721
2722         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2723                 pr_debug("gadget not in device mode, leaving early\n");
2724                 return 0;
2725         }
2726
2727         /* stop the controller */
2728         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2729         fsl_writel(usbcmd, &dr_regs->usbcmd);
2730
2731         udc->stopped = 1;
2732
2733         pr_info("USB Gadget suspended\n");
2734
2735         return 0;
2736 }
2737
2738 static int fsl_udc_otg_resume(struct device *dev)
2739 {
2740         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2741                  udc_controller->stopped, udc_controller->already_stopped);
2742
2743         /*
2744          * If the controller was stopped at suspend time, then
2745          * don't resume it now.
2746          */
2747         if (udc_controller->already_stopped) {
2748                 udc_controller->already_stopped = 0;
2749                 pr_debug("gadget was already stopped, leaving early\n");
2750                 return 0;
2751         }
2752
2753         pr_info("USB Gadget resume\n");
2754
2755         return fsl_udc_resume(NULL);
2756 }
2757
2758 /*-------------------------------------------------------------------------
2759         Register entry point for the peripheral controller driver
2760 --------------------------------------------------------------------------*/
2761
2762 static struct platform_driver udc_driver = {
2763         .remove  = __exit_p(fsl_udc_remove),
2764         /* these suspend and resume are not usb suspend and resume */
2765         .suspend = fsl_udc_suspend,
2766         .resume  = fsl_udc_resume,
2767         .driver  = {
2768                 .name = (char *)driver_name,
2769                 .owner = THIS_MODULE,
2770                 /* udc suspend/resume called from OTG driver */
2771                 .suspend = fsl_udc_otg_suspend,
2772                 .resume  = fsl_udc_otg_resume,
2773         },
2774 };
2775
2776 static int __init udc_init(void)
2777 {
2778         printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2779         return platform_driver_probe(&udc_driver, fsl_udc_probe);
2780 }
2781
2782 module_init(udc_init);
2783
2784 static void __exit udc_exit(void)
2785 {
2786         platform_driver_unregister(&udc_driver);
2787         printk(KERN_WARNING "%s unregistered\n", driver_desc);
2788 }
2789
2790 module_exit(udc_exit);
2791
2792 MODULE_DESCRIPTION(DRIVER_DESC);
2793 MODULE_AUTHOR(DRIVER_AUTHOR);
2794 MODULE_LICENSE("GPL");
2795 MODULE_ALIAS("platform:fsl-usb2-udc");