2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/of_platform.h>
34 #include <linux/usb/ch9.h>
35 #include <linux/usb/gadget.h>
36 #include <linux/usb/phy.h>
37 #include <linux/platform_data/s3c-hsotg.h>
39 #include "s3c-hsotg.h"
41 static const char * const s3c_hsotg_supply_names[] = {
42 "vusb_d", /* digital USB supply, 1.2V */
43 "vusb_a", /* analog USB supply, 1.1V */
49 * Unfortunately there seems to be a limit of the amount of data that can
50 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
51 * packets (which practically means 1 packet and 63 bytes of data) when the
54 * This means if we are wanting to move >127 bytes of data, we need to
55 * split the transactions up, but just doing one packet at a time does
56 * not work (this may be an implicit DATA0 PID on first packet of the
57 * transaction) and doing 2 packets is outside the controller's limits.
59 * If we try to lower the MPS size for EP0, then no transfers work properly
60 * for EP0, and the system will fail basic enumeration. As no cause for this
61 * has currently been found, we cannot support any large IN transfers for
64 #define EP0_MPS_LIMIT 64
70 * struct s3c_hsotg_ep - driver endpoint definition.
71 * @ep: The gadget layer representation of the endpoint.
72 * @name: The driver generated name for the endpoint.
73 * @queue: Queue of requests for this endpoint.
74 * @parent: Reference back to the parent device structure.
75 * @req: The current request that the endpoint is processing. This is
76 * used to indicate an request has been loaded onto the endpoint
77 * and has yet to be completed (maybe due to data move, or simply
78 * awaiting an ack from the core all the data has been completed).
79 * @debugfs: File entry for debugfs file for this endpoint.
80 * @lock: State lock to protect contents of endpoint.
81 * @dir_in: Set to true if this endpoint is of the IN direction, which
82 * means that it is sending data to the Host.
83 * @index: The index for the endpoint registers.
84 * @mc: Multi Count - number of transactions per microframe
85 * @interval - Interval for periodic endpoints
86 * @name: The name array passed to the USB core.
87 * @halted: Set if the endpoint has been halted.
88 * @periodic: Set if this is a periodic ep, such as Interrupt
89 * @isochronous: Set if this is a isochronous ep
90 * @sent_zlp: Set if we've sent a zero-length packet.
91 * @total_data: The total number of data bytes done.
92 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
93 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
94 * @last_load: The offset of data for the last start of request.
95 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
97 * This is the driver's state for each registered enpoint, allowing it
98 * to keep track of transactions that need doing. Each endpoint has a
99 * lock to protect the state, to try and avoid using an overall lock
100 * for the host controller as much as possible.
102 * For periodic IN endpoints, we have fifo_size and fifo_load to try
103 * and keep track of the amount of data in the periodic FIFO for each
104 * of these as we don't have a status register that tells us how much
105 * is in each of them. (note, this may actually be useless information
106 * as in shared-fifo mode periodic in acts like a single-frame packet
107 * buffer than a fifo)
109 struct s3c_hsotg_ep {
111 struct list_head queue;
112 struct s3c_hsotg *parent;
113 struct s3c_hsotg_req *req;
114 struct dentry *debugfs;
117 unsigned long total_data;
118 unsigned int size_loaded;
119 unsigned int last_load;
120 unsigned int fifo_load;
121 unsigned short fifo_size;
123 unsigned char dir_in;
126 unsigned char interval;
128 unsigned int halted:1;
129 unsigned int periodic:1;
130 unsigned int isochronous:1;
131 unsigned int sent_zlp:1;
137 * struct s3c_hsotg - driver state.
138 * @dev: The parent device supplied to the probe function
139 * @driver: USB gadget driver
140 * @phy: The otg phy transceiver structure for phy control.
141 * @plat: The platform specific configuration data. This can be removed once
142 * all SoCs support usb transceiver.
143 * @regs: The memory area mapped for accessing registers.
144 * @irq: The IRQ number we are using
145 * @supplies: Definition of USB power supplies
146 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
147 * @num_of_eps: Number of available EPs (excluding EP0)
148 * @debug_root: root directrory for debugfs.
149 * @debug_file: main status file for debugfs.
150 * @debug_fifo: FIFO status file for debugfs.
151 * @ep0_reply: Request used for ep0 reply.
152 * @ep0_buff: Buffer for EP0 reply data, if needed.
153 * @ctrl_buff: Buffer for EP0 control requests.
154 * @ctrl_req: Request for EP0 control packets.
155 * @setup: NAK management for EP0 SETUP
156 * @last_rst: Time of last reset
157 * @eps: The endpoints being supplied to the gadget framework
161 struct usb_gadget_driver *driver;
163 struct s3c_hsotg_plat *plat;
171 struct regulator_bulk_data supplies[ARRAY_SIZE(s3c_hsotg_supply_names)];
173 unsigned int dedicated_fifos:1;
174 unsigned char num_of_eps;
176 struct dentry *debug_root;
177 struct dentry *debug_file;
178 struct dentry *debug_fifo;
180 struct usb_request *ep0_reply;
181 struct usb_request *ctrl_req;
185 struct usb_gadget gadget;
187 unsigned long last_rst;
188 struct s3c_hsotg_ep *eps;
192 * struct s3c_hsotg_req - data transfer request
193 * @req: The USB gadget request
194 * @queue: The list of requests for the endpoint this is queued for.
195 * @in_progress: Has already had size/packets written to core
196 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
198 struct s3c_hsotg_req {
199 struct usb_request req;
200 struct list_head queue;
201 unsigned char in_progress;
202 unsigned char mapped;
205 /* conversion functions */
206 static inline struct s3c_hsotg_req *our_req(struct usb_request *req)
208 return container_of(req, struct s3c_hsotg_req, req);
211 static inline struct s3c_hsotg_ep *our_ep(struct usb_ep *ep)
213 return container_of(ep, struct s3c_hsotg_ep, ep);
216 static inline struct s3c_hsotg *to_hsotg(struct usb_gadget *gadget)
218 return container_of(gadget, struct s3c_hsotg, gadget);
221 static inline void __orr32(void __iomem *ptr, u32 val)
223 writel(readl(ptr) | val, ptr);
226 static inline void __bic32(void __iomem *ptr, u32 val)
228 writel(readl(ptr) & ~val, ptr);
231 /* forward decleration of functions */
232 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg);
235 * using_dma - return the DMA status of the driver.
236 * @hsotg: The driver state.
238 * Return true if we're using DMA.
240 * Currently, we have the DMA support code worked into everywhere
241 * that needs it, but the AMBA DMA implementation in the hardware can
242 * only DMA from 32bit aligned addresses. This means that gadgets such
243 * as the CDC Ethernet cannot work as they often pass packets which are
246 * Unfortunately the choice to use DMA or not is global to the controller
247 * and seems to be only settable when the controller is being put through
248 * a core reset. This means we either need to fix the gadgets to take
249 * account of DMA alignment, or add bounce buffers (yuerk).
251 * Until this issue is sorted out, we always return 'false'.
253 static inline bool using_dma(struct s3c_hsotg *hsotg)
255 return false; /* support is not complete */
259 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
260 * @hsotg: The device state
261 * @ints: A bitmask of the interrupts to enable
263 static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints)
265 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
268 new_gsintmsk = gsintmsk | ints;
270 if (new_gsintmsk != gsintmsk) {
271 dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
272 writel(new_gsintmsk, hsotg->regs + GINTMSK);
277 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
278 * @hsotg: The device state
279 * @ints: A bitmask of the interrupts to enable
281 static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints)
283 u32 gsintmsk = readl(hsotg->regs + GINTMSK);
286 new_gsintmsk = gsintmsk & ~ints;
288 if (new_gsintmsk != gsintmsk)
289 writel(new_gsintmsk, hsotg->regs + GINTMSK);
293 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
294 * @hsotg: The device state
295 * @ep: The endpoint index
296 * @dir_in: True if direction is in.
297 * @en: The enable value, true to enable
299 * Set or clear the mask for an individual endpoint's interrupt
302 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg *hsotg,
303 unsigned int ep, unsigned int dir_in,
313 local_irq_save(flags);
314 daint = readl(hsotg->regs + DAINTMSK);
319 writel(daint, hsotg->regs + DAINTMSK);
320 local_irq_restore(flags);
324 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
325 * @hsotg: The device instance.
327 static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
335 /* set FIFO sizes to 2048/1024 */
337 writel(2048, hsotg->regs + GRXFSIZ);
338 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
339 GNPTXFSIZ_NPTxFDep(1024),
340 hsotg->regs + GNPTXFSIZ);
343 * arange all the rest of the TX FIFOs, as some versions of this
344 * block have overlapping default addresses. This also ensures
345 * that if the settings have been changed, then they are set to
349 /* start at the end of the GNPTXFSIZ, rounded up */
354 * currently we allocate TX FIFOs for all possible endpoints,
355 * and assume that they are all the same size.
358 for (ep = 1; ep <= 15; ep++) {
360 val |= size << DPTXFSIZn_DPTxFSize_SHIFT;
363 writel(val, hsotg->regs + DPTXFSIZn(ep));
367 * according to p428 of the design guide, we need to ensure that
368 * all fifos are flushed before continuing
371 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh |
372 GRSTCTL_RxFFlsh, hsotg->regs + GRSTCTL);
374 /* wait until the fifos are both flushed */
377 val = readl(hsotg->regs + GRSTCTL);
379 if ((val & (GRSTCTL_TxFFlsh | GRSTCTL_RxFFlsh)) == 0)
382 if (--timeout == 0) {
384 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
391 dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
395 * @ep: USB endpoint to allocate request for.
396 * @flags: Allocation flags
398 * Allocate a new USB request structure appropriate for the specified endpoint
400 static struct usb_request *s3c_hsotg_ep_alloc_request(struct usb_ep *ep,
403 struct s3c_hsotg_req *req;
405 req = kzalloc(sizeof(struct s3c_hsotg_req), flags);
409 INIT_LIST_HEAD(&req->queue);
415 * is_ep_periodic - return true if the endpoint is in periodic mode.
416 * @hs_ep: The endpoint to query.
418 * Returns true if the endpoint is in periodic mode, meaning it is being
419 * used for an Interrupt or ISO transfer.
421 static inline int is_ep_periodic(struct s3c_hsotg_ep *hs_ep)
423 return hs_ep->periodic;
427 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
428 * @hsotg: The device state.
429 * @hs_ep: The endpoint for the request
430 * @hs_req: The request being processed.
432 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
433 * of a request to ensure the buffer is ready for access by the caller.
435 static void s3c_hsotg_unmap_dma(struct s3c_hsotg *hsotg,
436 struct s3c_hsotg_ep *hs_ep,
437 struct s3c_hsotg_req *hs_req)
439 struct usb_request *req = &hs_req->req;
441 /* ignore this if we're not moving any data */
442 if (hs_req->req.length == 0)
445 usb_gadget_unmap_request(&hsotg->gadget, req, hs_ep->dir_in);
449 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
450 * @hsotg: The controller state.
451 * @hs_ep: The endpoint we're going to write for.
452 * @hs_req: The request to write data for.
454 * This is called when the TxFIFO has some space in it to hold a new
455 * transmission and we have something to give it. The actual setup of
456 * the data size is done elsewhere, so all we have to do is to actually
459 * The return value is zero if there is more space (or nothing was done)
460 * otherwise -ENOSPC is returned if the FIFO space was used up.
462 * This routine is only needed for PIO
464 static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
465 struct s3c_hsotg_ep *hs_ep,
466 struct s3c_hsotg_req *hs_req)
468 bool periodic = is_ep_periodic(hs_ep);
469 u32 gnptxsts = readl(hsotg->regs + GNPTXSTS);
470 int buf_pos = hs_req->req.actual;
471 int to_write = hs_ep->size_loaded;
477 to_write -= (buf_pos - hs_ep->last_load);
479 /* if there's nothing to write, get out early */
483 if (periodic && !hsotg->dedicated_fifos) {
484 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
489 * work out how much data was loaded so we can calculate
490 * how much data is left in the fifo.
493 size_left = DxEPTSIZ_XferSize_GET(epsize);
496 * if shared fifo, we cannot write anything until the
497 * previous data has been completely sent.
499 if (hs_ep->fifo_load != 0) {
500 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
504 dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
506 hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
508 /* how much of the data has moved */
509 size_done = hs_ep->size_loaded - size_left;
511 /* how much data is left in the fifo */
512 can_write = hs_ep->fifo_load - size_done;
513 dev_dbg(hsotg->dev, "%s: => can_write1=%d\n",
514 __func__, can_write);
516 can_write = hs_ep->fifo_size - can_write;
517 dev_dbg(hsotg->dev, "%s: => can_write2=%d\n",
518 __func__, can_write);
520 if (can_write <= 0) {
521 s3c_hsotg_en_gsint(hsotg, GINTSTS_PTxFEmp);
524 } else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
525 can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index));
530 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
532 "%s: no queue slots available (0x%08x)\n",
535 s3c_hsotg_en_gsint(hsotg, GINTSTS_NPTxFEmp);
539 can_write = GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
540 can_write *= 4; /* fifo size is in 32bit quantities. */
543 max_transfer = hs_ep->ep.maxpacket * hs_ep->mc;
545 dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
546 __func__, gnptxsts, can_write, to_write, max_transfer);
549 * limit to 512 bytes of data, it seems at least on the non-periodic
550 * FIFO, requests of >512 cause the endpoint to get stuck with a
551 * fragment of the end of the transfer in it.
553 if (can_write > 512 && !periodic)
557 * limit the write to one max-packet size worth of data, but allow
558 * the transfer to return that it did not run out of fifo space
561 if (to_write > max_transfer) {
562 to_write = max_transfer;
564 /* it's needed only when we do not use dedicated fifos */
565 if (!hsotg->dedicated_fifos)
566 s3c_hsotg_en_gsint(hsotg,
567 periodic ? GINTSTS_PTxFEmp :
571 /* see if we can write data */
573 if (to_write > can_write) {
574 to_write = can_write;
575 pkt_round = to_write % max_transfer;
578 * Round the write down to an
579 * exact number of packets.
581 * Note, we do not currently check to see if we can ever
582 * write a full packet or not to the FIFO.
586 to_write -= pkt_round;
589 * enable correct FIFO interrupt to alert us when there
593 /* it's needed only when we do not use dedicated fifos */
594 if (!hsotg->dedicated_fifos)
595 s3c_hsotg_en_gsint(hsotg,
596 periodic ? GINTSTS_PTxFEmp :
600 dev_dbg(hsotg->dev, "write %d/%d, can_write %d, done %d\n",
601 to_write, hs_req->req.length, can_write, buf_pos);
606 hs_req->req.actual = buf_pos + to_write;
607 hs_ep->total_data += to_write;
610 hs_ep->fifo_load += to_write;
612 to_write = DIV_ROUND_UP(to_write, 4);
613 data = hs_req->req.buf + buf_pos;
615 writesl(hsotg->regs + EPFIFO(hs_ep->index), data, to_write);
617 return (to_write >= can_write) ? -ENOSPC : 0;
621 * get_ep_limit - get the maximum data legnth for this endpoint
622 * @hs_ep: The endpoint
624 * Return the maximum data that can be queued in one go on a given endpoint
625 * so that transfers that are too long can be split.
627 static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
629 int index = hs_ep->index;
634 maxsize = DxEPTSIZ_XferSize_LIMIT + 1;
635 maxpkt = DxEPTSIZ_PktCnt_LIMIT + 1;
639 maxpkt = DIEPTSIZ0_PktCnt_LIMIT + 1;
644 /* we made the constant loading easier above by using +1 */
649 * constrain by packet count if maxpkts*pktsize is greater
650 * than the length register size.
653 if ((maxpkt * hs_ep->ep.maxpacket) < maxsize)
654 maxsize = maxpkt * hs_ep->ep.maxpacket;
660 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
661 * @hsotg: The controller state.
662 * @hs_ep: The endpoint to process a request for
663 * @hs_req: The request to start.
664 * @continuing: True if we are doing more for the current request.
666 * Start the given request running by setting the endpoint registers
667 * appropriately, and writing any data to the FIFOs.
669 static void s3c_hsotg_start_req(struct s3c_hsotg *hsotg,
670 struct s3c_hsotg_ep *hs_ep,
671 struct s3c_hsotg_req *hs_req,
674 struct usb_request *ureq = &hs_req->req;
675 int index = hs_ep->index;
676 int dir_in = hs_ep->dir_in;
686 if (hs_ep->req && !continuing) {
687 dev_err(hsotg->dev, "%s: active request\n", __func__);
690 } else if (hs_ep->req != hs_req && continuing) {
692 "%s: continue different req\n", __func__);
698 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
699 epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index);
701 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
702 __func__, readl(hsotg->regs + epctrl_reg), index,
703 hs_ep->dir_in ? "in" : "out");
705 /* If endpoint is stalled, we will restart request later */
706 ctrl = readl(hsotg->regs + epctrl_reg);
708 if (ctrl & DxEPCTL_Stall) {
709 dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
713 length = ureq->length - ureq->actual;
714 dev_dbg(hsotg->dev, "ureq->length:%d ureq->actual:%d\n",
715 ureq->length, ureq->actual);
718 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
719 ureq->buf, length, ureq->dma,
720 ureq->no_interrupt, ureq->zero, ureq->short_not_ok);
722 maxreq = get_ep_limit(hs_ep);
723 if (length > maxreq) {
724 int round = maxreq % hs_ep->ep.maxpacket;
726 dev_dbg(hsotg->dev, "%s: length %d, max-req %d, r %d\n",
727 __func__, length, maxreq, round);
729 /* round down to multiple of packets */
737 packets = DIV_ROUND_UP(length, hs_ep->ep.maxpacket);
739 packets = 1; /* send one packet if length is zero. */
741 if (hs_ep->isochronous && length > (hs_ep->mc * hs_ep->ep.maxpacket)) {
742 dev_err(hsotg->dev, "req length > maxpacket*mc\n");
746 if (dir_in && index != 0)
747 if (hs_ep->isochronous)
748 epsize = DxEPTSIZ_MC(packets);
750 epsize = DxEPTSIZ_MC(1);
754 if (index != 0 && ureq->zero) {
756 * test for the packets being exactly right for the
760 if (length == (packets * hs_ep->ep.maxpacket))
764 epsize |= DxEPTSIZ_PktCnt(packets);
765 epsize |= DxEPTSIZ_XferSize(length);
767 dev_dbg(hsotg->dev, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
768 __func__, packets, length, ureq->length, epsize, epsize_reg);
770 /* store the request as the current one we're doing */
773 /* write size / packets */
774 writel(epsize, hsotg->regs + epsize_reg);
776 if (using_dma(hsotg) && !continuing) {
777 unsigned int dma_reg;
780 * write DMA address to control register, buffer already
781 * synced by s3c_hsotg_ep_queue().
784 dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index);
785 writel(ureq->dma, hsotg->regs + dma_reg);
787 dev_dbg(hsotg->dev, "%s: 0x%08x => 0x%08x\n",
788 __func__, ureq->dma, dma_reg);
791 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
792 ctrl |= DxEPCTL_USBActEp;
794 dev_dbg(hsotg->dev, "setup req:%d\n", hsotg->setup);
796 /* For Setup request do not clear NAK */
797 if (hsotg->setup && index == 0)
800 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
803 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
804 writel(ctrl, hsotg->regs + epctrl_reg);
807 * set these, it seems that DMA support increments past the end
808 * of the packet buffer so we need to calculate the length from
811 hs_ep->size_loaded = length;
812 hs_ep->last_load = ureq->actual;
814 if (dir_in && !using_dma(hsotg)) {
815 /* set these anyway, we may need them for non-periodic in */
816 hs_ep->fifo_load = 0;
818 s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
822 * clear the INTknTXFEmpMsk when we start request, more as a aide
823 * to debugging to see what is going on.
826 writel(DIEPMSK_INTknTXFEmpMsk,
827 hsotg->regs + DIEPINT(index));
830 * Note, trying to clear the NAK here causes problems with transmit
831 * on the S3C6400 ending up with the TXFIFO becoming full.
834 /* check ep is enabled */
835 if (!(readl(hsotg->regs + epctrl_reg) & DxEPCTL_EPEna))
837 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
838 index, readl(hsotg->regs + epctrl_reg));
840 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n",
841 __func__, readl(hsotg->regs + epctrl_reg));
843 /* enable ep interrupts */
844 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1);
848 * s3c_hsotg_map_dma - map the DMA memory being used for the request
849 * @hsotg: The device state.
850 * @hs_ep: The endpoint the request is on.
851 * @req: The request being processed.
853 * We've been asked to queue a request, so ensure that the memory buffer
854 * is correctly setup for DMA. If we've been passed an extant DMA address
855 * then ensure the buffer has been synced to memory. If our buffer has no
856 * DMA memory, then we map the memory and mark our request to allow us to
857 * cleanup on completion.
859 static int s3c_hsotg_map_dma(struct s3c_hsotg *hsotg,
860 struct s3c_hsotg_ep *hs_ep,
861 struct usb_request *req)
863 struct s3c_hsotg_req *hs_req = our_req(req);
866 /* if the length is zero, ignore the DMA data */
867 if (hs_req->req.length == 0)
870 ret = usb_gadget_map_request(&hsotg->gadget, req, hs_ep->dir_in);
877 dev_err(hsotg->dev, "%s: failed to map buffer %p, %d bytes\n",
878 __func__, req->buf, req->length);
883 static int s3c_hsotg_ep_queue(struct usb_ep *ep, struct usb_request *req,
886 struct s3c_hsotg_req *hs_req = our_req(req);
887 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
888 struct s3c_hsotg *hs = hs_ep->parent;
891 dev_dbg(hs->dev, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
892 ep->name, req, req->length, req->buf, req->no_interrupt,
893 req->zero, req->short_not_ok);
895 /* initialise status of the request */
896 INIT_LIST_HEAD(&hs_req->queue);
898 req->status = -EINPROGRESS;
900 /* if we're using DMA, sync the buffers as necessary */
902 int ret = s3c_hsotg_map_dma(hs, hs_ep, req);
907 first = list_empty(&hs_ep->queue);
908 list_add_tail(&hs_req->queue, &hs_ep->queue);
911 s3c_hsotg_start_req(hs, hs_ep, hs_req, false);
916 static int s3c_hsotg_ep_queue_lock(struct usb_ep *ep, struct usb_request *req,
919 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
920 struct s3c_hsotg *hs = hs_ep->parent;
921 unsigned long flags = 0;
924 spin_lock_irqsave(&hs->lock, flags);
925 ret = s3c_hsotg_ep_queue(ep, req, gfp_flags);
926 spin_unlock_irqrestore(&hs->lock, flags);
931 static void s3c_hsotg_ep_free_request(struct usb_ep *ep,
932 struct usb_request *req)
934 struct s3c_hsotg_req *hs_req = our_req(req);
940 * s3c_hsotg_complete_oursetup - setup completion callback
941 * @ep: The endpoint the request was on.
942 * @req: The request completed.
944 * Called on completion of any requests the driver itself
945 * submitted that need cleaning up.
947 static void s3c_hsotg_complete_oursetup(struct usb_ep *ep,
948 struct usb_request *req)
950 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
951 struct s3c_hsotg *hsotg = hs_ep->parent;
953 dev_dbg(hsotg->dev, "%s: ep %p, req %p\n", __func__, ep, req);
955 s3c_hsotg_ep_free_request(ep, req);
959 * ep_from_windex - convert control wIndex value to endpoint
960 * @hsotg: The driver state.
961 * @windex: The control request wIndex field (in host order).
963 * Convert the given wIndex into a pointer to an driver endpoint
964 * structure, or return NULL if it is not a valid endpoint.
966 static struct s3c_hsotg_ep *ep_from_windex(struct s3c_hsotg *hsotg,
969 struct s3c_hsotg_ep *ep = &hsotg->eps[windex & 0x7F];
970 int dir = (windex & USB_DIR_IN) ? 1 : 0;
971 int idx = windex & 0x7F;
976 if (idx > hsotg->num_of_eps)
979 if (idx && ep->dir_in != dir)
986 * s3c_hsotg_send_reply - send reply to control request
987 * @hsotg: The device state
989 * @buff: Buffer for request
990 * @length: Length of reply.
992 * Create a request and queue it on the given endpoint. This is useful as
993 * an internal method of sending replies to certain control requests, etc.
995 static int s3c_hsotg_send_reply(struct s3c_hsotg *hsotg,
996 struct s3c_hsotg_ep *ep,
1000 struct usb_request *req;
1003 dev_dbg(hsotg->dev, "%s: buff %p, len %d\n", __func__, buff, length);
1005 req = s3c_hsotg_ep_alloc_request(&ep->ep, GFP_ATOMIC);
1006 hsotg->ep0_reply = req;
1008 dev_warn(hsotg->dev, "%s: cannot alloc req\n", __func__);
1012 req->buf = hsotg->ep0_buff;
1013 req->length = length;
1014 req->zero = 1; /* always do zero-length final transfer */
1015 req->complete = s3c_hsotg_complete_oursetup;
1018 memcpy(req->buf, buff, length);
1022 ret = s3c_hsotg_ep_queue(&ep->ep, req, GFP_ATOMIC);
1024 dev_warn(hsotg->dev, "%s: cannot queue req\n", __func__);
1032 * s3c_hsotg_process_req_status - process request GET_STATUS
1033 * @hsotg: The device state
1034 * @ctrl: USB control request
1036 static int s3c_hsotg_process_req_status(struct s3c_hsotg *hsotg,
1037 struct usb_ctrlrequest *ctrl)
1039 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1040 struct s3c_hsotg_ep *ep;
1044 dev_dbg(hsotg->dev, "%s: USB_REQ_GET_STATUS\n", __func__);
1047 dev_warn(hsotg->dev, "%s: direction out?\n", __func__);
1051 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1052 case USB_RECIP_DEVICE:
1053 reply = cpu_to_le16(0); /* bit 0 => self powered,
1054 * bit 1 => remote wakeup */
1057 case USB_RECIP_INTERFACE:
1058 /* currently, the data result should be zero */
1059 reply = cpu_to_le16(0);
1062 case USB_RECIP_ENDPOINT:
1063 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1067 reply = cpu_to_le16(ep->halted ? 1 : 0);
1074 if (le16_to_cpu(ctrl->wLength) != 2)
1077 ret = s3c_hsotg_send_reply(hsotg, ep0, &reply, 2);
1079 dev_err(hsotg->dev, "%s: failed to send reply\n", __func__);
1086 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
1089 * get_ep_head - return the first request on the endpoint
1090 * @hs_ep: The controller endpoint to get
1092 * Get the first request on the endpoint.
1094 static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
1096 if (list_empty(&hs_ep->queue))
1099 return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
1103 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1104 * @hsotg: The device state
1105 * @ctrl: USB control request
1107 static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
1108 struct usb_ctrlrequest *ctrl)
1110 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1111 struct s3c_hsotg_req *hs_req;
1113 bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
1114 struct s3c_hsotg_ep *ep;
1118 dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
1119 __func__, set ? "SET" : "CLEAR");
1121 if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
1122 ep = ep_from_windex(hsotg, le16_to_cpu(ctrl->wIndex));
1124 dev_dbg(hsotg->dev, "%s: no endpoint for 0x%04x\n",
1125 __func__, le16_to_cpu(ctrl->wIndex));
1129 switch (le16_to_cpu(ctrl->wValue)) {
1130 case USB_ENDPOINT_HALT:
1131 halted = ep->halted;
1133 s3c_hsotg_ep_sethalt(&ep->ep, set);
1135 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1138 "%s: failed to send reply\n", __func__);
1143 * we have to complete all requests for ep if it was
1144 * halted, and the halt was cleared by CLEAR_FEATURE
1147 if (!set && halted) {
1149 * If we have request in progress,
1155 list_del_init(&hs_req->queue);
1156 hs_req->req.complete(&ep->ep,
1160 /* If we have pending request, then start it */
1161 restart = !list_empty(&ep->queue);
1163 hs_req = get_ep_head(ep);
1164 s3c_hsotg_start_req(hsotg, ep,
1175 return -ENOENT; /* currently only deal with endpoint */
1180 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg);
1181 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg);
1184 * s3c_hsotg_process_control - process a control request
1185 * @hsotg: The device state
1186 * @ctrl: The control request received
1188 * The controller has received the SETUP phase of a control request, and
1189 * needs to work out what to do next (and whether to pass it on to the
1192 static void s3c_hsotg_process_control(struct s3c_hsotg *hsotg,
1193 struct usb_ctrlrequest *ctrl)
1195 struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
1201 dev_dbg(hsotg->dev, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1202 ctrl->bRequest, ctrl->bRequestType,
1203 ctrl->wValue, ctrl->wLength);
1206 * record the direction of the request, for later use when enquing
1210 ep0->dir_in = (ctrl->bRequestType & USB_DIR_IN) ? 1 : 0;
1211 dev_dbg(hsotg->dev, "ctrl: dir_in=%d\n", ep0->dir_in);
1214 * if we've no data with this request, then the last part of the
1215 * transaction is going to implicitly be IN.
1217 if (ctrl->wLength == 0)
1220 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1221 switch (ctrl->bRequest) {
1222 case USB_REQ_SET_ADDRESS:
1223 s3c_hsotg_disconnect(hsotg);
1224 dcfg = readl(hsotg->regs + DCFG);
1225 dcfg &= ~DCFG_DevAddr_MASK;
1226 dcfg |= ctrl->wValue << DCFG_DevAddr_SHIFT;
1227 writel(dcfg, hsotg->regs + DCFG);
1229 dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
1231 ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
1234 case USB_REQ_GET_STATUS:
1235 ret = s3c_hsotg_process_req_status(hsotg, ctrl);
1238 case USB_REQ_CLEAR_FEATURE:
1239 case USB_REQ_SET_FEATURE:
1240 ret = s3c_hsotg_process_req_feature(hsotg, ctrl);
1245 /* as a fallback, try delivering it to the driver to deal with */
1247 if (ret == 0 && hsotg->driver) {
1248 spin_unlock(&hsotg->lock);
1249 ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
1250 spin_lock(&hsotg->lock);
1252 dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
1256 * the request is either unhandlable, or is not formatted correctly
1257 * so respond with a STALL for the status stage to indicate failure.
1264 dev_dbg(hsotg->dev, "ep0 stall (dir=%d)\n", ep0->dir_in);
1265 reg = (ep0->dir_in) ? DIEPCTL0 : DOEPCTL0;
1268 * DxEPCTL_Stall will be cleared by EP once it has
1269 * taken effect, so no need to clear later.
1272 ctrl = readl(hsotg->regs + reg);
1273 ctrl |= DxEPCTL_Stall;
1274 ctrl |= DxEPCTL_CNAK;
1275 writel(ctrl, hsotg->regs + reg);
1278 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1279 ctrl, reg, readl(hsotg->regs + reg));
1282 * don't believe we need to anything more to get the EP
1283 * to reply with a STALL packet
1287 * complete won't be called, so we enqueue
1288 * setup request here
1290 s3c_hsotg_enqueue_setup(hsotg);
1295 * s3c_hsotg_complete_setup - completion of a setup transfer
1296 * @ep: The endpoint the request was on.
1297 * @req: The request completed.
1299 * Called on completion of any requests the driver itself submitted for
1302 static void s3c_hsotg_complete_setup(struct usb_ep *ep,
1303 struct usb_request *req)
1305 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
1306 struct s3c_hsotg *hsotg = hs_ep->parent;
1308 if (req->status < 0) {
1309 dev_dbg(hsotg->dev, "%s: failed %d\n", __func__, req->status);
1313 spin_lock(&hsotg->lock);
1314 if (req->actual == 0)
1315 s3c_hsotg_enqueue_setup(hsotg);
1317 s3c_hsotg_process_control(hsotg, req->buf);
1318 spin_unlock(&hsotg->lock);
1322 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1323 * @hsotg: The device state.
1325 * Enqueue a request on EP0 if necessary to received any SETUP packets
1326 * received from the host.
1328 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg *hsotg)
1330 struct usb_request *req = hsotg->ctrl_req;
1331 struct s3c_hsotg_req *hs_req = our_req(req);
1334 dev_dbg(hsotg->dev, "%s: queueing setup request\n", __func__);
1338 req->buf = hsotg->ctrl_buff;
1339 req->complete = s3c_hsotg_complete_setup;
1341 if (!list_empty(&hs_req->queue)) {
1342 dev_dbg(hsotg->dev, "%s already queued???\n", __func__);
1346 hsotg->eps[0].dir_in = 0;
1348 ret = s3c_hsotg_ep_queue(&hsotg->eps[0].ep, req, GFP_ATOMIC);
1350 dev_err(hsotg->dev, "%s: failed queue (%d)\n", __func__, ret);
1352 * Don't think there's much we can do other than watch the
1359 * s3c_hsotg_complete_request - complete a request given to us
1360 * @hsotg: The device state.
1361 * @hs_ep: The endpoint the request was on.
1362 * @hs_req: The request to complete.
1363 * @result: The result code (0 => Ok, otherwise errno)
1365 * The given request has finished, so call the necessary completion
1366 * if it has one and then look to see if we can start a new request
1369 * Note, expects the ep to already be locked as appropriate.
1371 static void s3c_hsotg_complete_request(struct s3c_hsotg *hsotg,
1372 struct s3c_hsotg_ep *hs_ep,
1373 struct s3c_hsotg_req *hs_req,
1379 dev_dbg(hsotg->dev, "%s: nothing to complete?\n", __func__);
1383 dev_dbg(hsotg->dev, "complete: ep %p %s, req %p, %d => %p\n",
1384 hs_ep, hs_ep->ep.name, hs_req, result, hs_req->req.complete);
1387 * only replace the status if we've not already set an error
1388 * from a previous transaction
1391 if (hs_req->req.status == -EINPROGRESS)
1392 hs_req->req.status = result;
1395 list_del_init(&hs_req->queue);
1397 if (using_dma(hsotg))
1398 s3c_hsotg_unmap_dma(hsotg, hs_ep, hs_req);
1401 * call the complete request with the locks off, just in case the
1402 * request tries to queue more work for this endpoint.
1405 if (hs_req->req.complete) {
1406 spin_unlock(&hsotg->lock);
1407 hs_req->req.complete(&hs_ep->ep, &hs_req->req);
1408 spin_lock(&hsotg->lock);
1412 * Look to see if there is anything else to do. Note, the completion
1413 * of the previous request may have caused a new request to be started
1414 * so be careful when doing this.
1417 if (!hs_ep->req && result >= 0) {
1418 restart = !list_empty(&hs_ep->queue);
1420 hs_req = get_ep_head(hs_ep);
1421 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, false);
1427 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1428 * @hsotg: The device state.
1429 * @ep_idx: The endpoint index for the data
1430 * @size: The size of data in the fifo, in bytes
1432 * The FIFO status shows there is data to read from the FIFO for a given
1433 * endpoint, so sort out whether we need to read the data into a request
1434 * that has been made for that endpoint.
1436 static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
1438 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep_idx];
1439 struct s3c_hsotg_req *hs_req = hs_ep->req;
1440 void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx);
1447 u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx));
1450 dev_warn(hsotg->dev,
1451 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1452 __func__, size, ep_idx, epctl);
1454 /* dump the data from the FIFO, we've nothing we can do */
1455 for (ptr = 0; ptr < size; ptr += 4)
1462 read_ptr = hs_req->req.actual;
1463 max_req = hs_req->req.length - read_ptr;
1465 dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
1466 __func__, to_read, max_req, read_ptr, hs_req->req.length);
1468 if (to_read > max_req) {
1470 * more data appeared than we where willing
1471 * to deal with in this request.
1474 /* currently we don't deal this */
1478 hs_ep->total_data += to_read;
1479 hs_req->req.actual += to_read;
1480 to_read = DIV_ROUND_UP(to_read, 4);
1483 * note, we might over-write the buffer end by 3 bytes depending on
1484 * alignment of the data.
1486 readsl(fifo, hs_req->req.buf + read_ptr, to_read);
1490 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1491 * @hsotg: The device instance
1492 * @req: The request currently on this endpoint
1494 * Generate a zero-length IN packet request for terminating a SETUP
1497 * Note, since we don't write any data to the TxFIFO, then it is
1498 * currently believed that we do not need to wait for any space in
1501 static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
1502 struct s3c_hsotg_req *req)
1507 dev_warn(hsotg->dev, "%s: no request?\n", __func__);
1511 if (req->req.length == 0) {
1512 hsotg->eps[0].sent_zlp = 1;
1513 s3c_hsotg_enqueue_setup(hsotg);
1517 hsotg->eps[0].dir_in = 1;
1518 hsotg->eps[0].sent_zlp = 1;
1520 dev_dbg(hsotg->dev, "sending zero-length packet\n");
1522 /* issue a zero-sized packet to terminate this */
1523 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1524 DxEPTSIZ_XferSize(0), hsotg->regs + DIEPTSIZ(0));
1526 ctrl = readl(hsotg->regs + DIEPCTL0);
1527 ctrl |= DxEPCTL_CNAK; /* clear NAK set by core */
1528 ctrl |= DxEPCTL_EPEna; /* ensure ep enabled */
1529 ctrl |= DxEPCTL_USBActEp;
1530 writel(ctrl, hsotg->regs + DIEPCTL0);
1534 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1535 * @hsotg: The device instance
1536 * @epnum: The endpoint received from
1537 * @was_setup: Set if processing a SetupDone event.
1539 * The RXFIFO has delivered an OutDone event, which means that the data
1540 * transfer for an OUT endpoint has been completed, either by a short
1541 * packet or by the finish of a transfer.
1543 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
1544 int epnum, bool was_setup)
1546 u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum));
1547 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
1548 struct s3c_hsotg_req *hs_req = hs_ep->req;
1549 struct usb_request *req = &hs_req->req;
1550 unsigned size_left = DxEPTSIZ_XferSize_GET(epsize);
1554 dev_dbg(hsotg->dev, "%s: no request active\n", __func__);
1558 if (using_dma(hsotg)) {
1562 * Calculate the size of the transfer by checking how much
1563 * is left in the endpoint size register and then working it
1564 * out from the amount we loaded for the transfer.
1566 * We need to do this as DMA pointers are always 32bit aligned
1567 * so may overshoot/undershoot the transfer.
1570 size_done = hs_ep->size_loaded - size_left;
1571 size_done += hs_ep->last_load;
1573 req->actual = size_done;
1576 /* if there is more request to do, schedule new transfer */
1577 if (req->actual < req->length && size_left == 0) {
1578 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1580 } else if (epnum == 0) {
1582 * After was_setup = 1 =>
1583 * set CNAK for non Setup requests
1585 hsotg->setup = was_setup ? 0 : 1;
1588 if (req->actual < req->length && req->short_not_ok) {
1589 dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
1590 __func__, req->actual, req->length);
1593 * todo - what should we return here? there's no one else
1594 * even bothering to check the status.
1600 * Condition req->complete != s3c_hsotg_complete_setup says:
1601 * send ZLP when we have an asynchronous request from gadget
1603 if (!was_setup && req->complete != s3c_hsotg_complete_setup)
1604 s3c_hsotg_send_zlp(hsotg, hs_req);
1607 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, result);
1611 * s3c_hsotg_read_frameno - read current frame number
1612 * @hsotg: The device instance
1614 * Return the current frame number
1616 static u32 s3c_hsotg_read_frameno(struct s3c_hsotg *hsotg)
1620 dsts = readl(hsotg->regs + DSTS);
1621 dsts &= DSTS_SOFFN_MASK;
1622 dsts >>= DSTS_SOFFN_SHIFT;
1628 * s3c_hsotg_handle_rx - RX FIFO has data
1629 * @hsotg: The device instance
1631 * The IRQ handler has detected that the RX FIFO has some data in it
1632 * that requires processing, so find out what is in there and do the
1635 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1636 * chunks, so if you have x packets received on an endpoint you'll get x
1637 * FIFO events delivered, each with a packet's worth of data in it.
1639 * When using DMA, we should not be processing events from the RXFIFO
1640 * as the actual data should be sent to the memory directly and we turn
1641 * on the completion interrupts to get notifications of transfer completion.
1643 static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg)
1645 u32 grxstsr = readl(hsotg->regs + GRXSTSP);
1646 u32 epnum, status, size;
1648 WARN_ON(using_dma(hsotg));
1650 epnum = grxstsr & GRXSTS_EPNum_MASK;
1651 status = grxstsr & GRXSTS_PktSts_MASK;
1653 size = grxstsr & GRXSTS_ByteCnt_MASK;
1654 size >>= GRXSTS_ByteCnt_SHIFT;
1657 dev_dbg(hsotg->dev, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1658 __func__, grxstsr, size, epnum);
1660 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1662 switch (status >> GRXSTS_PktSts_SHIFT) {
1663 case __status(GRXSTS_PktSts_GlobalOutNAK):
1664 dev_dbg(hsotg->dev, "GlobalOutNAK\n");
1667 case __status(GRXSTS_PktSts_OutDone):
1668 dev_dbg(hsotg->dev, "OutDone (Frame=0x%08x)\n",
1669 s3c_hsotg_read_frameno(hsotg));
1671 if (!using_dma(hsotg))
1672 s3c_hsotg_handle_outdone(hsotg, epnum, false);
1675 case __status(GRXSTS_PktSts_SetupDone):
1677 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1678 s3c_hsotg_read_frameno(hsotg),
1679 readl(hsotg->regs + DOEPCTL(0)));
1681 s3c_hsotg_handle_outdone(hsotg, epnum, true);
1684 case __status(GRXSTS_PktSts_OutRX):
1685 s3c_hsotg_rx_data(hsotg, epnum, size);
1688 case __status(GRXSTS_PktSts_SetupRX):
1690 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1691 s3c_hsotg_read_frameno(hsotg),
1692 readl(hsotg->regs + DOEPCTL(0)));
1694 s3c_hsotg_rx_data(hsotg, epnum, size);
1698 dev_warn(hsotg->dev, "%s: unknown status %08x\n",
1701 s3c_hsotg_dump(hsotg);
1707 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1708 * @mps: The maximum packet size in bytes.
1710 static u32 s3c_hsotg_ep0_mps(unsigned int mps)
1714 return D0EPCTL_MPS_64;
1716 return D0EPCTL_MPS_32;
1718 return D0EPCTL_MPS_16;
1720 return D0EPCTL_MPS_8;
1723 /* bad max packet size, warn and return invalid result */
1729 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1730 * @hsotg: The driver state.
1731 * @ep: The index number of the endpoint
1732 * @mps: The maximum packet size in bytes
1734 * Configure the maximum packet size for the given endpoint, updating
1735 * the hardware control registers to reflect this.
1737 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg *hsotg,
1738 unsigned int ep, unsigned int mps)
1740 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[ep];
1741 void __iomem *regs = hsotg->regs;
1747 /* EP0 is a special case */
1748 mpsval = s3c_hsotg_ep0_mps(mps);
1751 hs_ep->ep.maxpacket = mps;
1754 mpsval = mps & DxEPCTL_MPS_MASK;
1757 mcval = ((mps >> 11) & 0x3) + 1;
1761 hs_ep->ep.maxpacket = mpsval;
1765 * update both the in and out endpoint controldir_ registers, even
1766 * if one of the directions may not be in use.
1769 reg = readl(regs + DIEPCTL(ep));
1770 reg &= ~DxEPCTL_MPS_MASK;
1772 writel(reg, regs + DIEPCTL(ep));
1775 reg = readl(regs + DOEPCTL(ep));
1776 reg &= ~DxEPCTL_MPS_MASK;
1778 writel(reg, regs + DOEPCTL(ep));
1784 dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
1788 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1789 * @hsotg: The driver state
1790 * @idx: The index for the endpoint (0..15)
1792 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
1797 writel(GRSTCTL_TxFNum(idx) | GRSTCTL_TxFFlsh,
1798 hsotg->regs + GRSTCTL);
1800 /* wait until the fifo is flushed */
1804 val = readl(hsotg->regs + GRSTCTL);
1806 if ((val & (GRSTCTL_TxFFlsh)) == 0)
1809 if (--timeout == 0) {
1811 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1820 * s3c_hsotg_trytx - check to see if anything needs transmitting
1821 * @hsotg: The driver state
1822 * @hs_ep: The driver endpoint to check.
1824 * Check to see if there is a request that has data to send, and if so
1825 * make an attempt to write data into the FIFO.
1827 static int s3c_hsotg_trytx(struct s3c_hsotg *hsotg,
1828 struct s3c_hsotg_ep *hs_ep)
1830 struct s3c_hsotg_req *hs_req = hs_ep->req;
1832 if (!hs_ep->dir_in || !hs_req) {
1834 * if request is not enqueued, we disable interrupts
1835 * for endpoints, excepting ep0
1837 if (hs_ep->index != 0)
1838 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index,
1843 if (hs_req->req.actual < hs_req->req.length) {
1844 dev_dbg(hsotg->dev, "trying to write more for ep%d\n",
1846 return s3c_hsotg_write_fifo(hsotg, hs_ep, hs_req);
1853 * s3c_hsotg_complete_in - complete IN transfer
1854 * @hsotg: The device state.
1855 * @hs_ep: The endpoint that has just completed.
1857 * An IN transfer has been completed, update the transfer's state and then
1858 * call the relevant completion routines.
1860 static void s3c_hsotg_complete_in(struct s3c_hsotg *hsotg,
1861 struct s3c_hsotg_ep *hs_ep)
1863 struct s3c_hsotg_req *hs_req = hs_ep->req;
1864 u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index));
1865 int size_left, size_done;
1868 dev_dbg(hsotg->dev, "XferCompl but no req\n");
1872 /* Finish ZLP handling for IN EP0 transactions */
1873 if (hsotg->eps[0].sent_zlp) {
1874 dev_dbg(hsotg->dev, "zlp packet received\n");
1875 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1880 * Calculate the size of the transfer by checking how much is left
1881 * in the endpoint size register and then working it out from
1882 * the amount we loaded for the transfer.
1884 * We do this even for DMA, as the transfer may have incremented
1885 * past the end of the buffer (DMA transfers are always 32bit
1889 size_left = DxEPTSIZ_XferSize_GET(epsize);
1891 size_done = hs_ep->size_loaded - size_left;
1892 size_done += hs_ep->last_load;
1894 if (hs_req->req.actual != size_done)
1895 dev_dbg(hsotg->dev, "%s: adjusting size done %d => %d\n",
1896 __func__, hs_req->req.actual, size_done);
1898 hs_req->req.actual = size_done;
1899 dev_dbg(hsotg->dev, "req->length:%d req->actual:%d req->zero:%d\n",
1900 hs_req->req.length, hs_req->req.actual, hs_req->req.zero);
1903 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1904 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1905 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1906 * inform the host that no more data is available.
1907 * The state of req.zero member is checked to be sure that the value to
1908 * send is smaller than wValue expected from host.
1909 * Check req.length to NOT send another ZLP when the current one is
1910 * under completion (the one for which this completion has been called).
1912 if (hs_req->req.length && hs_ep->index == 0 && hs_req->req.zero &&
1913 hs_req->req.length == hs_req->req.actual &&
1914 !(hs_req->req.length % hs_ep->ep.maxpacket)) {
1916 dev_dbg(hsotg->dev, "ep0 zlp IN packet sent\n");
1917 s3c_hsotg_send_zlp(hsotg, hs_req);
1922 if (!size_left && hs_req->req.actual < hs_req->req.length) {
1923 dev_dbg(hsotg->dev, "%s trying more for req...\n", __func__);
1924 s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
1926 s3c_hsotg_complete_request(hsotg, hs_ep, hs_req, 0);
1930 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1931 * @hsotg: The driver state
1932 * @idx: The index for the endpoint (0..15)
1933 * @dir_in: Set if this is an IN endpoint
1935 * Process and clear any interrupt pending for an individual endpoint
1937 static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
1940 struct s3c_hsotg_ep *hs_ep = &hsotg->eps[idx];
1941 u32 epint_reg = dir_in ? DIEPINT(idx) : DOEPINT(idx);
1942 u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx);
1943 u32 epsiz_reg = dir_in ? DIEPTSIZ(idx) : DOEPTSIZ(idx);
1947 ints = readl(hsotg->regs + epint_reg);
1948 ctrl = readl(hsotg->regs + epctl_reg);
1950 /* Clear endpoint interrupts */
1951 writel(ints, hsotg->regs + epint_reg);
1953 dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1954 __func__, idx, dir_in ? "in" : "out", ints);
1956 if (ints & DxEPINT_XferCompl) {
1957 if (hs_ep->isochronous && hs_ep->interval == 1) {
1958 if (ctrl & DxEPCTL_EOFrNum)
1959 ctrl |= DxEPCTL_SetEvenFr;
1961 ctrl |= DxEPCTL_SetOddFr;
1962 writel(ctrl, hsotg->regs + epctl_reg);
1966 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1967 __func__, readl(hsotg->regs + epctl_reg),
1968 readl(hsotg->regs + epsiz_reg));
1971 * we get OutDone from the FIFO, so we only need to look
1972 * at completing IN requests here
1975 s3c_hsotg_complete_in(hsotg, hs_ep);
1977 if (idx == 0 && !hs_ep->req)
1978 s3c_hsotg_enqueue_setup(hsotg);
1979 } else if (using_dma(hsotg)) {
1981 * We're using DMA, we need to fire an OutDone here
1982 * as we ignore the RXFIFO.
1985 s3c_hsotg_handle_outdone(hsotg, idx, false);
1989 if (ints & DxEPINT_EPDisbld) {
1990 dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
1993 int epctl = readl(hsotg->regs + epctl_reg);
1995 s3c_hsotg_txfifo_flush(hsotg, idx);
1997 if ((epctl & DxEPCTL_Stall) &&
1998 (epctl & DxEPCTL_EPType_Bulk)) {
1999 int dctl = readl(hsotg->regs + DCTL);
2001 dctl |= DCTL_CGNPInNAK;
2002 writel(dctl, hsotg->regs + DCTL);
2007 if (ints & DxEPINT_AHBErr)
2008 dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
2010 if (ints & DxEPINT_Setup) { /* Setup or Timeout */
2011 dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
2013 if (using_dma(hsotg) && idx == 0) {
2015 * this is the notification we've received a
2016 * setup packet. In non-DMA mode we'd get this
2017 * from the RXFIFO, instead we need to process
2024 s3c_hsotg_handle_outdone(hsotg, 0, true);
2028 if (ints & DxEPINT_Back2BackSetup)
2029 dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
2031 if (dir_in && !hs_ep->isochronous) {
2032 /* not sure if this is important, but we'll clear it anyway */
2033 if (ints & DIEPMSK_INTknTXFEmpMsk) {
2034 dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
2038 /* this probably means something bad is happening */
2039 if (ints & DIEPMSK_INTknEPMisMsk) {
2040 dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
2044 /* FIFO has space or is empty (see GAHBCFG) */
2045 if (hsotg->dedicated_fifos &&
2046 ints & DIEPMSK_TxFIFOEmpty) {
2047 dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
2049 if (!using_dma(hsotg))
2050 s3c_hsotg_trytx(hsotg, hs_ep);
2056 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2057 * @hsotg: The device state.
2059 * Handle updating the device settings after the enumeration phase has
2062 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg)
2064 u32 dsts = readl(hsotg->regs + DSTS);
2065 int ep0_mps = 0, ep_mps;
2068 * This should signal the finish of the enumeration phase
2069 * of the USB handshaking, so we should now know what rate
2073 dev_dbg(hsotg->dev, "EnumDone (DSTS=0x%08x)\n", dsts);
2076 * note, since we're limited by the size of transfer on EP0, and
2077 * it seems IN transfers must be a even number of packets we do
2078 * not advertise a 64byte MPS on EP0.
2081 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2082 switch (dsts & DSTS_EnumSpd_MASK) {
2083 case DSTS_EnumSpd_FS:
2084 case DSTS_EnumSpd_FS48:
2085 hsotg->gadget.speed = USB_SPEED_FULL;
2086 ep0_mps = EP0_MPS_LIMIT;
2090 case DSTS_EnumSpd_HS:
2091 hsotg->gadget.speed = USB_SPEED_HIGH;
2092 ep0_mps = EP0_MPS_LIMIT;
2096 case DSTS_EnumSpd_LS:
2097 hsotg->gadget.speed = USB_SPEED_LOW;
2099 * note, we don't actually support LS in this driver at the
2100 * moment, and the documentation seems to imply that it isn't
2101 * supported by the PHYs on some of the devices.
2105 dev_info(hsotg->dev, "new device is %s\n",
2106 usb_speed_string(hsotg->gadget.speed));
2109 * we should now know the maximum packet size for an
2110 * endpoint, so set the endpoints to a default value.
2115 s3c_hsotg_set_ep_maxpacket(hsotg, 0, ep0_mps);
2116 for (i = 1; i < hsotg->num_of_eps; i++)
2117 s3c_hsotg_set_ep_maxpacket(hsotg, i, ep_mps);
2120 /* ensure after enumeration our EP0 is active */
2122 s3c_hsotg_enqueue_setup(hsotg);
2124 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2125 readl(hsotg->regs + DIEPCTL0),
2126 readl(hsotg->regs + DOEPCTL0));
2130 * kill_all_requests - remove all requests from the endpoint's queue
2131 * @hsotg: The device state.
2132 * @ep: The endpoint the requests may be on.
2133 * @result: The result code to use.
2134 * @force: Force removal of any current requests
2136 * Go through the requests on the given endpoint and mark them
2137 * completed with the given result code.
2139 static void kill_all_requests(struct s3c_hsotg *hsotg,
2140 struct s3c_hsotg_ep *ep,
2141 int result, bool force)
2143 struct s3c_hsotg_req *req, *treq;
2145 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2147 * currently, we can't do much about an already
2148 * running request on an in endpoint
2151 if (ep->req == req && ep->dir_in && !force)
2154 s3c_hsotg_complete_request(hsotg, ep, req,
2157 if(hsotg->dedicated_fifos)
2158 if ((readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4 < 3072)
2159 s3c_hsotg_txfifo_flush(hsotg, ep->index);
2162 #define call_gadget(_hs, _entry) \
2164 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2165 (_hs)->driver && (_hs)->driver->_entry) { \
2166 spin_unlock(&_hs->lock); \
2167 (_hs)->driver->_entry(&(_hs)->gadget); \
2168 spin_lock(&_hs->lock); \
2173 * s3c_hsotg_disconnect - disconnect service
2174 * @hsotg: The device state.
2176 * The device has been disconnected. Remove all current
2177 * transactions and signal the gadget driver that this
2180 static void s3c_hsotg_disconnect(struct s3c_hsotg *hsotg)
2184 for (ep = 0; ep < hsotg->num_of_eps; ep++)
2185 kill_all_requests(hsotg, &hsotg->eps[ep], -ESHUTDOWN, true);
2187 call_gadget(hsotg, disconnect);
2191 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2192 * @hsotg: The device state:
2193 * @periodic: True if this is a periodic FIFO interrupt
2195 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg *hsotg, bool periodic)
2197 struct s3c_hsotg_ep *ep;
2200 /* look through for any more data to transmit */
2202 for (epno = 0; epno < hsotg->num_of_eps; epno++) {
2203 ep = &hsotg->eps[epno];
2208 if ((periodic && !ep->periodic) ||
2209 (!periodic && ep->periodic))
2212 ret = s3c_hsotg_trytx(hsotg, ep);
2218 /* IRQ flags which will trigger a retry around the IRQ loop */
2219 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2224 * s3c_hsotg_corereset - issue softreset to the core
2225 * @hsotg: The device state
2227 * Issue a soft reset to the core, and await the core finishing it.
2229 static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
2234 dev_dbg(hsotg->dev, "resetting core\n");
2236 /* issue soft reset */
2237 writel(GRSTCTL_CSftRst, hsotg->regs + GRSTCTL);
2241 grstctl = readl(hsotg->regs + GRSTCTL);
2242 } while ((grstctl & GRSTCTL_CSftRst) && timeout-- > 0);
2244 if (grstctl & GRSTCTL_CSftRst) {
2245 dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
2252 u32 grstctl = readl(hsotg->regs + GRSTCTL);
2254 if (timeout-- < 0) {
2255 dev_info(hsotg->dev,
2256 "%s: reset failed, GRSTCTL=%08x\n",
2261 if (!(grstctl & GRSTCTL_AHBIdle))
2264 break; /* reset done */
2267 dev_dbg(hsotg->dev, "reset successful\n");
2272 * s3c_hsotg_core_init - issue softreset to the core
2273 * @hsotg: The device state
2275 * Issue a soft reset to the core, and await the core finishing it.
2277 static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
2279 s3c_hsotg_corereset(hsotg);
2282 * we must now enable ep0 ready for host detection and then
2283 * set configuration.
2286 /* set the PLL on, remove the HNP/SRP and set the PHY */
2287 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) |
2288 (0x5 << 10), hsotg->regs + GUSBCFG);
2290 s3c_hsotg_init_fifo(hsotg);
2292 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2294 writel(1 << 18 | DCFG_DevSpd_HS, hsotg->regs + DCFG);
2296 /* Clear any pending OTG interrupts */
2297 writel(0xffffffff, hsotg->regs + GOTGINT);
2299 /* Clear any pending interrupts */
2300 writel(0xffffffff, hsotg->regs + GINTSTS);
2302 writel(GINTSTS_ErlySusp | GINTSTS_SessReqInt |
2303 GINTSTS_GOUTNakEff | GINTSTS_GINNakEff |
2304 GINTSTS_ConIDStsChng | GINTSTS_USBRst |
2305 GINTSTS_EnumDone | GINTSTS_OTGInt |
2306 GINTSTS_USBSusp | GINTSTS_WkUpInt,
2307 hsotg->regs + GINTMSK);
2309 if (using_dma(hsotg))
2310 writel(GAHBCFG_GlblIntrEn | GAHBCFG_DMAEn |
2311 GAHBCFG_HBstLen_Incr4,
2312 hsotg->regs + GAHBCFG);
2314 writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NPTxFEmpLvl |
2315 GAHBCFG_PTxFEmpLvl) : 0) |
2317 hsotg->regs + GAHBCFG);
2320 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2321 * when we have no data to transfer. Otherwise we get being flooded by
2325 writel(((hsotg->dedicated_fifos) ? DIEPMSK_TxFIFOEmpty |
2326 DIEPMSK_INTknTXFEmpMsk : 0) |
2327 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk |
2328 DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2329 DIEPMSK_INTknEPMisMsk,
2330 hsotg->regs + DIEPMSK);
2333 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2334 * DMA mode we may need this.
2336 writel((using_dma(hsotg) ? (DIEPMSK_XferComplMsk |
2337 DIEPMSK_TimeOUTMsk) : 0) |
2338 DOEPMSK_EPDisbldMsk | DOEPMSK_AHBErrMsk |
2340 hsotg->regs + DOEPMSK);
2342 writel(0, hsotg->regs + DAINTMSK);
2344 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2345 readl(hsotg->regs + DIEPCTL0),
2346 readl(hsotg->regs + DOEPCTL0));
2348 /* enable in and out endpoint interrupts */
2349 s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPInt | GINTSTS_IEPInt);
2352 * Enable the RXFIFO when in slave mode, as this is how we collect
2353 * the data. In DMA mode, we get events from the FIFO but also
2354 * things we cannot process, so do not use it.
2356 if (!using_dma(hsotg))
2357 s3c_hsotg_en_gsint(hsotg, GINTSTS_RxFLvl);
2359 /* Enable interrupts for EP0 in and out */
2360 s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
2361 s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
2363 __orr32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2364 udelay(10); /* see openiboot */
2365 __bic32(hsotg->regs + DCTL, DCTL_PWROnPrgDone);
2367 dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL));
2370 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2371 * writing to the EPCTL register..
2374 /* set to read 1 8byte packet */
2375 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2376 DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
2378 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2379 DxEPCTL_CNAK | DxEPCTL_EPEna |
2381 hsotg->regs + DOEPCTL0);
2383 /* enable, but don't activate EP0in */
2384 writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
2385 DxEPCTL_USBActEp, hsotg->regs + DIEPCTL0);
2387 s3c_hsotg_enqueue_setup(hsotg);
2389 dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2390 readl(hsotg->regs + DIEPCTL0),
2391 readl(hsotg->regs + DOEPCTL0));
2393 /* clear global NAKs */
2394 writel(DCTL_CGOUTNak | DCTL_CGNPInNAK,
2395 hsotg->regs + DCTL);
2397 /* must be at-least 3ms to allow bus to see disconnect */
2400 /* remove the soft-disconnect and let's go */
2401 __bic32(hsotg->regs + DCTL, DCTL_SftDiscon);
2405 * s3c_hsotg_irq - handle device interrupt
2406 * @irq: The IRQ number triggered
2407 * @pw: The pw value when registered the handler.
2409 static irqreturn_t s3c_hsotg_irq(int irq, void *pw)
2411 struct s3c_hsotg *hsotg = pw;
2412 int retry_count = 8;
2416 spin_lock(&hsotg->lock);
2418 gintsts = readl(hsotg->regs + GINTSTS);
2419 gintmsk = readl(hsotg->regs + GINTMSK);
2421 dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n",
2422 __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count);
2426 if (gintsts & GINTSTS_OTGInt) {
2427 u32 otgint = readl(hsotg->regs + GOTGINT);
2429 dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
2431 writel(otgint, hsotg->regs + GOTGINT);
2434 if (gintsts & GINTSTS_SessReqInt) {
2435 dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__);
2436 writel(GINTSTS_SessReqInt, hsotg->regs + GINTSTS);
2439 if (gintsts & GINTSTS_EnumDone) {
2440 writel(GINTSTS_EnumDone, hsotg->regs + GINTSTS);
2442 s3c_hsotg_irq_enumdone(hsotg);
2445 if (gintsts & GINTSTS_ConIDStsChng) {
2446 dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2447 readl(hsotg->regs + DSTS),
2448 readl(hsotg->regs + GOTGCTL));
2450 writel(GINTSTS_ConIDStsChng, hsotg->regs + GINTSTS);
2453 if (gintsts & (GINTSTS_OEPInt | GINTSTS_IEPInt)) {
2454 u32 daint = readl(hsotg->regs + DAINT);
2455 u32 daintmsk = readl(hsotg->regs + DAINTMSK);
2456 u32 daint_out, daint_in;
2460 daint_out = daint >> DAINT_OutEP_SHIFT;
2461 daint_in = daint & ~(daint_out << DAINT_OutEP_SHIFT);
2463 dev_dbg(hsotg->dev, "%s: daint=%08x\n", __func__, daint);
2465 for (ep = 0; ep < 15 && daint_out; ep++, daint_out >>= 1) {
2467 s3c_hsotg_epint(hsotg, ep, 0);
2470 for (ep = 0; ep < 15 && daint_in; ep++, daint_in >>= 1) {
2472 s3c_hsotg_epint(hsotg, ep, 1);
2476 if (gintsts & GINTSTS_USBRst) {
2478 u32 usb_status = readl(hsotg->regs + GOTGCTL);
2480 dev_info(hsotg->dev, "%s: USBRst\n", __func__);
2481 dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
2482 readl(hsotg->regs + GNPTXSTS));
2484 writel(GINTSTS_USBRst, hsotg->regs + GINTSTS);
2486 if (usb_status & GOTGCTL_BSESVLD) {
2487 if (time_after(jiffies, hsotg->last_rst +
2488 msecs_to_jiffies(200))) {
2490 kill_all_requests(hsotg, &hsotg->eps[0],
2493 s3c_hsotg_core_init(hsotg);
2494 hsotg->last_rst = jiffies;
2499 /* check both FIFOs */
2501 if (gintsts & GINTSTS_NPTxFEmp) {
2502 dev_dbg(hsotg->dev, "NPTxFEmp\n");
2505 * Disable the interrupt to stop it happening again
2506 * unless one of these endpoint routines decides that
2507 * it needs re-enabling
2510 s3c_hsotg_disable_gsint(hsotg, GINTSTS_NPTxFEmp);
2511 s3c_hsotg_irq_fifoempty(hsotg, false);
2514 if (gintsts & GINTSTS_PTxFEmp) {
2515 dev_dbg(hsotg->dev, "PTxFEmp\n");
2517 /* See note in GINTSTS_NPTxFEmp */
2519 s3c_hsotg_disable_gsint(hsotg, GINTSTS_PTxFEmp);
2520 s3c_hsotg_irq_fifoempty(hsotg, true);
2523 if (gintsts & GINTSTS_RxFLvl) {
2525 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2526 * we need to retry s3c_hsotg_handle_rx if this is still
2530 s3c_hsotg_handle_rx(hsotg);
2533 if (gintsts & GINTSTS_ModeMis) {
2534 dev_warn(hsotg->dev, "warning, mode mismatch triggered\n");
2535 writel(GINTSTS_ModeMis, hsotg->regs + GINTSTS);
2538 if (gintsts & GINTSTS_USBSusp) {
2539 dev_info(hsotg->dev, "GINTSTS_USBSusp\n");
2540 writel(GINTSTS_USBSusp, hsotg->regs + GINTSTS);
2542 call_gadget(hsotg, suspend);
2545 if (gintsts & GINTSTS_WkUpInt) {
2546 dev_info(hsotg->dev, "GINTSTS_WkUpIn\n");
2547 writel(GINTSTS_WkUpInt, hsotg->regs + GINTSTS);
2549 call_gadget(hsotg, resume);
2552 if (gintsts & GINTSTS_ErlySusp) {
2553 dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n");
2554 writel(GINTSTS_ErlySusp, hsotg->regs + GINTSTS);
2558 * these next two seem to crop-up occasionally causing the core
2559 * to shutdown the USB transfer, so try clearing them and logging
2563 if (gintsts & GINTSTS_GOUTNakEff) {
2564 dev_info(hsotg->dev, "GOUTNakEff triggered\n");
2566 writel(DCTL_CGOUTNak, hsotg->regs + DCTL);
2568 s3c_hsotg_dump(hsotg);
2571 if (gintsts & GINTSTS_GINNakEff) {
2572 dev_info(hsotg->dev, "GINNakEff triggered\n");
2574 writel(DCTL_CGNPInNAK, hsotg->regs + DCTL);
2576 s3c_hsotg_dump(hsotg);
2580 * if we've had fifo events, we should try and go around the
2581 * loop again to see if there's any point in returning yet.
2584 if (gintsts & IRQ_RETRY_MASK && --retry_count > 0)
2587 spin_unlock(&hsotg->lock);
2593 * s3c_hsotg_ep_enable - enable the given endpoint
2594 * @ep: The USB endpint to configure
2595 * @desc: The USB endpoint descriptor to configure with.
2597 * This is called from the USB gadget code's usb_ep_enable().
2599 static int s3c_hsotg_ep_enable(struct usb_ep *ep,
2600 const struct usb_endpoint_descriptor *desc)
2602 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2603 struct s3c_hsotg *hsotg = hs_ep->parent;
2604 unsigned long flags;
2605 int index = hs_ep->index;
2613 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2614 __func__, ep->name, desc->bEndpointAddress, desc->bmAttributes,
2615 desc->wMaxPacketSize, desc->bInterval);
2617 /* not to be called for EP0 */
2618 WARN_ON(index == 0);
2620 dir_in = (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK) ? 1 : 0;
2621 if (dir_in != hs_ep->dir_in) {
2622 dev_err(hsotg->dev, "%s: direction mismatch!\n", __func__);
2626 mps = usb_endpoint_maxp(desc);
2628 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2630 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2631 epctrl = readl(hsotg->regs + epctrl_reg);
2633 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2634 __func__, epctrl, epctrl_reg);
2636 spin_lock_irqsave(&hsotg->lock, flags);
2638 epctrl &= ~(DxEPCTL_EPType_MASK | DxEPCTL_MPS_MASK);
2639 epctrl |= DxEPCTL_MPS(mps);
2642 * mark the endpoint as active, otherwise the core may ignore
2643 * transactions entirely for this endpoint
2645 epctrl |= DxEPCTL_USBActEp;
2648 * set the NAK status on the endpoint, otherwise we might try and
2649 * do something with data that we've yet got a request to process
2650 * since the RXFIFO will take data for an endpoint even if the
2651 * size register hasn't been set.
2654 epctrl |= DxEPCTL_SNAK;
2656 /* update the endpoint state */
2657 s3c_hsotg_set_ep_maxpacket(hsotg, hs_ep->index, mps);
2659 /* default, set to non-periodic */
2660 hs_ep->isochronous = 0;
2661 hs_ep->periodic = 0;
2663 hs_ep->interval = desc->bInterval;
2665 if (hs_ep->interval > 1 && hs_ep->mc > 1)
2666 dev_err(hsotg->dev, "MC > 1 when interval is not 1\n");
2668 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
2669 case USB_ENDPOINT_XFER_ISOC:
2670 epctrl |= DxEPCTL_EPType_Iso;
2671 epctrl |= DxEPCTL_SetEvenFr;
2672 hs_ep->isochronous = 1;
2674 hs_ep->periodic = 1;
2677 case USB_ENDPOINT_XFER_BULK:
2678 epctrl |= DxEPCTL_EPType_Bulk;
2681 case USB_ENDPOINT_XFER_INT:
2684 * Allocate our TxFNum by simply using the index
2685 * of the endpoint for the moment. We could do
2686 * something better if the host indicates how
2687 * many FIFOs we are expecting to use.
2690 hs_ep->periodic = 1;
2691 epctrl |= DxEPCTL_TxFNum(index);
2694 epctrl |= DxEPCTL_EPType_Intterupt;
2697 case USB_ENDPOINT_XFER_CONTROL:
2698 epctrl |= DxEPCTL_EPType_Control;
2703 * if the hardware has dedicated fifos, we must give each IN EP
2704 * a unique tx-fifo even if it is non-periodic.
2706 if (dir_in && hsotg->dedicated_fifos)
2707 epctrl |= DxEPCTL_TxFNum(index);
2709 /* for non control endpoints, set PID to D0 */
2711 epctrl |= DxEPCTL_SetD0PID;
2713 dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n",
2716 writel(epctrl, hsotg->regs + epctrl_reg);
2717 dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n",
2718 __func__, readl(hsotg->regs + epctrl_reg));
2720 /* enable the endpoint interrupt */
2721 s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1);
2723 spin_unlock_irqrestore(&hsotg->lock, flags);
2728 * s3c_hsotg_ep_disable - disable given endpoint
2729 * @ep: The endpoint to disable.
2731 static int s3c_hsotg_ep_disable(struct usb_ep *ep)
2733 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2734 struct s3c_hsotg *hsotg = hs_ep->parent;
2735 int dir_in = hs_ep->dir_in;
2736 int index = hs_ep->index;
2737 unsigned long flags;
2741 dev_info(hsotg->dev, "%s(ep %p)\n", __func__, ep);
2743 if (ep == &hsotg->eps[0].ep) {
2744 dev_err(hsotg->dev, "%s: called for ep0\n", __func__);
2748 epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index);
2750 spin_lock_irqsave(&hsotg->lock, flags);
2751 /* terminate all requests with shutdown */
2752 kill_all_requests(hsotg, hs_ep, -ESHUTDOWN, false);
2755 ctrl = readl(hsotg->regs + epctrl_reg);
2756 ctrl &= ~DxEPCTL_EPEna;
2757 ctrl &= ~DxEPCTL_USBActEp;
2758 ctrl |= DxEPCTL_SNAK;
2760 dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl);
2761 writel(ctrl, hsotg->regs + epctrl_reg);
2763 /* disable endpoint interrupts */
2764 s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0);
2766 spin_unlock_irqrestore(&hsotg->lock, flags);
2771 * on_list - check request is on the given endpoint
2772 * @ep: The endpoint to check.
2773 * @test: The request to test if it is on the endpoint.
2775 static bool on_list(struct s3c_hsotg_ep *ep, struct s3c_hsotg_req *test)
2777 struct s3c_hsotg_req *req, *treq;
2779 list_for_each_entry_safe(req, treq, &ep->queue, queue) {
2788 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2789 * @ep: The endpoint to dequeue.
2790 * @req: The request to be removed from a queue.
2792 static int s3c_hsotg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
2794 struct s3c_hsotg_req *hs_req = our_req(req);
2795 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2796 struct s3c_hsotg *hs = hs_ep->parent;
2797 unsigned long flags;
2799 dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
2801 spin_lock_irqsave(&hs->lock, flags);
2803 if (!on_list(hs_ep, hs_req)) {
2804 spin_unlock_irqrestore(&hs->lock, flags);
2808 s3c_hsotg_complete_request(hs, hs_ep, hs_req, -ECONNRESET);
2809 spin_unlock_irqrestore(&hs->lock, flags);
2815 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2816 * @ep: The endpoint to set halt.
2817 * @value: Set or unset the halt.
2819 static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value)
2821 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2822 struct s3c_hsotg *hs = hs_ep->parent;
2823 int index = hs_ep->index;
2828 dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
2830 /* write both IN and OUT control registers */
2832 epreg = DIEPCTL(index);
2833 epctl = readl(hs->regs + epreg);
2836 epctl |= DxEPCTL_Stall + DxEPCTL_SNAK;
2837 if (epctl & DxEPCTL_EPEna)
2838 epctl |= DxEPCTL_EPDis;
2840 epctl &= ~DxEPCTL_Stall;
2841 xfertype = epctl & DxEPCTL_EPType_MASK;
2842 if (xfertype == DxEPCTL_EPType_Bulk ||
2843 xfertype == DxEPCTL_EPType_Intterupt)
2844 epctl |= DxEPCTL_SetD0PID;
2847 writel(epctl, hs->regs + epreg);
2849 epreg = DOEPCTL(index);
2850 epctl = readl(hs->regs + epreg);
2853 epctl |= DxEPCTL_Stall;
2855 epctl &= ~DxEPCTL_Stall;
2856 xfertype = epctl & DxEPCTL_EPType_MASK;
2857 if (xfertype == DxEPCTL_EPType_Bulk ||
2858 xfertype == DxEPCTL_EPType_Intterupt)
2859 epctl |= DxEPCTL_SetD0PID;
2862 writel(epctl, hs->regs + epreg);
2864 hs_ep->halted = value;
2870 * s3c_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
2871 * @ep: The endpoint to set halt.
2872 * @value: Set or unset the halt.
2874 static int s3c_hsotg_ep_sethalt_lock(struct usb_ep *ep, int value)
2876 struct s3c_hsotg_ep *hs_ep = our_ep(ep);
2877 struct s3c_hsotg *hs = hs_ep->parent;
2878 unsigned long flags = 0;
2881 spin_lock_irqsave(&hs->lock, flags);
2882 ret = s3c_hsotg_ep_sethalt(ep, value);
2883 spin_unlock_irqrestore(&hs->lock, flags);
2888 static struct usb_ep_ops s3c_hsotg_ep_ops = {
2889 .enable = s3c_hsotg_ep_enable,
2890 .disable = s3c_hsotg_ep_disable,
2891 .alloc_request = s3c_hsotg_ep_alloc_request,
2892 .free_request = s3c_hsotg_ep_free_request,
2893 .queue = s3c_hsotg_ep_queue_lock,
2894 .dequeue = s3c_hsotg_ep_dequeue,
2895 .set_halt = s3c_hsotg_ep_sethalt_lock,
2896 /* note, don't believe we have any call for the fifo routines */
2900 * s3c_hsotg_phy_enable - enable platform phy dev
2901 * @hsotg: The driver state
2903 * A wrapper for platform code responsible for controlling
2904 * low-level USB code
2906 static void s3c_hsotg_phy_enable(struct s3c_hsotg *hsotg)
2908 struct platform_device *pdev = to_platform_device(hsotg->dev);
2910 dev_dbg(hsotg->dev, "pdev 0x%p\n", pdev);
2913 usb_phy_init(hsotg->phy);
2914 else if (hsotg->plat->phy_init)
2915 hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
2919 * s3c_hsotg_phy_disable - disable platform phy dev
2920 * @hsotg: The driver state
2922 * A wrapper for platform code responsible for controlling
2923 * low-level USB code
2925 static void s3c_hsotg_phy_disable(struct s3c_hsotg *hsotg)
2927 struct platform_device *pdev = to_platform_device(hsotg->dev);
2930 usb_phy_shutdown(hsotg->phy);
2931 else if (hsotg->plat->phy_exit)
2932 hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
2936 * s3c_hsotg_init - initalize the usb core
2937 * @hsotg: The driver state
2939 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
2941 /* unmask subset of endpoint interrupts */
2943 writel(DIEPMSK_TimeOUTMsk | DIEPMSK_AHBErrMsk |
2944 DIEPMSK_EPDisbldMsk | DIEPMSK_XferComplMsk,
2945 hsotg->regs + DIEPMSK);
2947 writel(DOEPMSK_SetupMsk | DOEPMSK_AHBErrMsk |
2948 DOEPMSK_EPDisbldMsk | DOEPMSK_XferComplMsk,
2949 hsotg->regs + DOEPMSK);
2951 writel(0, hsotg->regs + DAINTMSK);
2953 /* Be in disconnected state until gadget is registered */
2954 __orr32(hsotg->regs + DCTL, DCTL_SftDiscon);
2957 /* post global nak until we're ready */
2958 writel(DCTL_SGNPInNAK | DCTL_SGOUTNak,
2959 hsotg->regs + DCTL);
2964 dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2965 readl(hsotg->regs + GRXFSIZ),
2966 readl(hsotg->regs + GNPTXFSIZ));
2968 s3c_hsotg_init_fifo(hsotg);
2970 /* set the PLL on, remove the HNP/SRP and set the PHY */
2971 writel(GUSBCFG_PHYIf16 | GUSBCFG_TOutCal(7) | (0x5 << 10),
2972 hsotg->regs + GUSBCFG);
2974 writel(using_dma(hsotg) ? GAHBCFG_DMAEn : 0x0,
2975 hsotg->regs + GAHBCFG);
2979 * s3c_hsotg_udc_start - prepare the udc for work
2980 * @gadget: The usb gadget state
2981 * @driver: The usb gadget driver
2983 * Perform initialization to prepare udc device and driver
2986 static int s3c_hsotg_udc_start(struct usb_gadget *gadget,
2987 struct usb_gadget_driver *driver)
2989 struct s3c_hsotg *hsotg = to_hsotg(gadget);
2993 pr_err("%s: called with no device\n", __func__);
2998 dev_err(hsotg->dev, "%s: no driver\n", __func__);
3002 if (driver->max_speed < USB_SPEED_FULL)
3003 dev_err(hsotg->dev, "%s: bad speed\n", __func__);
3005 if (!driver->setup) {
3006 dev_err(hsotg->dev, "%s: missing entry points\n", __func__);
3010 WARN_ON(hsotg->driver);
3012 driver->driver.bus = NULL;
3013 hsotg->driver = driver;
3014 hsotg->gadget.dev.of_node = hsotg->dev->of_node;
3015 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3017 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3020 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3024 hsotg->last_rst = jiffies;
3025 dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
3029 hsotg->driver = NULL;
3034 * s3c_hsotg_udc_stop - stop the udc
3035 * @gadget: The usb gadget state
3036 * @driver: The usb gadget driver
3038 * Stop udc hw block and stay tunned for future transmissions
3040 static int s3c_hsotg_udc_stop(struct usb_gadget *gadget,
3041 struct usb_gadget_driver *driver)
3043 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3044 unsigned long flags = 0;
3050 /* all endpoints should be shutdown */
3051 for (ep = 0; ep < hsotg->num_of_eps; ep++)
3052 s3c_hsotg_ep_disable(&hsotg->eps[ep].ep);
3054 spin_lock_irqsave(&hsotg->lock, flags);
3056 s3c_hsotg_phy_disable(hsotg);
3059 hsotg->driver = NULL;
3061 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3063 spin_unlock_irqrestore(&hsotg->lock, flags);
3065 regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies), hsotg->supplies);
3071 * s3c_hsotg_gadget_getframe - read the frame number
3072 * @gadget: The usb gadget state
3074 * Read the {micro} frame number
3076 static int s3c_hsotg_gadget_getframe(struct usb_gadget *gadget)
3078 return s3c_hsotg_read_frameno(to_hsotg(gadget));
3082 * s3c_hsotg_pullup - connect/disconnect the USB PHY
3083 * @gadget: The usb gadget state
3084 * @is_on: Current state of the USB PHY
3086 * Connect/Disconnect the USB PHY pullup
3088 static int s3c_hsotg_pullup(struct usb_gadget *gadget, int is_on)
3090 struct s3c_hsotg *hsotg = to_hsotg(gadget);
3091 unsigned long flags = 0;
3093 dev_dbg(hsotg->dev, "%s: is_in: %d\n", __func__, is_on);
3095 spin_lock_irqsave(&hsotg->lock, flags);
3097 s3c_hsotg_phy_enable(hsotg);
3098 s3c_hsotg_core_init(hsotg);
3100 s3c_hsotg_disconnect(hsotg);
3101 s3c_hsotg_phy_disable(hsotg);
3104 hsotg->gadget.speed = USB_SPEED_UNKNOWN;
3105 spin_unlock_irqrestore(&hsotg->lock, flags);
3110 static const struct usb_gadget_ops s3c_hsotg_gadget_ops = {
3111 .get_frame = s3c_hsotg_gadget_getframe,
3112 .udc_start = s3c_hsotg_udc_start,
3113 .udc_stop = s3c_hsotg_udc_stop,
3114 .pullup = s3c_hsotg_pullup,
3118 * s3c_hsotg_initep - initialise a single endpoint
3119 * @hsotg: The device state.
3120 * @hs_ep: The endpoint to be initialised.
3121 * @epnum: The endpoint number
3123 * Initialise the given endpoint (as part of the probe and device state
3124 * creation) to give to the gadget driver. Setup the endpoint name, any
3125 * direction information and other state that may be required.
3127 static void s3c_hsotg_initep(struct s3c_hsotg *hsotg,
3128 struct s3c_hsotg_ep *hs_ep,
3136 else if ((epnum % 2) == 0) {
3143 hs_ep->index = epnum;
3145 snprintf(hs_ep->name, sizeof(hs_ep->name), "ep%d%s", epnum, dir);
3147 INIT_LIST_HEAD(&hs_ep->queue);
3148 INIT_LIST_HEAD(&hs_ep->ep.ep_list);
3150 /* add to the list of endpoints known by the gadget driver */
3152 list_add_tail(&hs_ep->ep.ep_list, &hsotg->gadget.ep_list);
3154 hs_ep->parent = hsotg;
3155 hs_ep->ep.name = hs_ep->name;
3156 usb_ep_set_maxpacket_limit(&hs_ep->ep, epnum ? 1024 : EP0_MPS_LIMIT);
3157 hs_ep->ep.ops = &s3c_hsotg_ep_ops;
3160 * Read the FIFO size for the Periodic TX FIFO, even if we're
3161 * an OUT endpoint, we may as well do this if in future the
3162 * code is changed to make each endpoint's direction changeable.
3165 ptxfifo = readl(hsotg->regs + DPTXFSIZn(epnum));
3166 hs_ep->fifo_size = DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
3169 * if we're using dma, we need to set the next-endpoint pointer
3170 * to be something valid.
3173 if (using_dma(hsotg)) {
3174 u32 next = DxEPCTL_NextEp((epnum + 1) % 15);
3175 writel(next, hsotg->regs + DIEPCTL(epnum));
3176 writel(next, hsotg->regs + DOEPCTL(epnum));
3181 * s3c_hsotg_hw_cfg - read HW configuration registers
3182 * @param: The device state
3184 * Read the USB core HW configuration registers
3186 static void s3c_hsotg_hw_cfg(struct s3c_hsotg *hsotg)
3189 /* check hardware configuration */
3191 cfg2 = readl(hsotg->regs + 0x48);
3192 hsotg->num_of_eps = (cfg2 >> 10) & 0xF;
3194 dev_info(hsotg->dev, "EPs:%d\n", hsotg->num_of_eps);
3196 cfg4 = readl(hsotg->regs + 0x50);
3197 hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
3199 dev_info(hsotg->dev, "%s fifos\n",
3200 hsotg->dedicated_fifos ? "dedicated" : "shared");
3204 * s3c_hsotg_dump - dump state of the udc
3205 * @param: The device state
3207 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
3210 struct device *dev = hsotg->dev;
3211 void __iomem *regs = hsotg->regs;
3215 dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3216 readl(regs + DCFG), readl(regs + DCTL),
3217 readl(regs + DIEPMSK));
3219 dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3220 readl(regs + GAHBCFG), readl(regs + 0x44));
3222 dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3223 readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ));
3225 /* show periodic fifo settings */
3227 for (idx = 1; idx <= 15; idx++) {
3228 val = readl(regs + DPTXFSIZn(idx));
3229 dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx,
3230 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3231 val & DPTXFSIZn_DPTxFStAddr_MASK);
3234 for (idx = 0; idx < 15; idx++) {
3236 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx,
3237 readl(regs + DIEPCTL(idx)),
3238 readl(regs + DIEPTSIZ(idx)),
3239 readl(regs + DIEPDMA(idx)));
3241 val = readl(regs + DOEPCTL(idx));
3243 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3244 idx, readl(regs + DOEPCTL(idx)),
3245 readl(regs + DOEPTSIZ(idx)),
3246 readl(regs + DOEPDMA(idx)));
3250 dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3251 readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE));
3256 * state_show - debugfs: show overall driver and device state.
3257 * @seq: The seq file to write to.
3258 * @v: Unused parameter.
3260 * This debugfs entry shows the overall state of the hardware and
3261 * some general information about each of the endpoints available
3264 static int state_show(struct seq_file *seq, void *v)
3266 struct s3c_hsotg *hsotg = seq->private;
3267 void __iomem *regs = hsotg->regs;
3270 seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3273 readl(regs + DSTS));
3275 seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3276 readl(regs + DIEPMSK), readl(regs + DOEPMSK));
3278 seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3279 readl(regs + GINTMSK),
3280 readl(regs + GINTSTS));
3282 seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3283 readl(regs + DAINTMSK),
3284 readl(regs + DAINT));
3286 seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3287 readl(regs + GNPTXSTS),
3288 readl(regs + GRXSTSR));
3290 seq_puts(seq, "\nEndpoint status:\n");
3292 for (idx = 0; idx < 15; idx++) {
3295 in = readl(regs + DIEPCTL(idx));
3296 out = readl(regs + DOEPCTL(idx));
3298 seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3301 in = readl(regs + DIEPTSIZ(idx));
3302 out = readl(regs + DOEPTSIZ(idx));
3304 seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3307 seq_puts(seq, "\n");
3313 static int state_open(struct inode *inode, struct file *file)
3315 return single_open(file, state_show, inode->i_private);
3318 static const struct file_operations state_fops = {
3319 .owner = THIS_MODULE,
3322 .llseek = seq_lseek,
3323 .release = single_release,
3327 * fifo_show - debugfs: show the fifo information
3328 * @seq: The seq_file to write data to.
3329 * @v: Unused parameter.
3331 * Show the FIFO information for the overall fifo and all the
3332 * periodic transmission FIFOs.
3334 static int fifo_show(struct seq_file *seq, void *v)
3336 struct s3c_hsotg *hsotg = seq->private;
3337 void __iomem *regs = hsotg->regs;
3341 seq_puts(seq, "Non-periodic FIFOs:\n");
3342 seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ));
3344 val = readl(regs + GNPTXFSIZ);
3345 seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n",
3346 val >> GNPTXFSIZ_NPTxFDep_SHIFT,
3347 val & GNPTXFSIZ_NPTxFStAddr_MASK);
3349 seq_puts(seq, "\nPeriodic TXFIFOs:\n");
3351 for (idx = 1; idx <= 15; idx++) {
3352 val = readl(regs + DPTXFSIZn(idx));
3354 seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx,
3355 val >> DPTXFSIZn_DPTxFSize_SHIFT,
3356 val & DPTXFSIZn_DPTxFStAddr_MASK);
3362 static int fifo_open(struct inode *inode, struct file *file)
3364 return single_open(file, fifo_show, inode->i_private);
3367 static const struct file_operations fifo_fops = {
3368 .owner = THIS_MODULE,
3371 .llseek = seq_lseek,
3372 .release = single_release,
3376 static const char *decode_direction(int is_in)
3378 return is_in ? "in" : "out";
3382 * ep_show - debugfs: show the state of an endpoint.
3383 * @seq: The seq_file to write data to.
3384 * @v: Unused parameter.
3386 * This debugfs entry shows the state of the given endpoint (one is
3387 * registered for each available).
3389 static int ep_show(struct seq_file *seq, void *v)
3391 struct s3c_hsotg_ep *ep = seq->private;
3392 struct s3c_hsotg *hsotg = ep->parent;
3393 struct s3c_hsotg_req *req;
3394 void __iomem *regs = hsotg->regs;
3395 int index = ep->index;
3396 int show_limit = 15;
3397 unsigned long flags;
3399 seq_printf(seq, "Endpoint index %d, named %s, dir %s:\n",
3400 ep->index, ep->ep.name, decode_direction(ep->dir_in));
3402 /* first show the register state */
3404 seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3405 readl(regs + DIEPCTL(index)),
3406 readl(regs + DOEPCTL(index)));
3408 seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3409 readl(regs + DIEPDMA(index)),
3410 readl(regs + DOEPDMA(index)));
3412 seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3413 readl(regs + DIEPINT(index)),
3414 readl(regs + DOEPINT(index)));
3416 seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3417 readl(regs + DIEPTSIZ(index)),
3418 readl(regs + DOEPTSIZ(index)));
3420 seq_puts(seq, "\n");
3421 seq_printf(seq, "mps %d\n", ep->ep.maxpacket);
3422 seq_printf(seq, "total_data=%ld\n", ep->total_data);
3424 seq_printf(seq, "request list (%p,%p):\n",
3425 ep->queue.next, ep->queue.prev);
3427 spin_lock_irqsave(&hsotg->lock, flags);
3429 list_for_each_entry(req, &ep->queue, queue) {
3430 if (--show_limit < 0) {
3431 seq_puts(seq, "not showing more requests...\n");
3435 seq_printf(seq, "%c req %p: %d bytes @%p, ",
3436 req == ep->req ? '*' : ' ',
3437 req, req->req.length, req->req.buf);
3438 seq_printf(seq, "%d done, res %d\n",
3439 req->req.actual, req->req.status);
3442 spin_unlock_irqrestore(&hsotg->lock, flags);
3447 static int ep_open(struct inode *inode, struct file *file)
3449 return single_open(file, ep_show, inode->i_private);
3452 static const struct file_operations ep_fops = {
3453 .owner = THIS_MODULE,
3456 .llseek = seq_lseek,
3457 .release = single_release,
3461 * s3c_hsotg_create_debug - create debugfs directory and files
3462 * @hsotg: The driver state
3464 * Create the debugfs files to allow the user to get information
3465 * about the state of the system. The directory name is created
3466 * with the same name as the device itself, in case we end up
3467 * with multiple blocks in future systems.
3469 static void s3c_hsotg_create_debug(struct s3c_hsotg *hsotg)
3471 struct dentry *root;
3474 root = debugfs_create_dir(dev_name(hsotg->dev), NULL);
3475 hsotg->debug_root = root;
3477 dev_err(hsotg->dev, "cannot create debug root\n");
3481 /* create general state file */
3483 hsotg->debug_file = debugfs_create_file("state", 0444, root,
3484 hsotg, &state_fops);
3486 if (IS_ERR(hsotg->debug_file))
3487 dev_err(hsotg->dev, "%s: failed to create state\n", __func__);
3489 hsotg->debug_fifo = debugfs_create_file("fifo", 0444, root,
3492 if (IS_ERR(hsotg->debug_fifo))
3493 dev_err(hsotg->dev, "%s: failed to create fifo\n", __func__);
3495 /* create one file for each endpoint */
3497 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3498 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3500 ep->debugfs = debugfs_create_file(ep->name, 0444,
3501 root, ep, &ep_fops);
3503 if (IS_ERR(ep->debugfs))
3504 dev_err(hsotg->dev, "failed to create %s debug file\n",
3510 * s3c_hsotg_delete_debug - cleanup debugfs entries
3511 * @hsotg: The driver state
3513 * Cleanup (remove) the debugfs files for use on module exit.
3515 static void s3c_hsotg_delete_debug(struct s3c_hsotg *hsotg)
3519 for (epidx = 0; epidx < hsotg->num_of_eps; epidx++) {
3520 struct s3c_hsotg_ep *ep = &hsotg->eps[epidx];
3521 debugfs_remove(ep->debugfs);
3524 debugfs_remove(hsotg->debug_file);
3525 debugfs_remove(hsotg->debug_fifo);
3526 debugfs_remove(hsotg->debug_root);
3530 * s3c_hsotg_probe - probe function for hsotg driver
3531 * @pdev: The platform information for the driver
3534 static int s3c_hsotg_probe(struct platform_device *pdev)
3536 struct s3c_hsotg_plat *plat = dev_get_platdata(&pdev->dev);
3537 struct usb_phy *phy;
3538 struct device *dev = &pdev->dev;
3539 struct s3c_hsotg_ep *eps;
3540 struct s3c_hsotg *hsotg;
3541 struct resource *res;
3546 hsotg = devm_kzalloc(&pdev->dev, sizeof(struct s3c_hsotg), GFP_KERNEL);
3548 dev_err(dev, "cannot get memory\n");
3552 phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
3554 /* Fallback for pdata */
3555 plat = dev_get_platdata(&pdev->dev);
3557 dev_err(&pdev->dev, "no platform data or transceiver defined\n");
3558 return -EPROBE_DEFER;
3568 hsotg->clk = devm_clk_get(&pdev->dev, "otg");
3569 if (IS_ERR(hsotg->clk)) {
3570 dev_err(dev, "cannot get otg clock\n");
3571 return PTR_ERR(hsotg->clk);
3574 platform_set_drvdata(pdev, hsotg);
3576 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3578 hsotg->regs = devm_ioremap_resource(&pdev->dev, res);
3579 if (IS_ERR(hsotg->regs)) {
3580 ret = PTR_ERR(hsotg->regs);
3584 ret = platform_get_irq(pdev, 0);
3586 dev_err(dev, "cannot find IRQ\n");
3590 spin_lock_init(&hsotg->lock);
3594 ret = devm_request_irq(&pdev->dev, hsotg->irq, s3c_hsotg_irq, 0,
3595 dev_name(dev), hsotg);
3597 dev_err(dev, "cannot claim IRQ\n");
3601 dev_info(dev, "regs %p, irq %d\n", hsotg->regs, hsotg->irq);
3603 hsotg->gadget.max_speed = USB_SPEED_HIGH;
3604 hsotg->gadget.ops = &s3c_hsotg_gadget_ops;
3605 hsotg->gadget.name = dev_name(dev);
3607 /* reset the system */
3609 clk_prepare_enable(hsotg->clk);
3613 for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
3614 hsotg->supplies[i].supply = s3c_hsotg_supply_names[i];
3616 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(hsotg->supplies),
3619 dev_err(dev, "failed to request supplies: %d\n", ret);
3623 ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
3627 dev_err(hsotg->dev, "failed to enable supplies: %d\n", ret);
3631 /* usb phy enable */
3632 s3c_hsotg_phy_enable(hsotg);
3634 s3c_hsotg_corereset(hsotg);
3635 s3c_hsotg_init(hsotg);
3636 s3c_hsotg_hw_cfg(hsotg);
3638 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3640 if (hsotg->num_of_eps == 0) {
3641 dev_err(dev, "wrong number of EPs (zero)\n");
3646 eps = kcalloc(hsotg->num_of_eps + 1, sizeof(struct s3c_hsotg_ep),
3649 dev_err(dev, "cannot get memory\n");
3656 /* setup endpoint information */
3658 INIT_LIST_HEAD(&hsotg->gadget.ep_list);
3659 hsotg->gadget.ep0 = &hsotg->eps[0].ep;
3661 /* allocate EP0 request */
3663 hsotg->ctrl_req = s3c_hsotg_ep_alloc_request(&hsotg->eps[0].ep,
3665 if (!hsotg->ctrl_req) {
3666 dev_err(dev, "failed to allocate ctrl req\n");
3671 /* initialise the endpoints now the core has been initialised */
3672 for (epnum = 0; epnum < hsotg->num_of_eps; epnum++)
3673 s3c_hsotg_initep(hsotg, &hsotg->eps[epnum], epnum);
3675 /* disable power and clock */
3677 ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
3680 dev_err(hsotg->dev, "failed to disable supplies: %d\n", ret);
3684 s3c_hsotg_phy_disable(hsotg);
3686 ret = usb_add_gadget_udc(&pdev->dev, &hsotg->gadget);
3690 s3c_hsotg_create_debug(hsotg);
3692 s3c_hsotg_dump(hsotg);
3699 s3c_hsotg_phy_disable(hsotg);
3701 clk_disable_unprepare(hsotg->clk);
3707 * s3c_hsotg_remove - remove function for hsotg driver
3708 * @pdev: The platform information for the driver
3710 static int s3c_hsotg_remove(struct platform_device *pdev)
3712 struct s3c_hsotg *hsotg = platform_get_drvdata(pdev);
3714 usb_del_gadget_udc(&hsotg->gadget);
3716 s3c_hsotg_delete_debug(hsotg);
3718 if (hsotg->driver) {
3719 /* should have been done already by driver model core */
3720 usb_gadget_unregister_driver(hsotg->driver);
3723 s3c_hsotg_phy_disable(hsotg);
3724 clk_disable_unprepare(hsotg->clk);
3730 #define s3c_hsotg_suspend NULL
3731 #define s3c_hsotg_resume NULL
3735 static const struct of_device_id s3c_hsotg_of_ids[] = {
3736 { .compatible = "samsung,s3c6400-hsotg", },
3737 { .compatible = "snps,dwc2", },
3740 MODULE_DEVICE_TABLE(of, s3c_hsotg_of_ids);
3743 static struct platform_driver s3c_hsotg_driver = {
3745 .name = "s3c-hsotg",
3746 .owner = THIS_MODULE,
3747 .of_match_table = of_match_ptr(s3c_hsotg_of_ids),
3749 .probe = s3c_hsotg_probe,
3750 .remove = s3c_hsotg_remove,
3751 .suspend = s3c_hsotg_suspend,
3752 .resume = s3c_hsotg_resume,
3755 module_platform_driver(s3c_hsotg_driver);
3757 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3758 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3759 MODULE_LICENSE("GPL");
3760 MODULE_ALIAS("platform:s3c-hsotg");