2 * Handles the Intel 27x USB Device Controller (UDC)
4 * Inspired by original driver by Frank Becker, David Brownell, and others.
5 * Copyright (C) 2008 Robert Jarzmik
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/types.h>
15 #include <linux/errno.h>
16 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <linux/delay.h>
19 #include <linux/list.h>
20 #include <linux/interrupt.h>
21 #include <linux/proc_fs.h>
22 #include <linux/clk.h>
23 #include <linux/irq.h>
24 #include <linux/gpio.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/slab.h>
27 #include <linux/prefetch.h>
28 #include <linux/byteorder/generic.h>
29 #include <linux/platform_data/pxa2xx_udc.h>
31 #include <linux/usb.h>
32 #include <linux/usb/ch9.h>
33 #include <linux/usb/gadget.h>
35 #include "pxa27x_udc.h"
38 * This driver handles the USB Device Controller (UDC) in Intel's PXA 27x
41 * Such controller drivers work with a gadget driver. The gadget driver
42 * returns descriptors, implements configuration and data protocols used
43 * by the host to interact with this device, and allocates endpoints to
44 * the different protocol interfaces. The controller driver virtualizes
45 * usb hardware so that the gadget drivers will be more portable.
47 * This UDC hardware wants to implement a bit too much USB protocol. The
48 * biggest issues are: that the endpoints have to be set up before the
49 * controller can be enabled (minor, and not uncommon); and each endpoint
50 * can only have one configuration, interface and alternative interface
51 * number (major, and very unusual). Once set up, these cannot be changed
52 * without a controller reset.
54 * The workaround is to setup all combinations necessary for the gadgets which
55 * will work with this driver. This is done in pxa_udc structure, statically.
56 * See pxa_udc, udc_usb_ep versus pxa_ep, and matching function find_pxa_ep.
57 * (You could modify this if needed. Some drivers have a "fifo_mode" module
58 * parameter to facilitate such changes.)
60 * The combinations have been tested with these gadgets :
62 * - file storage gadget
65 * The driver doesn't use DMA, only IO access and IRQ callbacks. No use is
66 * made of UDC's double buffering either. USB "On-The-Go" is not implemented.
68 * All the requests are handled the same way :
69 * - the drivers tries to handle the request directly to the IO
70 * - if the IO fifo is not big enough, the remaining is send/received in
74 #define DRIVER_VERSION "2008-04-18"
75 #define DRIVER_DESC "PXA 27x USB Device Controller driver"
77 static const char driver_name[] = "pxa27x_udc";
78 static struct pxa_udc *the_controller;
80 static void handle_ep(struct pxa_ep *ep);
85 #ifdef CONFIG_USB_GADGET_DEBUG_FS
87 #include <linux/debugfs.h>
88 #include <linux/uaccess.h>
89 #include <linux/seq_file.h>
91 static int state_dbg_show(struct seq_file *s, void *p)
93 struct pxa_udc *udc = s->private;
101 /* basic device status */
102 pos += seq_printf(s, DRIVER_DESC "\n"
103 "%s version: %s\nGadget driver: %s\n",
104 driver_name, DRIVER_VERSION,
105 udc->driver ? udc->driver->driver.name : "(none)");
107 tmp = udc_readl(udc, UDCCR);
109 "udccr=0x%0x(%s%s%s%s%s%s%s%s%s%s), "
110 "con=%d,inter=%d,altinter=%d\n", tmp,
111 (tmp & UDCCR_OEN) ? " oen":"",
112 (tmp & UDCCR_AALTHNP) ? " aalthnp":"",
113 (tmp & UDCCR_AHNP) ? " rem" : "",
114 (tmp & UDCCR_BHNP) ? " rstir" : "",
115 (tmp & UDCCR_DWRE) ? " dwre" : "",
116 (tmp & UDCCR_SMAC) ? " smac" : "",
117 (tmp & UDCCR_EMCE) ? " emce" : "",
118 (tmp & UDCCR_UDR) ? " udr" : "",
119 (tmp & UDCCR_UDA) ? " uda" : "",
120 (tmp & UDCCR_UDE) ? " ude" : "",
121 (tmp & UDCCR_ACN) >> UDCCR_ACN_S,
122 (tmp & UDCCR_AIN) >> UDCCR_AIN_S,
123 (tmp & UDCCR_AAISN) >> UDCCR_AAISN_S);
124 /* registers for device and ep0 */
125 pos += seq_printf(s, "udcicr0=0x%08x udcicr1=0x%08x\n",
126 udc_readl(udc, UDCICR0), udc_readl(udc, UDCICR1));
127 pos += seq_printf(s, "udcisr0=0x%08x udcisr1=0x%08x\n",
128 udc_readl(udc, UDCISR0), udc_readl(udc, UDCISR1));
129 pos += seq_printf(s, "udcfnr=%d\n", udc_readl(udc, UDCFNR));
130 pos += seq_printf(s, "irqs: reset=%lu, suspend=%lu, resume=%lu, "
132 udc->stats.irqs_reset, udc->stats.irqs_suspend,
133 udc->stats.irqs_resume, udc->stats.irqs_reconfig);
140 static int queues_dbg_show(struct seq_file *s, void *p)
142 struct pxa_udc *udc = s->private;
144 struct pxa27x_request *req;
145 int pos = 0, i, maxpkt, ret;
151 /* dump endpoint queues */
152 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
153 ep = &udc->pxa_ep[i];
154 maxpkt = ep->fifo_size;
155 pos += seq_printf(s, "%-12s max_pkt=%d %s\n",
156 EPNAME(ep), maxpkt, "pio");
158 if (list_empty(&ep->queue)) {
159 pos += seq_printf(s, "\t(nothing queued)\n");
163 list_for_each_entry(req, &ep->queue, queue) {
164 pos += seq_printf(s, "\treq %p len %d/%d buf %p\n",
165 &req->req, req->req.actual,
166 req->req.length, req->req.buf);
175 static int eps_dbg_show(struct seq_file *s, void *p)
177 struct pxa_udc *udc = s->private;
186 ep = &udc->pxa_ep[0];
187 tmp = udc_ep_readl(ep, UDCCSR);
188 pos += seq_printf(s, "udccsr0=0x%03x(%s%s%s%s%s%s%s)\n", tmp,
189 (tmp & UDCCSR0_SA) ? " sa" : "",
190 (tmp & UDCCSR0_RNE) ? " rne" : "",
191 (tmp & UDCCSR0_FST) ? " fst" : "",
192 (tmp & UDCCSR0_SST) ? " sst" : "",
193 (tmp & UDCCSR0_DME) ? " dme" : "",
194 (tmp & UDCCSR0_IPR) ? " ipr" : "",
195 (tmp & UDCCSR0_OPC) ? " opc" : "");
196 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
197 ep = &udc->pxa_ep[i];
198 tmp = i? udc_ep_readl(ep, UDCCR) : udc_readl(udc, UDCCR);
199 pos += seq_printf(s, "%-12s: "
200 "IN %lu(%lu reqs), OUT %lu(%lu reqs), "
201 "irqs=%lu, udccr=0x%08x, udccsr=0x%03x, "
204 ep->stats.in_bytes, ep->stats.in_ops,
205 ep->stats.out_bytes, ep->stats.out_ops,
207 tmp, udc_ep_readl(ep, UDCCSR),
208 udc_ep_readl(ep, UDCBCR));
216 static int eps_dbg_open(struct inode *inode, struct file *file)
218 return single_open(file, eps_dbg_show, inode->i_private);
221 static int queues_dbg_open(struct inode *inode, struct file *file)
223 return single_open(file, queues_dbg_show, inode->i_private);
226 static int state_dbg_open(struct inode *inode, struct file *file)
228 return single_open(file, state_dbg_show, inode->i_private);
231 static const struct file_operations state_dbg_fops = {
232 .owner = THIS_MODULE,
233 .open = state_dbg_open,
236 .release = single_release,
239 static const struct file_operations queues_dbg_fops = {
240 .owner = THIS_MODULE,
241 .open = queues_dbg_open,
244 .release = single_release,
247 static const struct file_operations eps_dbg_fops = {
248 .owner = THIS_MODULE,
249 .open = eps_dbg_open,
252 .release = single_release,
255 static void pxa_init_debugfs(struct pxa_udc *udc)
257 struct dentry *root, *state, *queues, *eps;
259 root = debugfs_create_dir(udc->gadget.name, NULL);
260 if (IS_ERR(root) || !root)
263 state = debugfs_create_file("udcstate", 0400, root, udc,
267 queues = debugfs_create_file("queues", 0400, root, udc,
271 eps = debugfs_create_file("epstate", 0400, root, udc,
276 udc->debugfs_root = root;
277 udc->debugfs_state = state;
278 udc->debugfs_queues = queues;
279 udc->debugfs_eps = eps;
284 debugfs_remove(queues);
286 debugfs_remove(root);
288 dev_err(udc->dev, "debugfs is not available\n");
291 static void pxa_cleanup_debugfs(struct pxa_udc *udc)
293 debugfs_remove(udc->debugfs_eps);
294 debugfs_remove(udc->debugfs_queues);
295 debugfs_remove(udc->debugfs_state);
296 debugfs_remove(udc->debugfs_root);
297 udc->debugfs_eps = NULL;
298 udc->debugfs_queues = NULL;
299 udc->debugfs_state = NULL;
300 udc->debugfs_root = NULL;
304 static inline void pxa_init_debugfs(struct pxa_udc *udc)
308 static inline void pxa_cleanup_debugfs(struct pxa_udc *udc)
314 * is_match_usb_pxa - check if usb_ep and pxa_ep match
315 * @udc_usb_ep: usb endpoint
317 * @config: configuration required in pxa_ep
318 * @interface: interface required in pxa_ep
319 * @altsetting: altsetting required in pxa_ep
321 * Returns 1 if all criteria match between pxa and usb endpoint, 0 otherwise
323 static int is_match_usb_pxa(struct udc_usb_ep *udc_usb_ep, struct pxa_ep *ep,
324 int config, int interface, int altsetting)
326 if (usb_endpoint_num(&udc_usb_ep->desc) != ep->addr)
328 if (usb_endpoint_dir_in(&udc_usb_ep->desc) != ep->dir_in)
330 if (usb_endpoint_type(&udc_usb_ep->desc) != ep->type)
332 if ((ep->config != config) || (ep->interface != interface)
333 || (ep->alternate != altsetting))
339 * find_pxa_ep - find pxa_ep structure matching udc_usb_ep
341 * @udc_usb_ep: udc_usb_ep structure
343 * Match udc_usb_ep and all pxa_ep available, to see if one matches.
344 * This is necessary because of the strong pxa hardware restriction requiring
345 * that once pxa endpoints are initialized, their configuration is freezed, and
346 * no change can be made to their address, direction, or in which configuration,
347 * interface or altsetting they are active ... which differs from more usual
348 * models which have endpoints be roughly just addressable fifos, and leave
349 * configuration events up to gadget drivers (like all control messages).
351 * Note that there is still a blurred point here :
352 * - we rely on UDCCR register "active interface" and "active altsetting".
353 * This is a nonsense in regard of USB spec, where multiple interfaces are
354 * active at the same time.
355 * - if we knew for sure that the pxa can handle multiple interface at the
356 * same time, assuming Intel's Developer Guide is wrong, this function
357 * should be reviewed, and a cache of couples (iface, altsetting) should
358 * be kept in the pxa_udc structure. In this case this function would match
359 * against the cache of couples instead of the "last altsetting" set up.
361 * Returns the matched pxa_ep structure or NULL if none found
363 static struct pxa_ep *find_pxa_ep(struct pxa_udc *udc,
364 struct udc_usb_ep *udc_usb_ep)
368 int cfg = udc->config;
369 int iface = udc->last_interface;
370 int alt = udc->last_alternate;
372 if (udc_usb_ep == &udc->udc_usb_ep[0])
373 return &udc->pxa_ep[0];
375 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
376 ep = &udc->pxa_ep[i];
377 if (is_match_usb_pxa(udc_usb_ep, ep, cfg, iface, alt))
384 * update_pxa_ep_matches - update pxa_ep cached values in all udc_usb_ep
387 * Context: in_interrupt()
389 * Updates all pxa_ep fields in udc_usb_ep structures, if this field was
390 * previously set up (and is not NULL). The update is necessary is a
391 * configuration change or altsetting change was issued by the USB host.
393 static void update_pxa_ep_matches(struct pxa_udc *udc)
396 struct udc_usb_ep *udc_usb_ep;
398 for (i = 1; i < NR_USB_ENDPOINTS; i++) {
399 udc_usb_ep = &udc->udc_usb_ep[i];
400 if (udc_usb_ep->pxa_ep)
401 udc_usb_ep->pxa_ep = find_pxa_ep(udc, udc_usb_ep);
406 * pio_irq_enable - Enables irq generation for one endpoint
409 static void pio_irq_enable(struct pxa_ep *ep)
411 struct pxa_udc *udc = ep->dev;
412 int index = EPIDX(ep);
413 u32 udcicr0 = udc_readl(udc, UDCICR0);
414 u32 udcicr1 = udc_readl(udc, UDCICR1);
417 udc_writel(udc, UDCICR0, udcicr0 | (3 << (index * 2)));
419 udc_writel(udc, UDCICR1, udcicr1 | (3 << ((index - 16) * 2)));
423 * pio_irq_disable - Disables irq generation for one endpoint
426 static void pio_irq_disable(struct pxa_ep *ep)
428 struct pxa_udc *udc = ep->dev;
429 int index = EPIDX(ep);
430 u32 udcicr0 = udc_readl(udc, UDCICR0);
431 u32 udcicr1 = udc_readl(udc, UDCICR1);
434 udc_writel(udc, UDCICR0, udcicr0 & ~(3 << (index * 2)));
436 udc_writel(udc, UDCICR1, udcicr1 & ~(3 << ((index - 16) * 2)));
440 * udc_set_mask_UDCCR - set bits in UDCCR
442 * @mask: bits to set in UDCCR
444 * Sets bits in UDCCR, leaving DME and FST bits as they were.
446 static inline void udc_set_mask_UDCCR(struct pxa_udc *udc, int mask)
448 u32 udccr = udc_readl(udc, UDCCR);
449 udc_writel(udc, UDCCR,
450 (udccr & UDCCR_MASK_BITS) | (mask & UDCCR_MASK_BITS));
454 * udc_clear_mask_UDCCR - clears bits in UDCCR
456 * @mask: bit to clear in UDCCR
458 * Clears bits in UDCCR, leaving DME and FST bits as they were.
460 static inline void udc_clear_mask_UDCCR(struct pxa_udc *udc, int mask)
462 u32 udccr = udc_readl(udc, UDCCR);
463 udc_writel(udc, UDCCR,
464 (udccr & UDCCR_MASK_BITS) & ~(mask & UDCCR_MASK_BITS));
468 * ep_write_UDCCSR - set bits in UDCCSR
470 * @mask: bits to set in UDCCR
472 * Sets bits in UDCCSR (UDCCSR0 and UDCCSR*).
474 * A specific case is applied to ep0 : the ACM bit is always set to 1, for
475 * SET_INTERFACE and SET_CONFIGURATION.
477 static inline void ep_write_UDCCSR(struct pxa_ep *ep, int mask)
481 udc_ep_writel(ep, UDCCSR, mask);
485 * ep_count_bytes_remain - get how many bytes in udc endpoint
488 * Returns number of bytes in OUT fifos. Broken for IN fifos (-EOPNOTSUPP)
490 static int ep_count_bytes_remain(struct pxa_ep *ep)
494 return udc_ep_readl(ep, UDCBCR) & 0x3ff;
498 * ep_is_empty - checks if ep has byte ready for reading
501 * If endpoint is the control endpoint, checks if there are bytes in the
502 * control endpoint fifo. If endpoint is a data endpoint, checks if bytes
503 * are ready for reading on OUT endpoint.
505 * Returns 0 if ep not empty, 1 if ep empty, -EOPNOTSUPP if IN endpoint
507 static int ep_is_empty(struct pxa_ep *ep)
511 if (!is_ep0(ep) && ep->dir_in)
514 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR0_RNE);
516 ret = !(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNE);
521 * ep_is_full - checks if ep has place to write bytes
524 * If endpoint is not the control endpoint and is an IN endpoint, checks if
525 * there is place to write bytes into the endpoint.
527 * Returns 0 if ep not full, 1 if ep full, -EOPNOTSUPP if OUT endpoint
529 static int ep_is_full(struct pxa_ep *ep)
532 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_IPR);
535 return (!(udc_ep_readl(ep, UDCCSR) & UDCCSR_BNF));
539 * epout_has_pkt - checks if OUT endpoint fifo has a packet available
542 * Returns 1 if a complete packet is available, 0 if not, -EOPNOTSUPP for IN ep.
544 static int epout_has_pkt(struct pxa_ep *ep)
546 if (!is_ep0(ep) && ep->dir_in)
549 return (udc_ep_readl(ep, UDCCSR) & UDCCSR0_OPC);
550 return (udc_ep_readl(ep, UDCCSR) & UDCCSR_PC);
554 * set_ep0state - Set ep0 automata state
558 static void set_ep0state(struct pxa_udc *udc, int state)
560 struct pxa_ep *ep = &udc->pxa_ep[0];
561 char *old_stname = EP0_STNAME(udc);
563 udc->ep0state = state;
564 ep_dbg(ep, "state=%s->%s, udccsr0=0x%03x, udcbcr=%d\n", old_stname,
565 EP0_STNAME(udc), udc_ep_readl(ep, UDCCSR),
566 udc_ep_readl(ep, UDCBCR));
570 * ep0_idle - Put control endpoint into idle state
573 static void ep0_idle(struct pxa_udc *dev)
575 set_ep0state(dev, WAIT_FOR_SETUP);
579 * inc_ep_stats_reqs - Update ep stats counts
580 * @ep: physical endpoint
582 * @is_in: ep direction (USB_DIR_IN or 0)
585 static void inc_ep_stats_reqs(struct pxa_ep *ep, int is_in)
594 * inc_ep_stats_bytes - Update ep stats counts
595 * @ep: physical endpoint
596 * @count: bytes transferred on endpoint
597 * @is_in: ep direction (USB_DIR_IN or 0)
599 static void inc_ep_stats_bytes(struct pxa_ep *ep, int count, int is_in)
602 ep->stats.in_bytes += count;
604 ep->stats.out_bytes += count;
608 * pxa_ep_setup - Sets up an usb physical endpoint
609 * @ep: pxa27x physical endpoint
611 * Find the physical pxa27x ep, and setup its UDCCR
613 static void pxa_ep_setup(struct pxa_ep *ep)
617 new_udccr = ((ep->config << UDCCONR_CN_S) & UDCCONR_CN)
618 | ((ep->interface << UDCCONR_IN_S) & UDCCONR_IN)
619 | ((ep->alternate << UDCCONR_AISN_S) & UDCCONR_AISN)
620 | ((EPADDR(ep) << UDCCONR_EN_S) & UDCCONR_EN)
621 | ((EPXFERTYPE(ep) << UDCCONR_ET_S) & UDCCONR_ET)
622 | ((ep->dir_in) ? UDCCONR_ED : 0)
623 | ((ep->fifo_size << UDCCONR_MPS_S) & UDCCONR_MPS)
626 udc_ep_writel(ep, UDCCR, new_udccr);
630 * pxa_eps_setup - Sets up all usb physical endpoints
633 * Setup all pxa physical endpoints, except ep0
635 static void pxa_eps_setup(struct pxa_udc *dev)
639 dev_dbg(dev->dev, "%s: dev=%p\n", __func__, dev);
641 for (i = 1; i < NR_PXA_ENDPOINTS; i++)
642 pxa_ep_setup(&dev->pxa_ep[i]);
646 * pxa_ep_alloc_request - Allocate usb request
650 * For the pxa27x, these can just wrap kmalloc/kfree. gadget drivers
651 * must still pass correctly initialized endpoints, since other controller
652 * drivers may care about how it's currently set up (dma issues etc).
654 static struct usb_request *
655 pxa_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
657 struct pxa27x_request *req;
659 req = kzalloc(sizeof *req, gfp_flags);
663 INIT_LIST_HEAD(&req->queue);
665 req->udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
671 * pxa_ep_free_request - Free usb request
675 * Wrapper around kfree to free _req
677 static void pxa_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
679 struct pxa27x_request *req;
681 req = container_of(_req, struct pxa27x_request, req);
682 WARN_ON(!list_empty(&req->queue));
687 * ep_add_request - add a request to the endpoint's queue
691 * Context: ep->lock held
693 * Queues the request in the endpoint's queue, and enables the interrupts
696 static void ep_add_request(struct pxa_ep *ep, struct pxa27x_request *req)
700 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req,
701 req->req.length, udc_ep_readl(ep, UDCCSR));
704 list_add_tail(&req->queue, &ep->queue);
709 * ep_del_request - removes a request from the endpoint's queue
713 * Context: ep->lock held
715 * Unqueue the request from the endpoint's queue. If there are no more requests
716 * on the endpoint, and if it's not the control endpoint, interrupts are
717 * disabled on the endpoint.
719 static void ep_del_request(struct pxa_ep *ep, struct pxa27x_request *req)
723 ep_vdbg(ep, "req:%p, lg=%d, udccsr=0x%03x\n", req,
724 req->req.length, udc_ep_readl(ep, UDCCSR));
726 list_del_init(&req->queue);
728 if (!is_ep0(ep) && list_empty(&ep->queue))
733 * req_done - Complete an usb request
734 * @ep: pxa physical endpoint
736 * @status: usb request status sent to gadget API
737 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
739 * Context: ep->lock held if flags not NULL, else ep->lock released
741 * Retire a pxa27x usb request. Endpoint must be locked.
743 static void req_done(struct pxa_ep *ep, struct pxa27x_request *req, int status,
744 unsigned long *pflags)
748 ep_del_request(ep, req);
749 if (likely(req->req.status == -EINPROGRESS))
750 req->req.status = status;
752 status = req->req.status;
754 if (status && status != -ESHUTDOWN)
755 ep_dbg(ep, "complete req %p stat %d len %u/%u\n",
757 req->req.actual, req->req.length);
760 spin_unlock_irqrestore(&ep->lock, *pflags);
761 local_irq_save(flags);
762 usb_gadget_giveback_request(&req->udc_usb_ep->usb_ep, &req->req);
763 local_irq_restore(flags);
765 spin_lock_irqsave(&ep->lock, *pflags);
769 * ep_end_out_req - Ends endpoint OUT request
770 * @ep: physical endpoint
772 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
774 * Context: ep->lock held or released (see req_done())
776 * Ends endpoint OUT request (completes usb request).
778 static void ep_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req,
779 unsigned long *pflags)
781 inc_ep_stats_reqs(ep, !USB_DIR_IN);
782 req_done(ep, req, 0, pflags);
786 * ep0_end_out_req - Ends control endpoint OUT request (ends data stage)
787 * @ep: physical endpoint
789 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
791 * Context: ep->lock held or released (see req_done())
793 * Ends control endpoint OUT request (completes usb request), and puts
794 * control endpoint into idle state
796 static void ep0_end_out_req(struct pxa_ep *ep, struct pxa27x_request *req,
797 unsigned long *pflags)
799 set_ep0state(ep->dev, OUT_STATUS_STAGE);
800 ep_end_out_req(ep, req, pflags);
805 * ep_end_in_req - Ends endpoint IN request
806 * @ep: physical endpoint
808 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
810 * Context: ep->lock held or released (see req_done())
812 * Ends endpoint IN request (completes usb request).
814 static void ep_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req,
815 unsigned long *pflags)
817 inc_ep_stats_reqs(ep, USB_DIR_IN);
818 req_done(ep, req, 0, pflags);
822 * ep0_end_in_req - Ends control endpoint IN request (ends data stage)
823 * @ep: physical endpoint
825 * @pflags: flags of previous spinlock_irq_save() or NULL if no lock held
827 * Context: ep->lock held or released (see req_done())
829 * Ends control endpoint IN request (completes usb request), and puts
830 * control endpoint into status state
832 static void ep0_end_in_req(struct pxa_ep *ep, struct pxa27x_request *req,
833 unsigned long *pflags)
835 set_ep0state(ep->dev, IN_STATUS_STAGE);
836 ep_end_in_req(ep, req, pflags);
840 * nuke - Dequeue all requests
842 * @status: usb request status
844 * Context: ep->lock released
846 * Dequeues all requests on an endpoint. As a side effect, interrupts will be
847 * disabled on that endpoint (because no more requests).
849 static void nuke(struct pxa_ep *ep, int status)
851 struct pxa27x_request *req;
854 spin_lock_irqsave(&ep->lock, flags);
855 while (!list_empty(&ep->queue)) {
856 req = list_entry(ep->queue.next, struct pxa27x_request, queue);
857 req_done(ep, req, status, &flags);
859 spin_unlock_irqrestore(&ep->lock, flags);
863 * read_packet - transfer 1 packet from an OUT endpoint into request
864 * @ep: pxa physical endpoint
867 * Takes bytes from OUT endpoint and transfers them info the usb request.
868 * If there is less space in request than bytes received in OUT endpoint,
869 * bytes are left in the OUT endpoint.
871 * Returns how many bytes were actually transferred
873 static int read_packet(struct pxa_ep *ep, struct pxa27x_request *req)
876 int bytes_ep, bufferspace, count, i;
878 bytes_ep = ep_count_bytes_remain(ep);
879 bufferspace = req->req.length - req->req.actual;
881 buf = (u32 *)(req->req.buf + req->req.actual);
884 if (likely(!ep_is_empty(ep)))
885 count = min(bytes_ep, bufferspace);
889 for (i = count; i > 0; i -= 4)
890 *buf++ = udc_ep_readl(ep, UDCDR);
891 req->req.actual += count;
893 ep_write_UDCCSR(ep, UDCCSR_PC);
899 * write_packet - transfer 1 packet from request into an IN endpoint
900 * @ep: pxa physical endpoint
902 * @max: max bytes that fit into endpoint
904 * Takes bytes from usb request, and transfers them into the physical
905 * endpoint. If there are no bytes to transfer, doesn't write anything
906 * to physical endpoint.
908 * Returns how many bytes were actually transferred.
910 static int write_packet(struct pxa_ep *ep, struct pxa27x_request *req,
913 int length, count, remain, i;
917 buf = (u32 *)(req->req.buf + req->req.actual);
920 length = min(req->req.length - req->req.actual, max);
921 req->req.actual += length;
923 remain = length & 0x3;
924 count = length & ~(0x3);
925 for (i = count; i > 0 ; i -= 4)
926 udc_ep_writel(ep, UDCDR, *buf++);
929 for (i = remain; i > 0; i--)
930 udc_ep_writeb(ep, UDCDR, *buf_8++);
932 ep_vdbg(ep, "length=%d+%d, udccsr=0x%03x\n", count, remain,
933 udc_ep_readl(ep, UDCCSR));
939 * read_fifo - Transfer packets from OUT endpoint into usb request
940 * @ep: pxa physical endpoint
943 * Context: callable when in_interrupt()
945 * Unload as many packets as possible from the fifo we use for usb OUT
946 * transfers and put them into the request. Caller should have made sure
947 * there's at least one packet ready.
948 * Doesn't complete the request, that's the caller's job
950 * Returns 1 if the request completed, 0 otherwise
952 static int read_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
954 int count, is_short, completed = 0;
956 while (epout_has_pkt(ep)) {
957 count = read_packet(ep, req);
958 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
960 is_short = (count < ep->fifo_size);
961 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
962 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "",
963 &req->req, req->req.actual, req->req.length);
966 if (is_short || req->req.actual == req->req.length) {
970 /* finished that packet. the next one may be waiting... */
976 * write_fifo - transfer packets from usb request into an IN endpoint
977 * @ep: pxa physical endpoint
978 * @req: pxa usb request
980 * Write to an IN endpoint fifo, as many packets as possible.
981 * irqs will use this to write the rest later.
982 * caller guarantees at least one packet buffer is ready (or a zlp).
983 * Doesn't complete the request, that's the caller's job
985 * Returns 1 if request fully transferred, 0 if partial transfer
987 static int write_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
990 int count, is_short, is_last = 0, completed = 0, totcount = 0;
997 udccsr = udc_ep_readl(ep, UDCCSR);
998 if (udccsr & UDCCSR_PC) {
999 ep_vdbg(ep, "Clearing Transmit Complete, udccsr=%x\n",
1001 ep_write_UDCCSR(ep, UDCCSR_PC);
1003 if (udccsr & UDCCSR_TRN) {
1004 ep_vdbg(ep, "Clearing Underrun on, udccsr=%x\n",
1006 ep_write_UDCCSR(ep, UDCCSR_TRN);
1009 count = write_packet(ep, req, max);
1010 inc_ep_stats_bytes(ep, count, USB_DIR_IN);
1013 /* last packet is usually short (or a zlp) */
1014 if (unlikely(count < max)) {
1018 if (likely(req->req.length > req->req.actual)
1023 /* interrupt/iso maxpacket may not fill the fifo */
1024 is_short = unlikely(max < ep->fifo_size);
1028 ep_write_UDCCSR(ep, UDCCSR_SP);
1030 /* requests complete when all IN data is in the FIFO */
1035 } while (!ep_is_full(ep));
1037 ep_dbg(ep, "wrote count:%d bytes%s%s, left:%d req=%p\n",
1038 totcount, is_last ? "/L" : "", is_short ? "/S" : "",
1039 req->req.length - req->req.actual, &req->req);
1045 * read_ep0_fifo - Transfer packets from control endpoint into usb request
1046 * @ep: control endpoint
1047 * @req: pxa usb request
1049 * Special ep0 version of the above read_fifo. Reads as many bytes from control
1050 * endpoint as can be read, and stores them into usb request (limited by request
1053 * Returns 0 if usb request only partially filled, 1 if fully filled
1055 static int read_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1057 int count, is_short, completed = 0;
1059 while (epout_has_pkt(ep)) {
1060 count = read_packet(ep, req);
1061 ep_write_UDCCSR(ep, UDCCSR0_OPC);
1062 inc_ep_stats_bytes(ep, count, !USB_DIR_IN);
1064 is_short = (count < ep->fifo_size);
1065 ep_dbg(ep, "read udccsr:%03x, count:%d bytes%s req %p %d/%d\n",
1066 udc_ep_readl(ep, UDCCSR), count, is_short ? "/S" : "",
1067 &req->req, req->req.actual, req->req.length);
1069 if (is_short || req->req.actual >= req->req.length) {
1079 * write_ep0_fifo - Send a request to control endpoint (ep0 in)
1080 * @ep: control endpoint
1083 * Context: callable when in_interrupt()
1085 * Sends a request (or a part of the request) to the control endpoint (ep0 in).
1086 * If the request doesn't fit, the remaining part will be sent from irq.
1087 * The request is considered fully written only if either :
1088 * - last write transferred all remaining bytes, but fifo was not fully filled
1089 * - last write was a 0 length write
1091 * Returns 1 if request fully written, 0 if request only partially sent
1093 static int write_ep0_fifo(struct pxa_ep *ep, struct pxa27x_request *req)
1096 int is_last, is_short;
1098 count = write_packet(ep, req, EP0_FIFO_SIZE);
1099 inc_ep_stats_bytes(ep, count, USB_DIR_IN);
1101 is_short = (count < EP0_FIFO_SIZE);
1102 is_last = ((count == 0) || (count < EP0_FIFO_SIZE));
1104 /* Sends either a short packet or a 0 length packet */
1105 if (unlikely(is_short))
1106 ep_write_UDCCSR(ep, UDCCSR0_IPR);
1108 ep_dbg(ep, "in %d bytes%s%s, %d left, req=%p, udccsr0=0x%03x\n",
1109 count, is_short ? "/S" : "", is_last ? "/L" : "",
1110 req->req.length - req->req.actual,
1111 &req->req, udc_ep_readl(ep, UDCCSR));
1117 * pxa_ep_queue - Queue a request into an IN endpoint
1118 * @_ep: usb endpoint
1119 * @_req: usb request
1122 * Context: normally called when !in_interrupt, but callable when in_interrupt()
1123 * in the special case of ep0 setup :
1124 * (irq->handle_ep0_ctrl_req->gadget_setup->pxa_ep_queue)
1126 * Returns 0 if succedeed, error otherwise
1128 static int pxa_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
1131 struct udc_usb_ep *udc_usb_ep;
1133 struct pxa27x_request *req;
1134 struct pxa_udc *dev;
1135 unsigned long flags;
1139 int recursion_detected;
1141 req = container_of(_req, struct pxa27x_request, req);
1142 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1144 if (unlikely(!_req || !_req->complete || !_req->buf))
1150 dev = udc_usb_ep->dev;
1151 ep = udc_usb_ep->pxa_ep;
1156 if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1157 ep_dbg(ep, "bogus device state\n");
1161 /* iso is always one packet per request, that's the only way
1162 * we can report per-packet status. that also helps with dma.
1164 if (unlikely(EPXFERTYPE_is_ISO(ep)
1165 && req->req.length > ep->fifo_size))
1168 spin_lock_irqsave(&ep->lock, flags);
1169 recursion_detected = ep->in_handle_ep;
1171 is_first_req = list_empty(&ep->queue);
1172 ep_dbg(ep, "queue req %p(first=%s), len %d buf %p\n",
1173 _req, is_first_req ? "yes" : "no",
1174 _req->length, _req->buf);
1177 _req->status = -ESHUTDOWN;
1183 ep_err(ep, "refusing to queue req %p (already queued)\n", req);
1187 length = _req->length;
1188 _req->status = -EINPROGRESS;
1191 ep_add_request(ep, req);
1192 spin_unlock_irqrestore(&ep->lock, flags);
1195 switch (dev->ep0state) {
1196 case WAIT_ACK_SET_CONF_INTERF:
1198 ep_end_in_req(ep, req, NULL);
1200 ep_err(ep, "got a request of %d bytes while"
1201 "in state WAIT_ACK_SET_CONF_INTERF\n",
1203 ep_del_request(ep, req);
1209 if (!ep_is_full(ep))
1210 if (write_ep0_fifo(ep, req))
1211 ep0_end_in_req(ep, req, NULL);
1213 case OUT_DATA_STAGE:
1214 if ((length == 0) || !epout_has_pkt(ep))
1215 if (read_ep0_fifo(ep, req))
1216 ep0_end_out_req(ep, req, NULL);
1219 ep_err(ep, "odd state %s to send me a request\n",
1220 EP0_STNAME(ep->dev));
1221 ep_del_request(ep, req);
1226 if (!recursion_detected)
1233 spin_unlock_irqrestore(&ep->lock, flags);
1238 * pxa_ep_dequeue - Dequeue one request
1239 * @_ep: usb endpoint
1240 * @_req: usb request
1242 * Return 0 if no error, -EINVAL or -ECONNRESET otherwise
1244 static int pxa_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1247 struct udc_usb_ep *udc_usb_ep;
1248 struct pxa27x_request *req;
1249 unsigned long flags;
1254 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1255 ep = udc_usb_ep->pxa_ep;
1256 if (!ep || is_ep0(ep))
1259 spin_lock_irqsave(&ep->lock, flags);
1261 /* make sure it's actually queued on this endpoint */
1262 list_for_each_entry(req, &ep->queue, queue) {
1263 if (&req->req == _req) {
1269 spin_unlock_irqrestore(&ep->lock, flags);
1271 req_done(ep, req, -ECONNRESET, NULL);
1276 * pxa_ep_set_halt - Halts operations on one endpoint
1277 * @_ep: usb endpoint
1280 * Returns 0 if no error, -EINVAL, -EROFS, -EAGAIN otherwise
1282 static int pxa_ep_set_halt(struct usb_ep *_ep, int value)
1285 struct udc_usb_ep *udc_usb_ep;
1286 unsigned long flags;
1292 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1293 ep = udc_usb_ep->pxa_ep;
1294 if (!ep || is_ep0(ep))
1299 * This path (reset toggle+halt) is needed to implement
1300 * SET_INTERFACE on normal hardware. but it can't be
1301 * done from software on the PXA UDC, and the hardware
1302 * forgets to do it as part of SET_INTERFACE automagic.
1304 ep_dbg(ep, "only host can clear halt\n");
1308 spin_lock_irqsave(&ep->lock, flags);
1311 if (ep->dir_in && (ep_is_full(ep) || !list_empty(&ep->queue)))
1314 /* FST, FEF bits are the same for control and non control endpoints */
1316 ep_write_UDCCSR(ep, UDCCSR_FST | UDCCSR_FEF);
1318 set_ep0state(ep->dev, STALL);
1321 spin_unlock_irqrestore(&ep->lock, flags);
1326 * pxa_ep_fifo_status - Get how many bytes in physical endpoint
1327 * @_ep: usb endpoint
1329 * Returns number of bytes in OUT fifos. Broken for IN fifos.
1331 static int pxa_ep_fifo_status(struct usb_ep *_ep)
1334 struct udc_usb_ep *udc_usb_ep;
1338 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1339 ep = udc_usb_ep->pxa_ep;
1340 if (!ep || is_ep0(ep))
1345 if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN || ep_is_empty(ep))
1348 return ep_count_bytes_remain(ep) + 1;
1352 * pxa_ep_fifo_flush - Flushes one endpoint
1353 * @_ep: usb endpoint
1355 * Discards all data in one endpoint(IN or OUT), except control endpoint.
1357 static void pxa_ep_fifo_flush(struct usb_ep *_ep)
1360 struct udc_usb_ep *udc_usb_ep;
1361 unsigned long flags;
1365 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1366 ep = udc_usb_ep->pxa_ep;
1367 if (!ep || is_ep0(ep))
1370 spin_lock_irqsave(&ep->lock, flags);
1372 if (unlikely(!list_empty(&ep->queue)))
1373 ep_dbg(ep, "called while queue list not empty\n");
1374 ep_dbg(ep, "called\n");
1376 /* for OUT, just read and discard the FIFO contents. */
1378 while (!ep_is_empty(ep))
1379 udc_ep_readl(ep, UDCDR);
1381 /* most IN status is the same, but ISO can't stall */
1383 UDCCSR_PC | UDCCSR_FEF | UDCCSR_TRN
1384 | (EPXFERTYPE_is_ISO(ep) ? 0 : UDCCSR_SST));
1387 spin_unlock_irqrestore(&ep->lock, flags);
1391 * pxa_ep_enable - Enables usb endpoint
1392 * @_ep: usb endpoint
1393 * @desc: usb endpoint descriptor
1395 * Nothing much to do here, as ep configuration is done once and for all
1396 * before udc is enabled. After udc enable, no physical endpoint configuration
1398 * Function makes sanity checks and flushes the endpoint.
1400 static int pxa_ep_enable(struct usb_ep *_ep,
1401 const struct usb_endpoint_descriptor *desc)
1404 struct udc_usb_ep *udc_usb_ep;
1405 struct pxa_udc *udc;
1410 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1411 if (udc_usb_ep->pxa_ep) {
1412 ep = udc_usb_ep->pxa_ep;
1413 ep_warn(ep, "usb_ep %s already enabled, doing nothing\n",
1416 ep = find_pxa_ep(udc_usb_ep->dev, udc_usb_ep);
1419 if (!ep || is_ep0(ep)) {
1420 dev_err(udc_usb_ep->dev->dev,
1421 "unable to match pxa_ep for ep %s\n",
1426 if ((desc->bDescriptorType != USB_DT_ENDPOINT)
1427 || (ep->type != usb_endpoint_type(desc))) {
1428 ep_err(ep, "type mismatch\n");
1432 if (ep->fifo_size < usb_endpoint_maxp(desc)) {
1433 ep_err(ep, "bad maxpacket\n");
1437 udc_usb_ep->pxa_ep = ep;
1440 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
1441 ep_err(ep, "bogus device state\n");
1447 /* flush fifo (mostly for OUT buffers) */
1448 pxa_ep_fifo_flush(_ep);
1450 ep_dbg(ep, "enabled\n");
1455 * pxa_ep_disable - Disable usb endpoint
1456 * @_ep: usb endpoint
1458 * Same as for pxa_ep_enable, no physical endpoint configuration can be
1460 * Function flushes the endpoint and related requests.
1462 static int pxa_ep_disable(struct usb_ep *_ep)
1465 struct udc_usb_ep *udc_usb_ep;
1470 udc_usb_ep = container_of(_ep, struct udc_usb_ep, usb_ep);
1471 ep = udc_usb_ep->pxa_ep;
1472 if (!ep || is_ep0(ep) || !list_empty(&ep->queue))
1476 nuke(ep, -ESHUTDOWN);
1478 pxa_ep_fifo_flush(_ep);
1479 udc_usb_ep->pxa_ep = NULL;
1481 ep_dbg(ep, "disabled\n");
1485 static struct usb_ep_ops pxa_ep_ops = {
1486 .enable = pxa_ep_enable,
1487 .disable = pxa_ep_disable,
1489 .alloc_request = pxa_ep_alloc_request,
1490 .free_request = pxa_ep_free_request,
1492 .queue = pxa_ep_queue,
1493 .dequeue = pxa_ep_dequeue,
1495 .set_halt = pxa_ep_set_halt,
1496 .fifo_status = pxa_ep_fifo_status,
1497 .fifo_flush = pxa_ep_fifo_flush,
1501 * dplus_pullup - Connect or disconnect pullup resistor to D+ pin
1503 * @on: 0 if disconnect pullup resistor, 1 otherwise
1506 * Handle D+ pullup resistor, make the device visible to the usb bus, and
1507 * declare it as a full speed usb device
1509 static void dplus_pullup(struct pxa_udc *udc, int on)
1512 gpiod_set_value(udc->gpiod, on);
1513 } else if (udc->udc_command) {
1515 udc->udc_command(PXA2XX_UDC_CMD_CONNECT);
1517 udc->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
1519 udc->pullup_on = on;
1523 * pxa_udc_get_frame - Returns usb frame number
1524 * @_gadget: usb gadget
1526 static int pxa_udc_get_frame(struct usb_gadget *_gadget)
1528 struct pxa_udc *udc = to_gadget_udc(_gadget);
1530 return (udc_readl(udc, UDCFNR) & 0x7ff);
1534 * pxa_udc_wakeup - Force udc device out of suspend
1535 * @_gadget: usb gadget
1537 * Returns 0 if successful, error code otherwise
1539 static int pxa_udc_wakeup(struct usb_gadget *_gadget)
1541 struct pxa_udc *udc = to_gadget_udc(_gadget);
1543 /* host may not have enabled remote wakeup */
1544 if ((udc_readl(udc, UDCCR) & UDCCR_DWRE) == 0)
1545 return -EHOSTUNREACH;
1546 udc_set_mask_UDCCR(udc, UDCCR_UDR);
1550 static void udc_enable(struct pxa_udc *udc);
1551 static void udc_disable(struct pxa_udc *udc);
1554 * should_enable_udc - Tells if UDC should be enabled
1558 * The UDC should be enabled if :
1560 * - the pullup resistor is connected
1561 * - and a gadget driver is bound
1562 * - and vbus is sensed (or no vbus sense is available)
1564 * Returns 1 if UDC should be enabled, 0 otherwise
1566 static int should_enable_udc(struct pxa_udc *udc)
1570 put_on = ((udc->pullup_on) && (udc->driver));
1571 put_on &= ((udc->vbus_sensed) || (IS_ERR_OR_NULL(udc->transceiver)));
1576 * should_disable_udc - Tells if UDC should be disabled
1580 * The UDC should be disabled if :
1581 * - the pullup resistor is not connected
1582 * - or no gadget driver is bound
1583 * - or no vbus is sensed (when vbus sesing is available)
1585 * Returns 1 if UDC should be disabled
1587 static int should_disable_udc(struct pxa_udc *udc)
1591 put_off = ((!udc->pullup_on) || (!udc->driver));
1592 put_off |= ((!udc->vbus_sensed) && (!IS_ERR_OR_NULL(udc->transceiver)));
1597 * pxa_udc_pullup - Offer manual D+ pullup control
1598 * @_gadget: usb gadget using the control
1599 * @is_active: 0 if disconnect, else connect D+ pullup resistor
1600 * Context: !in_interrupt()
1602 * Returns 0 if OK, -EOPNOTSUPP if udc driver doesn't handle D+ pullup
1604 static int pxa_udc_pullup(struct usb_gadget *_gadget, int is_active)
1606 struct pxa_udc *udc = to_gadget_udc(_gadget);
1608 if (!udc->gpiod && !udc->udc_command)
1611 dplus_pullup(udc, is_active);
1613 if (should_enable_udc(udc))
1615 if (should_disable_udc(udc))
1620 static void udc_enable(struct pxa_udc *udc);
1621 static void udc_disable(struct pxa_udc *udc);
1624 * pxa_udc_vbus_session - Called by external transceiver to enable/disable udc
1625 * @_gadget: usb gadget
1626 * @is_active: 0 if should disable the udc, 1 if should enable
1628 * Enables the udc, and optionnaly activates D+ pullup resistor. Or disables the
1629 * udc, and deactivates D+ pullup resistor.
1633 static int pxa_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
1635 struct pxa_udc *udc = to_gadget_udc(_gadget);
1637 udc->vbus_sensed = is_active;
1638 if (should_enable_udc(udc))
1640 if (should_disable_udc(udc))
1647 * pxa_udc_vbus_draw - Called by gadget driver after SET_CONFIGURATION completed
1648 * @_gadget: usb gadget
1649 * @mA: current drawn
1651 * Context: !in_interrupt()
1653 * Called after a configuration was chosen by a USB host, to inform how much
1654 * current can be drawn by the device from VBus line.
1656 * Returns 0 or -EOPNOTSUPP if no transceiver is handling the udc
1658 static int pxa_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
1660 struct pxa_udc *udc;
1662 udc = to_gadget_udc(_gadget);
1663 if (!IS_ERR_OR_NULL(udc->transceiver))
1664 return usb_phy_set_power(udc->transceiver, mA);
1668 static int pxa27x_udc_start(struct usb_gadget *g,
1669 struct usb_gadget_driver *driver);
1670 static int pxa27x_udc_stop(struct usb_gadget *g,
1671 struct usb_gadget_driver *driver);
1673 static const struct usb_gadget_ops pxa_udc_ops = {
1674 .get_frame = pxa_udc_get_frame,
1675 .wakeup = pxa_udc_wakeup,
1676 .pullup = pxa_udc_pullup,
1677 .vbus_session = pxa_udc_vbus_session,
1678 .vbus_draw = pxa_udc_vbus_draw,
1679 .udc_start = pxa27x_udc_start,
1680 .udc_stop = pxa27x_udc_stop,
1684 * udc_disable - disable udc device controller
1688 * Disables the udc device : disables clocks, udc interrupts, control endpoint
1691 static void udc_disable(struct pxa_udc *udc)
1696 udc_writel(udc, UDCICR0, 0);
1697 udc_writel(udc, UDCICR1, 0);
1699 udc_clear_mask_UDCCR(udc, UDCCR_UDE);
1700 clk_disable(udc->clk);
1703 udc->gadget.speed = USB_SPEED_UNKNOWN;
1709 * udc_init_data - Initialize udc device data structures
1712 * Initializes gadget endpoint list, endpoints locks. No action is taken
1715 static void udc_init_data(struct pxa_udc *dev)
1720 /* device/ep0 records init */
1721 INIT_LIST_HEAD(&dev->gadget.ep_list);
1722 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1723 dev->udc_usb_ep[0].pxa_ep = &dev->pxa_ep[0];
1726 /* PXA endpoints init */
1727 for (i = 0; i < NR_PXA_ENDPOINTS; i++) {
1728 ep = &dev->pxa_ep[i];
1730 ep->enabled = is_ep0(ep);
1731 INIT_LIST_HEAD(&ep->queue);
1732 spin_lock_init(&ep->lock);
1735 /* USB endpoints init */
1736 for (i = 1; i < NR_USB_ENDPOINTS; i++) {
1737 list_add_tail(&dev->udc_usb_ep[i].usb_ep.ep_list,
1738 &dev->gadget.ep_list);
1739 usb_ep_set_maxpacket_limit(&dev->udc_usb_ep[i].usb_ep,
1740 dev->udc_usb_ep[i].usb_ep.maxpacket);
1745 * udc_enable - Enables the udc device
1748 * Enables the udc device : enables clocks, udc interrupts, control endpoint
1749 * interrupts, sets usb as UDC client and setups endpoints.
1751 static void udc_enable(struct pxa_udc *udc)
1756 udc_writel(udc, UDCICR0, 0);
1757 udc_writel(udc, UDCICR1, 0);
1758 udc_clear_mask_UDCCR(udc, UDCCR_UDE);
1760 clk_enable(udc->clk);
1763 udc->gadget.speed = USB_SPEED_FULL;
1764 memset(&udc->stats, 0, sizeof(udc->stats));
1766 udc_set_mask_UDCCR(udc, UDCCR_UDE);
1767 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_ACM);
1769 if (udc_readl(udc, UDCCR) & UDCCR_EMCE)
1770 dev_err(udc->dev, "Configuration errors, udc disabled\n");
1773 * Caller must be able to sleep in order to cope with startup transients
1777 /* enable suspend/resume and reset irqs */
1778 udc_writel(udc, UDCICR1,
1779 UDCICR1_IECC | UDCICR1_IERU
1780 | UDCICR1_IESU | UDCICR1_IERS);
1782 /* enable ep0 irqs */
1783 pio_irq_enable(&udc->pxa_ep[0]);
1789 * pxa27x_start - Register gadget driver
1790 * @driver: gadget driver
1791 * @bind: bind function
1793 * When a driver is successfully registered, it will receive control requests
1794 * including set_configuration(), which enables non-control requests. Then
1795 * usb traffic follows until a disconnect is reported. Then a host may connect
1796 * again, or the driver might get unbound.
1798 * Note that the udc is not automatically enabled. Check function
1799 * should_enable_udc().
1801 * Returns 0 if no error, -EINVAL, -ENODEV, -EBUSY otherwise
1803 static int pxa27x_udc_start(struct usb_gadget *g,
1804 struct usb_gadget_driver *driver)
1806 struct pxa_udc *udc = to_pxa(g);
1809 /* first hook up the driver ... */
1810 udc->driver = driver;
1811 dplus_pullup(udc, 1);
1813 if (!IS_ERR_OR_NULL(udc->transceiver)) {
1814 retval = otg_set_peripheral(udc->transceiver->otg,
1817 dev_err(udc->dev, "can't bind to transceiver\n");
1822 if (should_enable_udc(udc))
1832 * stop_activity - Stops udc endpoints
1834 * @driver: gadget driver
1836 * Disables all udc endpoints (even control endpoint), report disconnect to
1839 static void stop_activity(struct pxa_udc *udc, struct usb_gadget_driver *driver)
1843 /* don't disconnect drivers more than once */
1844 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1846 udc->gadget.speed = USB_SPEED_UNKNOWN;
1848 for (i = 0; i < NR_USB_ENDPOINTS; i++)
1849 pxa_ep_disable(&udc->udc_usb_ep[i].usb_ep);
1853 * pxa27x_udc_stop - Unregister the gadget driver
1854 * @driver: gadget driver
1856 * Returns 0 if no error, -ENODEV, -EINVAL otherwise
1858 static int pxa27x_udc_stop(struct usb_gadget *g,
1859 struct usb_gadget_driver *driver)
1861 struct pxa_udc *udc = to_pxa(g);
1863 stop_activity(udc, driver);
1865 dplus_pullup(udc, 0);
1869 if (!IS_ERR_OR_NULL(udc->transceiver))
1870 return otg_set_peripheral(udc->transceiver->otg, NULL);
1875 * handle_ep0_ctrl_req - handle control endpoint control request
1877 * @req: control request
1879 static void handle_ep0_ctrl_req(struct pxa_udc *udc,
1880 struct pxa27x_request *req)
1882 struct pxa_ep *ep = &udc->pxa_ep[0];
1884 struct usb_ctrlrequest r;
1888 int have_extrabytes = 0;
1889 unsigned long flags;
1892 spin_lock_irqsave(&ep->lock, flags);
1895 * In the PXA320 manual, in the section about Back-to-Back setup
1896 * packets, it describes this situation. The solution is to set OPC to
1897 * get rid of the status packet, and then continue with the setup
1898 * packet. Generalize to pxa27x CPUs.
1900 if (epout_has_pkt(ep) && (ep_count_bytes_remain(ep) == 0))
1901 ep_write_UDCCSR(ep, UDCCSR0_OPC);
1903 /* read SETUP packet */
1904 for (i = 0; i < 2; i++) {
1905 if (unlikely(ep_is_empty(ep)))
1907 u.word[i] = udc_ep_readl(ep, UDCDR);
1910 have_extrabytes = !ep_is_empty(ep);
1911 while (!ep_is_empty(ep)) {
1912 i = udc_ep_readl(ep, UDCDR);
1913 ep_err(ep, "wrong to have extra bytes for setup : 0x%08x\n", i);
1916 ep_dbg(ep, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1917 u.r.bRequestType, u.r.bRequest,
1918 le16_to_cpu(u.r.wValue), le16_to_cpu(u.r.wIndex),
1919 le16_to_cpu(u.r.wLength));
1920 if (unlikely(have_extrabytes))
1923 if (u.r.bRequestType & USB_DIR_IN)
1924 set_ep0state(udc, IN_DATA_STAGE);
1926 set_ep0state(udc, OUT_DATA_STAGE);
1928 /* Tell UDC to enter Data Stage */
1929 ep_write_UDCCSR(ep, UDCCSR0_SA | UDCCSR0_OPC);
1931 spin_unlock_irqrestore(&ep->lock, flags);
1932 i = udc->driver->setup(&udc->gadget, &u.r);
1933 spin_lock_irqsave(&ep->lock, flags);
1937 spin_unlock_irqrestore(&ep->lock, flags);
1940 ep_dbg(ep, "protocol STALL, udccsr0=%03x err %d\n",
1941 udc_ep_readl(ep, UDCCSR), i);
1942 ep_write_UDCCSR(ep, UDCCSR0_FST | UDCCSR0_FTF);
1943 set_ep0state(udc, STALL);
1948 * handle_ep0 - Handle control endpoint data transfers
1950 * @fifo_irq: 1 if triggered by fifo service type irq
1951 * @opc_irq: 1 if triggered by output packet complete type irq
1953 * Context : when in_interrupt() or with ep->lock held
1955 * Tries to transfer all pending request data into the endpoint and/or
1956 * transfer all pending data in the endpoint into usb requests.
1957 * Handles states of ep0 automata.
1959 * PXA27x hardware handles several standard usb control requests without
1960 * driver notification. The requests fully handled by hardware are :
1961 * SET_ADDRESS, SET_FEATURE, CLEAR_FEATURE, GET_CONFIGURATION, GET_INTERFACE,
1963 * The requests handled by hardware, but with irq notification are :
1964 * SYNCH_FRAME, SET_CONFIGURATION, SET_INTERFACE
1965 * The remaining standard requests really handled by handle_ep0 are :
1966 * GET_DESCRIPTOR, SET_DESCRIPTOR, specific requests.
1967 * Requests standardized outside of USB 2.0 chapter 9 are handled more
1968 * uniformly, by gadget drivers.
1970 * The control endpoint state machine is _not_ USB spec compliant, it's even
1971 * hardly compliant with Intel PXA270 developers guide.
1972 * The key points which inferred this state machine are :
1973 * - on every setup token, bit UDCCSR0_SA is raised and held until cleared by
1975 * - on every OUT packet received, UDCCSR0_OPC is raised and held until
1976 * cleared by software.
1977 * - clearing UDCCSR0_OPC always flushes ep0. If in setup stage, never do it
1978 * before reading ep0.
1979 * This is true only for PXA27x. This is not true anymore for PXA3xx family
1980 * (check Back-to-Back setup packet in developers guide).
1981 * - irq can be called on a "packet complete" event (opc_irq=1), while
1982 * UDCCSR0_OPC is not yet raised (delta can be as big as 100ms
1983 * from experimentation).
1984 * - as UDCCSR0_SA can be activated while in irq handling, and clearing
1985 * UDCCSR0_OPC would flush the setup data, we almost never clear UDCCSR0_OPC
1986 * => we never actually read the "status stage" packet of an IN data stage
1987 * => this is not documented in Intel documentation
1988 * - hardware as no idea of STATUS STAGE, it only handle SETUP STAGE and DATA
1989 * STAGE. The driver add STATUS STAGE to send last zero length packet in
1991 * - special attention was needed for IN_STATUS_STAGE. If a packet complete
1992 * event is detected, we terminate the status stage without ackowledging the
1993 * packet (not to risk to loose a potential SETUP packet)
1995 static void handle_ep0(struct pxa_udc *udc, int fifo_irq, int opc_irq)
1998 struct pxa_ep *ep = &udc->pxa_ep[0];
1999 struct pxa27x_request *req = NULL;
2002 if (!list_empty(&ep->queue))
2003 req = list_entry(ep->queue.next, struct pxa27x_request, queue);
2005 udccsr0 = udc_ep_readl(ep, UDCCSR);
2006 ep_dbg(ep, "state=%s, req=%p, udccsr0=0x%03x, udcbcr=%d, irq_msk=%x\n",
2007 EP0_STNAME(udc), req, udccsr0, udc_ep_readl(ep, UDCBCR),
2008 (fifo_irq << 1 | opc_irq));
2010 if (udccsr0 & UDCCSR0_SST) {
2011 ep_dbg(ep, "clearing stall status\n");
2013 ep_write_UDCCSR(ep, UDCCSR0_SST);
2017 if (udccsr0 & UDCCSR0_SA) {
2019 set_ep0state(udc, SETUP_STAGE);
2022 switch (udc->ep0state) {
2023 case WAIT_FOR_SETUP:
2025 * Hardware bug : beware, we cannot clear OPC, since we would
2026 * miss a potential OPC irq for a setup packet.
2027 * So, we only do ... nothing, and hope for a next irq with
2032 udccsr0 &= UDCCSR0_CTRL_REQ_MASK;
2033 if (likely(udccsr0 == UDCCSR0_CTRL_REQ_MASK))
2034 handle_ep0_ctrl_req(udc, req);
2036 case IN_DATA_STAGE: /* GET_DESCRIPTOR */
2037 if (epout_has_pkt(ep))
2038 ep_write_UDCCSR(ep, UDCCSR0_OPC);
2039 if (req && !ep_is_full(ep))
2040 completed = write_ep0_fifo(ep, req);
2042 ep0_end_in_req(ep, req, NULL);
2044 case OUT_DATA_STAGE: /* SET_DESCRIPTOR */
2045 if (epout_has_pkt(ep) && req)
2046 completed = read_ep0_fifo(ep, req);
2048 ep0_end_out_req(ep, req, NULL);
2051 ep_write_UDCCSR(ep, UDCCSR0_FST);
2053 case IN_STATUS_STAGE:
2055 * Hardware bug : beware, we cannot clear OPC, since we would
2056 * miss a potential PC irq for a setup packet.
2057 * So, we only put the ep0 into WAIT_FOR_SETUP state.
2062 case OUT_STATUS_STAGE:
2063 case WAIT_ACK_SET_CONF_INTERF:
2064 ep_warn(ep, "should never get in %s state here!!!\n",
2065 EP0_STNAME(ep->dev));
2072 * handle_ep - Handle endpoint data tranfers
2073 * @ep: pxa physical endpoint
2075 * Tries to transfer all pending request data into the endpoint and/or
2076 * transfer all pending data in the endpoint into usb requests.
2078 * Is always called when in_interrupt() and with ep->lock released.
2080 static void handle_ep(struct pxa_ep *ep)
2082 struct pxa27x_request *req;
2085 int is_in = ep->dir_in;
2087 unsigned long flags;
2089 spin_lock_irqsave(&ep->lock, flags);
2090 if (ep->in_handle_ep)
2091 goto recursion_detected;
2092 ep->in_handle_ep = 1;
2096 udccsr = udc_ep_readl(ep, UDCCSR);
2098 if (likely(!list_empty(&ep->queue)))
2099 req = list_entry(ep->queue.next,
2100 struct pxa27x_request, queue);
2104 ep_dbg(ep, "req:%p, udccsr 0x%03x loop=%d\n",
2105 req, udccsr, loop++);
2107 if (unlikely(udccsr & (UDCCSR_SST | UDCCSR_TRN)))
2108 udc_ep_writel(ep, UDCCSR,
2109 udccsr & (UDCCSR_SST | UDCCSR_TRN));
2113 if (unlikely(is_in)) {
2114 if (likely(!ep_is_full(ep)))
2115 completed = write_fifo(ep, req);
2117 if (likely(epout_has_pkt(ep)))
2118 completed = read_fifo(ep, req);
2123 ep_end_in_req(ep, req, &flags);
2125 ep_end_out_req(ep, req, &flags);
2127 } while (completed);
2129 ep->in_handle_ep = 0;
2131 spin_unlock_irqrestore(&ep->lock, flags);
2135 * pxa27x_change_configuration - Handle SET_CONF usb request notification
2137 * @config: usb configuration
2139 * Post the request to upper level.
2140 * Don't use any pxa specific harware configuration capabilities
2142 static void pxa27x_change_configuration(struct pxa_udc *udc, int config)
2144 struct usb_ctrlrequest req ;
2146 dev_dbg(udc->dev, "config=%d\n", config);
2148 udc->config = config;
2149 udc->last_interface = 0;
2150 udc->last_alternate = 0;
2152 req.bRequestType = 0;
2153 req.bRequest = USB_REQ_SET_CONFIGURATION;
2154 req.wValue = config;
2158 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2159 udc->driver->setup(&udc->gadget, &req);
2160 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
2164 * pxa27x_change_interface - Handle SET_INTERF usb request notification
2166 * @iface: interface number
2167 * @alt: alternate setting number
2169 * Post the request to upper level.
2170 * Don't use any pxa specific harware configuration capabilities
2172 static void pxa27x_change_interface(struct pxa_udc *udc, int iface, int alt)
2174 struct usb_ctrlrequest req;
2176 dev_dbg(udc->dev, "interface=%d, alternate setting=%d\n", iface, alt);
2178 udc->last_interface = iface;
2179 udc->last_alternate = alt;
2181 req.bRequestType = USB_RECIP_INTERFACE;
2182 req.bRequest = USB_REQ_SET_INTERFACE;
2187 set_ep0state(udc, WAIT_ACK_SET_CONF_INTERF);
2188 udc->driver->setup(&udc->gadget, &req);
2189 ep_write_UDCCSR(&udc->pxa_ep[0], UDCCSR0_AREN);
2193 * irq_handle_data - Handle data transfer
2194 * @irq: irq IRQ number
2195 * @udc: dev pxa_udc device structure
2197 * Called from irq handler, transferts data to or from endpoint to queue
2199 static void irq_handle_data(int irq, struct pxa_udc *udc)
2203 u32 udcisr0 = udc_readl(udc, UDCISR0) & UDCCISR0_EP_MASK;
2204 u32 udcisr1 = udc_readl(udc, UDCISR1) & UDCCISR1_EP_MASK;
2206 if (udcisr0 & UDCISR_INT_MASK) {
2207 udc->pxa_ep[0].stats.irqs++;
2208 udc_writel(udc, UDCISR0, UDCISR_INT(0, UDCISR_INT_MASK));
2209 handle_ep0(udc, !!(udcisr0 & UDCICR_FIFOERR),
2210 !!(udcisr0 & UDCICR_PKTCOMPL));
2214 for (i = 1; udcisr0 != 0 && i < 16; udcisr0 >>= 2, i++) {
2215 if (!(udcisr0 & UDCISR_INT_MASK))
2218 udc_writel(udc, UDCISR0, UDCISR_INT(i, UDCISR_INT_MASK));
2220 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep));
2221 if (i < ARRAY_SIZE(udc->pxa_ep)) {
2222 ep = &udc->pxa_ep[i];
2228 for (i = 16; udcisr1 != 0 && i < 24; udcisr1 >>= 2, i++) {
2229 udc_writel(udc, UDCISR1, UDCISR_INT(i - 16, UDCISR_INT_MASK));
2230 if (!(udcisr1 & UDCISR_INT_MASK))
2233 WARN_ON(i >= ARRAY_SIZE(udc->pxa_ep));
2234 if (i < ARRAY_SIZE(udc->pxa_ep)) {
2235 ep = &udc->pxa_ep[i];
2244 * irq_udc_suspend - Handle IRQ "UDC Suspend"
2247 static void irq_udc_suspend(struct pxa_udc *udc)
2249 udc_writel(udc, UDCISR1, UDCISR1_IRSU);
2250 udc->stats.irqs_suspend++;
2252 if (udc->gadget.speed != USB_SPEED_UNKNOWN
2253 && udc->driver && udc->driver->suspend)
2254 udc->driver->suspend(&udc->gadget);
2259 * irq_udc_resume - Handle IRQ "UDC Resume"
2262 static void irq_udc_resume(struct pxa_udc *udc)
2264 udc_writel(udc, UDCISR1, UDCISR1_IRRU);
2265 udc->stats.irqs_resume++;
2267 if (udc->gadget.speed != USB_SPEED_UNKNOWN
2268 && udc->driver && udc->driver->resume)
2269 udc->driver->resume(&udc->gadget);
2273 * irq_udc_reconfig - Handle IRQ "UDC Change Configuration"
2276 static void irq_udc_reconfig(struct pxa_udc *udc)
2278 unsigned config, interface, alternate, config_change;
2279 u32 udccr = udc_readl(udc, UDCCR);
2281 udc_writel(udc, UDCISR1, UDCISR1_IRCC);
2282 udc->stats.irqs_reconfig++;
2284 config = (udccr & UDCCR_ACN) >> UDCCR_ACN_S;
2285 config_change = (config != udc->config);
2286 pxa27x_change_configuration(udc, config);
2288 interface = (udccr & UDCCR_AIN) >> UDCCR_AIN_S;
2289 alternate = (udccr & UDCCR_AAISN) >> UDCCR_AAISN_S;
2290 pxa27x_change_interface(udc, interface, alternate);
2293 update_pxa_ep_matches(udc);
2294 udc_set_mask_UDCCR(udc, UDCCR_SMAC);
2298 * irq_udc_reset - Handle IRQ "UDC Reset"
2301 static void irq_udc_reset(struct pxa_udc *udc)
2303 u32 udccr = udc_readl(udc, UDCCR);
2304 struct pxa_ep *ep = &udc->pxa_ep[0];
2306 dev_info(udc->dev, "USB reset\n");
2307 udc_writel(udc, UDCISR1, UDCISR1_IRRS);
2308 udc->stats.irqs_reset++;
2310 if ((udccr & UDCCR_UDA) == 0) {
2311 dev_dbg(udc->dev, "USB reset start\n");
2312 stop_activity(udc, udc->driver);
2314 udc->gadget.speed = USB_SPEED_FULL;
2315 memset(&udc->stats, 0, sizeof udc->stats);
2318 ep_write_UDCCSR(ep, UDCCSR0_FTF | UDCCSR0_OPC);
2323 * pxa_udc_irq - Main irq handler
2327 * Handles all udc interrupts
2329 static irqreturn_t pxa_udc_irq(int irq, void *_dev)
2331 struct pxa_udc *udc = _dev;
2332 u32 udcisr0 = udc_readl(udc, UDCISR0);
2333 u32 udcisr1 = udc_readl(udc, UDCISR1);
2334 u32 udccr = udc_readl(udc, UDCCR);
2337 dev_vdbg(udc->dev, "Interrupt, UDCISR0:0x%08x, UDCISR1:0x%08x, "
2338 "UDCCR:0x%08x\n", udcisr0, udcisr1, udccr);
2340 udcisr1_spec = udcisr1 & 0xf8000000;
2341 if (unlikely(udcisr1_spec & UDCISR1_IRSU))
2342 irq_udc_suspend(udc);
2343 if (unlikely(udcisr1_spec & UDCISR1_IRRU))
2344 irq_udc_resume(udc);
2345 if (unlikely(udcisr1_spec & UDCISR1_IRCC))
2346 irq_udc_reconfig(udc);
2347 if (unlikely(udcisr1_spec & UDCISR1_IRRS))
2350 if ((udcisr0 & UDCCISR0_EP_MASK) | (udcisr1 & UDCCISR1_EP_MASK))
2351 irq_handle_data(irq, udc);
2356 static struct pxa_udc memory = {
2358 .ops = &pxa_udc_ops,
2359 .ep0 = &memory.udc_usb_ep[0].usb_ep,
2360 .name = driver_name,
2362 .init_name = "gadget",
2377 /* Endpoints for gadget zero */
2378 PXA_EP_OUT_BULK(1, 1, 3, 0, 0),
2379 PXA_EP_IN_BULK(2, 2, 3, 0, 0),
2380 /* Endpoints for ether gadget, file storage gadget */
2381 PXA_EP_OUT_BULK(3, 1, 1, 0, 0),
2382 PXA_EP_IN_BULK(4, 2, 1, 0, 0),
2383 PXA_EP_IN_ISO(5, 3, 1, 0, 0),
2384 PXA_EP_OUT_ISO(6, 4, 1, 0, 0),
2385 PXA_EP_IN_INT(7, 5, 1, 0, 0),
2386 /* Endpoints for RNDIS, serial */
2387 PXA_EP_OUT_BULK(8, 1, 2, 0, 0),
2388 PXA_EP_IN_BULK(9, 2, 2, 0, 0),
2389 PXA_EP_IN_INT(10, 5, 2, 0, 0),
2391 * All the following endpoints are only for completion. They
2392 * won't never work, as multiple interfaces are really broken on
2395 PXA_EP_OUT_BULK(11, 1, 2, 1, 0),
2396 PXA_EP_IN_BULK(12, 2, 2, 1, 0),
2397 /* Endpoint for CDC Ether */
2398 PXA_EP_OUT_BULK(13, 1, 1, 1, 1),
2399 PXA_EP_IN_BULK(14, 2, 1, 1, 1),
2404 * pxa_udc_probe - probes the udc device
2405 * @_dev: platform device
2407 * Perform basic init : allocates udc clock, creates sysfs files, requests
2410 static int pxa_udc_probe(struct platform_device *pdev)
2412 struct resource *regs;
2413 struct pxa_udc *udc = &memory;
2414 int retval = 0, gpio;
2415 struct pxa2xx_udc_mach_info *mach = dev_get_platdata(&pdev->dev);
2416 unsigned long gpio_flags;
2419 gpio_flags = mach->gpio_pullup_inverted ? GPIOF_ACTIVE_LOW : 0;
2420 gpio = mach->gpio_pullup;
2421 if (gpio_is_valid(gpio)) {
2422 retval = devm_gpio_request_one(&pdev->dev, gpio,
2427 udc->gpiod = gpio_to_desc(mach->gpio_pullup);
2429 udc->udc_command = mach->udc_command;
2432 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2435 udc->irq = platform_get_irq(pdev, 0);
2439 udc->dev = &pdev->dev;
2440 udc->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2442 if (IS_ERR(udc->gpiod)) {
2443 dev_err(&pdev->dev, "Couldn't find or request D+ gpio : %ld\n",
2444 PTR_ERR(udc->gpiod));
2445 return PTR_ERR(udc->gpiod);
2448 gpiod_direction_output(udc->gpiod, 0);
2450 udc->clk = clk_get(&pdev->dev, NULL);
2451 if (IS_ERR(udc->clk)) {
2452 retval = PTR_ERR(udc->clk);
2455 retval = clk_prepare(udc->clk);
2457 goto err_clk_prepare;
2460 udc->regs = ioremap(regs->start, resource_size(regs));
2462 dev_err(&pdev->dev, "Unable to map UDC I/O memory\n");
2466 udc->vbus_sensed = 0;
2468 the_controller = udc;
2469 platform_set_drvdata(pdev, udc);
2473 /* irq setup after old hardware state is cleaned up */
2474 retval = request_irq(udc->irq, pxa_udc_irq,
2475 IRQF_SHARED, driver_name, udc);
2477 dev_err(udc->dev, "%s: can't get irq %i, err %d\n",
2478 driver_name, udc->irq, retval);
2482 retval = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2486 pxa_init_debugfs(udc);
2491 free_irq(udc->irq, udc);
2495 clk_unprepare(udc->clk);
2504 * pxa_udc_remove - removes the udc device driver
2505 * @_dev: platform device
2507 static int pxa_udc_remove(struct platform_device *_dev)
2509 struct pxa_udc *udc = platform_get_drvdata(_dev);
2511 usb_del_gadget_udc(&udc->gadget);
2512 usb_gadget_unregister_driver(udc->driver);
2513 free_irq(udc->irq, udc);
2514 pxa_cleanup_debugfs(udc);
2516 usb_put_phy(udc->transceiver);
2518 udc->transceiver = NULL;
2519 the_controller = NULL;
2520 clk_unprepare(udc->clk);
2527 static void pxa_udc_shutdown(struct platform_device *_dev)
2529 struct pxa_udc *udc = platform_get_drvdata(_dev);
2531 if (udc_readl(udc, UDCCR) & UDCCR_UDE)
2535 #ifdef CONFIG_PXA27x
2536 extern void pxa27x_clear_otgph(void);
2538 #define pxa27x_clear_otgph() do {} while (0)
2543 * pxa_udc_suspend - Suspend udc device
2544 * @_dev: platform device
2545 * @state: suspend state
2547 * Suspends udc : saves configuration registers (UDCCR*), then disables the udc
2550 static int pxa_udc_suspend(struct platform_device *_dev, pm_message_t state)
2553 struct pxa_udc *udc = platform_get_drvdata(_dev);
2556 ep = &udc->pxa_ep[0];
2557 udc->udccsr0 = udc_ep_readl(ep, UDCCSR);
2558 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
2559 ep = &udc->pxa_ep[i];
2560 ep->udccsr_value = udc_ep_readl(ep, UDCCSR);
2561 ep->udccr_value = udc_ep_readl(ep, UDCCR);
2562 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n",
2563 ep->udccsr_value, ep->udccr_value);
2567 udc->pullup_resume = udc->pullup_on;
2568 dplus_pullup(udc, 0);
2574 * pxa_udc_resume - Resume udc device
2575 * @_dev: platform device
2577 * Resumes udc : restores configuration registers (UDCCR*), then enables the udc
2580 static int pxa_udc_resume(struct platform_device *_dev)
2583 struct pxa_udc *udc = platform_get_drvdata(_dev);
2586 ep = &udc->pxa_ep[0];
2587 udc_ep_writel(ep, UDCCSR, udc->udccsr0 & (UDCCSR0_FST | UDCCSR0_DME));
2588 for (i = 1; i < NR_PXA_ENDPOINTS; i++) {
2589 ep = &udc->pxa_ep[i];
2590 udc_ep_writel(ep, UDCCSR, ep->udccsr_value);
2591 udc_ep_writel(ep, UDCCR, ep->udccr_value);
2592 ep_dbg(ep, "udccsr:0x%03x, udccr:0x%x\n",
2593 ep->udccsr_value, ep->udccr_value);
2596 dplus_pullup(udc, udc->pullup_resume);
2597 if (should_enable_udc(udc))
2600 * We do not handle OTG yet.
2602 * OTGPH bit is set when sleep mode is entered.
2603 * it indicates that OTG pad is retaining its state.
2604 * Upon exit from sleep mode and before clearing OTGPH,
2605 * Software must configure the USB OTG pad, UDC, and UHC
2606 * to the state they were in before entering sleep mode.
2608 pxa27x_clear_otgph();
2614 /* work with hotplug and coldplug */
2615 MODULE_ALIAS("platform:pxa27x-udc");
2617 static struct platform_driver udc_driver = {
2619 .name = "pxa27x-udc",
2620 .owner = THIS_MODULE,
2622 .probe = pxa_udc_probe,
2623 .remove = pxa_udc_remove,
2624 .shutdown = pxa_udc_shutdown,
2626 .suspend = pxa_udc_suspend,
2627 .resume = pxa_udc_resume
2631 module_platform_driver(udc_driver);
2633 MODULE_DESCRIPTION(DRIVER_DESC);
2634 MODULE_AUTHOR("Robert Jarzmik");
2635 MODULE_LICENSE("GPL");