2 * Enhanced Host Controller Interface (EHCI) driver for USB.
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
6 * Copyright (c) 2000-2004 by David Brownell
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/vmalloc.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/hrtimer.h>
34 #include <linux/list.h>
35 #include <linux/interrupt.h>
36 #include <linux/usb.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/moduleparam.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/debugfs.h>
41 #include <linux/slab.h>
42 #include <linux/uaccess.h>
44 #include <asm/byteorder.h>
47 #include <asm/unaligned.h>
49 #if defined(CONFIG_PPC_PS3)
50 #include <asm/firmware.h>
53 /*-------------------------------------------------------------------------*/
56 * EHCI hc_driver implementation ... experimental, incomplete.
57 * Based on the final 1.0 register interface specification.
59 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
60 * First was PCMCIA, like ISA; then CardBus, which is PCI.
61 * Next comes "CardBay", using USB 2.0 signals.
63 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
64 * Special thanks to Intel and VIA for providing host controllers to
65 * test this driver on, and Cypress (including In-System Design) for
66 * providing early devices for those host controllers to talk to!
69 #define DRIVER_AUTHOR "David Brownell"
70 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
72 static const char hcd_name [] = "ehci_hcd";
82 /* magic numbers that can affect system performance */
83 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
84 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
85 #define EHCI_TUNE_RL_TT 0
86 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
87 #define EHCI_TUNE_MULT_TT 1
89 * Some drivers think it's safe to schedule isochronous transfers more than
90 * 256 ms into the future (partly as a result of an old bug in the scheduling
91 * code). In an attempt to avoid trouble, we will use a minimum scheduling
92 * length of 512 frames instead of 256.
94 #define EHCI_TUNE_FLS 1 /* (medium) 512-frame schedule */
96 /* Initial IRQ latency: faster than hw default */
97 static int log2_irq_thresh = 0; // 0 to 6
98 module_param (log2_irq_thresh, int, S_IRUGO);
99 MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes");
101 /* initial park setting: slower than hw default */
102 static unsigned park = 0;
103 module_param (park, uint, S_IRUGO);
104 MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets");
106 /* for flakey hardware, ignore overcurrent indicators */
107 static bool ignore_oc = 0;
108 module_param (ignore_oc, bool, S_IRUGO);
109 MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications");
111 /* for link power management(LPM) feature */
112 static unsigned int hird;
113 module_param(hird, int, S_IRUGO);
114 MODULE_PARM_DESC(hird, "host initiated resume duration, +1 for each 75us");
116 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
118 /*-------------------------------------------------------------------------*/
121 #include "ehci-dbg.c"
122 #include "pci-quirks.h"
124 /*-------------------------------------------------------------------------*/
127 * handshake - spin reading hc until handshake completes or fails
128 * @ptr: address of hc register to be read
129 * @mask: bits to look at in result of read
130 * @done: value of those bits when handshake succeeds
131 * @usec: timeout in microseconds
133 * Returns negative errno, or zero on success
135 * Success happens when the "mask" bits have the specified value (hardware
136 * handshake done). There are two failure modes: "usec" have passed (major
137 * hardware flakeout), or the register reads as all-ones (hardware removed).
139 * That last failure should_only happen in cases like physical cardbus eject
140 * before driver shutdown. But it also seems to be caused by bugs in cardbus
141 * bridge shutdown: shutting down the bridge before the devices using it.
143 static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
144 u32 mask, u32 done, int usec)
149 result = ehci_readl(ehci, ptr);
150 if (result == ~(u32)0) /* card removed */
161 /* check TDI/ARC silicon is in host mode */
162 static int tdi_in_host_mode (struct ehci_hcd *ehci)
166 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
167 return (tmp & 3) == USBMODE_CM_HC;
171 * Force HC to halt state from unknown (EHCI spec section 2.3).
172 * Must be called with interrupts enabled and the lock not held.
174 static int ehci_halt (struct ehci_hcd *ehci)
178 spin_lock_irq(&ehci->lock);
180 /* disable any irqs left enabled by previous code */
181 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
183 if (ehci_is_TDI(ehci) && !tdi_in_host_mode(ehci)) {
184 spin_unlock_irq(&ehci->lock);
189 * This routine gets called during probe before ehci->command
190 * has been initialized, so we can't rely on its value.
192 ehci->command &= ~CMD_RUN;
193 temp = ehci_readl(ehci, &ehci->regs->command);
194 temp &= ~(CMD_RUN | CMD_IAAD);
195 ehci_writel(ehci, temp, &ehci->regs->command);
197 spin_unlock_irq(&ehci->lock);
198 synchronize_irq(ehci_to_hcd(ehci)->irq);
200 return handshake(ehci, &ehci->regs->status,
201 STS_HALT, STS_HALT, 16 * 125);
204 /* put TDI/ARC silicon into EHCI mode */
205 static void tdi_reset (struct ehci_hcd *ehci)
209 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
210 tmp |= USBMODE_CM_HC;
211 /* The default byte access to MMR space is LE after
212 * controller reset. Set the required endian mode
213 * for transfer buffers to match the host microprocessor
215 if (ehci_big_endian_mmio(ehci))
217 ehci_writel(ehci, tmp, &ehci->regs->usbmode);
221 * Reset a non-running (STS_HALT == 1) controller.
222 * Must be called with interrupts enabled and the lock not held.
224 static int ehci_reset (struct ehci_hcd *ehci)
227 u32 command = ehci_readl(ehci, &ehci->regs->command);
229 /* If the EHCI debug controller is active, special care must be
230 * taken before and after a host controller reset */
231 if (ehci->debug && !dbgp_reset_prep(ehci_to_hcd(ehci)))
234 command |= CMD_RESET;
235 dbg_cmd (ehci, "reset", command);
236 ehci_writel(ehci, command, &ehci->regs->command);
237 ehci->rh_state = EHCI_RH_HALTED;
238 ehci->next_statechange = jiffies;
239 retval = handshake (ehci, &ehci->regs->command,
240 CMD_RESET, 0, 250 * 1000);
242 if (ehci->has_hostpc) {
243 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
244 &ehci->regs->usbmode_ex);
245 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
250 if (ehci_is_TDI(ehci))
254 dbgp_external_startup(ehci_to_hcd(ehci));
256 ehci->port_c_suspend = ehci->suspended_ports =
257 ehci->resuming_ports = 0;
262 * Idle the controller (turn off the schedules).
263 * Must be called with interrupts enabled and the lock not held.
265 static void ehci_quiesce (struct ehci_hcd *ehci)
269 if (ehci->rh_state != EHCI_RH_RUNNING)
272 /* wait for any schedule enables/disables to take effect */
273 temp = (ehci->command << 10) & (STS_ASS | STS_PSS);
274 handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, temp, 16 * 125);
276 /* then disable anything that's still active */
277 spin_lock_irq(&ehci->lock);
278 ehci->command &= ~(CMD_ASE | CMD_PSE);
279 ehci_writel(ehci, ehci->command, &ehci->regs->command);
280 spin_unlock_irq(&ehci->lock);
282 /* hardware can take 16 microframes to turn off ... */
283 handshake(ehci, &ehci->regs->status, STS_ASS | STS_PSS, 0, 16 * 125);
286 /*-------------------------------------------------------------------------*/
288 static void end_unlink_async(struct ehci_hcd *ehci);
289 static void unlink_empty_async(struct ehci_hcd *ehci);
290 static void ehci_work(struct ehci_hcd *ehci);
291 static void start_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
292 static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh);
294 #include "ehci-timer.c"
295 #include "ehci-hub.c"
296 #include "ehci-lpm.c"
297 #include "ehci-mem.c"
299 #include "ehci-sched.c"
300 #include "ehci-sysfs.c"
302 /*-------------------------------------------------------------------------*/
304 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
305 * The firmware seems to think that powering off is a wakeup event!
306 * This routine turns off remote wakeup and everything else, on all ports.
308 static void ehci_turn_off_all_ports(struct ehci_hcd *ehci)
310 int port = HCS_N_PORTS(ehci->hcs_params);
313 ehci_writel(ehci, PORT_RWC_BITS,
314 &ehci->regs->port_status[port]);
318 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
319 * Must be called with interrupts enabled and the lock not held.
321 static void ehci_silence_controller(struct ehci_hcd *ehci)
325 spin_lock_irq(&ehci->lock);
326 ehci->rh_state = EHCI_RH_HALTED;
327 ehci_turn_off_all_ports(ehci);
329 /* make BIOS/etc use companion controller during reboot */
330 ehci_writel(ehci, 0, &ehci->regs->configured_flag);
332 /* unblock posted writes */
333 ehci_readl(ehci, &ehci->regs->configured_flag);
334 spin_unlock_irq(&ehci->lock);
337 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
338 * This forcibly disables dma and IRQs, helping kexec and other cases
339 * where the next system software may expect clean state.
341 static void ehci_shutdown(struct usb_hcd *hcd)
343 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
345 spin_lock_irq(&ehci->lock);
346 ehci->shutdown = true;
347 ehci->rh_state = EHCI_RH_STOPPING;
348 ehci->enabled_hrtimer_events = 0;
349 spin_unlock_irq(&ehci->lock);
351 ehci_silence_controller(ehci);
353 hrtimer_cancel(&ehci->hrtimer);
356 static void ehci_port_power (struct ehci_hcd *ehci, int is_on)
360 if (!HCS_PPC (ehci->hcs_params))
363 ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down");
364 for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; )
365 (void) ehci_hub_control(ehci_to_hcd(ehci),
366 is_on ? SetPortFeature : ClearPortFeature,
369 /* Flush those writes */
370 ehci_readl(ehci, &ehci->regs->command);
374 /*-------------------------------------------------------------------------*/
377 * ehci_work is called from some interrupts, timers, and so on.
378 * it calls driver completion functions, after dropping ehci->lock.
380 static void ehci_work (struct ehci_hcd *ehci)
382 /* another CPU may drop ehci->lock during a schedule scan while
383 * it reports urb completions. this flag guards against bogus
384 * attempts at re-entrant schedule scanning.
386 if (ehci->scanning) {
387 ehci->need_rescan = true;
390 ehci->scanning = true;
393 ehci->need_rescan = false;
394 if (ehci->async_count)
396 if (ehci->intr_count > 0)
398 if (ehci->isoc_count > 0)
400 if (ehci->need_rescan)
402 ehci->scanning = false;
404 /* the IO watchdog guards against hardware or driver bugs that
405 * misplace IRQs, and should let us run completely without IRQs.
406 * such lossage has been observed on both VT6202 and VT8235.
408 turn_on_io_watchdog(ehci);
412 * Called when the ehci_hcd module is removed.
414 static void ehci_stop (struct usb_hcd *hcd)
416 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
418 ehci_dbg (ehci, "stop\n");
420 /* no more interrupts ... */
422 spin_lock_irq(&ehci->lock);
423 ehci->enabled_hrtimer_events = 0;
424 spin_unlock_irq(&ehci->lock);
427 ehci_silence_controller(ehci);
430 hrtimer_cancel(&ehci->hrtimer);
431 remove_sysfs_files(ehci);
432 remove_debug_files (ehci);
434 /* root hub is shut down separately (first, when possible) */
435 spin_lock_irq (&ehci->lock);
437 spin_unlock_irq (&ehci->lock);
438 ehci_mem_cleanup (ehci);
440 if (ehci->amd_pll_fix == 1)
444 ehci_dbg(ehci, "irq normal %ld err %ld iaa %ld (lost %ld)\n",
445 ehci->stats.normal, ehci->stats.error, ehci->stats.iaa,
446 ehci->stats.lost_iaa);
447 ehci_dbg (ehci, "complete %ld unlink %ld\n",
448 ehci->stats.complete, ehci->stats.unlink);
451 dbg_status (ehci, "ehci_stop completed",
452 ehci_readl(ehci, &ehci->regs->status));
455 /* one-time init, only for memory state */
456 static int ehci_init(struct usb_hcd *hcd)
458 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
462 struct ehci_qh_hw *hw;
464 spin_lock_init(&ehci->lock);
467 * keep io watchdog by default, those good HCDs could turn off it later
469 ehci->need_io_watchdog = 1;
471 hrtimer_init(&ehci->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
472 ehci->hrtimer.function = ehci_hrtimer_func;
473 ehci->next_hrtimer_event = EHCI_HRTIMER_NO_EVENT;
475 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
478 * by default set standard 80% (== 100 usec/uframe) max periodic
479 * bandwidth as required by USB 2.0
481 ehci->uframe_periodic_max = 100;
484 * hw default: 1K periodic list heads, one per frame.
485 * periodic_size can shrink by USBCMD update if hcc_params allows.
487 ehci->periodic_size = DEFAULT_I_TDPS;
488 INIT_LIST_HEAD(&ehci->intr_qh_list);
489 INIT_LIST_HEAD(&ehci->cached_itd_list);
490 INIT_LIST_HEAD(&ehci->cached_sitd_list);
492 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
493 /* periodic schedule size can be smaller than default */
494 switch (EHCI_TUNE_FLS) {
495 case 0: ehci->periodic_size = 1024; break;
496 case 1: ehci->periodic_size = 512; break;
497 case 2: ehci->periodic_size = 256; break;
501 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
504 /* controllers may cache some of the periodic schedule ... */
505 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
506 ehci->i_thresh = 2 + 8;
507 else // N microframes cached
508 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
511 * dedicate a qh for the async ring head, since we couldn't unlink
512 * a 'real' qh without stopping the async schedule [4.8]. use it
513 * as the 'reclamation list head' too.
514 * its dummy is used in hw_alt_next of many tds, to prevent the qh
515 * from automatically advancing to the next td after short reads.
517 ehci->async->qh_next.qh = NULL;
518 hw = ehci->async->hw;
519 hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma);
520 hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD);
521 #if defined(CONFIG_PPC_PS3)
522 hw->hw_info1 |= cpu_to_hc32(ehci, QH_INACTIVATE);
524 hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
525 hw->hw_qtd_next = EHCI_LIST_END(ehci);
526 ehci->async->qh_state = QH_STATE_LINKED;
527 hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma);
529 /* clear interrupt enables, set irq latency */
530 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
532 temp = 1 << (16 + log2_irq_thresh);
533 if (HCC_PER_PORT_CHANGE_EVENT(hcc_params)) {
535 ehci_dbg(ehci, "enable per-port change event\n");
538 if (HCC_CANPARK(hcc_params)) {
539 /* HW default park == 3, on hardware that supports it (like
540 * NVidia and ALI silicon), maximizes throughput on the async
541 * schedule by avoiding QH fetches between transfers.
543 * With fast usb storage devices and NForce2, "park" seems to
544 * make problems: throughput reduction (!), data errors...
547 park = min(park, (unsigned) 3);
551 ehci_dbg(ehci, "park %d\n", park);
553 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
554 /* periodic schedule size can be smaller than default */
556 temp |= (EHCI_TUNE_FLS << 2);
558 if (HCC_LPM(hcc_params)) {
559 /* support link power management EHCI 1.1 addendum */
560 ehci_dbg(ehci, "support lpm\n");
563 ehci_dbg(ehci, "hird %d invalid, use default 0",
569 ehci->command = temp;
571 /* Accept arbitrarily long scatter-gather lists */
572 if (!(hcd->driver->flags & HCD_LOCAL_MEM))
573 hcd->self.sg_tablesize = ~0;
577 /* start HC running; it's halted, ehci_init() has been run (once) */
578 static int ehci_run (struct usb_hcd *hcd)
580 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
584 hcd->uses_new_polling = 1;
586 /* EHCI spec section 4.1 */
588 ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
589 ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
592 * hcc_params controls whether ehci->regs->segment must (!!!)
593 * be used; it constrains QH/ITD/SITD and QTD locations.
594 * pci_pool consistent memory always uses segment zero.
595 * streaming mappings for I/O buffers, like pci_map_single(),
596 * can return segments above 4GB, if the device allows.
598 * NOTE: the dma mask is visible through dma_supported(), so
599 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
600 * Scsi_Host.highmem_io, and so forth. It's readonly to all
601 * host side drivers though.
603 hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
604 if (HCC_64BIT_ADDR(hcc_params)) {
605 ehci_writel(ehci, 0, &ehci->regs->segment);
607 // this is deeply broken on almost all architectures
608 if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64)))
609 ehci_info(ehci, "enabled 64bit DMA\n");
614 // Philips, Intel, and maybe others need CMD_RUN before the
615 // root hub will detect new devices (why?); NEC doesn't
616 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
617 ehci->command |= CMD_RUN;
618 ehci_writel(ehci, ehci->command, &ehci->regs->command);
619 dbg_cmd (ehci, "init", ehci->command);
622 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
623 * are explicitly handed to companion controller(s), so no TT is
624 * involved with the root hub. (Except where one is integrated,
625 * and there's no companion controller unless maybe for USB OTG.)
627 * Turning on the CF flag will transfer ownership of all ports
628 * from the companions to the EHCI controller. If any of the
629 * companions are in the middle of a port reset at the time, it
630 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
631 * guarantees that no resets are in progress. After we set CF,
632 * a short delay lets the hardware catch up; new resets shouldn't
633 * be started before the port switching actions could complete.
635 down_write(&ehci_cf_port_reset_rwsem);
636 ehci->rh_state = EHCI_RH_RUNNING;
637 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
638 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
640 up_write(&ehci_cf_port_reset_rwsem);
641 ehci->last_periodic_enable = ktime_get_real();
643 temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
645 "USB %x.%x started, EHCI %x.%02x%s\n",
646 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
647 temp >> 8, temp & 0xff,
648 ignore_oc ? ", overcurrent ignored" : "");
650 ehci_writel(ehci, INTR_MASK,
651 &ehci->regs->intr_enable); /* Turn On Interrupts */
653 /* GRR this is run-once init(), being done every time the HC starts.
654 * So long as they're part of class devices, we can't do it init()
655 * since the class device isn't created that early.
657 create_debug_files(ehci);
658 create_sysfs_files(ehci);
663 static int ehci_setup(struct usb_hcd *hcd)
665 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
668 ehci->regs = (void __iomem *)ehci->caps +
669 HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
670 dbg_hcs_params(ehci, "reset");
671 dbg_hcc_params(ehci, "reset");
673 /* cache this readonly data; minimize chip reads */
674 ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
676 ehci->sbrn = HCD_USB2;
678 /* data structure init */
679 retval = ehci_init(hcd);
683 retval = ehci_halt(ehci);
687 if (ehci_is_TDI(ehci))
695 /*-------------------------------------------------------------------------*/
697 static irqreturn_t ehci_irq (struct usb_hcd *hcd)
699 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
700 u32 status, masked_status, pcd_status = 0, cmd;
703 spin_lock (&ehci->lock);
705 status = ehci_readl(ehci, &ehci->regs->status);
707 /* e.g. cardbus physical eject */
708 if (status == ~(u32) 0) {
709 ehci_dbg (ehci, "device removed\n");
714 * We don't use STS_FLR, but some controllers don't like it to
715 * remain on, so mask it out along with the other status bits.
717 masked_status = status & (INTR_MASK | STS_FLR);
720 if (!masked_status || unlikely(ehci->rh_state == EHCI_RH_HALTED)) {
721 spin_unlock(&ehci->lock);
725 /* clear (just) interrupts */
726 ehci_writel(ehci, masked_status, &ehci->regs->status);
727 cmd = ehci_readl(ehci, &ehci->regs->command);
731 /* unrequested/ignored: Frame List Rollover */
732 dbg_status (ehci, "irq", status);
735 /* INT, ERR, and IAA interrupt rates can be throttled */
737 /* normal [4.15.1.2] or error [4.15.1.1] completion */
738 if (likely ((status & (STS_INT|STS_ERR)) != 0)) {
739 if (likely ((status & STS_ERR) == 0))
740 COUNT (ehci->stats.normal);
742 COUNT (ehci->stats.error);
746 /* complete the unlinking of some qh [4.15.2.3] */
747 if (status & STS_IAA) {
749 /* Turn off the IAA watchdog */
750 ehci->enabled_hrtimer_events &= ~BIT(EHCI_HRTIMER_IAA_WATCHDOG);
753 * Mild optimization: Allow another IAAD to reset the
754 * hrtimer, if one occurs before the next expiration.
755 * In theory we could always cancel the hrtimer, but
756 * tests show that about half the time it will be reset
757 * for some other event anyway.
759 if (ehci->next_hrtimer_event == EHCI_HRTIMER_IAA_WATCHDOG)
760 ++ehci->next_hrtimer_event;
762 /* guard against (alleged) silicon errata */
764 ehci_dbg(ehci, "IAA with IAAD still set?\n");
765 if (ehci->async_iaa) {
766 COUNT(ehci->stats.iaa);
767 end_unlink_async(ehci);
769 ehci_dbg(ehci, "IAA with nothing unlinked?\n");
772 /* remote wakeup [4.3.1] */
773 if (status & STS_PCD) {
774 unsigned i = HCS_N_PORTS (ehci->hcs_params);
777 /* kick root hub later */
780 /* resume root hub? */
781 if (ehci->rh_state == EHCI_RH_SUSPENDED)
782 usb_hcd_resume_root_hub(hcd);
784 /* get per-port change detect bits */
791 /* leverage per-port change bits feature */
792 if (ehci->has_ppcd && !(ppcd & (1 << i)))
794 pstatus = ehci_readl(ehci,
795 &ehci->regs->port_status[i]);
797 if (pstatus & PORT_OWNER)
799 if (!(test_bit(i, &ehci->suspended_ports) &&
800 ((pstatus & PORT_RESUME) ||
801 !(pstatus & PORT_SUSPEND)) &&
802 (pstatus & PORT_PE) &&
803 ehci->reset_done[i] == 0))
806 /* start 20 msec resume signaling from this port,
807 * and make khubd collect PORT_STAT_C_SUSPEND to
808 * stop that signaling. Use 5 ms extra for safety,
809 * like usb_port_resume() does.
811 ehci->reset_done[i] = jiffies + msecs_to_jiffies(25);
812 set_bit(i, &ehci->resuming_ports);
813 ehci_dbg (ehci, "port %d remote wakeup\n", i + 1);
814 mod_timer(&hcd->rh_timer, ehci->reset_done[i]);
818 /* PCI errors [4.15.2.4] */
819 if (unlikely ((status & STS_FATAL) != 0)) {
820 ehci_err(ehci, "fatal error\n");
821 dbg_cmd(ehci, "fatal", cmd);
822 dbg_status(ehci, "fatal", status);
826 /* Don't let the controller do anything more */
827 ehci->shutdown = true;
828 ehci->rh_state = EHCI_RH_STOPPING;
829 ehci->command &= ~(CMD_RUN | CMD_ASE | CMD_PSE);
830 ehci_writel(ehci, ehci->command, &ehci->regs->command);
831 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
832 ehci_handle_controller_death(ehci);
834 /* Handle completions when the controller stops */
840 spin_unlock (&ehci->lock);
842 usb_hcd_poll_rh_status(hcd);
846 /*-------------------------------------------------------------------------*/
849 * non-error returns are a promise to giveback() the urb later
850 * we drop ownership so next owner (or urb unlink) can get it
852 * urb + dev is in hcd.self.controller.urb_list
853 * we're queueing TDs onto software and hardware lists
855 * hcd-specific init for hcpriv hasn't been done yet
857 * NOTE: control, bulk, and interrupt share the same code to append TDs
858 * to a (possibly active) QH, and the same QH scanning code.
860 static int ehci_urb_enqueue (
865 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
866 struct list_head qtd_list;
868 INIT_LIST_HEAD (&qtd_list);
870 switch (usb_pipetype (urb->pipe)) {
872 /* qh_completions() code doesn't handle all the fault cases
873 * in multi-TD control transfers. Even 1KB is rare anyway.
875 if (urb->transfer_buffer_length > (16 * 1024))
878 /* case PIPE_BULK: */
880 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
882 return submit_async(ehci, urb, &qtd_list, mem_flags);
885 if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags))
887 return intr_submit(ehci, urb, &qtd_list, mem_flags);
889 case PIPE_ISOCHRONOUS:
890 if (urb->dev->speed == USB_SPEED_HIGH)
891 return itd_submit (ehci, urb, mem_flags);
893 return sitd_submit (ehci, urb, mem_flags);
897 /* remove from hardware lists
898 * completions normally happen asynchronously
901 static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
903 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
908 spin_lock_irqsave (&ehci->lock, flags);
909 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
913 switch (usb_pipetype (urb->pipe)) {
914 // case PIPE_CONTROL:
917 qh = (struct ehci_qh *) urb->hcpriv;
920 switch (qh->qh_state) {
921 case QH_STATE_LINKED:
922 case QH_STATE_COMPLETING:
923 start_unlink_async(ehci, qh);
925 case QH_STATE_UNLINK:
926 case QH_STATE_UNLINK_WAIT:
927 /* already started */
930 /* QH might be waiting for a Clear-TT-Buffer */
931 qh_completions(ehci, qh);
937 qh = (struct ehci_qh *) urb->hcpriv;
940 switch (qh->qh_state) {
941 case QH_STATE_LINKED:
942 case QH_STATE_COMPLETING:
943 start_unlink_intr(ehci, qh);
946 qh_completions (ehci, qh);
949 ehci_dbg (ehci, "bogus qh %p state %d\n",
955 case PIPE_ISOCHRONOUS:
958 // wait till next completion, do it then.
959 // completion irqs can wait up to 1024 msec,
963 spin_unlock_irqrestore (&ehci->lock, flags);
967 /*-------------------------------------------------------------------------*/
969 // bulk qh holds the data toggle
972 ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
974 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
976 struct ehci_qh *qh, *tmp;
978 /* ASSERT: any requests/urbs are being unlinked */
979 /* ASSERT: nobody can be submitting urbs for this any more */
982 spin_lock_irqsave (&ehci->lock, flags);
987 /* endpoints can be iso streams. for now, we don't
988 * accelerate iso completions ... so spin a while.
990 if (qh->hw == NULL) {
991 struct ehci_iso_stream *stream = ep->hcpriv;
993 if (!list_empty(&stream->td_list))
996 /* BUG_ON(!list_empty(&stream->free_list)); */
1001 if (ehci->rh_state < EHCI_RH_RUNNING)
1002 qh->qh_state = QH_STATE_IDLE;
1003 switch (qh->qh_state) {
1004 case QH_STATE_LINKED:
1005 case QH_STATE_COMPLETING:
1006 for (tmp = ehci->async->qh_next.qh;
1008 tmp = tmp->qh_next.qh)
1010 /* periodic qh self-unlinks on empty, and a COMPLETING qh
1011 * may already be unlinked.
1014 start_unlink_async(ehci, qh);
1016 case QH_STATE_UNLINK: /* wait for hw to finish? */
1017 case QH_STATE_UNLINK_WAIT:
1019 spin_unlock_irqrestore (&ehci->lock, flags);
1020 schedule_timeout_uninterruptible(1);
1022 case QH_STATE_IDLE: /* fully unlinked */
1023 if (qh->clearing_tt)
1025 if (list_empty (&qh->qtd_list)) {
1026 qh_destroy(ehci, qh);
1029 /* else FALL THROUGH */
1031 /* caller was supposed to have unlinked any requests;
1032 * that's not our job. just leak this memory.
1034 ehci_err (ehci, "qh %p (#%02x) state %d%s\n",
1035 qh, ep->desc.bEndpointAddress, qh->qh_state,
1036 list_empty (&qh->qtd_list) ? "" : "(has tds)");
1041 spin_unlock_irqrestore (&ehci->lock, flags);
1045 ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
1047 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1049 int eptype = usb_endpoint_type(&ep->desc);
1050 int epnum = usb_endpoint_num(&ep->desc);
1051 int is_out = usb_endpoint_dir_out(&ep->desc);
1052 unsigned long flags;
1054 if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT)
1057 spin_lock_irqsave(&ehci->lock, flags);
1060 /* For Bulk and Interrupt endpoints we maintain the toggle state
1061 * in the hardware; the toggle bits in udev aren't used at all.
1062 * When an endpoint is reset by usb_clear_halt() we must reset
1063 * the toggle bit in the QH.
1066 usb_settoggle(qh->dev, epnum, is_out, 0);
1067 if (!list_empty(&qh->qtd_list)) {
1068 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1069 } else if (qh->qh_state == QH_STATE_LINKED ||
1070 qh->qh_state == QH_STATE_COMPLETING) {
1072 /* The toggle value in the QH can't be updated
1073 * while the QH is active. Unlink it now;
1074 * re-linking will call qh_refresh().
1076 if (eptype == USB_ENDPOINT_XFER_BULK)
1077 start_unlink_async(ehci, qh);
1079 start_unlink_intr(ehci, qh);
1082 spin_unlock_irqrestore(&ehci->lock, flags);
1085 static int ehci_get_frame (struct usb_hcd *hcd)
1087 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
1088 return (ehci_read_frame_index(ehci) >> 3) % ehci->periodic_size;
1091 /*-------------------------------------------------------------------------*/
1095 /* suspend/resume, section 4.3 */
1097 /* These routines handle the generic parts of controller suspend/resume */
1099 static int __maybe_unused ehci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1101 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1103 if (time_before(jiffies, ehci->next_statechange))
1107 * Root hub was already suspended. Disable IRQ emission and
1108 * mark HW unaccessible. The PM and USB cores make sure that
1109 * the root hub is either suspended or stopped.
1111 ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
1113 spin_lock_irq(&ehci->lock);
1114 ehci_writel(ehci, 0, &ehci->regs->intr_enable);
1115 (void) ehci_readl(ehci, &ehci->regs->intr_enable);
1117 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1118 spin_unlock_irq(&ehci->lock);
1123 /* Returns 0 if power was preserved, 1 if power was lost */
1124 static int __maybe_unused ehci_resume(struct usb_hcd *hcd, bool hibernated)
1126 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1128 if (time_before(jiffies, ehci->next_statechange))
1131 /* Mark hardware accessible again as we are back to full power by now */
1132 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1135 return 0; /* Controller is dead */
1138 * If CF is still set and we aren't resuming from hibernation
1139 * then we maintained suspend power.
1140 * Just undo the effect of ehci_suspend().
1142 if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
1144 int mask = INTR_MASK;
1146 ehci_prepare_ports_for_controller_resume(ehci);
1148 spin_lock_irq(&ehci->lock);
1152 if (!hcd->self.root_hub->do_remote_wakeup)
1154 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
1155 ehci_readl(ehci, &ehci->regs->intr_enable);
1157 spin_unlock_irq(&ehci->lock);
1162 * Else reset, to cope with power loss or resume from hibernation
1163 * having let the firmware kick in during reboot.
1165 usb_root_hub_lost_power(hcd->self.root_hub);
1166 (void) ehci_halt(ehci);
1167 (void) ehci_reset(ehci);
1169 spin_lock_irq(&ehci->lock);
1173 ehci_writel(ehci, ehci->command, &ehci->regs->command);
1174 ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
1175 ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
1177 ehci->rh_state = EHCI_RH_SUSPENDED;
1178 spin_unlock_irq(&ehci->lock);
1180 /* here we "know" root ports should always stay powered */
1181 ehci_port_power(ehci, 1);
1188 /*-------------------------------------------------------------------------*/
1191 * The EHCI in ChipIdea HDRC cannot be a separate module or device,
1192 * because its registers (and irq) are shared between host/gadget/otg
1193 * functions and in order to facilitate role switching we cannot
1194 * give the ehci driver exclusive access to those.
1196 #ifndef CHIPIDEA_EHCI
1198 MODULE_DESCRIPTION(DRIVER_DESC);
1199 MODULE_AUTHOR (DRIVER_AUTHOR);
1200 MODULE_LICENSE ("GPL");
1203 #include "ehci-pci.c"
1204 #define PCI_DRIVER ehci_pci_driver
1207 #ifdef CONFIG_USB_EHCI_FSL
1208 #include "ehci-fsl.c"
1209 #define PLATFORM_DRIVER ehci_fsl_driver
1212 #ifdef CONFIG_USB_EHCI_MXC
1213 #include "ehci-mxc.c"
1214 #define PLATFORM_DRIVER ehci_mxc_driver
1217 #ifdef CONFIG_USB_EHCI_SH
1218 #include "ehci-sh.c"
1219 #define PLATFORM_DRIVER ehci_hcd_sh_driver
1222 #ifdef CONFIG_MIPS_ALCHEMY
1223 #include "ehci-au1xxx.c"
1224 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1227 #ifdef CONFIG_USB_EHCI_HCD_OMAP
1228 #include "ehci-omap.c"
1229 #define PLATFORM_DRIVER ehci_hcd_omap_driver
1232 #ifdef CONFIG_PPC_PS3
1233 #include "ehci-ps3.c"
1234 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1237 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1238 #include "ehci-ppc-of.c"
1239 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1242 #ifdef CONFIG_XPS_USB_HCD_XILINX
1243 #include "ehci-xilinx-of.c"
1244 #define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver
1247 #ifdef CONFIG_PLAT_ORION
1248 #include "ehci-orion.c"
1249 #define PLATFORM_DRIVER ehci_orion_driver
1252 #ifdef CONFIG_ARCH_IXP4XX
1253 #include "ehci-ixp4xx.c"
1254 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1257 #ifdef CONFIG_USB_W90X900_EHCI
1258 #include "ehci-w90x900.c"
1259 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1262 #ifdef CONFIG_ARCH_AT91
1263 #include "ehci-atmel.c"
1264 #define PLATFORM_DRIVER ehci_atmel_driver
1267 #ifdef CONFIG_USB_OCTEON_EHCI
1268 #include "ehci-octeon.c"
1269 #define PLATFORM_DRIVER ehci_octeon_driver
1272 #ifdef CONFIG_USB_CNS3XXX_EHCI
1273 #include "ehci-cns3xxx.c"
1274 #define PLATFORM_DRIVER cns3xxx_ehci_driver
1277 #ifdef CONFIG_ARCH_VT8500
1278 #include "ehci-vt8500.c"
1279 #define PLATFORM_DRIVER vt8500_ehci_driver
1282 #ifdef CONFIG_PLAT_SPEAR
1283 #include "ehci-spear.c"
1284 #define PLATFORM_DRIVER spear_ehci_hcd_driver
1287 #ifdef CONFIG_USB_EHCI_MSM
1288 #include "ehci-msm.c"
1289 #define PLATFORM_DRIVER ehci_msm_driver
1292 #ifdef CONFIG_TILE_USB
1293 #include "ehci-tilegx.c"
1294 #define PLATFORM_DRIVER ehci_hcd_tilegx_driver
1297 #ifdef CONFIG_USB_EHCI_HCD_PMC_MSP
1298 #include "ehci-pmcmsp.c"
1299 #define PLATFORM_DRIVER ehci_hcd_msp_driver
1302 #ifdef CONFIG_USB_EHCI_TEGRA
1303 #include "ehci-tegra.c"
1304 #define PLATFORM_DRIVER tegra_ehci_driver
1307 #ifdef CONFIG_USB_EHCI_S5P
1308 #include "ehci-s5p.c"
1309 #define PLATFORM_DRIVER s5p_ehci_driver
1312 #ifdef CONFIG_SPARC_LEON
1313 #include "ehci-grlib.c"
1314 #define PLATFORM_DRIVER ehci_grlib_driver
1317 #ifdef CONFIG_CPU_XLR
1318 #include "ehci-xls.c"
1319 #define PLATFORM_DRIVER ehci_xls_driver
1322 #ifdef CONFIG_USB_EHCI_MV
1323 #include "ehci-mv.c"
1324 #define PLATFORM_DRIVER ehci_mv_driver
1327 #ifdef CONFIG_MACH_LOONGSON1
1328 #include "ehci-ls1x.c"
1329 #define PLATFORM_DRIVER ehci_ls1x_driver
1332 #ifdef CONFIG_MIPS_SEAD3
1333 #include "ehci-sead3.c"
1334 #define PLATFORM_DRIVER ehci_hcd_sead3_driver
1337 #ifdef CONFIG_USB_EHCI_HCD_PLATFORM
1338 #include "ehci-platform.c"
1339 #define PLATFORM_DRIVER ehci_platform_driver
1342 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1343 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
1344 !defined(XILINX_OF_PLATFORM_DRIVER)
1345 #error "missing bus glue for ehci-hcd"
1348 static int __init ehci_hcd_init(void)
1355 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1356 set_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1357 if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) ||
1358 test_bit(USB_OHCI_LOADED, &usb_hcds_loaded))
1359 printk(KERN_WARNING "Warning! ehci_hcd should always be loaded"
1360 " before uhci_hcd and ohci_hcd, not after\n");
1362 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1364 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
1365 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
1368 ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root);
1369 if (!ehci_debug_root) {
1375 #ifdef PLATFORM_DRIVER
1376 retval = platform_driver_register(&PLATFORM_DRIVER);
1382 retval = pci_register_driver(&PCI_DRIVER);
1387 #ifdef PS3_SYSTEM_BUS_DRIVER
1388 retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1393 #ifdef OF_PLATFORM_DRIVER
1394 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1399 #ifdef XILINX_OF_PLATFORM_DRIVER
1400 retval = platform_driver_register(&XILINX_OF_PLATFORM_DRIVER);
1406 #ifdef XILINX_OF_PLATFORM_DRIVER
1407 /* platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER); */
1410 #ifdef OF_PLATFORM_DRIVER
1411 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1414 #ifdef PS3_SYSTEM_BUS_DRIVER
1415 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1419 pci_unregister_driver(&PCI_DRIVER);
1422 #ifdef PLATFORM_DRIVER
1423 platform_driver_unregister(&PLATFORM_DRIVER);
1427 debugfs_remove(ehci_debug_root);
1428 ehci_debug_root = NULL;
1431 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1434 module_init(ehci_hcd_init);
1436 static void __exit ehci_hcd_cleanup(void)
1438 #ifdef XILINX_OF_PLATFORM_DRIVER
1439 platform_driver_unregister(&XILINX_OF_PLATFORM_DRIVER);
1441 #ifdef OF_PLATFORM_DRIVER
1442 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1444 #ifdef PLATFORM_DRIVER
1445 platform_driver_unregister(&PLATFORM_DRIVER);
1448 pci_unregister_driver(&PCI_DRIVER);
1450 #ifdef PS3_SYSTEM_BUS_DRIVER
1451 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1454 debugfs_remove(ehci_debug_root);
1456 clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded);
1458 module_exit(ehci_hcd_cleanup);
1460 #endif /* CHIPIDEA_EHCI */