drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* called after powerup, by probe or system-pm "wakeup" */
  28 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  29 {
  30         int                     retval;
  31
  32         /* we expect static quirk code to handle the "extended capabilities"
  33          * (currently just BIOS handoff) allowed starting with EHCI 0.96
  34          */
  35
  36         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
  37         retval = pci_set_mwi(pdev);
  38         if (!retval)
  39                 ehci_dbg(ehci, "MWI active\n");
  40
  41         return 0;
  42 }
  43
  44 /* called during probe() after chip reset completes */
  45 static int ehci_pci_setup(struct usb_hcd *hcd)
  46 {
  47         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
  48         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
  49         struct pci_dev          *p_smbus;
  50         u8                      rev;
  51         u32                     temp;
  52         int                     retval;
  53
  54         switch (pdev->vendor) {
  55         case PCI_VENDOR_ID_TOSHIBA_2:
  56                 /* celleb's companion chip */
  57                 if (pdev->device == 0x01b5) {
  58 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
  59                         ehci->big_endian_mmio = 1;
  60 #else
  61                         ehci_warn(ehci,
  62                                   "unsupported big endian Toshiba quirk\n");
  63 #endif
  64                 }
  65                 break;
  66         }
  67
  68         ehci->caps = hcd->regs;
  69         ehci->regs = hcd->regs +
  70                 HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
  71
  72         dbg_hcs_params(ehci, "reset");
  73         dbg_hcc_params(ehci, "reset");
  74
  75         /* ehci_init() causes memory for DMA transfers to be
  76          * allocated.  Thus, any vendor-specific workarounds based on
  77          * limiting the type of memory used for DMA transfers must
  78          * happen before ehci_init() is called. */
  79         switch (pdev->vendor) {
  80         case PCI_VENDOR_ID_NVIDIA:
  81                 /* NVidia reports that certain chips don't handle
  82                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
  83                  * data buffer, and periodic schedule are normal.)
  84                  */
  85                 switch (pdev->device) {
  86                 case 0x003c:    /* MCP04 */
  87                 case 0x005b:    /* CK804 */
  88                 case 0x00d8:    /* CK8 */
  89                 case 0x00e8:    /* CK8S */
  90                         if (pci_set_consistent_dma_mask(pdev,
  91                                                 DMA_BIT_MASK(31)) < 0)
  92                                 ehci_warn(ehci, "can't enable NVidia "
  93                                         "workaround for >2GB RAM\n");
  94                         break;
  95                 }
  96                 break;
  97         }
  98
  99         /* cache this readonly data; minimize chip reads */
 100         ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
 101
 102         retval = ehci_halt(ehci);
 103         if (retval)
 104                 return retval;
 105
 106         if ((pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x7808) ||
 107             (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x4396)) {
 108                 /* EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
 109                  * read/write memory space which does not belong to it when
 110                  * there is NULL pointer with T-bit set to 1 in the frame list
 111                  * table. To avoid the issue, the frame list link pointer
 112                  * should always contain a valid pointer to a inactive qh.
 113                  */
 114                 ehci->use_dummy_qh = 1;
 115                 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI "
 116                                 "dummy qh workaround\n");
 117         }
 118
 119         /* data structure init */
 120         retval = ehci_init(hcd);
 121         if (retval)
 122                 return retval;
 123
 124         switch (pdev->vendor) {
 125         case PCI_VENDOR_ID_NEC:
 126                 ehci->need_io_watchdog = 0;
 127                 break;
 128         case PCI_VENDOR_ID_INTEL:
 129                 ehci->need_io_watchdog = 0;
 130                 ehci->fs_i_thresh = 1;
 131                 if (pdev->device == 0x27cc) {
 132                         ehci->broken_periodic = 1;
 133                         ehci_info(ehci, "using broken periodic workaround\n");
 134                 }
 135                 if (pdev->device == 0x0806 || pdev->device == 0x0811
 136                                 || pdev->device == 0x0829) {
 137                         ehci_info(ehci, "disable lpm for langwell/penwell\n");
 138                         ehci->has_lpm = 0;
 139                 }
 140                 break;
 141         case PCI_VENDOR_ID_TDI:
 142                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 143                         hcd->has_tt = 1;
 144                         tdi_reset(ehci);
 145                 }
 146                 break;
 147         case PCI_VENDOR_ID_AMD:
 148                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 149                 if (pdev->device == 0x7463) {
 150                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 151                         retval = -EIO;
 152                         goto done;
 153                 }
 154                 break;
 155         case PCI_VENDOR_ID_NVIDIA:
 156                 switch (pdev->device) {
 157                 /* Some NForce2 chips have problems with selective suspend;
 158                  * fixed in newer silicon.
 159                  */
 160                 case 0x0068:
 161                         if (pdev->revision < 0xa4)
 162                                 ehci->no_selective_suspend = 1;
 163                         break;
 164
 165                 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
 166                  * fetching device descriptors unless LPM is disabled.
 167                  * There are also intermittent problems enumerating
 168                  * devices with PPCD enabled.
 169                  */
 170                 case 0x0d9d:
 171                         ehci_info(ehci, "disable lpm/ppcd for nvidia mcp89");
 172                         ehci->has_lpm = 0;
 173                         ehci->has_ppcd = 0;
 174                         ehci->command &= ~CMD_PPCEE;
 175                         break;
 176                 }
 177                 break;
 178         case PCI_VENDOR_ID_VIA:
 179                 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
 180                         u8 tmp;
 181
 182                         /* The VT6212 defaults to a 1 usec EHCI sleep time which
 183                          * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
 184                          * that sleep time use the conventional 10 usec.
 185                          */
 186                         pci_read_config_byte(pdev, 0x4b, &tmp);
 187                         if (tmp & 0x20)
 188                                 break;
 189                         pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
 190                 }
 191                 break;
 192         case PCI_VENDOR_ID_ATI:
 193                 /* SB600 and old version of SB700 have a bug in EHCI controller,
 194                  * which causes usb devices lose response in some cases.
 195                  */
 196                 if ((pdev->device == 0x4386) || (pdev->device == 0x4396)) {
 197                         p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
 198                                                  PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 199                                                  NULL);
 200                         if (!p_smbus)
 201                                 break;
 202                         rev = p_smbus->revision;
 203                         if ((pdev->device == 0x4386) || (rev == 0x3a)
 204                             || (rev == 0x3b)) {
 205                                 u8 tmp;
 206                                 ehci_info(ehci, "applying AMD SB600/SB700 USB "
 207                                         "freeze workaround\n");
 208                                 pci_read_config_byte(pdev, 0x53, &tmp);
 209                                 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
 210                         }
 211                         pci_dev_put(p_smbus);
 212                 }
 213                 break;
 214         }
 215
 216         /* optional debug port, normally in the first BAR */
 217         temp = pci_find_capability(pdev, 0x0a);
 218         if (temp) {
 219                 pci_read_config_dword(pdev, temp, &temp);
 220                 temp >>= 16;
 221                 if ((temp & (3 << 13)) == (1 << 13)) {
 222                         temp &= 0x1fff;
 223                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
 224                         temp = ehci_readl(ehci, &ehci->debug->control);
 225                         ehci_info(ehci, "debug port %d%s\n",
 226                                 HCS_DEBUG_PORT(ehci->hcs_params),
 227                                 (temp & DBGP_ENABLED)
 228                                         ? " IN USE"
 229                                         : "");
 230                         if (!(temp & DBGP_ENABLED))
 231                                 ehci->debug = NULL;
 232                 }
 233         }
 234
 235         ehci_reset(ehci);
 236
 237         /* at least the Genesys GL880S needs fixup here */
 238         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 239         temp &= 0x0f;
 240         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 241                 ehci_dbg(ehci, "bogus port configuration: "
 242                         "cc=%d x pcc=%d < ports=%d\n",
 243                         HCS_N_CC(ehci->hcs_params),
 244                         HCS_N_PCC(ehci->hcs_params),
 245                         HCS_N_PORTS(ehci->hcs_params));
 246
 247                 switch (pdev->vendor) {
 248                 case 0x17a0:            /* GENESYS */
 249                         /* GL880S: should be PORTS=2 */
 250                         temp |= (ehci->hcs_params & ~0xf);
 251                         ehci->hcs_params = temp;
 252                         break;
 253                 case PCI_VENDOR_ID_NVIDIA:
 254                         /* NF4: should be PCC=10 */
 255                         break;
 256                 }
 257         }
 258
 259         /* Serial Bus Release Number is at PCI 0x60 offset */
 260         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 261
 262         /* Keep this around for a while just in case some EHCI
 263          * implementation uses legacy PCI PM support.  This test
 264          * can be removed on 17 Dec 2009 if the dev_warn() hasn't
 265          * been triggered by then.
 266          */
 267         if (!device_can_wakeup(&pdev->dev)) {
 268                 u16     port_wake;
 269
 270                 pci_read_config_word(pdev, 0x62, &port_wake);
 271                 if (port_wake & 0x0001) {
 272                         dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
 273                         device_set_wakeup_capable(&pdev->dev, 1);
 274                 }
 275         }
 276
 277 #ifdef  CONFIG_USB_SUSPEND
 278         /* REVISIT: the controller works fine for wakeup iff the root hub
 279          * itself is "globally" suspended, but usbcore currently doesn't
 280          * understand such things.
 281          *
 282          * System suspend currently expects to be able to suspend the entire
 283          * device tree, device-at-a-time.  If we failed selective suspend
 284          * reports, system suspend would fail; so the root hub code must claim
 285          * success.  That's lying to usbcore, and it matters for runtime
 286          * PM scenarios with selective suspend and remote wakeup...
 287          */
 288         if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
 289                 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
 290 #endif
 291
 292         ehci_port_power(ehci, 1);
 293         retval = ehci_pci_reinit(ehci, pdev);
 294 done:
 295         return retval;
 296 }
 297
 298 /*-------------------------------------------------------------------------*/
 299
 300 #ifdef  CONFIG_PM
 301
 302 /* suspend/resume, section 4.3 */
 303
 304 /* These routines rely on the PCI bus glue
 305  * to handle powerdown and wakeup, and currently also on
 306  * transceivers that don't need any software attention to set up
 307  * the right sort of wakeup.
 308  * Also they depend on separate root hub suspend/resume.
 309  */
 310
 311 static int ehci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 312 {
 313         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 314         unsigned long           flags;
 315         int                     rc = 0;
 316
 317         if (time_before(jiffies, ehci->next_statechange))
 318                 msleep(10);
 319
 320         /* Root hub was already suspended. Disable irq emission and
 321          * mark HW unaccessible.  The PM and USB cores make sure that
 322          * the root hub is either suspended or stopped.
 323          */
 324         spin_lock_irqsave (&ehci->lock, flags);
 325         ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup);
 326         ehci_writel(ehci, 0, &ehci->regs->intr_enable);
 327         (void)ehci_readl(ehci, &ehci->regs->intr_enable);
 328
 329         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 330         spin_unlock_irqrestore (&ehci->lock, flags);
 331
 332         // could save FLADJ in case of Vaux power loss
 333         // ... we'd only use it to handle clock skew
 334
 335         return rc;
 336 }
 337
 338 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
 339 {
 340         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 341         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 342
 343         // maybe restore FLADJ
 344
 345         if (time_before(jiffies, ehci->next_statechange))
 346                 msleep(100);
 347
 348         /* Mark hardware accessible again as we are out of D3 state by now */
 349         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 350
 351         /* If CF is still set and we aren't resuming from hibernation
 352          * then we maintained PCI Vaux power.
 353          * Just undo the effect of ehci_pci_suspend().
 354          */
 355         if (ehci_readl(ehci, &ehci->regs->configured_flag) == FLAG_CF &&
 356                                 !hibernated) {
 357                 int     mask = INTR_MASK;
 358
 359                 ehci_prepare_ports_for_controller_resume(ehci);
 360                 if (!hcd->self.root_hub->do_remote_wakeup)
 361                         mask &= ~STS_PCD;
 362                 ehci_writel(ehci, mask, &ehci->regs->intr_enable);
 363                 ehci_readl(ehci, &ehci->regs->intr_enable);
 364                 return 0;
 365         }
 366
 367         usb_root_hub_lost_power(hcd->self.root_hub);
 368
 369         /* Else reset, to cope with power loss or flush-to-storage
 370          * style "resume" having let BIOS kick in during reboot.
 371          */
 372         (void) ehci_halt(ehci);
 373         (void) ehci_reset(ehci);
 374         (void) ehci_pci_reinit(ehci, pdev);
 375
 376         /* emptying the schedule aborts any urbs */
 377         spin_lock_irq(&ehci->lock);
 378         if (ehci->reclaim)
 379                 end_unlink_async(ehci);
 380         ehci_work(ehci);
 381         spin_unlock_irq(&ehci->lock);
 382
 383         ehci_writel(ehci, ehci->command, &ehci->regs->command);
 384         ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
 385         ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
 386
 387         /* here we "know" root ports should always stay powered */
 388         ehci_port_power(ehci, 1);
 389
 390         hcd->state = HC_STATE_SUSPENDED;
 391         return 0;
 392 }
 393 #endif
 394
 395 static int ehci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
 396 {
 397         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 398         int rc = 0;
 399
 400         if (!udev->parent) /* udev is root hub itself, impossible */
 401                 rc = -1;
 402         /* we only support lpm device connected to root hub yet */
 403         if (ehci->has_lpm && !udev->parent->parent) {
 404                 rc = ehci_lpm_set_da(ehci, udev->devnum, udev->portnum);
 405                 if (!rc)
 406                         rc = ehci_lpm_check(ehci, udev->portnum);
 407         }
 408         return rc;
 409 }
 410
 411 static const struct hc_driver ehci_pci_hc_driver = {
 412         .description =          hcd_name,
 413         .product_desc =         "EHCI Host Controller",
 414         .hcd_priv_size =        sizeof(struct ehci_hcd),
 415
 416         /*
 417          * generic hardware linkage
 418          */
 419         .irq =                  ehci_irq,
 420         .flags =                HCD_MEMORY | HCD_USB2,
 421
 422         /*
 423          * basic lifecycle operations
 424          */
 425         .reset =                ehci_pci_setup,
 426         .start =                ehci_run,
 427 #ifdef  CONFIG_PM
 428         .pci_suspend =          ehci_pci_suspend,
 429         .pci_resume =           ehci_pci_resume,
 430 #endif
 431         .stop =                 ehci_stop,
 432         .shutdown =             ehci_shutdown,
 433
 434         /*
 435          * managing i/o requests and associated device resources
 436          */
 437         .urb_enqueue =          ehci_urb_enqueue,
 438         .urb_dequeue =          ehci_urb_dequeue,
 439         .endpoint_disable =     ehci_endpoint_disable,
 440         .endpoint_reset =       ehci_endpoint_reset,
 441
 442         /*
 443          * scheduling support
 444          */
 445         .get_frame_number =     ehci_get_frame,
 446
 447         /*
 448          * root hub support
 449          */
 450         .hub_status_data =      ehci_hub_status_data,
 451         .hub_control =          ehci_hub_control,
 452         .bus_suspend =          ehci_bus_suspend,
 453         .bus_resume =           ehci_bus_resume,
 454         .relinquish_port =      ehci_relinquish_port,
 455         .port_handed_over =     ehci_port_handed_over,
 456
 457         /*
 458          * call back when device connected and addressed
 459          */
 460         .update_device =        ehci_update_device,
 461
 462         .clear_tt_buffer_complete       = ehci_clear_tt_buffer_complete,
 463 };
 464
 465 /*-------------------------------------------------------------------------*/
 466
 467 /* PCI driver selection metadata; PCI hotplugging uses this */
 468 static const struct pci_device_id pci_ids [] = { {
 469         /* handle any USB 2.0 EHCI controller */
 470         PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
 471         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 472         },
 473         { /* end: all zeroes */ }
 474 };
 475 MODULE_DEVICE_TABLE(pci, pci_ids);
 476
 477 /* pci driver glue; this is a "new style" PCI driver module */
 478 static struct pci_driver ehci_pci_driver = {
 479         .name =         (char *) hcd_name,
 480         .id_table =     pci_ids,
 481
 482         .probe =        usb_hcd_pci_probe,
 483         .remove =       usb_hcd_pci_remove,
 484         .shutdown =     usb_hcd_pci_shutdown,
 485
 486 #ifdef CONFIG_PM_SLEEP
 487         .driver =       {
 488                 .pm =   &usb_hcd_pci_pm_ops
 489         },
 490 #endif
 491 };