2 * EHCI HCD (Host Controller Driver) PCI Bus Glue.
4 * Copyright (c) 2000-2004 by David Brownell
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/usb.h>
25 #include <linux/usb/hcd.h>
28 #include "pci-quirks.h"
30 #define DRIVER_DESC "EHCI PCI platform driver"
32 static const char hcd_name[] = "ehci-pci";
34 /* defined here to avoid adding to pci_ids.h for single instance use */
35 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
37 /*-------------------------------------------------------------------------*/
38 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
39 static inline bool is_intel_quark_x1000(struct pci_dev *pdev)
41 return pdev->vendor == PCI_VENDOR_ID_INTEL &&
42 pdev->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC;
45 static const struct pci_device_id ci_hdrc_pci_id_table[] = {
46 { PCI_DEVICE(0x153F, 0x1004), },
47 { PCI_DEVICE(0x153F, 0x1006), },
48 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
49 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
50 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
54 static inline bool is_ci_hdrc_pci(struct pci_dev *pdev)
56 return !!pci_match_id(ci_hdrc_pci_id_table, pdev);
60 * 0x84 is the offset of in/out threshold register,
61 * and it is the same offset as the register of 'hostpc'.
63 #define intel_quark_x1000_insnreg01 hostpc
65 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
66 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
68 /* called after powerup, by probe or system-pm "wakeup" */
69 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
73 /* we expect static quirk code to handle the "extended capabilities"
74 * (currently just BIOS handoff) allowed starting with EHCI 0.96
77 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
78 retval = pci_set_mwi(pdev);
80 ehci_dbg(ehci, "MWI active\n");
82 /* Reset the threshold limit */
83 if (is_intel_quark_x1000(pdev)) {
85 * For the Intel QUARK X1000, raise the I/O threshold to the
86 * maximum usable value in order to improve performance.
88 ehci_writel(ehci, INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD,
89 ehci->regs->intel_quark_x1000_insnreg01);
95 /* called during probe() after chip reset completes */
96 static int ehci_pci_setup(struct usb_hcd *hcd)
98 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
99 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
103 ehci->caps = hcd->regs;
106 * ehci_init() causes memory for DMA transfers to be
107 * allocated. Thus, any vendor-specific workarounds based on
108 * limiting the type of memory used for DMA transfers must
109 * happen before ehci_setup() is called.
111 * Most other workarounds can be done either before or after
112 * init and reset; they are located here too.
114 switch (pdev->vendor) {
115 case PCI_VENDOR_ID_TOSHIBA_2:
116 /* celleb's companion chip */
117 if (pdev->device == 0x01b5) {
118 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
119 ehci->big_endian_mmio = 1;
122 "unsupported big endian Toshiba quirk\n");
126 case PCI_VENDOR_ID_NVIDIA:
127 /* NVidia reports that certain chips don't handle
128 * QH, ITD, or SITD addresses above 2GB. (But TD,
129 * data buffer, and periodic schedule are normal.)
131 switch (pdev->device) {
132 case 0x003c: /* MCP04 */
133 case 0x005b: /* CK804 */
134 case 0x00d8: /* CK8 */
135 case 0x00e8: /* CK8S */
136 if (pci_set_consistent_dma_mask(pdev,
137 DMA_BIT_MASK(31)) < 0)
138 ehci_warn(ehci, "can't enable NVidia "
139 "workaround for >2GB RAM\n");
142 /* Some NForce2 chips have problems with selective suspend;
143 * fixed in newer silicon.
146 if (pdev->revision < 0xa4)
147 ehci->no_selective_suspend = 1;
151 case PCI_VENDOR_ID_INTEL:
152 if (pdev->device == PCI_DEVICE_ID_INTEL_CE4100_USB)
155 case PCI_VENDOR_ID_TDI:
156 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI)
159 case PCI_VENDOR_ID_AMD:
161 if (usb_amd_find_chipset_info())
162 ehci->amd_pll_fix = 1;
163 /* AMD8111 EHCI doesn't work, according to AMD errata */
164 if (pdev->device == 0x7463) {
165 ehci_info(ehci, "ignoring AMD8111 (errata)\n");
171 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
172 * read/write memory space which does not belong to it when
173 * there is NULL pointer with T-bit set to 1 in the frame list
174 * table. To avoid the issue, the frame list link pointer
175 * should always contain a valid pointer to a inactive qh.
177 if (pdev->device == 0x7808) {
178 ehci->use_dummy_qh = 1;
179 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
182 case PCI_VENDOR_ID_VIA:
183 if (pdev->device == 0x3104 && (pdev->revision & 0xf0) == 0x60) {
186 /* The VT6212 defaults to a 1 usec EHCI sleep time which
187 * hogs the PCI bus *badly*. Setting bit 5 of 0x4B makes
188 * that sleep time use the conventional 10 usec.
190 pci_read_config_byte(pdev, 0x4b, &tmp);
193 pci_write_config_byte(pdev, 0x4b, tmp | 0x20);
196 case PCI_VENDOR_ID_ATI:
198 if (usb_amd_find_chipset_info())
199 ehci->amd_pll_fix = 1;
202 * EHCI controller on AMD SB700/SB800/Hudson-2/3 platforms may
203 * read/write memory space which does not belong to it when
204 * there is NULL pointer with T-bit set to 1 in the frame list
205 * table. To avoid the issue, the frame list link pointer
206 * should always contain a valid pointer to a inactive qh.
208 if (pdev->device == 0x4396) {
209 ehci->use_dummy_qh = 1;
210 ehci_info(ehci, "applying AMD SB700/SB800/Hudson-2/3 EHCI dummy qh workaround\n");
212 /* SB600 and old version of SB700 have a bug in EHCI controller,
213 * which causes usb devices lose response in some cases.
215 if ((pdev->device == 0x4386 || pdev->device == 0x4396) &&
216 usb_amd_hang_symptom_quirk()) {
218 ehci_info(ehci, "applying AMD SB600/SB700 USB freeze workaround\n");
219 pci_read_config_byte(pdev, 0x53, &tmp);
220 pci_write_config_byte(pdev, 0x53, tmp | (1<<3));
223 case PCI_VENDOR_ID_NETMOS:
224 /* MosChip frame-index-register bug */
225 ehci_info(ehci, "applying MosChip frame-index workaround\n");
226 ehci->frame_index_bug = 1;
230 /* optional debug port, normally in the first BAR */
231 temp = pci_find_capability(pdev, PCI_CAP_ID_DBG);
233 pci_read_config_dword(pdev, temp, &temp);
235 if (((temp >> 13) & 7) == 1) {
236 u32 hcs_params = ehci_readl(ehci,
237 &ehci->caps->hcs_params);
240 ehci->debug = hcd->regs + temp;
241 temp = ehci_readl(ehci, &ehci->debug->control);
242 ehci_info(ehci, "debug port %d%s\n",
243 HCS_DEBUG_PORT(hcs_params),
244 (temp & DBGP_ENABLED) ? " IN USE" : "");
245 if (!(temp & DBGP_ENABLED))
250 retval = ehci_setup(hcd);
254 /* These workarounds need to be applied after ehci_setup() */
255 switch (pdev->vendor) {
256 case PCI_VENDOR_ID_NEC:
257 ehci->need_io_watchdog = 0;
259 case PCI_VENDOR_ID_INTEL:
260 ehci->need_io_watchdog = 0;
262 case PCI_VENDOR_ID_NVIDIA:
263 switch (pdev->device) {
264 /* MCP89 chips on the MacBookAir3,1 give EPROTO when
265 * fetching device descriptors unless LPM is disabled.
266 * There are also intermittent problems enumerating
267 * devices with PPCD enabled.
270 ehci_info(ehci, "disable ppcd for nvidia mcp89\n");
272 ehci->command &= ~CMD_PPCEE;
278 /* at least the Genesys GL880S needs fixup here */
279 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
281 if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
282 ehci_dbg(ehci, "bogus port configuration: "
283 "cc=%d x pcc=%d < ports=%d\n",
284 HCS_N_CC(ehci->hcs_params),
285 HCS_N_PCC(ehci->hcs_params),
286 HCS_N_PORTS(ehci->hcs_params));
288 switch (pdev->vendor) {
289 case 0x17a0: /* GENESYS */
290 /* GL880S: should be PORTS=2 */
291 temp |= (ehci->hcs_params & ~0xf);
292 ehci->hcs_params = temp;
294 case PCI_VENDOR_ID_NVIDIA:
295 /* NF4: should be PCC=10 */
300 /* Serial Bus Release Number is at PCI 0x60 offset */
301 if (pdev->vendor == PCI_VENDOR_ID_STMICRO
302 && pdev->device == PCI_DEVICE_ID_STMICRO_USB_HOST)
303 ; /* ConneXT has no sbrn register */
305 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
307 /* Keep this around for a while just in case some EHCI
308 * implementation uses legacy PCI PM support. This test
309 * can be removed on 17 Dec 2009 if the dev_warn() hasn't
310 * been triggered by then.
312 if (!device_can_wakeup(&pdev->dev)) {
315 pci_read_config_word(pdev, 0x62, &port_wake);
316 if (port_wake & 0x0001) {
317 dev_warn(&pdev->dev, "Enabling legacy PCI PM\n");
318 device_set_wakeup_capable(&pdev->dev, 1);
323 if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
324 ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
327 retval = ehci_pci_reinit(ehci, pdev);
332 /*-------------------------------------------------------------------------*/
336 /* suspend/resume, section 4.3 */
338 /* These routines rely on the PCI bus glue
339 * to handle powerdown and wakeup, and currently also on
340 * transceivers that don't need any software attention to set up
341 * the right sort of wakeup.
342 * Also they depend on separate root hub suspend/resume.
345 static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
347 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
348 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
350 if (ehci_resume(hcd, hibernated) != 0)
351 (void) ehci_pci_reinit(ehci, pdev);
357 #define ehci_suspend NULL
358 #define ehci_pci_resume NULL
359 #endif /* CONFIG_PM */
361 static struct hc_driver __read_mostly ehci_pci_hc_driver;
363 static const struct ehci_driver_overrides pci_overrides __initconst = {
364 .reset = ehci_pci_setup,
367 /*-------------------------------------------------------------------------*/
369 static int ehci_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
371 if (is_ci_hdrc_pci(pdev))
373 return usb_hcd_pci_probe(pdev, id);
376 /* PCI driver selection metadata; PCI hotplugging uses this */
377 static const struct pci_device_id pci_ids [] = { {
378 /* handle any USB 2.0 EHCI controller */
379 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
380 .driver_data = (unsigned long) &ehci_pci_hc_driver,
382 PCI_VDEVICE(STMICRO, PCI_DEVICE_ID_STMICRO_USB_HOST),
383 .driver_data = (unsigned long) &ehci_pci_hc_driver,
385 { /* end: all zeroes */ }
387 MODULE_DEVICE_TABLE(pci, pci_ids);
389 /* pci driver glue; this is a "new style" PCI driver module */
390 static struct pci_driver ehci_pci_driver = {
391 .name = (char *) hcd_name,
394 .probe = ehci_pci_probe,
395 .remove = usb_hcd_pci_remove,
396 .shutdown = usb_hcd_pci_shutdown,
400 .pm = &usb_hcd_pci_pm_ops
405 static int __init ehci_pci_init(void)
410 pr_info("%s: " DRIVER_DESC "\n", hcd_name);
412 ehci_init_driver(&ehci_pci_hc_driver, &pci_overrides);
414 /* Entries for the PCI suspend/resume callbacks are special */
415 ehci_pci_hc_driver.pci_suspend = ehci_suspend;
416 ehci_pci_hc_driver.pci_resume = ehci_pci_resume;
418 return pci_register_driver(&ehci_pci_driver);
420 module_init(ehci_pci_init);
422 static void __exit ehci_pci_cleanup(void)
424 pci_unregister_driver(&ehci_pci_driver);
426 module_exit(ehci_pci_cleanup);
428 MODULE_DESCRIPTION(DRIVER_DESC);
429 MODULE_AUTHOR("David Brownell");
430 MODULE_AUTHOR("Alan Stern");
431 MODULE_LICENSE("GPL");