2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
69 #include <linux/dma-mapping.h>
71 #include "xhci-trace.h"
75 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
78 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
81 unsigned long segment_offset;
83 if (!seg || !trb || trb < seg->trbs)
86 segment_offset = trb - seg->trbs;
87 if (segment_offset >= TRBS_PER_SEGMENT)
89 return seg->dma + (segment_offset * sizeof(*trb));
92 static bool trb_is_link(union xhci_trb *trb)
94 return TRB_TYPE_LINK_LE32(trb->link.control);
97 static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
99 return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
102 static bool last_trb_on_ring(struct xhci_ring *ring,
103 struct xhci_segment *seg, union xhci_trb *trb)
105 return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
108 static bool link_trb_toggles_cycle(union xhci_trb *trb)
110 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
113 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
114 * TRB is in a new segment. This does not skip over link TRBs, and it does not
115 * effect the ring dequeue or enqueue pointers.
117 static void next_trb(struct xhci_hcd *xhci,
118 struct xhci_ring *ring,
119 struct xhci_segment **seg,
120 union xhci_trb **trb)
122 if (trb_is_link(*trb)) {
124 *trb = ((*seg)->trbs);
131 * See Cycle bit rules. SW is the consumer for the event ring only.
132 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
134 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
138 /* event ring doesn't have link trbs, check for last trb */
139 if (ring->type == TYPE_EVENT) {
140 if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
144 if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
145 ring->cycle_state ^= 1;
146 ring->deq_seg = ring->deq_seg->next;
147 ring->dequeue = ring->deq_seg->trbs;
151 /* All other rings have link trbs */
152 if (!trb_is_link(ring->dequeue)) {
154 ring->num_trbs_free++;
156 while (trb_is_link(ring->dequeue)) {
157 ring->deq_seg = ring->deq_seg->next;
158 ring->dequeue = ring->deq_seg->trbs;
164 * See Cycle bit rules. SW is the consumer for the event ring only.
165 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
167 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
168 * chain bit is set), then set the chain bit in all the following link TRBs.
169 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
170 * have their chain bit cleared (so that each Link TRB is a separate TD).
172 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
173 * set, but other sections talk about dealing with the chain bit set. This was
174 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
175 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
177 * @more_trbs_coming: Will you enqueue more TRBs before calling
178 * prepare_transfer()?
180 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
181 bool more_trbs_coming)
184 union xhci_trb *next;
186 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
187 /* If this is not event ring, there is one less usable TRB */
188 if (!trb_is_link(ring->enqueue))
189 ring->num_trbs_free--;
190 next = ++(ring->enqueue);
193 /* Update the dequeue pointer further if that was a link TRB */
194 while (trb_is_link(next)) {
197 * If the caller doesn't plan on enqueueing more TDs before
198 * ringing the doorbell, then we don't want to give the link TRB
199 * to the hardware just yet. We'll give the link TRB back in
200 * prepare_ring() just before we enqueue the TD at the top of
203 if (!chain && !more_trbs_coming)
206 /* If we're not dealing with 0.95 hardware or isoc rings on
207 * AMD 0.96 host, carry over the chain bit of the previous TRB
208 * (which may mean the chain bit is cleared).
210 if (!(ring->type == TYPE_ISOC &&
211 (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
212 !xhci_link_trb_quirk(xhci)) {
213 next->link.control &= cpu_to_le32(~TRB_CHAIN);
214 next->link.control |= cpu_to_le32(chain);
216 /* Give this link TRB to the hardware */
218 next->link.control ^= cpu_to_le32(TRB_CYCLE);
220 /* Toggle the cycle bit after the last ring segment. */
221 if (link_trb_toggles_cycle(next))
222 ring->cycle_state ^= 1;
224 ring->enq_seg = ring->enq_seg->next;
225 ring->enqueue = ring->enq_seg->trbs;
226 next = ring->enqueue;
231 * Check to see if there's room to enqueue num_trbs on the ring and make sure
232 * enqueue pointer will not advance into dequeue segment. See rules above.
234 static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
235 unsigned int num_trbs)
237 int num_trbs_in_deq_seg;
239 if (ring->num_trbs_free < num_trbs)
242 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
243 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
244 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
251 /* Ring the host controller doorbell after placing a command on the ring */
252 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
254 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
257 xhci_dbg(xhci, "// Ding dong!\n");
258 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
259 /* Flush PCI posted writes */
260 readl(&xhci->dba->doorbell[0]);
263 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
268 xhci_dbg(xhci, "Abort command ring\n");
270 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
271 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
274 * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
275 * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
276 * but the completion event in never sent. Use the cmd timeout timer to
277 * handle those cases. Use twice the time to cover the bit polling retry
279 mod_timer(&xhci->cmd_timer, jiffies + (2 * XHCI_CMD_DEFAULT_TIMEOUT));
280 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
281 &xhci->op_regs->cmd_ring);
283 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
284 * time the completion od all xHCI commands, including
285 * the Command Abort operation. If software doesn't see
286 * CRR negated in a timely manner (e.g. longer than 5
287 * seconds), then it should assume that the there are
288 * larger problems with the xHC and assert HCRST.
290 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
291 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
293 /* we are about to kill xhci, give it one more chance */
294 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
295 &xhci->op_regs->cmd_ring);
297 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
298 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
302 xhci_err(xhci, "Stopped the command ring failed, "
303 "maybe the host is dead\n");
304 del_timer(&xhci->cmd_timer);
305 xhci->xhc_state |= XHCI_STATE_DYING;
314 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
315 unsigned int slot_id,
316 unsigned int ep_index,
317 unsigned int stream_id)
319 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
320 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
321 unsigned int ep_state = ep->ep_state;
323 /* Don't ring the doorbell for this endpoint if there are pending
324 * cancellations because we don't want to interrupt processing.
325 * We don't want to restart any stream rings if there's a set dequeue
326 * pointer command pending because the device can choose to start any
327 * stream once the endpoint is on the HW schedule.
329 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
330 (ep_state & EP_HALTED))
332 writel(DB_VALUE(ep_index, stream_id), db_addr);
333 /* The CPU has better things to do at this point than wait for a
334 * write-posting flush. It'll get there soon enough.
338 /* Ring the doorbell for any rings with pending URBs */
339 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
340 unsigned int slot_id,
341 unsigned int ep_index)
343 unsigned int stream_id;
344 struct xhci_virt_ep *ep;
346 ep = &xhci->devs[slot_id]->eps[ep_index];
348 /* A ring has pending URBs if its TD list is not empty */
349 if (!(ep->ep_state & EP_HAS_STREAMS)) {
350 if (ep->ring && !(list_empty(&ep->ring->td_list)))
351 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
355 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
357 struct xhci_stream_info *stream_info = ep->stream_info;
358 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
359 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
364 /* Get the right ring for the given slot_id, ep_index and stream_id.
365 * If the endpoint supports streams, boundary check the URB's stream ID.
366 * If the endpoint doesn't support streams, return the singular endpoint ring.
368 struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
369 unsigned int slot_id, unsigned int ep_index,
370 unsigned int stream_id)
372 struct xhci_virt_ep *ep;
374 ep = &xhci->devs[slot_id]->eps[ep_index];
375 /* Common case: no streams */
376 if (!(ep->ep_state & EP_HAS_STREAMS))
379 if (stream_id == 0) {
381 "WARN: Slot ID %u, ep index %u has streams, "
382 "but URB has no stream ID.\n",
387 if (stream_id < ep->stream_info->num_streams)
388 return ep->stream_info->stream_rings[stream_id];
391 "WARN: Slot ID %u, ep index %u has "
392 "stream IDs 1 to %u allocated, "
393 "but stream ID %u is requested.\n",
395 ep->stream_info->num_streams - 1,
401 * Move the xHC's endpoint ring dequeue pointer past cur_td.
402 * Record the new state of the xHC's endpoint ring dequeue segment,
403 * dequeue pointer, and new consumer cycle state in state.
404 * Update our internal representation of the ring's dequeue pointer.
406 * We do this in three jumps:
407 * - First we update our new ring state to be the same as when the xHC stopped.
408 * - Then we traverse the ring to find the segment that contains
409 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
410 * any link TRBs with the toggle cycle bit set.
411 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
412 * if we've moved it past a link TRB with the toggle cycle bit set.
414 * Some of the uses of xhci_generic_trb are grotty, but if they're done
415 * with correct __le32 accesses they should work fine. Only users of this are
418 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
419 unsigned int slot_id, unsigned int ep_index,
420 unsigned int stream_id, struct xhci_td *cur_td,
421 struct xhci_dequeue_state *state)
423 struct xhci_virt_device *dev = xhci->devs[slot_id];
424 struct xhci_virt_ep *ep = &dev->eps[ep_index];
425 struct xhci_ring *ep_ring;
426 struct xhci_segment *new_seg;
427 union xhci_trb *new_deq;
430 bool cycle_found = false;
431 bool td_last_trb_found = false;
433 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
434 ep_index, stream_id);
436 xhci_warn(xhci, "WARN can't find new dequeue state "
437 "for invalid stream ID %u.\n",
442 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
443 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
444 "Finding endpoint context");
445 /* 4.6.9 the css flag is written to the stream context for streams */
446 if (ep->ep_state & EP_HAS_STREAMS) {
447 struct xhci_stream_ctx *ctx =
448 &ep->stream_info->stream_ctx_array[stream_id];
449 hw_dequeue = le64_to_cpu(ctx->stream_ring);
451 struct xhci_ep_ctx *ep_ctx
452 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
453 hw_dequeue = le64_to_cpu(ep_ctx->deq);
456 new_seg = ep_ring->deq_seg;
457 new_deq = ep_ring->dequeue;
458 state->new_cycle_state = hw_dequeue & 0x1;
461 * We want to find the pointer, segment and cycle state of the new trb
462 * (the one after current TD's last_trb). We know the cycle state at
463 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
467 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
468 == (dma_addr_t)(hw_dequeue & ~0xf)) {
470 if (td_last_trb_found)
473 if (new_deq == cur_td->last_trb)
474 td_last_trb_found = true;
477 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
478 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
479 state->new_cycle_state ^= 0x1;
481 next_trb(xhci, ep_ring, &new_seg, &new_deq);
483 /* Search wrapped around, bail out */
484 if (new_deq == ep->ring->dequeue) {
485 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
486 state->new_deq_seg = NULL;
487 state->new_deq_ptr = NULL;
491 } while (!cycle_found || !td_last_trb_found);
493 state->new_deq_seg = new_seg;
494 state->new_deq_ptr = new_deq;
496 /* Don't update the ring cycle state for the producer (us). */
497 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
498 "Cycle state = 0x%x", state->new_cycle_state);
500 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
501 "New dequeue segment = %p (virtual)",
503 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
504 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
505 "New dequeue pointer = 0x%llx (DMA)",
506 (unsigned long long) addr);
509 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
510 * (The last TRB actually points to the ring enqueue pointer, which is not part
511 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
513 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
514 struct xhci_td *cur_td, bool flip_cycle)
516 struct xhci_segment *cur_seg;
517 union xhci_trb *cur_trb;
519 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
521 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
522 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
523 /* Unchain any chained Link TRBs, but
524 * leave the pointers intact.
526 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
527 /* Flip the cycle bit (link TRBs can't be the first
531 cur_trb->generic.field[3] ^=
532 cpu_to_le32(TRB_CYCLE);
533 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
534 "Cancel (unchain) link TRB");
535 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
536 "Address = %p (0x%llx dma); "
537 "in seg %p (0x%llx dma)",
539 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
541 (unsigned long long)cur_seg->dma);
543 cur_trb->generic.field[0] = 0;
544 cur_trb->generic.field[1] = 0;
545 cur_trb->generic.field[2] = 0;
546 /* Preserve only the cycle bit of this TRB */
547 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
548 /* Flip the cycle bit except on the first or last TRB */
549 if (flip_cycle && cur_trb != cur_td->first_trb &&
550 cur_trb != cur_td->last_trb)
551 cur_trb->generic.field[3] ^=
552 cpu_to_le32(TRB_CYCLE);
553 cur_trb->generic.field[3] |= cpu_to_le32(
554 TRB_TYPE(TRB_TR_NOOP));
555 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
556 "TRB to noop at offset 0x%llx",
558 xhci_trb_virt_to_dma(cur_seg, cur_trb));
560 if (cur_trb == cur_td->last_trb)
565 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
566 struct xhci_virt_ep *ep)
568 ep->ep_state &= ~EP_HALT_PENDING;
569 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
570 * timer is running on another CPU, we don't decrement stop_cmds_pending
571 * (since we didn't successfully stop the watchdog timer).
573 if (del_timer(&ep->stop_cmd_timer))
574 ep->stop_cmds_pending--;
577 /* Must be called with xhci->lock held in interrupt context */
578 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
579 struct xhci_td *cur_td, int status)
583 struct urb_priv *urb_priv;
586 urb_priv = urb->hcpriv;
588 hcd = bus_to_hcd(urb->dev->bus);
590 /* Only giveback urb when this is the last td in urb */
591 if (urb_priv->td_cnt == urb_priv->length) {
592 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
593 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
594 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
595 if (xhci->quirks & XHCI_AMD_PLL_FIX)
596 usb_amd_quirk_pll_enable();
599 usb_hcd_unlink_urb_from_ep(hcd, urb);
601 spin_unlock(&xhci->lock);
602 usb_hcd_giveback_urb(hcd, urb, status);
603 xhci_urb_free_priv(urb_priv);
604 spin_lock(&xhci->lock);
608 void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring,
611 struct device *dev = xhci_to_hcd(xhci)->self.controller;
612 struct xhci_segment *seg = td->bounce_seg;
613 struct urb *urb = td->urb;
618 if (usb_urb_dir_out(urb)) {
619 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
624 /* for in tranfers we need to copy the data from bounce to sg */
625 sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf,
626 seg->bounce_len, seg->bounce_offs);
627 dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
630 seg->bounce_offs = 0;
634 * When we get a command completion for a Stop Endpoint Command, we need to
635 * unlink any cancelled TDs from the ring. There are two ways to do that:
637 * 1. If the HW was in the middle of processing the TD that needs to be
638 * cancelled, then we must move the ring's dequeue pointer past the last TRB
639 * in the TD with a Set Dequeue Pointer Command.
640 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
641 * bit cleared) so that the HW will skip over them.
643 static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
644 union xhci_trb *trb, struct xhci_event_cmd *event)
646 unsigned int ep_index;
647 struct xhci_ring *ep_ring;
648 struct xhci_virt_ep *ep;
649 struct list_head *entry;
650 struct xhci_td *cur_td = NULL;
651 struct xhci_td *last_unlinked_td;
653 struct xhci_dequeue_state deq_state;
655 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
656 if (!xhci->devs[slot_id])
657 xhci_warn(xhci, "Stop endpoint command "
658 "completion for disabled slot %u\n",
663 memset(&deq_state, 0, sizeof(deq_state));
664 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
665 ep = &xhci->devs[slot_id]->eps[ep_index];
667 if (list_empty(&ep->cancelled_td_list)) {
668 xhci_stop_watchdog_timer_in_irq(xhci, ep);
669 ep->stopped_td = NULL;
670 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
674 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
675 * We have the xHCI lock, so nothing can modify this list until we drop
676 * it. We're also in the event handler, so we can't get re-interrupted
677 * if another Stop Endpoint command completes
679 list_for_each(entry, &ep->cancelled_td_list) {
680 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
681 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
682 "Removing canceled TD starting at 0x%llx (dma).",
683 (unsigned long long)xhci_trb_virt_to_dma(
684 cur_td->start_seg, cur_td->first_trb));
685 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
687 /* This shouldn't happen unless a driver is mucking
688 * with the stream ID after submission. This will
689 * leave the TD on the hardware ring, and the hardware
690 * will try to execute it, and may access a buffer
691 * that has already been freed. In the best case, the
692 * hardware will execute it, and the event handler will
693 * ignore the completion event for that TD, since it was
694 * removed from the td_list for that endpoint. In
695 * short, don't muck with the stream ID after
698 xhci_warn(xhci, "WARN Cancelled URB %p "
699 "has invalid stream ID %u.\n",
701 cur_td->urb->stream_id);
702 goto remove_finished_td;
705 * If we stopped on the TD we need to cancel, then we have to
706 * move the xHC endpoint ring dequeue pointer past this TD.
708 if (cur_td == ep->stopped_td)
709 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
710 cur_td->urb->stream_id,
713 td_to_noop(xhci, ep_ring, cur_td, false);
716 * The event handler won't see a completion for this TD anymore,
717 * so remove it from the endpoint ring's TD list. Keep it in
718 * the cancelled TD list for URB completion later.
720 list_del_init(&cur_td->td_list);
722 last_unlinked_td = cur_td;
723 xhci_stop_watchdog_timer_in_irq(xhci, ep);
725 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
726 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
727 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
728 ep->stopped_td->urb->stream_id, &deq_state);
729 xhci_ring_cmd_db(xhci);
731 /* Otherwise ring the doorbell(s) to restart queued transfers */
732 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
735 ep->stopped_td = NULL;
738 * Drop the lock and complete the URBs in the cancelled TD list.
739 * New TDs to be cancelled might be added to the end of the list before
740 * we can complete all the URBs for the TDs we already unlinked.
741 * So stop when we've completed the URB for the last TD we unlinked.
744 cur_td = list_entry(ep->cancelled_td_list.next,
745 struct xhci_td, cancelled_td_list);
746 list_del_init(&cur_td->cancelled_td_list);
748 /* Clean up the cancelled URB */
749 /* Doesn't matter what we pass for status, since the core will
750 * just overwrite it (because the URB has been unlinked).
752 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
753 if (ep_ring && cur_td->bounce_seg)
754 xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
755 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
757 /* Stop processing the cancelled list if the watchdog timer is
760 if (xhci->xhc_state & XHCI_STATE_DYING)
762 } while (cur_td != last_unlinked_td);
764 /* Return to the event handler with xhci->lock re-acquired */
767 static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
769 struct xhci_td *cur_td;
771 while (!list_empty(&ring->td_list)) {
772 cur_td = list_first_entry(&ring->td_list,
773 struct xhci_td, td_list);
774 list_del_init(&cur_td->td_list);
775 if (!list_empty(&cur_td->cancelled_td_list))
776 list_del_init(&cur_td->cancelled_td_list);
778 if (cur_td->bounce_seg)
779 xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
780 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
784 static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
785 int slot_id, int ep_index)
787 struct xhci_td *cur_td;
788 struct xhci_virt_ep *ep;
789 struct xhci_ring *ring;
791 ep = &xhci->devs[slot_id]->eps[ep_index];
792 if ((ep->ep_state & EP_HAS_STREAMS) ||
793 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
796 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
798 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
799 "Killing URBs for slot ID %u, ep index %u, stream %u",
800 slot_id, ep_index, stream_id + 1);
801 xhci_kill_ring_urbs(xhci,
802 ep->stream_info->stream_rings[stream_id]);
808 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
809 "Killing URBs for slot ID %u, ep index %u",
811 xhci_kill_ring_urbs(xhci, ring);
813 while (!list_empty(&ep->cancelled_td_list)) {
814 cur_td = list_first_entry(&ep->cancelled_td_list,
815 struct xhci_td, cancelled_td_list);
816 list_del_init(&cur_td->cancelled_td_list);
817 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
821 /* Watchdog timer function for when a stop endpoint command fails to complete.
822 * In this case, we assume the host controller is broken or dying or dead. The
823 * host may still be completing some other events, so we have to be careful to
824 * let the event ring handler and the URB dequeueing/enqueueing functions know
825 * through xhci->state.
827 * The timer may also fire if the host takes a very long time to respond to the
828 * command, and the stop endpoint command completion handler cannot delete the
829 * timer before the timer function is called. Another endpoint cancellation may
830 * sneak in before the timer function can grab the lock, and that may queue
831 * another stop endpoint command and add the timer back. So we cannot use a
832 * simple flag to say whether there is a pending stop endpoint command for a
833 * particular endpoint.
835 * Instead we use a combination of that flag and a counter for the number of
836 * pending stop endpoint commands. If the timer is the tail end of the last
837 * stop endpoint command, and the endpoint's command is still pending, we assume
840 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
842 struct xhci_hcd *xhci;
843 struct xhci_virt_ep *ep;
847 ep = (struct xhci_virt_ep *) arg;
850 spin_lock_irqsave(&xhci->lock, flags);
852 ep->stop_cmds_pending--;
853 if (xhci->xhc_state & XHCI_STATE_DYING) {
854 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
855 "Stop EP timer ran, but another timer marked "
856 "xHCI as DYING, exiting.");
857 spin_unlock_irqrestore(&xhci->lock, flags);
860 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
861 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
862 "Stop EP timer ran, but no command pending, "
864 spin_unlock_irqrestore(&xhci->lock, flags);
868 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
869 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
870 /* Oops, HC is dead or dying or at least not responding to the stop
873 xhci->xhc_state |= XHCI_STATE_DYING;
874 /* Disable interrupts from the host controller and start halting it */
876 spin_unlock_irqrestore(&xhci->lock, flags);
878 ret = xhci_halt(xhci);
880 spin_lock_irqsave(&xhci->lock, flags);
882 /* This is bad; the host is not responding to commands and it's
883 * not allowing itself to be halted. At least interrupts are
884 * disabled. If we call usb_hc_died(), it will attempt to
885 * disconnect all device drivers under this host. Those
886 * disconnect() methods will wait for all URBs to be unlinked,
887 * so we must complete them.
889 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
890 xhci_warn(xhci, "Completing active URBs anyway.\n");
891 /* We could turn all TDs on the rings to no-ops. This won't
892 * help if the host has cached part of the ring, and is slow if
893 * we want to preserve the cycle bit. Skip it and hope the host
894 * doesn't touch the memory.
897 for (i = 0; i < MAX_HC_SLOTS; i++) {
900 for (j = 0; j < 31; j++)
901 xhci_kill_endpoint_urbs(xhci, i, j);
903 spin_unlock_irqrestore(&xhci->lock, flags);
904 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
905 "Calling usb_hc_died()");
906 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
907 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
908 "xHCI host controller is dead.");
912 static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
913 struct xhci_virt_device *dev,
914 struct xhci_ring *ep_ring,
915 unsigned int ep_index)
917 union xhci_trb *dequeue_temp;
918 int num_trbs_free_temp;
921 num_trbs_free_temp = ep_ring->num_trbs_free;
922 dequeue_temp = ep_ring->dequeue;
924 /* If we get two back-to-back stalls, and the first stalled transfer
925 * ends just before a link TRB, the dequeue pointer will be left on
926 * the link TRB by the code in the while loop. So we have to update
927 * the dequeue pointer one segment further, or we'll jump off
928 * the segment into la-la-land.
930 if (trb_is_link(ep_ring->dequeue)) {
931 ep_ring->deq_seg = ep_ring->deq_seg->next;
932 ep_ring->dequeue = ep_ring->deq_seg->trbs;
935 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
936 /* We have more usable TRBs */
937 ep_ring->num_trbs_free++;
939 if (trb_is_link(ep_ring->dequeue)) {
940 if (ep_ring->dequeue ==
941 dev->eps[ep_index].queued_deq_ptr)
943 ep_ring->deq_seg = ep_ring->deq_seg->next;
944 ep_ring->dequeue = ep_ring->deq_seg->trbs;
946 if (ep_ring->dequeue == dequeue_temp) {
953 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
954 ep_ring->num_trbs_free = num_trbs_free_temp;
959 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
960 * we need to clear the set deq pending flag in the endpoint ring state, so that
961 * the TD queueing code can ring the doorbell again. We also need to ring the
962 * endpoint doorbell to restart the ring, but only if there aren't more
963 * cancellations pending.
965 static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
966 union xhci_trb *trb, u32 cmd_comp_code)
968 unsigned int ep_index;
969 unsigned int stream_id;
970 struct xhci_ring *ep_ring;
971 struct xhci_virt_device *dev;
972 struct xhci_virt_ep *ep;
973 struct xhci_ep_ctx *ep_ctx;
974 struct xhci_slot_ctx *slot_ctx;
976 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
977 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
978 dev = xhci->devs[slot_id];
979 ep = &dev->eps[ep_index];
981 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
983 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
985 /* XXX: Harmless??? */
989 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
990 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
992 if (cmd_comp_code != COMP_SUCCESS) {
993 unsigned int ep_state;
994 unsigned int slot_state;
996 switch (cmd_comp_code) {
998 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1000 case COMP_CTX_STATE:
1001 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1002 ep_state = le32_to_cpu(ep_ctx->ep_info);
1003 ep_state &= EP_STATE_MASK;
1004 slot_state = le32_to_cpu(slot_ctx->dev_state);
1005 slot_state = GET_SLOT_STATE(slot_state);
1006 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1007 "Slot state = %u, EP state = %u",
1008 slot_state, ep_state);
1011 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1015 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1019 /* OK what do we do now? The endpoint state is hosed, and we
1020 * should never get to this point if the synchronization between
1021 * queueing, and endpoint state are correct. This might happen
1022 * if the device gets disconnected after we've finished
1023 * cancelling URBs, which might not be an error...
1027 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1028 if (ep->ep_state & EP_HAS_STREAMS) {
1029 struct xhci_stream_ctx *ctx =
1030 &ep->stream_info->stream_ctx_array[stream_id];
1031 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1033 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1035 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1036 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1037 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1038 ep->queued_deq_ptr) == deq) {
1039 /* Update the ring's dequeue segment and dequeue pointer
1040 * to reflect the new position.
1042 update_ring_for_set_deq_completion(xhci, dev,
1045 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1046 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1047 ep->queued_deq_seg, ep->queued_deq_ptr);
1052 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1053 dev->eps[ep_index].queued_deq_seg = NULL;
1054 dev->eps[ep_index].queued_deq_ptr = NULL;
1055 /* Restart any rings with pending URBs */
1056 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1059 static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1060 union xhci_trb *trb, u32 cmd_comp_code)
1062 unsigned int ep_index;
1064 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1065 /* This command will only fail if the endpoint wasn't halted,
1066 * but we don't care.
1068 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1069 "Ignoring reset ep completion code of %u", cmd_comp_code);
1071 /* HW with the reset endpoint quirk needs to have a configure endpoint
1072 * command complete before the endpoint can be used. Queue that here
1073 * because the HW can't handle two commands being queued in a row.
1075 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1076 struct xhci_command *command;
1077 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1079 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1082 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1083 "Queueing configure endpoint command");
1084 xhci_queue_configure_endpoint(xhci, command,
1085 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1087 xhci_ring_cmd_db(xhci);
1089 /* Clear our internal halted state */
1090 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1094 static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1097 if (cmd_comp_code == COMP_SUCCESS)
1098 xhci->slot_id = slot_id;
1103 static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1105 struct xhci_virt_device *virt_dev;
1107 virt_dev = xhci->devs[slot_id];
1110 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1111 /* Delete default control endpoint resources */
1112 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1113 xhci_free_virt_device(xhci, slot_id);
1116 static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1117 struct xhci_event_cmd *event, u32 cmd_comp_code)
1119 struct xhci_virt_device *virt_dev;
1120 struct xhci_input_control_ctx *ctrl_ctx;
1121 unsigned int ep_index;
1122 unsigned int ep_state;
1123 u32 add_flags, drop_flags;
1126 * Configure endpoint commands can come from the USB core
1127 * configuration or alt setting changes, or because the HW
1128 * needed an extra configure endpoint command after a reset
1129 * endpoint command or streams were being configured.
1130 * If the command was for a halted endpoint, the xHCI driver
1131 * is not waiting on the configure endpoint command.
1133 virt_dev = xhci->devs[slot_id];
1134 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1136 xhci_warn(xhci, "Could not get input context, bad type.\n");
1140 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1141 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1142 /* Input ctx add_flags are the endpoint index plus one */
1143 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1145 /* A usb_set_interface() call directly after clearing a halted
1146 * condition may race on this quirky hardware. Not worth
1147 * worrying about, since this is prototype hardware. Not sure
1148 * if this will work for streams, but streams support was
1149 * untested on this prototype.
1151 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1152 ep_index != (unsigned int) -1 &&
1153 add_flags - SLOT_FLAG == drop_flags) {
1154 ep_state = virt_dev->eps[ep_index].ep_state;
1155 if (!(ep_state & EP_HALTED))
1157 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1158 "Completed config ep cmd - "
1159 "last ep index = %d, state = %d",
1160 ep_index, ep_state);
1161 /* Clear internal halted state and restart ring(s) */
1162 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1163 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1169 static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1170 struct xhci_event_cmd *event)
1172 xhci_dbg(xhci, "Completed reset device command.\n");
1173 if (!xhci->devs[slot_id])
1174 xhci_warn(xhci, "Reset device command completion "
1175 "for disabled slot %u\n", slot_id);
1178 static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1179 struct xhci_event_cmd *event)
1181 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1182 xhci->error_bitmask |= 1 << 6;
1185 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1186 "NEC firmware version %2x.%02x",
1187 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1188 NEC_FW_MINOR(le32_to_cpu(event->status)));
1191 static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1193 list_del(&cmd->cmd_list);
1195 if (cmd->completion) {
1196 cmd->status = status;
1197 complete(cmd->completion);
1203 void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1205 struct xhci_command *cur_cmd, *tmp_cmd;
1206 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1207 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
1211 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1212 * If there are other commands waiting then restart the ring and kick the timer.
1213 * This must be called with command ring stopped and xhci->lock held.
1215 static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1216 struct xhci_command *cur_cmd)
1218 struct xhci_command *i_cmd, *tmp_cmd;
1221 /* Turn all aborted commands in list to no-ops, then restart */
1222 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1225 if (i_cmd->status != COMP_CMD_ABORT)
1228 i_cmd->status = COMP_CMD_STOP;
1230 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1231 i_cmd->command_trb);
1232 /* get cycle state from the original cmd trb */
1233 cycle_state = le32_to_cpu(
1234 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1235 /* modify the command trb to no-op command */
1236 i_cmd->command_trb->generic.field[0] = 0;
1237 i_cmd->command_trb->generic.field[1] = 0;
1238 i_cmd->command_trb->generic.field[2] = 0;
1239 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1240 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1243 * caller waiting for completion is called when command
1244 * completion event is received for these no-op commands
1248 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1250 /* ring command ring doorbell to restart the command ring */
1251 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1252 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1253 xhci->current_cmd = cur_cmd;
1254 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1255 xhci_ring_cmd_db(xhci);
1261 void xhci_handle_command_timeout(unsigned long data)
1263 struct xhci_hcd *xhci;
1265 unsigned long flags;
1267 bool second_timeout = false;
1268 xhci = (struct xhci_hcd *) data;
1270 /* mark this command to be cancelled */
1271 spin_lock_irqsave(&xhci->lock, flags);
1272 if (xhci->current_cmd) {
1273 if (xhci->current_cmd->status == COMP_CMD_ABORT)
1274 second_timeout = true;
1275 xhci->current_cmd->status = COMP_CMD_ABORT;
1278 /* Make sure command ring is running before aborting it */
1279 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1280 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1281 (hw_ring_state & CMD_RING_RUNNING)) {
1282 spin_unlock_irqrestore(&xhci->lock, flags);
1283 xhci_dbg(xhci, "Command timeout\n");
1284 ret = xhci_abort_cmd_ring(xhci);
1285 if (unlikely(ret == -ESHUTDOWN)) {
1286 xhci_err(xhci, "Abort command ring failed\n");
1287 xhci_cleanup_command_queue(xhci);
1288 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1289 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1294 /* command ring failed to restart, or host removed. Bail out */
1295 if (second_timeout || xhci->xhc_state & XHCI_STATE_REMOVING) {
1296 spin_unlock_irqrestore(&xhci->lock, flags);
1297 xhci_dbg(xhci, "command timed out twice, ring start fail?\n");
1298 xhci_cleanup_command_queue(xhci);
1302 /* command timeout on stopped ring, ring can't be aborted */
1303 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1304 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1305 spin_unlock_irqrestore(&xhci->lock, flags);
1309 static void handle_cmd_completion(struct xhci_hcd *xhci,
1310 struct xhci_event_cmd *event)
1312 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1314 dma_addr_t cmd_dequeue_dma;
1316 union xhci_trb *cmd_trb;
1317 struct xhci_command *cmd;
1320 cmd_dma = le64_to_cpu(event->cmd_trb);
1321 cmd_trb = xhci->cmd_ring->dequeue;
1322 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1324 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1325 if (cmd_dequeue_dma == 0) {
1326 xhci->error_bitmask |= 1 << 4;
1329 /* Does the DMA address match our internal dequeue pointer address? */
1330 if (cmd_dma != (u64) cmd_dequeue_dma) {
1331 xhci->error_bitmask |= 1 << 5;
1335 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1337 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1339 "Command completion event does not match command\n");
1343 del_timer(&xhci->cmd_timer);
1345 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
1347 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1349 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1350 if (cmd_comp_code == COMP_CMD_STOP) {
1351 xhci_handle_stopped_cmd_ring(xhci, cmd);
1355 * Host aborted the command ring, check if the current command was
1356 * supposed to be aborted, otherwise continue normally.
1357 * The command ring is stopped now, but the xHC will issue a Command
1358 * Ring Stopped event which will cause us to restart it.
1360 if (cmd_comp_code == COMP_CMD_ABORT) {
1361 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1362 if (cmd->status == COMP_CMD_ABORT)
1366 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1368 case TRB_ENABLE_SLOT:
1369 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
1371 case TRB_DISABLE_SLOT:
1372 xhci_handle_cmd_disable_slot(xhci, slot_id);
1375 if (!cmd->completion)
1376 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1379 case TRB_EVAL_CONTEXT:
1384 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1385 le32_to_cpu(cmd_trb->generic.field[3])));
1386 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1389 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1390 le32_to_cpu(cmd_trb->generic.field[3])));
1391 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1394 /* Is this an aborted command turned to NO-OP? */
1395 if (cmd->status == COMP_CMD_STOP)
1396 cmd_comp_code = COMP_CMD_STOP;
1399 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1400 le32_to_cpu(cmd_trb->generic.field[3])));
1401 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1404 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1405 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1407 slot_id = TRB_TO_SLOT_ID(
1408 le32_to_cpu(cmd_trb->generic.field[3]));
1409 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1411 case TRB_NEC_GET_FW:
1412 xhci_handle_cmd_nec_get_fw(xhci, event);
1415 /* Skip over unknown commands on the event ring */
1416 xhci->error_bitmask |= 1 << 6;
1420 /* restart timer if this wasn't the last command */
1421 if (cmd->cmd_list.next != &xhci->cmd_list) {
1422 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1423 struct xhci_command, cmd_list);
1424 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1428 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1430 inc_deq(xhci, xhci->cmd_ring);
1433 static void handle_vendor_event(struct xhci_hcd *xhci,
1434 union xhci_trb *event)
1438 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1439 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1440 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1441 handle_cmd_completion(xhci, &event->event_cmd);
1444 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1445 * port registers -- USB 3.0 and USB 2.0).
1447 * Returns a zero-based port number, which is suitable for indexing into each of
1448 * the split roothubs' port arrays and bus state arrays.
1449 * Add one to it in order to call xhci_find_slot_id_by_port.
1451 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1452 struct xhci_hcd *xhci, u32 port_id)
1455 unsigned int num_similar_speed_ports = 0;
1457 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1458 * and usb2_ports are 0-based indexes. Count the number of similar
1459 * speed ports, up to 1 port before this port.
1461 for (i = 0; i < (port_id - 1); i++) {
1462 u8 port_speed = xhci->port_array[i];
1465 * Skip ports that don't have known speeds, or have duplicate
1466 * Extended Capabilities port speed entries.
1468 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1472 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1473 * 1.1 ports are under the USB 2.0 hub. If the port speed
1474 * matches the device speed, it's a similar speed port.
1476 if ((port_speed == 0x03) == (hcd->speed >= HCD_USB3))
1477 num_similar_speed_ports++;
1479 return num_similar_speed_ports;
1482 static void handle_device_notification(struct xhci_hcd *xhci,
1483 union xhci_trb *event)
1486 struct usb_device *udev;
1488 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1489 if (!xhci->devs[slot_id]) {
1490 xhci_warn(xhci, "Device Notification event for "
1491 "unused slot %u\n", slot_id);
1495 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1497 udev = xhci->devs[slot_id]->udev;
1498 if (udev && udev->parent)
1499 usb_wakeup_notification(udev->parent, udev->portnum);
1502 static void handle_port_status(struct xhci_hcd *xhci,
1503 union xhci_trb *event)
1505 struct usb_hcd *hcd;
1510 unsigned int faked_port_index;
1512 struct xhci_bus_state *bus_state;
1513 __le32 __iomem **port_array;
1514 bool bogus_port_status = false;
1516 /* Port status change events always have a successful completion code */
1517 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1518 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1519 xhci->error_bitmask |= 1 << 8;
1521 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1522 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1524 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1525 if ((port_id <= 0) || (port_id > max_ports)) {
1526 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1527 inc_deq(xhci, xhci->event_ring);
1531 /* Figure out which usb_hcd this port is attached to:
1532 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1534 major_revision = xhci->port_array[port_id - 1];
1536 /* Find the right roothub. */
1537 hcd = xhci_to_hcd(xhci);
1538 if ((major_revision == 0x03) != (hcd->speed >= HCD_USB3))
1539 hcd = xhci->shared_hcd;
1541 if (major_revision == 0) {
1542 xhci_warn(xhci, "Event for port %u not in "
1543 "Extended Capabilities, ignoring.\n",
1545 bogus_port_status = true;
1548 if (major_revision == DUPLICATE_ENTRY) {
1549 xhci_warn(xhci, "Event for port %u duplicated in"
1550 "Extended Capabilities, ignoring.\n",
1552 bogus_port_status = true;
1557 * Hardware port IDs reported by a Port Status Change Event include USB
1558 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1559 * resume event, but we first need to translate the hardware port ID
1560 * into the index into the ports on the correct split roothub, and the
1561 * correct bus_state structure.
1563 bus_state = &xhci->bus_state[hcd_index(hcd)];
1564 if (hcd->speed >= HCD_USB3)
1565 port_array = xhci->usb3_ports;
1567 port_array = xhci->usb2_ports;
1568 /* Find the faked port hub number */
1569 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1572 temp = readl(port_array[faked_port_index]);
1573 if (hcd->state == HC_STATE_SUSPENDED) {
1574 xhci_dbg(xhci, "resume root hub\n");
1575 usb_hcd_resume_root_hub(hcd);
1578 if (hcd->speed >= HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
1579 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1581 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1582 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1584 temp1 = readl(&xhci->op_regs->command);
1585 if (!(temp1 & CMD_RUN)) {
1586 xhci_warn(xhci, "xHC is not running.\n");
1590 if (DEV_SUPERSPEED_ANY(temp)) {
1591 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1592 /* Set a flag to say the port signaled remote wakeup,
1593 * so we can tell the difference between the end of
1594 * device and host initiated resume.
1596 bus_state->port_remote_wakeup |= 1 << faked_port_index;
1597 xhci_test_and_clear_bit(xhci, port_array,
1598 faked_port_index, PORT_PLC);
1599 xhci_set_link_state(xhci, port_array, faked_port_index,
1601 /* Need to wait until the next link state change
1602 * indicates the device is actually in U0.
1604 bogus_port_status = true;
1606 } else if (!test_bit(faked_port_index,
1607 &bus_state->resuming_ports)) {
1608 xhci_dbg(xhci, "resume HS port %d\n", port_id);
1609 bus_state->resume_done[faked_port_index] = jiffies +
1610 msecs_to_jiffies(USB_RESUME_TIMEOUT);
1611 set_bit(faked_port_index, &bus_state->resuming_ports);
1612 mod_timer(&hcd->rh_timer,
1613 bus_state->resume_done[faked_port_index]);
1614 /* Do the rest in GetPortStatus */
1618 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1619 DEV_SUPERSPEED_ANY(temp)) {
1620 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1621 /* We've just brought the device into U0 through either the
1622 * Resume state after a device remote wakeup, or through the
1623 * U3Exit state after a host-initiated resume. If it's a device
1624 * initiated remote wake, don't pass up the link state change,
1625 * so the roothub behavior is consistent with external
1626 * USB 3.0 hub behavior.
1628 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1629 faked_port_index + 1);
1630 if (slot_id && xhci->devs[slot_id])
1631 xhci_ring_device(xhci, slot_id);
1632 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1633 bus_state->port_remote_wakeup &=
1634 ~(1 << faked_port_index);
1635 xhci_test_and_clear_bit(xhci, port_array,
1636 faked_port_index, PORT_PLC);
1637 usb_wakeup_notification(hcd->self.root_hub,
1638 faked_port_index + 1);
1639 bogus_port_status = true;
1645 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1646 * RExit to a disconnect state). If so, let the the driver know it's
1647 * out of the RExit state.
1649 if (!DEV_SUPERSPEED_ANY(temp) &&
1650 test_and_clear_bit(faked_port_index,
1651 &bus_state->rexit_ports)) {
1652 complete(&bus_state->rexit_done[faked_port_index]);
1653 bogus_port_status = true;
1657 if (hcd->speed < HCD_USB3)
1658 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1662 /* Update event ring dequeue pointer before dropping the lock */
1663 inc_deq(xhci, xhci->event_ring);
1665 /* Don't make the USB core poll the roothub if we got a bad port status
1666 * change event. Besides, at that point we can't tell which roothub
1667 * (USB 2.0 or USB 3.0) to kick.
1669 if (bogus_port_status)
1673 * xHCI port-status-change events occur when the "or" of all the
1674 * status-change bits in the portsc register changes from 0 to 1.
1675 * New status changes won't cause an event if any other change
1676 * bits are still set. When an event occurs, switch over to
1677 * polling to avoid losing status changes.
1679 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1680 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1681 spin_unlock(&xhci->lock);
1682 /* Pass this up to the core */
1683 usb_hcd_poll_rh_status(hcd);
1684 spin_lock(&xhci->lock);
1688 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1689 * at end_trb, which may be in another segment. If the suspect DMA address is a
1690 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1693 struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1694 struct xhci_segment *start_seg,
1695 union xhci_trb *start_trb,
1696 union xhci_trb *end_trb,
1697 dma_addr_t suspect_dma,
1700 dma_addr_t start_dma;
1701 dma_addr_t end_seg_dma;
1702 dma_addr_t end_trb_dma;
1703 struct xhci_segment *cur_seg;
1705 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1706 cur_seg = start_seg;
1711 /* We may get an event for a Link TRB in the middle of a TD */
1712 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1713 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1714 /* If the end TRB isn't in this segment, this is set to 0 */
1715 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1719 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1720 (unsigned long long)suspect_dma,
1721 (unsigned long long)start_dma,
1722 (unsigned long long)end_trb_dma,
1723 (unsigned long long)cur_seg->dma,
1724 (unsigned long long)end_seg_dma);
1726 if (end_trb_dma > 0) {
1727 /* The end TRB is in this segment, so suspect should be here */
1728 if (start_dma <= end_trb_dma) {
1729 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1732 /* Case for one segment with
1733 * a TD wrapped around to the top
1735 if ((suspect_dma >= start_dma &&
1736 suspect_dma <= end_seg_dma) ||
1737 (suspect_dma >= cur_seg->dma &&
1738 suspect_dma <= end_trb_dma))
1743 /* Might still be somewhere in this segment */
1744 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1747 cur_seg = cur_seg->next;
1748 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1749 } while (cur_seg != start_seg);
1754 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1755 unsigned int slot_id, unsigned int ep_index,
1756 unsigned int stream_id,
1757 struct xhci_td *td, union xhci_trb *event_trb)
1759 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1760 struct xhci_command *command;
1761 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1765 ep->ep_state |= EP_HALTED;
1766 ep->stopped_stream = stream_id;
1768 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
1769 xhci_cleanup_stalled_ring(xhci, ep_index, td);
1771 ep->stopped_stream = 0;
1773 xhci_ring_cmd_db(xhci);
1776 /* Check if an error has halted the endpoint ring. The class driver will
1777 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1778 * However, a babble and other errors also halt the endpoint ring, and the class
1779 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1780 * Ring Dequeue Pointer command manually.
1782 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1783 struct xhci_ep_ctx *ep_ctx,
1784 unsigned int trb_comp_code)
1786 /* TRB completion codes that may require a manual halt cleanup */
1787 if (trb_comp_code == COMP_TX_ERR ||
1788 trb_comp_code == COMP_BABBLE ||
1789 trb_comp_code == COMP_SPLIT_ERR)
1790 /* The 0.95 spec says a babbling control endpoint
1791 * is not halted. The 0.96 spec says it is. Some HW
1792 * claims to be 0.95 compliant, but it halts the control
1793 * endpoint anyway. Check if a babble halted the
1796 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1797 cpu_to_le32(EP_STATE_HALTED))
1803 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1805 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1806 /* Vendor defined "informational" completion code,
1807 * treat as not-an-error.
1809 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1811 xhci_dbg(xhci, "Treating code as success.\n");
1818 * Finish the td processing, remove the td from td list;
1819 * Return 1 if the urb can be given back.
1821 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1822 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1823 struct xhci_virt_ep *ep, int *status, bool skip)
1825 struct xhci_virt_device *xdev;
1826 struct xhci_ring *ep_ring;
1827 unsigned int slot_id;
1829 struct urb *urb = NULL;
1830 struct xhci_ep_ctx *ep_ctx;
1832 struct urb_priv *urb_priv;
1835 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1836 xdev = xhci->devs[slot_id];
1837 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1838 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1839 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1840 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1845 if (trb_comp_code == COMP_STOP_INVAL ||
1846 trb_comp_code == COMP_STOP ||
1847 trb_comp_code == COMP_STOP_SHORT) {
1848 /* The Endpoint Stop Command completion will take care of any
1849 * stopped TDs. A stopped TD may be restarted, so don't update
1850 * the ring dequeue pointer or take this TD off any lists yet.
1852 ep->stopped_td = td;
1855 if (trb_comp_code == COMP_STALL ||
1856 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1858 /* Issue a reset endpoint command to clear the host side
1859 * halt, followed by a set dequeue command to move the
1860 * dequeue pointer past the TD.
1861 * The class driver clears the device side halt later.
1863 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1864 ep_ring->stream_id, td, event_trb);
1866 /* Update ring dequeue pointer */
1867 while (ep_ring->dequeue != td->last_trb)
1868 inc_deq(xhci, ep_ring);
1869 inc_deq(xhci, ep_ring);
1873 /* Clean up the endpoint's TD list */
1875 urb_priv = urb->hcpriv;
1877 /* if a bounce buffer was used to align this td then unmap it */
1879 xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1881 /* Do one last check of the actual transfer length.
1882 * If the host controller said we transferred more data than the buffer
1883 * length, urb->actual_length will be a very big number (since it's
1884 * unsigned). Play it safe and say we didn't transfer anything.
1886 if (urb->actual_length > urb->transfer_buffer_length) {
1887 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1888 urb->transfer_buffer_length,
1889 urb->actual_length);
1890 urb->actual_length = 0;
1891 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1892 *status = -EREMOTEIO;
1896 list_del_init(&td->td_list);
1897 /* Was this TD slated to be cancelled but completed anyway? */
1898 if (!list_empty(&td->cancelled_td_list))
1899 list_del_init(&td->cancelled_td_list);
1902 /* Giveback the urb when all the tds are completed */
1903 if (urb_priv->td_cnt == urb_priv->length) {
1905 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1906 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1907 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1908 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1909 usb_amd_quirk_pll_enable();
1918 * Process control tds, update urb status and actual_length.
1920 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1921 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1922 struct xhci_virt_ep *ep, int *status)
1924 struct xhci_virt_device *xdev;
1925 struct xhci_ring *ep_ring;
1926 unsigned int slot_id;
1928 struct xhci_ep_ctx *ep_ctx;
1931 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1932 xdev = xhci->devs[slot_id];
1933 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1934 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1935 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1936 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1938 switch (trb_comp_code) {
1940 if (event_trb == ep_ring->dequeue) {
1941 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1942 "without IOC set??\n");
1943 *status = -ESHUTDOWN;
1944 } else if (event_trb != td->last_trb) {
1945 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1946 "without IOC set??\n");
1947 *status = -ESHUTDOWN;
1953 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1954 *status = -EREMOTEIO;
1958 case COMP_STOP_SHORT:
1959 if (event_trb == ep_ring->dequeue || event_trb == td->last_trb)
1960 xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1962 td->urb->actual_length =
1963 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1965 return finish_td(xhci, td, event_trb, event, ep, status, false);
1967 /* Did we stop at data stage? */
1968 if (event_trb != ep_ring->dequeue && event_trb != td->last_trb)
1969 td->urb->actual_length =
1970 td->urb->transfer_buffer_length -
1971 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1973 case COMP_STOP_INVAL:
1974 return finish_td(xhci, td, event_trb, event, ep, status, false);
1976 if (!xhci_requires_manual_halt_cleanup(xhci,
1977 ep_ctx, trb_comp_code))
1979 xhci_dbg(xhci, "TRB error code %u, "
1980 "halted endpoint index = %u\n",
1981 trb_comp_code, ep_index);
1982 /* else fall through */
1984 /* Did we transfer part of the data (middle) phase? */
1985 if (event_trb != ep_ring->dequeue &&
1986 event_trb != td->last_trb)
1987 td->urb->actual_length =
1988 td->urb->transfer_buffer_length -
1989 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1990 else if (!td->urb_length_set)
1991 td->urb->actual_length = 0;
1993 return finish_td(xhci, td, event_trb, event, ep, status, false);
1996 * Did we transfer any data, despite the errors that might have
1997 * happened? I.e. did we get past the setup stage?
1999 if (event_trb != ep_ring->dequeue) {
2000 /* The event was for the status stage */
2001 if (event_trb == td->last_trb) {
2002 if (td->urb_length_set) {
2003 /* Don't overwrite a previously set error code
2005 if ((*status == -EINPROGRESS || *status == 0) &&
2006 (td->urb->transfer_flags
2007 & URB_SHORT_NOT_OK))
2008 /* Did we already see a short data
2010 *status = -EREMOTEIO;
2012 td->urb->actual_length =
2013 td->urb->transfer_buffer_length;
2017 * Maybe the event was for the data stage? If so, update
2018 * already the actual_length of the URB and flag it as
2019 * set, so that it is not overwritten in the event for
2022 td->urb_length_set = true;
2023 td->urb->actual_length =
2024 td->urb->transfer_buffer_length -
2025 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2026 xhci_dbg(xhci, "Waiting for status "
2032 return finish_td(xhci, td, event_trb, event, ep, status, false);
2036 * Process isochronous tds, update urb packet status and actual_length.
2038 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2039 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2040 struct xhci_virt_ep *ep, int *status)
2042 struct xhci_ring *ep_ring;
2043 struct urb_priv *urb_priv;
2046 union xhci_trb *cur_trb;
2047 struct xhci_segment *cur_seg;
2048 struct usb_iso_packet_descriptor *frame;
2050 bool skip_td = false;
2052 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2053 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2054 urb_priv = td->urb->hcpriv;
2055 idx = urb_priv->td_cnt;
2056 frame = &td->urb->iso_frame_desc[idx];
2058 /* handle completion code */
2059 switch (trb_comp_code) {
2061 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2065 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2066 trb_comp_code = COMP_SHORT_TX;
2068 case COMP_STOP_SHORT:
2070 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2074 frame->status = -ECOMM;
2077 case COMP_BUFF_OVER:
2079 frame->status = -EOVERFLOW;
2084 frame->status = -EPROTO;
2088 frame->status = -EPROTO;
2089 if (event_trb != td->last_trb)
2094 case COMP_STOP_INVAL:
2101 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2102 frame->actual_length = frame->length;
2103 td->urb->actual_length += frame->length;
2104 } else if (trb_comp_code == COMP_STOP_SHORT) {
2105 frame->actual_length =
2106 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2107 td->urb->actual_length += frame->actual_length;
2109 for (cur_trb = ep_ring->dequeue,
2110 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2111 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2112 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2113 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2114 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2116 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2117 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2119 if (trb_comp_code != COMP_STOP_INVAL) {
2120 frame->actual_length = len;
2121 td->urb->actual_length += len;
2125 return finish_td(xhci, td, event_trb, event, ep, status, false);
2128 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2129 struct xhci_transfer_event *event,
2130 struct xhci_virt_ep *ep, int *status)
2132 struct xhci_ring *ep_ring;
2133 struct urb_priv *urb_priv;
2134 struct usb_iso_packet_descriptor *frame;
2137 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2138 urb_priv = td->urb->hcpriv;
2139 idx = urb_priv->td_cnt;
2140 frame = &td->urb->iso_frame_desc[idx];
2142 /* The transfer is partly done. */
2143 frame->status = -EXDEV;
2145 /* calc actual length */
2146 frame->actual_length = 0;
2148 /* Update ring dequeue pointer */
2149 while (ep_ring->dequeue != td->last_trb)
2150 inc_deq(xhci, ep_ring);
2151 inc_deq(xhci, ep_ring);
2153 return finish_td(xhci, td, NULL, event, ep, status, true);
2157 * Process bulk and interrupt tds, update urb status and actual_length.
2159 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2160 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2161 struct xhci_virt_ep *ep, int *status)
2163 struct xhci_ring *ep_ring;
2164 union xhci_trb *cur_trb;
2165 struct xhci_segment *cur_seg;
2168 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2169 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2171 switch (trb_comp_code) {
2173 /* Double check that the HW transferred everything. */
2174 if (event_trb != td->last_trb ||
2175 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2176 xhci_warn(xhci, "WARN Successful completion "
2178 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2179 *status = -EREMOTEIO;
2182 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2183 trb_comp_code = COMP_SHORT_TX;
2188 case COMP_STOP_SHORT:
2190 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2191 *status = -EREMOTEIO;
2196 /* Others already handled above */
2199 if (trb_comp_code == COMP_SHORT_TX)
2200 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2201 "%d bytes untransferred\n",
2202 td->urb->ep->desc.bEndpointAddress,
2203 td->urb->transfer_buffer_length,
2204 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2205 /* Stopped - short packet completion */
2206 if (trb_comp_code == COMP_STOP_SHORT) {
2207 td->urb->actual_length =
2208 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2210 if (td->urb->transfer_buffer_length <
2211 td->urb->actual_length) {
2212 xhci_warn(xhci, "HC gave bad length of %d bytes txed\n",
2213 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2214 td->urb->actual_length = 0;
2215 /* status will be set by usb core for canceled urbs */
2217 /* Fast path - was this the last TRB in the TD for this URB? */
2218 } else if (event_trb == td->last_trb) {
2219 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2220 td->urb->actual_length =
2221 td->urb->transfer_buffer_length -
2222 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2223 if (td->urb->transfer_buffer_length <
2224 td->urb->actual_length) {
2225 xhci_warn(xhci, "HC gave bad length "
2226 "of %d bytes left\n",
2227 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2228 td->urb->actual_length = 0;
2229 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2230 *status = -EREMOTEIO;
2234 /* Don't overwrite a previously set error code */
2235 if (*status == -EINPROGRESS) {
2236 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2237 *status = -EREMOTEIO;
2242 td->urb->actual_length =
2243 td->urb->transfer_buffer_length;
2244 /* Ignore a short packet completion if the
2245 * untransferred length was zero.
2247 if (*status == -EREMOTEIO)
2251 /* Slow path - walk the list, starting from the dequeue
2252 * pointer, to get the actual length transferred.
2254 td->urb->actual_length = 0;
2255 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2256 cur_trb != event_trb;
2257 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2258 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2259 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2260 td->urb->actual_length +=
2261 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2263 /* If the ring didn't stop on a Link or No-op TRB, add
2264 * in the actual bytes transferred from the Normal TRB
2266 if (trb_comp_code != COMP_STOP_INVAL)
2267 td->urb->actual_length +=
2268 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2269 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2272 return finish_td(xhci, td, event_trb, event, ep, status, false);
2276 * If this function returns an error condition, it means it got a Transfer
2277 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2278 * At this point, the host controller is probably hosed and should be reset.
2280 static int handle_tx_event(struct xhci_hcd *xhci,
2281 struct xhci_transfer_event *event)
2282 __releases(&xhci->lock)
2283 __acquires(&xhci->lock)
2285 struct xhci_virt_device *xdev;
2286 struct xhci_virt_ep *ep;
2287 struct xhci_ring *ep_ring;
2288 unsigned int slot_id;
2290 struct xhci_td *td = NULL;
2291 dma_addr_t event_dma;
2292 struct xhci_segment *event_seg;
2293 union xhci_trb *event_trb;
2294 struct urb *urb = NULL;
2295 int status = -EINPROGRESS;
2296 struct urb_priv *urb_priv;
2297 struct xhci_ep_ctx *ep_ctx;
2298 struct list_head *tmp;
2302 bool handling_skipped_tds = false;
2304 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2305 xdev = xhci->devs[slot_id];
2307 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2308 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2309 (unsigned long long) xhci_trb_virt_to_dma(
2310 xhci->event_ring->deq_seg,
2311 xhci->event_ring->dequeue),
2312 lower_32_bits(le64_to_cpu(event->buffer)),
2313 upper_32_bits(le64_to_cpu(event->buffer)),
2314 le32_to_cpu(event->transfer_len),
2315 le32_to_cpu(event->flags));
2316 xhci_dbg(xhci, "Event ring:\n");
2317 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2321 /* Endpoint ID is 1 based, our index is zero based */
2322 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2323 ep = &xdev->eps[ep_index];
2324 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2325 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2327 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2328 EP_STATE_DISABLED) {
2329 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2330 "or incorrect stream ring\n");
2331 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2332 (unsigned long long) xhci_trb_virt_to_dma(
2333 xhci->event_ring->deq_seg,
2334 xhci->event_ring->dequeue),
2335 lower_32_bits(le64_to_cpu(event->buffer)),
2336 upper_32_bits(le64_to_cpu(event->buffer)),
2337 le32_to_cpu(event->transfer_len),
2338 le32_to_cpu(event->flags));
2339 xhci_dbg(xhci, "Event ring:\n");
2340 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2344 /* Count current td numbers if ep->skip is set */
2346 list_for_each(tmp, &ep_ring->td_list)
2350 event_dma = le64_to_cpu(event->buffer);
2351 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2352 /* Look for common error cases */
2353 switch (trb_comp_code) {
2354 /* Skip codes that require special handling depending on
2358 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2360 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2361 trb_comp_code = COMP_SHORT_TX;
2363 xhci_warn_ratelimited(xhci,
2364 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2368 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2370 case COMP_STOP_INVAL:
2371 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2373 case COMP_STOP_SHORT:
2374 xhci_dbg(xhci, "Stopped with short packet transfer detected\n");
2377 xhci_dbg(xhci, "Stalled endpoint\n");
2378 ep->ep_state |= EP_HALTED;
2382 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2385 case COMP_SPLIT_ERR:
2387 xhci_dbg(xhci, "Transfer error on endpoint\n");
2391 xhci_dbg(xhci, "Babble error on endpoint\n");
2392 status = -EOVERFLOW;
2395 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2399 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2401 case COMP_BUFF_OVER:
2402 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2406 * When the Isoch ring is empty, the xHC will generate
2407 * a Ring Overrun Event for IN Isoch endpoint or Ring
2408 * Underrun Event for OUT Isoch endpoint.
2410 xhci_dbg(xhci, "underrun event on endpoint\n");
2411 if (!list_empty(&ep_ring->td_list))
2412 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2413 "still with TDs queued?\n",
2414 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2418 xhci_dbg(xhci, "overrun event on endpoint\n");
2419 if (!list_empty(&ep_ring->td_list))
2420 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2421 "still with TDs queued?\n",
2422 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2426 xhci_warn(xhci, "WARN: detect an incompatible device");
2429 case COMP_MISSED_INT:
2431 * When encounter missed service error, one or more isoc tds
2432 * may be missed by xHC.
2433 * Set skip flag of the ep_ring; Complete the missed tds as
2434 * short transfer when process the ep_ring next time.
2437 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2441 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2444 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2448 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2454 /* This TRB should be in the TD at the head of this ring's
2457 if (list_empty(&ep_ring->td_list)) {
2459 * A stopped endpoint may generate an extra completion
2460 * event if the device was suspended. Don't print
2463 if (!(trb_comp_code == COMP_STOP ||
2464 trb_comp_code == COMP_STOP_INVAL)) {
2465 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2466 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2468 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2469 (le32_to_cpu(event->flags) &
2470 TRB_TYPE_BITMASK)>>10);
2471 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2475 xhci_dbg(xhci, "td_list is empty while skip "
2476 "flag set. Clear skip flag.\n");
2482 /* We've skipped all the TDs on the ep ring when ep->skip set */
2483 if (ep->skip && td_num == 0) {
2485 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2486 "Clear skip flag.\n");
2491 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2495 /* Is this a TRB in the currently executing TD? */
2496 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2497 td->last_trb, event_dma, false);
2500 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2501 * is not in the current TD pointed by ep_ring->dequeue because
2502 * that the hardware dequeue pointer still at the previous TRB
2503 * of the current TD. The previous TRB maybe a Link TD or the
2504 * last TRB of the previous TD. The command completion handle
2505 * will take care the rest.
2507 if (!event_seg && (trb_comp_code == COMP_STOP ||
2508 trb_comp_code == COMP_STOP_INVAL)) {
2515 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2516 /* Some host controllers give a spurious
2517 * successful event after a short transfer.
2520 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2521 ep_ring->last_td_was_short) {
2522 ep_ring->last_td_was_short = false;
2526 /* HC is busted, give up! */
2528 "ERROR Transfer event TRB DMA ptr not "
2529 "part of current TD ep_index %d "
2530 "comp_code %u\n", ep_index,
2532 trb_in_td(xhci, ep_ring->deq_seg,
2533 ep_ring->dequeue, td->last_trb,
2538 ret = skip_isoc_td(xhci, td, event, ep, &status);
2541 if (trb_comp_code == COMP_SHORT_TX)
2542 ep_ring->last_td_was_short = true;
2544 ep_ring->last_td_was_short = false;
2547 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2551 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2552 sizeof(*event_trb)];
2554 * No-op TRB should not trigger interrupts.
2555 * If event_trb is a no-op TRB, it means the
2556 * corresponding TD has been cancelled. Just ignore
2559 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2561 "event_trb is a no-op TRB. Skip it\n");
2565 /* Now update the urb's actual_length and give back to
2568 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2569 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2571 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2572 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2575 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2581 handling_skipped_tds = ep->skip &&
2582 trb_comp_code != COMP_MISSED_INT &&
2583 trb_comp_code != COMP_PING_ERR;
2586 * Do not update event ring dequeue pointer if we're in a loop
2587 * processing missed tds.
2589 if (!handling_skipped_tds)
2590 inc_deq(xhci, xhci->event_ring);
2594 urb_priv = urb->hcpriv;
2596 xhci_urb_free_priv(urb_priv);
2598 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2599 if ((urb->actual_length != urb->transfer_buffer_length &&
2600 (urb->transfer_flags &
2601 URB_SHORT_NOT_OK)) ||
2603 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2604 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2605 "expected = %d, status = %d\n",
2606 urb, urb->actual_length,
2607 urb->transfer_buffer_length,
2609 spin_unlock(&xhci->lock);
2610 /* EHCI, UHCI, and OHCI always unconditionally set the
2611 * urb->status of an isochronous endpoint to 0.
2613 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2615 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2616 spin_lock(&xhci->lock);
2620 * If ep->skip is set, it means there are missed tds on the
2621 * endpoint ring need to take care of.
2622 * Process them as short transfer until reach the td pointed by
2625 } while (handling_skipped_tds);
2631 * This function handles all OS-owned events on the event ring. It may drop
2632 * xhci->lock between event processing (e.g. to pass up port status changes).
2633 * Returns >0 for "possibly more events to process" (caller should call again),
2634 * otherwise 0 if done. In future, <0 returns should indicate error code.
2636 static int xhci_handle_event(struct xhci_hcd *xhci)
2638 union xhci_trb *event;
2639 int update_ptrs = 1;
2642 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2643 xhci->error_bitmask |= 1 << 1;
2647 event = xhci->event_ring->dequeue;
2648 /* Does the HC or OS own the TRB? */
2649 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2650 xhci->event_ring->cycle_state) {
2651 xhci->error_bitmask |= 1 << 2;
2656 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2657 * speculative reads of the event's flags/data below.
2660 /* FIXME: Handle more event types. */
2661 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2662 case TRB_TYPE(TRB_COMPLETION):
2663 handle_cmd_completion(xhci, &event->event_cmd);
2665 case TRB_TYPE(TRB_PORT_STATUS):
2666 handle_port_status(xhci, event);
2669 case TRB_TYPE(TRB_TRANSFER):
2670 ret = handle_tx_event(xhci, &event->trans_event);
2672 xhci->error_bitmask |= 1 << 9;
2676 case TRB_TYPE(TRB_DEV_NOTE):
2677 handle_device_notification(xhci, event);
2680 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2682 handle_vendor_event(xhci, event);
2684 xhci->error_bitmask |= 1 << 3;
2686 /* Any of the above functions may drop and re-acquire the lock, so check
2687 * to make sure a watchdog timer didn't mark the host as non-responsive.
2689 if (xhci->xhc_state & XHCI_STATE_DYING) {
2690 xhci_dbg(xhci, "xHCI host dying, returning from "
2691 "event handler.\n");
2696 /* Update SW event ring dequeue pointer */
2697 inc_deq(xhci, xhci->event_ring);
2699 /* Are there more items on the event ring? Caller will call us again to
2706 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2707 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2708 * indicators of an event TRB error, but we check the status *first* to be safe.
2710 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2712 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2715 union xhci_trb *event_ring_deq;
2718 spin_lock(&xhci->lock);
2719 /* Check if the xHC generated the interrupt, or the irq is shared */
2720 status = readl(&xhci->op_regs->status);
2721 if (status == 0xffffffff)
2724 if (!(status & STS_EINT)) {
2725 spin_unlock(&xhci->lock);
2728 if (status & STS_FATAL) {
2729 xhci_warn(xhci, "WARNING: Host System Error\n");
2732 spin_unlock(&xhci->lock);
2737 * Clear the op reg interrupt status first,
2738 * so we can receive interrupts from other MSI-X interrupters.
2739 * Write 1 to clear the interrupt status.
2742 writel(status, &xhci->op_regs->status);
2743 /* FIXME when MSI-X is supported and there are multiple vectors */
2744 /* Clear the MSI-X event interrupt status */
2748 /* Acknowledge the PCI interrupt */
2749 irq_pending = readl(&xhci->ir_set->irq_pending);
2750 irq_pending |= IMAN_IP;
2751 writel(irq_pending, &xhci->ir_set->irq_pending);
2754 if (xhci->xhc_state & XHCI_STATE_DYING ||
2755 xhci->xhc_state & XHCI_STATE_HALTED) {
2756 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2757 "Shouldn't IRQs be disabled?\n");
2758 /* Clear the event handler busy flag (RW1C);
2759 * the event ring should be empty.
2761 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2762 xhci_write_64(xhci, temp_64 | ERST_EHB,
2763 &xhci->ir_set->erst_dequeue);
2764 spin_unlock(&xhci->lock);
2769 event_ring_deq = xhci->event_ring->dequeue;
2770 /* FIXME this should be a delayed service routine
2771 * that clears the EHB.
2773 while (xhci_handle_event(xhci) > 0) {}
2775 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2776 /* If necessary, update the HW's version of the event ring deq ptr. */
2777 if (event_ring_deq != xhci->event_ring->dequeue) {
2778 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2779 xhci->event_ring->dequeue);
2781 xhci_warn(xhci, "WARN something wrong with SW event "
2782 "ring dequeue ptr.\n");
2783 /* Update HC event ring dequeue pointer */
2784 temp_64 &= ERST_PTR_MASK;
2785 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2788 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2789 temp_64 |= ERST_EHB;
2790 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2792 spin_unlock(&xhci->lock);
2797 irqreturn_t xhci_msi_irq(int irq, void *hcd)
2799 return xhci_irq(hcd);
2802 /**** Endpoint Ring Operations ****/
2805 * Generic function for queueing a TRB on a ring.
2806 * The caller must have checked to make sure there's room on the ring.
2808 * @more_trbs_coming: Will you enqueue more TRBs before calling
2809 * prepare_transfer()?
2811 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2812 bool more_trbs_coming,
2813 u32 field1, u32 field2, u32 field3, u32 field4)
2815 struct xhci_generic_trb *trb;
2817 trb = &ring->enqueue->generic;
2818 trb->field[0] = cpu_to_le32(field1);
2819 trb->field[1] = cpu_to_le32(field2);
2820 trb->field[2] = cpu_to_le32(field3);
2821 trb->field[3] = cpu_to_le32(field4);
2822 inc_enq(xhci, ring, more_trbs_coming);
2826 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2827 * FIXME allocate segments if the ring is full.
2829 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2830 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2832 unsigned int num_trbs_needed;
2834 /* Make sure the endpoint has been added to xHC schedule */
2836 case EP_STATE_DISABLED:
2838 * USB core changed config/interfaces without notifying us,
2839 * or hardware is reporting the wrong state.
2841 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2843 case EP_STATE_ERROR:
2844 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2845 /* FIXME event handling code for error needs to clear it */
2846 /* XXX not sure if this should be -ENOENT or not */
2848 case EP_STATE_HALTED:
2849 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2850 case EP_STATE_STOPPED:
2851 case EP_STATE_RUNNING:
2854 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2856 * FIXME issue Configure Endpoint command to try to get the HC
2857 * back into a known state.
2863 if (room_on_ring(xhci, ep_ring, num_trbs))
2866 if (ep_ring == xhci->cmd_ring) {
2867 xhci_err(xhci, "Do not support expand command ring\n");
2871 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2872 "ERROR no room on ep ring, try ring expansion");
2873 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2874 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2876 xhci_err(xhci, "Ring expansion failed\n");
2881 while (trb_is_link(ep_ring->enqueue)) {
2882 /* If we're not dealing with 0.95 hardware or isoc rings
2883 * on AMD 0.96 host, clear the chain bit.
2885 if (!xhci_link_trb_quirk(xhci) &&
2886 !(ep_ring->type == TYPE_ISOC &&
2887 (xhci->quirks & XHCI_AMD_0x96_HOST)))
2888 ep_ring->enqueue->link.control &=
2889 cpu_to_le32(~TRB_CHAIN);
2891 ep_ring->enqueue->link.control |=
2892 cpu_to_le32(TRB_CHAIN);
2895 ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2897 /* Toggle the cycle bit after the last ring segment. */
2898 if (link_trb_toggles_cycle(ep_ring->enqueue))
2899 ep_ring->cycle_state ^= 1;
2901 ep_ring->enq_seg = ep_ring->enq_seg->next;
2902 ep_ring->enqueue = ep_ring->enq_seg->trbs;
2907 static int prepare_transfer(struct xhci_hcd *xhci,
2908 struct xhci_virt_device *xdev,
2909 unsigned int ep_index,
2910 unsigned int stream_id,
2911 unsigned int num_trbs,
2913 unsigned int td_index,
2917 struct urb_priv *urb_priv;
2919 struct xhci_ring *ep_ring;
2920 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2922 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2924 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2929 ret = prepare_ring(xhci, ep_ring,
2930 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2931 num_trbs, mem_flags);
2935 urb_priv = urb->hcpriv;
2936 td = urb_priv->td[td_index];
2938 INIT_LIST_HEAD(&td->td_list);
2939 INIT_LIST_HEAD(&td->cancelled_td_list);
2941 if (td_index == 0) {
2942 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2948 /* Add this TD to the tail of the endpoint ring's TD list */
2949 list_add_tail(&td->td_list, &ep_ring->td_list);
2950 td->start_seg = ep_ring->enq_seg;
2951 td->first_trb = ep_ring->enqueue;
2953 urb_priv->td[td_index] = td;
2958 static unsigned int count_trbs(u64 addr, u64 len)
2960 unsigned int num_trbs;
2962 num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2970 static inline unsigned int count_trbs_needed(struct urb *urb)
2972 return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2975 static unsigned int count_sg_trbs_needed(struct urb *urb)
2977 struct scatterlist *sg;
2978 unsigned int i, len, full_len, num_trbs = 0;
2980 full_len = urb->transfer_buffer_length;
2982 for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2983 len = sg_dma_len(sg);
2984 num_trbs += count_trbs(sg_dma_address(sg), len);
2985 len = min_t(unsigned int, len, full_len);
2994 static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
2998 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2999 len = urb->iso_frame_desc[i].length;
3001 return count_trbs(addr, len);
3004 static void check_trb_math(struct urb *urb, int running_total)
3006 if (unlikely(running_total != urb->transfer_buffer_length))
3007 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3008 "queued %#x (%d), asked for %#x (%d)\n",
3010 urb->ep->desc.bEndpointAddress,
3011 running_total, running_total,
3012 urb->transfer_buffer_length,
3013 urb->transfer_buffer_length);
3016 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3017 unsigned int ep_index, unsigned int stream_id, int start_cycle,
3018 struct xhci_generic_trb *start_trb)
3021 * Pass all the TRBs to the hardware at once and make sure this write
3026 start_trb->field[3] |= cpu_to_le32(start_cycle);
3028 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3029 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3032 static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
3033 struct xhci_ep_ctx *ep_ctx)
3038 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3039 ep_interval = urb->interval;
3041 /* Convert to microframes */
3042 if (urb->dev->speed == USB_SPEED_LOW ||
3043 urb->dev->speed == USB_SPEED_FULL)
3046 /* FIXME change this to a warning and a suggestion to use the new API
3047 * to set the polling interval (once the API is added).
3049 if (xhci_interval != ep_interval) {
3050 dev_dbg_ratelimited(&urb->dev->dev,
3051 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3052 ep_interval, ep_interval == 1 ? "" : "s",
3053 xhci_interval, xhci_interval == 1 ? "" : "s");
3054 urb->interval = xhci_interval;
3055 /* Convert back to frames for LS/FS devices */
3056 if (urb->dev->speed == USB_SPEED_LOW ||
3057 urb->dev->speed == USB_SPEED_FULL)
3063 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3064 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3065 * (comprised of sg list entries) can take several service intervals to
3068 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3069 struct urb *urb, int slot_id, unsigned int ep_index)
3071 struct xhci_ep_ctx *ep_ctx;
3073 ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3074 check_interval(xhci, urb, ep_ctx);
3076 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3080 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3081 * packets remaining in the TD (*not* including this TRB).
3083 * Total TD packet count = total_packet_count =
3084 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3086 * Packets transferred up to and including this TRB = packets_transferred =
3087 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3089 * TD size = total_packet_count - packets_transferred
3091 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3092 * including this TRB, right shifted by 10
3094 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3095 * This is taken care of in the TRB_TD_SIZE() macro
3097 * The last TRB in a TD must have the TD size set to zero.
3099 static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3100 int trb_buff_len, unsigned int td_total_len,
3101 struct urb *urb, bool more_trbs_coming)
3103 u32 maxp, total_packet_count;
3105 /* MTK xHCI is mostly 0.97 but contains some features from 1.0 */
3106 if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3107 return ((td_total_len - transferred) >> 10);
3109 /* One TRB with a zero-length data packet. */
3110 if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3111 trb_buff_len == td_total_len)
3114 /* for MTK xHCI, TD size doesn't include this TRB */
3115 if (xhci->quirks & XHCI_MTK_HOST)
3118 maxp = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3119 total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3121 /* Queueing functions don't count the current TRB into transferred */
3122 return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3126 static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3127 u32 *trb_buff_len, struct xhci_segment *seg)
3129 struct device *dev = xhci_to_hcd(xhci)->self.controller;
3130 unsigned int unalign;
3131 unsigned int max_pkt;
3134 max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3135 unalign = (enqd_len + *trb_buff_len) % max_pkt;
3137 /* we got lucky, last normal TRB data on segment is packet aligned */
3141 xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3142 unalign, *trb_buff_len);
3144 /* is the last nornal TRB alignable by splitting it */
3145 if (*trb_buff_len > unalign) {
3146 *trb_buff_len -= unalign;
3147 xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3152 * We want enqd_len + trb_buff_len to sum up to a number aligned to
3153 * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3154 * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3156 new_buff_len = max_pkt - (enqd_len % max_pkt);
3158 if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3159 new_buff_len = (urb->transfer_buffer_length - enqd_len);
3161 /* create a max max_pkt sized bounce buffer pointed to by last trb */
3162 if (usb_urb_dir_out(urb)) {
3163 sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs,
3164 seg->bounce_buf, new_buff_len, enqd_len);
3165 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3166 max_pkt, DMA_TO_DEVICE);
3168 seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3169 max_pkt, DMA_FROM_DEVICE);
3172 if (dma_mapping_error(dev, seg->bounce_dma)) {
3173 /* try without aligning. Some host controllers survive */
3174 xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3177 *trb_buff_len = new_buff_len;
3178 seg->bounce_len = new_buff_len;
3179 seg->bounce_offs = enqd_len;
3181 xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3186 /* This is very similar to what ehci-q.c qtd_fill() does */
3187 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3188 struct urb *urb, int slot_id, unsigned int ep_index)
3190 struct xhci_ring *ring;
3191 struct urb_priv *urb_priv;
3193 struct xhci_generic_trb *start_trb;
3194 struct scatterlist *sg = NULL;
3195 bool more_trbs_coming = true;
3196 bool need_zero_pkt = false;
3197 bool first_trb = true;
3198 unsigned int num_trbs;
3199 unsigned int start_cycle, num_sgs = 0;
3200 unsigned int enqd_len, block_len, trb_buff_len, full_len;
3202 u32 field, length_field, remainder;
3203 u64 addr, send_addr;
3205 ring = xhci_urb_to_transfer_ring(xhci, urb);
3209 full_len = urb->transfer_buffer_length;
3210 /* If we have scatter/gather list, we use it. */
3212 num_sgs = urb->num_mapped_sgs;
3214 addr = (u64) sg_dma_address(sg);
3215 block_len = sg_dma_len(sg);
3216 num_trbs = count_sg_trbs_needed(urb);
3218 num_trbs = count_trbs_needed(urb);
3219 addr = (u64) urb->transfer_dma;
3220 block_len = full_len;
3222 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3223 ep_index, urb->stream_id,
3224 num_trbs, urb, 0, mem_flags);
3225 if (unlikely(ret < 0))
3228 urb_priv = urb->hcpriv;
3230 /* Deal with URB_ZERO_PACKET - need one more td/trb */
3231 if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->length > 1)
3232 need_zero_pkt = true;
3234 td = urb_priv->td[0];
3237 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3238 * until we've finished creating all the other TRBs. The ring's cycle
3239 * state may change as we enqueue the other TRBs, so save it too.
3241 start_trb = &ring->enqueue->generic;
3242 start_cycle = ring->cycle_state;
3245 /* Queue the TRBs, even if they are zero-length */
3246 for (enqd_len = 0; enqd_len < full_len; enqd_len += trb_buff_len) {
3247 field = TRB_TYPE(TRB_NORMAL);
3249 /* TRB buffer should not cross 64KB boundaries */
3250 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3251 trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3253 if (enqd_len + trb_buff_len > full_len)
3254 trb_buff_len = full_len - enqd_len;
3256 /* Don't change the cycle bit of the first TRB until later */
3259 if (start_cycle == 0)
3262 field |= ring->cycle_state;
3264 /* Chain all the TRBs together; clear the chain bit in the last
3265 * TRB to indicate it's the last TRB in the chain.
3267 if (enqd_len + trb_buff_len < full_len) {
3269 if (trb_is_link(ring->enqueue + 1)) {
3270 if (xhci_align_td(xhci, urb, enqd_len,
3273 send_addr = ring->enq_seg->bounce_dma;
3274 /* assuming TD won't span 2 segs */
3275 td->bounce_seg = ring->enq_seg;
3279 if (enqd_len + trb_buff_len >= full_len) {
3280 field &= ~TRB_CHAIN;
3282 more_trbs_coming = false;
3283 td->last_trb = ring->enqueue;
3286 /* Only set interrupt on short packet for IN endpoints */
3287 if (usb_urb_dir_in(urb))
3290 /* Set the TRB length, TD size, and interrupter fields. */
3291 remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3292 full_len, urb, more_trbs_coming);
3294 length_field = TRB_LEN(trb_buff_len) |
3295 TRB_TD_SIZE(remainder) |
3298 queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3299 lower_32_bits(send_addr),
3300 upper_32_bits(send_addr),
3304 addr += trb_buff_len;
3305 sent_len = trb_buff_len;
3307 while (sg && sent_len >= block_len) {
3310 sent_len -= block_len;
3313 block_len = sg_dma_len(sg);
3314 addr = (u64) sg_dma_address(sg);
3318 block_len -= sent_len;
3322 if (need_zero_pkt) {
3323 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3324 ep_index, urb->stream_id,
3325 1, urb, 1, mem_flags);
3326 urb_priv->td[1]->last_trb = ring->enqueue;
3327 field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3328 queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3331 check_trb_math(urb, enqd_len);
3332 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3333 start_cycle, start_trb);
3337 /* Caller must have locked xhci->lock */
3338 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3339 struct urb *urb, int slot_id, unsigned int ep_index)
3341 struct xhci_ring *ep_ring;
3344 struct usb_ctrlrequest *setup;
3345 struct xhci_generic_trb *start_trb;
3347 u32 field, length_field, remainder;
3348 struct urb_priv *urb_priv;
3351 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3356 * Need to copy setup packet into setup TRB, so we can't use the setup
3359 if (!urb->setup_packet)
3362 /* 1 TRB for setup, 1 for status */
3365 * Don't need to check if we need additional event data and normal TRBs,
3366 * since data in control transfers will never get bigger than 16MB
3367 * XXX: can we get a buffer that crosses 64KB boundaries?
3369 if (urb->transfer_buffer_length > 0)
3371 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3372 ep_index, urb->stream_id,
3373 num_trbs, urb, 0, mem_flags);
3377 urb_priv = urb->hcpriv;
3378 td = urb_priv->td[0];
3381 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3382 * until we've finished creating all the other TRBs. The ring's cycle
3383 * state may change as we enqueue the other TRBs, so save it too.
3385 start_trb = &ep_ring->enqueue->generic;
3386 start_cycle = ep_ring->cycle_state;
3388 /* Queue setup TRB - see section 6.4.1.2.1 */
3389 /* FIXME better way to translate setup_packet into two u32 fields? */
3390 setup = (struct usb_ctrlrequest *) urb->setup_packet;
3392 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3393 if (start_cycle == 0)
3396 /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3397 if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3398 if (urb->transfer_buffer_length > 0) {
3399 if (setup->bRequestType & USB_DIR_IN)
3400 field |= TRB_TX_TYPE(TRB_DATA_IN);
3402 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3406 queue_trb(xhci, ep_ring, true,
3407 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3408 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3409 TRB_LEN(8) | TRB_INTR_TARGET(0),
3410 /* Immediate data in pointer */
3413 /* If there's data, queue data TRBs */
3414 /* Only set interrupt on short packet for IN endpoints */
3415 if (usb_urb_dir_in(urb))
3416 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3418 field = TRB_TYPE(TRB_DATA);
3420 remainder = xhci_td_remainder(xhci, 0,
3421 urb->transfer_buffer_length,
3422 urb->transfer_buffer_length,
3425 length_field = TRB_LEN(urb->transfer_buffer_length) |
3426 TRB_TD_SIZE(remainder) |
3429 if (urb->transfer_buffer_length > 0) {
3430 if (setup->bRequestType & USB_DIR_IN)
3431 field |= TRB_DIR_IN;
3432 queue_trb(xhci, ep_ring, true,
3433 lower_32_bits(urb->transfer_dma),
3434 upper_32_bits(urb->transfer_dma),
3436 field | ep_ring->cycle_state);
3439 /* Save the DMA address of the last TRB in the TD */
3440 td->last_trb = ep_ring->enqueue;
3442 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3443 /* If the device sent data, the status stage is an OUT transfer */
3444 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3448 queue_trb(xhci, ep_ring, false,
3452 /* Event on completion */
3453 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3455 giveback_first_trb(xhci, slot_id, ep_index, 0,
3456 start_cycle, start_trb);
3461 * The transfer burst count field of the isochronous TRB defines the number of
3462 * bursts that are required to move all packets in this TD. Only SuperSpeed
3463 * devices can burst up to bMaxBurst number of packets per service interval.
3464 * This field is zero based, meaning a value of zero in the field means one
3465 * burst. Basically, for everything but SuperSpeed devices, this field will be
3466 * zero. Only xHCI 1.0 host controllers support this field.
3468 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3469 struct urb *urb, unsigned int total_packet_count)
3471 unsigned int max_burst;
3473 if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3476 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3477 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3481 * Returns the number of packets in the last "burst" of packets. This field is
3482 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3483 * the last burst packet count is equal to the total number of packets in the
3484 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3485 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3486 * contain 1 to (bMaxBurst + 1) packets.
3488 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3489 struct urb *urb, unsigned int total_packet_count)
3491 unsigned int max_burst;
3492 unsigned int residue;
3494 if (xhci->hci_version < 0x100)
3497 if (urb->dev->speed >= USB_SPEED_SUPER) {
3498 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3499 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3500 residue = total_packet_count % (max_burst + 1);
3501 /* If residue is zero, the last burst contains (max_burst + 1)
3502 * number of packets, but the TLBPC field is zero-based.
3508 if (total_packet_count == 0)
3510 return total_packet_count - 1;
3514 * Calculates Frame ID field of the isochronous TRB identifies the
3515 * target frame that the Interval associated with this Isochronous
3516 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3518 * Returns actual frame id on success, negative value on error.
3520 static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3521 struct urb *urb, int index)
3523 int start_frame, ist, ret = 0;
3524 int start_frame_id, end_frame_id, current_frame_id;
3526 if (urb->dev->speed == USB_SPEED_LOW ||
3527 urb->dev->speed == USB_SPEED_FULL)
3528 start_frame = urb->start_frame + index * urb->interval;
3530 start_frame = (urb->start_frame + index * urb->interval) >> 3;
3532 /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3534 * If bit [3] of IST is cleared to '0', software can add a TRB no
3535 * later than IST[2:0] Microframes before that TRB is scheduled to
3537 * If bit [3] of IST is set to '1', software can add a TRB no later
3538 * than IST[2:0] Frames before that TRB is scheduled to be executed.
3540 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3541 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3544 /* Software shall not schedule an Isoch TD with a Frame ID value that
3545 * is less than the Start Frame ID or greater than the End Frame ID,
3548 * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3549 * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3551 * Both the End Frame ID and Start Frame ID values are calculated
3552 * in microframes. When software determines the valid Frame ID value;
3553 * The End Frame ID value should be rounded down to the nearest Frame
3554 * boundary, and the Start Frame ID value should be rounded up to the
3555 * nearest Frame boundary.
3557 current_frame_id = readl(&xhci->run_regs->microframe_index);
3558 start_frame_id = roundup(current_frame_id + ist + 1, 8);
3559 end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3561 start_frame &= 0x7ff;
3562 start_frame_id = (start_frame_id >> 3) & 0x7ff;
3563 end_frame_id = (end_frame_id >> 3) & 0x7ff;
3565 xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3566 __func__, index, readl(&xhci->run_regs->microframe_index),
3567 start_frame_id, end_frame_id, start_frame);
3569 if (start_frame_id < end_frame_id) {
3570 if (start_frame > end_frame_id ||
3571 start_frame < start_frame_id)
3573 } else if (start_frame_id > end_frame_id) {
3574 if ((start_frame > end_frame_id &&
3575 start_frame < start_frame_id))
3582 if (ret == -EINVAL || start_frame == start_frame_id) {
3583 start_frame = start_frame_id + 1;
3584 if (urb->dev->speed == USB_SPEED_LOW ||
3585 urb->dev->speed == USB_SPEED_FULL)
3586 urb->start_frame = start_frame;
3588 urb->start_frame = start_frame << 3;
3594 xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3595 start_frame, current_frame_id, index,
3596 start_frame_id, end_frame_id);
3597 xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3604 /* This is for isoc transfer */
3605 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3606 struct urb *urb, int slot_id, unsigned int ep_index)
3608 struct xhci_ring *ep_ring;
3609 struct urb_priv *urb_priv;
3611 int num_tds, trbs_per_td;
3612 struct xhci_generic_trb *start_trb;
3615 u32 field, length_field;
3616 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3617 u64 start_addr, addr;
3619 bool more_trbs_coming;
3620 struct xhci_virt_ep *xep;
3623 xep = &xhci->devs[slot_id]->eps[ep_index];
3624 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3626 num_tds = urb->number_of_packets;
3628 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3631 start_addr = (u64) urb->transfer_dma;
3632 start_trb = &ep_ring->enqueue->generic;
3633 start_cycle = ep_ring->cycle_state;
3635 urb_priv = urb->hcpriv;
3636 /* Queue the TRBs for each TD, even if they are zero-length */
3637 for (i = 0; i < num_tds; i++) {
3638 unsigned int total_pkt_count, max_pkt;
3639 unsigned int burst_count, last_burst_pkt_count;
3644 addr = start_addr + urb->iso_frame_desc[i].offset;
3645 td_len = urb->iso_frame_desc[i].length;
3646 td_remain_len = td_len;
3647 max_pkt = GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3648 total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3650 /* A zero-length transfer still involves at least one packet. */
3651 if (total_pkt_count == 0)
3653 burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3654 last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3655 urb, total_pkt_count);
3657 trbs_per_td = count_isoc_trbs_needed(urb, i);
3659 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3660 urb->stream_id, trbs_per_td, urb, i, mem_flags);
3666 td = urb_priv->td[i];
3668 /* use SIA as default, if frame id is used overwrite it */
3669 sia_frame_id = TRB_SIA;
3670 if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3671 HCC_CFC(xhci->hcc_params)) {
3672 frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3674 sia_frame_id = TRB_FRAME_ID(frame_id);
3677 * Set isoc specific data for the first TRB in a TD.
3678 * Prevent HW from getting the TRBs by keeping the cycle state
3679 * inverted in the first TDs isoc TRB.
3681 field = TRB_TYPE(TRB_ISOC) |
3682 TRB_TLBPC(last_burst_pkt_count) |
3684 (i ? ep_ring->cycle_state : !start_cycle);
3686 /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3687 if (!xep->use_extended_tbc)
3688 field |= TRB_TBC(burst_count);
3690 /* fill the rest of the TRB fields, and remaining normal TRBs */
3691 for (j = 0; j < trbs_per_td; j++) {
3694 /* only first TRB is isoc, overwrite otherwise */
3696 field = TRB_TYPE(TRB_NORMAL) |
3697 ep_ring->cycle_state;
3699 /* Only set interrupt on short packet for IN EPs */
3700 if (usb_urb_dir_in(urb))
3703 /* Set the chain bit for all except the last TRB */
3704 if (j < trbs_per_td - 1) {
3705 more_trbs_coming = true;
3708 more_trbs_coming = false;
3709 td->last_trb = ep_ring->enqueue;
3711 /* set BEI, except for the last TD */
3712 if (xhci->hci_version >= 0x100 &&
3713 !(xhci->quirks & XHCI_AVOID_BEI) &&
3717 /* Calculate TRB length */
3718 trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3719 if (trb_buff_len > td_remain_len)
3720 trb_buff_len = td_remain_len;
3722 /* Set the TRB length, TD size, & interrupter fields. */
3723 remainder = xhci_td_remainder(xhci, running_total,
3724 trb_buff_len, td_len,
3725 urb, more_trbs_coming);
3727 length_field = TRB_LEN(trb_buff_len) |
3730 /* xhci 1.1 with ETE uses TD Size field for TBC */
3731 if (first_trb && xep->use_extended_tbc)
3732 length_field |= TRB_TD_SIZE_TBC(burst_count);
3734 length_field |= TRB_TD_SIZE(remainder);
3737 queue_trb(xhci, ep_ring, more_trbs_coming,
3738 lower_32_bits(addr),
3739 upper_32_bits(addr),
3742 running_total += trb_buff_len;
3744 addr += trb_buff_len;
3745 td_remain_len -= trb_buff_len;
3748 /* Check TD length */
3749 if (running_total != td_len) {
3750 xhci_err(xhci, "ISOC TD length unmatch\n");
3756 /* store the next frame id */
3757 if (HCC_CFC(xhci->hcc_params))
3758 xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3760 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3761 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3762 usb_amd_quirk_pll_disable();
3764 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3766 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3767 start_cycle, start_trb);
3770 /* Clean up a partially enqueued isoc transfer. */
3772 for (i--; i >= 0; i--)
3773 list_del_init(&urb_priv->td[i]->td_list);
3775 /* Use the first TD as a temporary variable to turn the TDs we've queued
3776 * into No-ops with a software-owned cycle bit. That way the hardware
3777 * won't accidentally start executing bogus TDs when we partially
3778 * overwrite them. td->first_trb and td->start_seg are already set.
3780 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3781 /* Every TRB except the first & last will have its cycle bit flipped. */
3782 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3784 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3785 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3786 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3787 ep_ring->cycle_state = start_cycle;
3788 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3789 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3794 * Check transfer ring to guarantee there is enough room for the urb.
3795 * Update ISO URB start_frame and interval.
3796 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3797 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3798 * Contiguous Frame ID is not supported by HC.
3800 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3801 struct urb *urb, int slot_id, unsigned int ep_index)
3803 struct xhci_virt_device *xdev;
3804 struct xhci_ring *ep_ring;
3805 struct xhci_ep_ctx *ep_ctx;
3807 int num_tds, num_trbs, i;
3809 struct xhci_virt_ep *xep;
3812 xdev = xhci->devs[slot_id];
3813 xep = &xhci->devs[slot_id]->eps[ep_index];
3814 ep_ring = xdev->eps[ep_index].ring;
3815 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3818 num_tds = urb->number_of_packets;
3819 for (i = 0; i < num_tds; i++)
3820 num_trbs += count_isoc_trbs_needed(urb, i);
3822 /* Check the ring to guarantee there is enough room for the whole urb.
3823 * Do not insert any td of the urb to the ring if the check failed.
3825 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3826 num_trbs, mem_flags);
3831 * Check interval value. This should be done before we start to
3832 * calculate the start frame value.
3834 check_interval(xhci, urb, ep_ctx);
3836 /* Calculate the start frame and put it in urb->start_frame. */
3837 if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3838 if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
3840 urb->start_frame = xep->next_frame_id;
3841 goto skip_start_over;
3845 start_frame = readl(&xhci->run_regs->microframe_index);
3846 start_frame &= 0x3fff;
3848 * Round up to the next frame and consider the time before trb really
3849 * gets scheduled by hardare.
3851 ist = HCS_IST(xhci->hcs_params2) & 0x7;
3852 if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3854 start_frame += ist + XHCI_CFC_DELAY;
3855 start_frame = roundup(start_frame, 8);
3858 * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3859 * is greate than 8 microframes.
3861 if (urb->dev->speed == USB_SPEED_LOW ||
3862 urb->dev->speed == USB_SPEED_FULL) {
3863 start_frame = roundup(start_frame, urb->interval << 3);
3864 urb->start_frame = start_frame >> 3;
3866 start_frame = roundup(start_frame, urb->interval);
3867 urb->start_frame = start_frame;
3871 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3873 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3876 /**** Command Ring Operations ****/
3878 /* Generic function for queueing a command TRB on the command ring.
3879 * Check to make sure there's room on the command ring for one command TRB.
3880 * Also check that there's room reserved for commands that must not fail.
3881 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3882 * then only check for the number of reserved spots.
3883 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3884 * because the command event handler may want to resubmit a failed command.
3886 static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3887 u32 field1, u32 field2,
3888 u32 field3, u32 field4, bool command_must_succeed)
3890 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3893 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3894 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3895 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3899 if (!command_must_succeed)
3902 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3903 reserved_trbs, GFP_ATOMIC);
3905 xhci_err(xhci, "ERR: No room for command on command ring\n");
3906 if (command_must_succeed)
3907 xhci_err(xhci, "ERR: Reserved TRB counting for "
3908 "unfailable commands failed.\n");
3912 cmd->command_trb = xhci->cmd_ring->enqueue;
3913 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3915 /* if there are no other commands queued we start the timeout timer */
3916 if (xhci->cmd_list.next == &cmd->cmd_list &&
3917 !timer_pending(&xhci->cmd_timer)) {
3918 xhci->current_cmd = cmd;
3919 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3922 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3923 field4 | xhci->cmd_ring->cycle_state);
3927 /* Queue a slot enable or disable request on the command ring */
3928 int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3929 u32 trb_type, u32 slot_id)
3931 return queue_command(xhci, cmd, 0, 0, 0,
3932 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3935 /* Queue an address device command TRB */
3936 int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3937 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3939 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3940 upper_32_bits(in_ctx_ptr), 0,
3941 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3942 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3945 int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3946 u32 field1, u32 field2, u32 field3, u32 field4)
3948 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3951 /* Queue a reset device command TRB */
3952 int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3955 return queue_command(xhci, cmd, 0, 0, 0,
3956 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3960 /* Queue a configure endpoint command TRB */
3961 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3962 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3963 u32 slot_id, bool command_must_succeed)
3965 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3966 upper_32_bits(in_ctx_ptr), 0,
3967 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3968 command_must_succeed);
3971 /* Queue an evaluate context command TRB */
3972 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3973 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3975 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3976 upper_32_bits(in_ctx_ptr), 0,
3977 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3978 command_must_succeed);
3982 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3983 * activity on an endpoint that is about to be suspended.
3985 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3986 int slot_id, unsigned int ep_index, int suspend)
3988 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3989 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3990 u32 type = TRB_TYPE(TRB_STOP_RING);
3991 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3993 return queue_command(xhci, cmd, 0, 0, 0,
3994 trb_slot_id | trb_ep_index | type | trb_suspend, false);
3997 /* Set Transfer Ring Dequeue Pointer command */
3998 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3999 unsigned int slot_id, unsigned int ep_index,
4000 unsigned int stream_id,
4001 struct xhci_dequeue_state *deq_state)
4004 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4005 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4006 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
4008 u32 type = TRB_TYPE(TRB_SET_DEQ);
4009 struct xhci_virt_ep *ep;
4010 struct xhci_command *cmd;
4013 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
4014 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
4015 deq_state->new_deq_seg,
4016 (unsigned long long)deq_state->new_deq_seg->dma,
4017 deq_state->new_deq_ptr,
4018 (unsigned long long)xhci_trb_virt_to_dma(
4019 deq_state->new_deq_seg, deq_state->new_deq_ptr),
4020 deq_state->new_cycle_state);
4022 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
4023 deq_state->new_deq_ptr);
4025 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4026 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
4027 deq_state->new_deq_seg, deq_state->new_deq_ptr);
4030 ep = &xhci->devs[slot_id]->eps[ep_index];
4031 if ((ep->ep_state & SET_DEQ_PENDING)) {
4032 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
4033 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
4037 /* This function gets called from contexts where it cannot sleep */
4038 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
4040 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
4044 ep->queued_deq_seg = deq_state->new_deq_seg;
4045 ep->queued_deq_ptr = deq_state->new_deq_ptr;
4047 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
4048 ret = queue_command(xhci, cmd,
4049 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
4050 upper_32_bits(addr), trb_stream_id,
4051 trb_slot_id | trb_ep_index | type, false);
4053 xhci_free_command(xhci, cmd);
4057 /* Stop the TD queueing code from ringing the doorbell until
4058 * this command completes. The HC won't set the dequeue pointer
4059 * if the ring is running, and ringing the doorbell starts the
4062 ep->ep_state |= SET_DEQ_PENDING;
4065 int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
4066 int slot_id, unsigned int ep_index)
4068 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4069 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4070 u32 type = TRB_TYPE(TRB_RESET_EP);
4072 return queue_command(xhci, cmd, 0, 0, 0,
4073 trb_slot_id | trb_ep_index | type, false);