drivers/video/exynos/exynos_dp_reg.c

   1 /*
   2  * Samsung DP (Display port) register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16
  17 #include <video/exynos_dp.h>
  18
  19 #include <plat/cpu.h>
  20
  21 #include "exynos_dp_core.h"
  22 #include "exynos_dp_reg.h"
  23
  24 #define COMMON_INT_MASK_1 (0)
  25 #define COMMON_INT_MASK_2 (0)
  26 #define COMMON_INT_MASK_3 (0)
  27 #define COMMON_INT_MASK_4 (0)
  28 #define INT_STA_MASK (0)
  29
  30 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
  31 {
  32         u32 reg;
  33
  34         if (enable) {
  35                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  36                 reg |= HDCP_VIDEO_MUTE;
  37                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  38         } else {
  39                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  40                 reg &= ~HDCP_VIDEO_MUTE;
  41                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  42         }
  43 }
  44
  45 void exynos_dp_stop_video(struct exynos_dp_device *dp)
  46 {
  47         u32 reg;
  48
  49         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  50         reg &= ~VIDEO_EN;
  51         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  52 }
  53
  54 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
  55 {
  56         u32 reg;
  57
  58         if (enable)
  59                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  60                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  61         else
  62                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  63                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  64
  65         writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
  66 }
  67
  68 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
  69 {
  70         u32 reg;
  71
  72         reg = TX_TERMINAL_CTRL_50_OHM;
  73         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
  74
  75         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  76         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
  77
  78         reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
  79         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
  80
  81         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
  82                 TX_CUR1_2X | TX_CUR_8_MA;
  83         writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
  84
  85         reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
  86                 CH1_AMP_400_MV | CH0_AMP_400_MV;
  87         writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
  88 }
  89
  90 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
  91 {
  92         /* Set interrupt pin assertion polarity as high */
  93         writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
  94
  95         /* Clear pending regisers */
  96         writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
  97         writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
  98         writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
  99         writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 100         writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
 101
 102         /* 0:mask,1: unmask */
 103         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
 104         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
 105         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
 106         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 107         writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 108 }
 109
 110 void exynos_dp_reset(struct exynos_dp_device *dp)
 111 {
 112         u32 reg;
 113
 114         writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
 115
 116         exynos_dp_stop_video(dp);
 117         exynos_dp_enable_video_mute(dp, 0);
 118
 119         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 120                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 121                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 122         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 123
 124         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 125                 SERDES_FIFO_FUNC_EN_N |
 126                 LS_CLK_DOMAIN_FUNC_EN_N;
 127         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 128
 129         udelay(20);
 130
 131         exynos_dp_lane_swap(dp, 0);
 132
 133         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 134         writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 135         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 136         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 137
 138         writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
 139         writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
 140
 141         writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
 142         writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
 143
 144         writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
 145
 146         writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
 147
 148         writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
 149         writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
 150
 151         writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
 152         writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
 153
 154         writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 155
 156         exynos_dp_init_analog_param(dp);
 157         exynos_dp_init_interrupt(dp);
 158 }
 159
 160 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
 161 {
 162         u32 reg;
 163
 164         /* 0: mask, 1: unmask */
 165         reg = COMMON_INT_MASK_1;
 166         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
 167
 168         reg = COMMON_INT_MASK_2;
 169         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
 170
 171         reg = COMMON_INT_MASK_3;
 172         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
 173
 174         reg = COMMON_INT_MASK_4;
 175         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 176
 177         reg = INT_STA_MASK;
 178         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 179 }
 180
 181 u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 182 {
 183         u32 reg;
 184
 185         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 186         if (reg & PLL_LOCK)
 187                 return PLL_LOCKED;
 188         else
 189                 return PLL_UNLOCKED;
 190 }
 191
 192 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 193 {
 194         u32 reg;
 195
 196         if (enable) {
 197                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 198                 reg |= DP_PLL_PD;
 199                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 200         } else {
 201                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 202                 reg &= ~DP_PLL_PD;
 203                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 204         }
 205 }
 206
 207 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 208                                 enum analog_power_block block,
 209                                 bool enable)
 210 {
 211         u32 reg;
 212
 213         switch (block) {
 214         case AUX_BLOCK:
 215                 if (enable) {
 216                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 217                         reg |= AUX_PD;
 218                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 219                 } else {
 220                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 221                         reg &= ~AUX_PD;
 222                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 223                 }
 224                 break;
 225         case CH0_BLOCK:
 226                 if (enable) {
 227                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 228                         reg |= CH0_PD;
 229                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 230                 } else {
 231                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 232                         reg &= ~CH0_PD;
 233                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 234                 }
 235                 break;
 236         case CH1_BLOCK:
 237                 if (enable) {
 238                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 239                         reg |= CH1_PD;
 240                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 241                 } else {
 242                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 243                         reg &= ~CH1_PD;
 244                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 245                 }
 246                 break;
 247         case CH2_BLOCK:
 248                 if (enable) {
 249                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 250                         reg |= CH2_PD;
 251                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 252                 } else {
 253                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 254                         reg &= ~CH2_PD;
 255                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 256                 }
 257                 break;
 258         case CH3_BLOCK:
 259                 if (enable) {
 260                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 261                         reg |= CH3_PD;
 262                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 263                 } else {
 264                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 265                         reg &= ~CH3_PD;
 266                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 267                 }
 268                 break;
 269         case ANALOG_TOTAL:
 270                 if (enable) {
 271                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 272                         reg |= DP_PHY_PD;
 273                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 274                 } else {
 275                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 276                         reg &= ~DP_PHY_PD;
 277                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 278                 }
 279                 break;
 280         case POWER_ALL:
 281                 if (enable) {
 282                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 283                                 CH1_PD | CH0_PD;
 284                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 285                 } else {
 286                         writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
 287                 }
 288                 break;
 289         default:
 290                 break;
 291         }
 292 }
 293
 294 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 295 {
 296         u32 reg;
 297         int timeout_loop = 0;
 298
 299         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 300
 301         reg = PLL_LOCK_CHG;
 302         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 303
 304         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 305         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 306         writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 307
 308         /* Power up PLL */
 309         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 310                 exynos_dp_set_pll_power_down(dp, 0);
 311
 312                 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 313                         timeout_loop++;
 314                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 315                                 dev_err(dp->dev, "failed to get pll lock status\n");
 316                                 return;
 317                         }
 318                         usleep_range(10, 20);
 319                 }
 320         }
 321
 322         /* Enable Serdes FIFO function and Link symbol clock domain module */
 323         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 324         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 325                 | AUX_FUNC_EN_N);
 326         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 327 }
 328
 329 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
 330 {
 331         u32 reg;
 332
 333         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 334         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 335
 336         reg = INT_HPD;
 337         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 338
 339         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 340         reg &= ~(F_HPD | HPD_CTRL);
 341         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 342 }
 343
 344 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 345 {
 346         u32 reg;
 347
 348         /* Disable AUX channel module */
 349         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 350         reg |= AUX_FUNC_EN_N;
 351         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 352 }
 353
 354 void exynos_dp_init_aux(struct exynos_dp_device *dp)
 355 {
 356         u32 reg;
 357
 358         /* Clear inerrupts related to AUX channel */
 359         reg = RPLY_RECEIV | AUX_ERR;
 360         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 361
 362         exynos_dp_reset_aux(dp);
 363
 364         /* Disable AUX transaction H/W retry */
 365         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 366                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 367         writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
 368
 369         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 370         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 371         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
 372
 373         /* Enable AUX channel module */
 374         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 375         reg &= ~AUX_FUNC_EN_N;
 376         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 377 }
 378
 379 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 380 {
 381         u32 reg;
 382
 383         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 384         if (reg & HPD_STATUS)
 385                 return 0;
 386
 387         return -EINVAL;
 388 }
 389
 390 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 391 {
 392         u32 reg;
 393
 394         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 395         reg &= ~SW_FUNC_EN_N;
 396         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 397 }
 398
 399 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 400 {
 401         int reg;
 402         int retval = 0;
 403
 404         /* Enable AUX CH operation */
 405         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 406         reg |= AUX_EN;
 407         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 408
 409         /* Is AUX CH command reply received? */
 410         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 411         while (!(reg & RPLY_RECEIV))
 412                 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 413
 414         /* Clear interrupt source for AUX CH command reply */
 415         writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
 416
 417         /* Clear interrupt source for AUX CH access error */
 418         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 419         if (reg & AUX_ERR) {
 420                 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
 421                 return -EREMOTEIO;
 422         }
 423
 424         /* Check AUX CH error access status */
 425         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
 426         if ((reg & AUX_STATUS_MASK) != 0) {
 427                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 428                         reg & AUX_STATUS_MASK);
 429                 return -EREMOTEIO;
 430         }
 431
 432         return retval;
 433 }
 434
 435 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 436                                 unsigned int reg_addr,
 437                                 unsigned char data)
 438 {
 439         u32 reg;
 440         int i;
 441         int retval;
 442
 443         for (i = 0; i < 3; i++) {
 444                 /* Clear AUX CH data buffer */
 445                 reg = BUF_CLR;
 446                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 447
 448                 /* Select DPCD device address */
 449                 reg = AUX_ADDR_7_0(reg_addr);
 450                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 451                 reg = AUX_ADDR_15_8(reg_addr);
 452                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 453                 reg = AUX_ADDR_19_16(reg_addr);
 454                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 455
 456                 /* Write data buffer */
 457                 reg = (unsigned int)data;
 458                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 459
 460                 /*
 461                  * Set DisplayPort transaction and write 1 byte
 462                  * If bit 3 is 1, DisplayPort transaction.
 463                  * If Bit 3 is 0, I2C transaction.
 464                  */
 465                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 466                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 467
 468                 /* Start AUX transaction */
 469                 retval = exynos_dp_start_aux_transaction(dp);
 470                 if (retval == 0)
 471                         break;
 472                 else
 473                         dev_err(dp->dev, "Aux Transaction fail!\n");
 474         }
 475
 476         return retval;
 477 }
 478
 479 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 480                                 unsigned int reg_addr,
 481                                 unsigned char *data)
 482 {
 483         u32 reg;
 484         int i;
 485         int retval;
 486
 487         for (i = 0; i < 10; i++) {
 488                 /* Clear AUX CH data buffer */
 489                 reg = BUF_CLR;
 490                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 491
 492                 /* Select DPCD device address */
 493                 reg = AUX_ADDR_7_0(reg_addr);
 494                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 495                 reg = AUX_ADDR_15_8(reg_addr);
 496                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 497                 reg = AUX_ADDR_19_16(reg_addr);
 498                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 499
 500                 /*
 501                  * Set DisplayPort transaction and read 1 byte
 502                  * If bit 3 is 1, DisplayPort transaction.
 503                  * If Bit 3 is 0, I2C transaction.
 504                  */
 505                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 506                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 507
 508                 /* Start AUX transaction */
 509                 retval = exynos_dp_start_aux_transaction(dp);
 510                 if (retval == 0)
 511                         break;
 512                 else
 513                         dev_err(dp->dev, "Aux Transaction fail!\n");
 514         }
 515
 516         /* Read data buffer */
 517         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 518         *data = (unsigned char)(reg & 0xff);
 519
 520         return retval;
 521 }
 522
 523 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 524                                 unsigned int reg_addr,
 525                                 unsigned int count,
 526                                 unsigned char data[])
 527 {
 528         u32 reg;
 529         unsigned int start_offset;
 530         unsigned int cur_data_count;
 531         unsigned int cur_data_idx;
 532         int i;
 533         int retval = 0;
 534
 535         /* Clear AUX CH data buffer */
 536         reg = BUF_CLR;
 537         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 538
 539         start_offset = 0;
 540         while (start_offset < count) {
 541                 /* Buffer size of AUX CH is 16 * 4bytes */
 542                 if ((count - start_offset) > 16)
 543                         cur_data_count = 16;
 544                 else
 545                         cur_data_count = count - start_offset;
 546
 547                 for (i = 0; i < 10; i++) {
 548                         /* Select DPCD device address */
 549                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 550                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 551                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 552                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 553                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 554                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 555
 556                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 557                              cur_data_idx++) {
 558                                 reg = data[start_offset + cur_data_idx];
 559                                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
 560                                                           + 4 * cur_data_idx);
 561                         }
 562
 563                         /*
 564                          * Set DisplayPort transaction and write
 565                          * If bit 3 is 1, DisplayPort transaction.
 566                          * If Bit 3 is 0, I2C transaction.
 567                          */
 568                         reg = AUX_LENGTH(cur_data_count) |
 569                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 570                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 571
 572                         /* Start AUX transaction */
 573                         retval = exynos_dp_start_aux_transaction(dp);
 574                         if (retval == 0)
 575                                 break;
 576                         else
 577                                 dev_err(dp->dev, "Aux Transaction fail!\n");
 578                 }
 579
 580                 start_offset += cur_data_count;
 581         }
 582
 583         return retval;
 584 }
 585
 586 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 587                                 unsigned int reg_addr,
 588                                 unsigned int count,
 589                                 unsigned char data[])
 590 {
 591         u32 reg;
 592         unsigned int start_offset;
 593         unsigned int cur_data_count;
 594         unsigned int cur_data_idx;
 595         int i;
 596         int retval = 0;
 597
 598         /* Clear AUX CH data buffer */
 599         reg = BUF_CLR;
 600         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 601
 602         start_offset = 0;
 603         while (start_offset < count) {
 604                 /* Buffer size of AUX CH is 16 * 4bytes */
 605                 if ((count - start_offset) > 16)
 606                         cur_data_count = 16;
 607                 else
 608                         cur_data_count = count - start_offset;
 609
 610                 /* AUX CH Request Transaction process */
 611                 for (i = 0; i < 10; i++) {
 612                         /* Select DPCD device address */
 613                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 614                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 615                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 616                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 617                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 618                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 619
 620                         /*
 621                          * Set DisplayPort transaction and read
 622                          * If bit 3 is 1, DisplayPort transaction.
 623                          * If Bit 3 is 0, I2C transaction.
 624                          */
 625                         reg = AUX_LENGTH(cur_data_count) |
 626                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 627                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 628
 629                         /* Start AUX transaction */
 630                         retval = exynos_dp_start_aux_transaction(dp);
 631                         if (retval == 0)
 632                                 break;
 633                         else
 634                                 dev_err(dp->dev, "Aux Transaction fail!\n");
 635                 }
 636
 637                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 638                     cur_data_idx++) {
 639                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 640                                                  + 4 * cur_data_idx);
 641                         data[start_offset + cur_data_idx] =
 642                                 (unsigned char)reg;
 643                 }
 644
 645                 start_offset += cur_data_count;
 646         }
 647
 648         return retval;
 649 }
 650
 651 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 652                                 unsigned int device_addr,
 653                                 unsigned int reg_addr)
 654 {
 655         u32 reg;
 656         int retval;
 657
 658         /* Set EDID device address */
 659         reg = device_addr;
 660         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 661         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 662         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 663
 664         /* Set offset from base address of EDID device */
 665         writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 666
 667         /*
 668          * Set I2C transaction and write address
 669          * If bit 3 is 1, DisplayPort transaction.
 670          * If Bit 3 is 0, I2C transaction.
 671          */
 672         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 673                 AUX_TX_COMM_WRITE;
 674         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 675
 676         /* Start AUX transaction */
 677         retval = exynos_dp_start_aux_transaction(dp);
 678         if (retval != 0)
 679                 dev_err(dp->dev, "Aux Transaction fail!\n");
 680
 681         return retval;
 682 }
 683
 684 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 685                                 unsigned int device_addr,
 686                                 unsigned int reg_addr,
 687                                 unsigned int *data)
 688 {
 689         u32 reg;
 690         int i;
 691         int retval;
 692
 693         for (i = 0; i < 10; i++) {
 694                 /* Clear AUX CH data buffer */
 695                 reg = BUF_CLR;
 696                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 697
 698                 /* Select EDID device */
 699                 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
 700                 if (retval != 0) {
 701                         dev_err(dp->dev, "Select EDID device fail!\n");
 702                         continue;
 703                 }
 704
 705                 /*
 706                  * Set I2C transaction and read data
 707                  * If bit 3 is 1, DisplayPort transaction.
 708                  * If Bit 3 is 0, I2C transaction.
 709                  */
 710                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 711                         AUX_TX_COMM_READ;
 712                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 713
 714                 /* Start AUX transaction */
 715                 retval = exynos_dp_start_aux_transaction(dp);
 716                 if (retval == 0)
 717                         break;
 718                 else
 719                         dev_err(dp->dev, "Aux Transaction fail!\n");
 720         }
 721
 722         /* Read data */
 723         if (retval == 0)
 724                 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 725
 726         return retval;
 727 }
 728
 729 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 730                                 unsigned int device_addr,
 731                                 unsigned int reg_addr,
 732                                 unsigned int count,
 733                                 unsigned char edid[])
 734 {
 735         u32 reg;
 736         unsigned int i, j;
 737         unsigned int cur_data_idx;
 738         unsigned int defer = 0;
 739         int retval = 0;
 740
 741         for (i = 0; i < count; i += 16) {
 742                 for (j = 0; j < 100; j++) {
 743                         /* Clear AUX CH data buffer */
 744                         reg = BUF_CLR;
 745                         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 746
 747                         /* Set normal AUX CH command */
 748                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 749                         reg &= ~ADDR_ONLY;
 750                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 751
 752                         /*
 753                          * If Rx sends defer, Tx sends only reads
 754                          * request without sending addres
 755                          */
 756                         if (!defer)
 757                                 retval = exynos_dp_select_i2c_device(dp,
 758                                                 device_addr, reg_addr + i);
 759                         else
 760                                 defer = 0;
 761
 762                         if (retval == 0) {
 763                                 /*
 764                                  * Set I2C transaction and write data
 765                                  * If bit 3 is 1, DisplayPort transaction.
 766                                  * If Bit 3 is 0, I2C transaction.
 767                                  */
 768                                 reg = AUX_LENGTH(16) |
 769                                         AUX_TX_COMM_I2C_TRANSACTION |
 770                                         AUX_TX_COMM_READ;
 771                                 writel(reg, dp->reg_base +
 772                                         EXYNOS_DP_AUX_CH_CTL_1);
 773
 774                                 /* Start AUX transaction */
 775                                 retval = exynos_dp_start_aux_transaction(dp);
 776                                 if (retval == 0)
 777                                         break;
 778                                 else
 779                                         dev_err(dp->dev, "Aux Transaction fail!\n");
 780                         }
 781                         /* Check if Rx sends defer */
 782                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 783                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 784                                 reg == AUX_RX_COMM_I2C_DEFER) {
 785                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 786                                 defer = 1;
 787                         }
 788                 }
 789
 790                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 791                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 792                                                  + 4 * cur_data_idx);
 793                         edid[i + cur_data_idx] = (unsigned char)reg;
 794                 }
 795         }
 796
 797         return retval;
 798 }
 799
 800 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 801 {
 802         u32 reg;
 803
 804         reg = bwtype;
 805         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 806                 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 807 }
 808
 809 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 810 {
 811         u32 reg;
 812
 813         reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 814         *bwtype = reg;
 815 }
 816
 817 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 818 {
 819         u32 reg;
 820
 821         reg = count;
 822         writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 823 }
 824
 825 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 826 {
 827         u32 reg;
 828
 829         reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 830         *count = reg;
 831 }
 832
 833 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 834 {
 835         u32 reg;
 836
 837         if (enable) {
 838                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 839                 reg |= ENHANCED;
 840                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 841         } else {
 842                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 843                 reg &= ~ENHANCED;
 844                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 845         }
 846 }
 847
 848 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 849                                  enum pattern_set pattern)
 850 {
 851         u32 reg;
 852
 853         switch (pattern) {
 854         case PRBS7:
 855                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 856                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 857                 break;
 858         case D10_2:
 859                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 860                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 861                 break;
 862         case TRAINING_PTN1:
 863                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 864                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 865                 break;
 866         case TRAINING_PTN2:
 867                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 868                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 869                 break;
 870         case DP_NONE:
 871                 reg = SCRAMBLING_ENABLE |
 872                         LINK_QUAL_PATTERN_SET_DISABLE |
 873                         SW_TRAINING_PATTERN_SET_NORMAL;
 874                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 875                 break;
 876         default:
 877                 break;
 878         }
 879 }
 880
 881 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 882 {
 883         u32 reg;
 884
 885         reg = level << PRE_EMPHASIS_SET_SHIFT;
 886         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 887 }
 888
 889 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 890 {
 891         u32 reg;
 892
 893         reg = level << PRE_EMPHASIS_SET_SHIFT;
 894         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 895 }
 896
 897 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 898 {
 899         u32 reg;
 900
 901         reg = level << PRE_EMPHASIS_SET_SHIFT;
 902         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 903 }
 904
 905 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 906 {
 907         u32 reg;
 908
 909         reg = level << PRE_EMPHASIS_SET_SHIFT;
 910         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 911 }
 912
 913 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 914                                         u32 training_lane)
 915 {
 916         u32 reg;
 917
 918         reg = training_lane;
 919         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 920 }
 921
 922 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 923                                         u32 training_lane)
 924 {
 925         u32 reg;
 926
 927         reg = training_lane;
 928         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 929 }
 930
 931 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 932                                         u32 training_lane)
 933 {
 934         u32 reg;
 935
 936         reg = training_lane;
 937         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 938 }
 939
 940 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 941                                         u32 training_lane)
 942 {
 943         u32 reg;
 944
 945         reg = training_lane;
 946         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 947 }
 948
 949 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 950 {
 951         u32 reg;
 952
 953         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 954         return reg;
 955 }
 956
 957 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
 958 {
 959         u32 reg;
 960
 961         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 962         return reg;
 963 }
 964
 965 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
 966 {
 967         u32 reg;
 968
 969         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 970         return reg;
 971 }
 972
 973 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
 974 {
 975         u32 reg;
 976
 977         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 978         return reg;
 979 }
 980
 981 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
 982 {
 983         u32 reg;
 984
 985         reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
 986         reg |= MACRO_RST;
 987         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 988
 989         /* 10 us is the minimum reset time. */
 990         udelay(10);
 991
 992         reg &= ~MACRO_RST;
 993         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 994 }
 995
 996 int exynos_dp_init_video(struct exynos_dp_device *dp)
 997 {
 998         u32 reg;
 999
1000         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1001         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1002
1003         reg = 0x0;
1004         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1005
1006         reg = CHA_CRI(4) | CHA_CTRL;
1007         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1008
1009         reg = 0x0;
1010         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1011
1012         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1013         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1014
1015         return 0;
1016 }
1017
1018 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
1019                         u32 color_depth,
1020                         u32 color_space,
1021                         u32 dynamic_range,
1022                         u32 ycbcr_coeff)
1023 {
1024         u32 reg;
1025
1026         /* Configure the input color depth, color space, dynamic range */
1027         reg = (dynamic_range << IN_D_RANGE_SHIFT) |
1028                 (color_depth << IN_BPC_SHIFT) |
1029                 (color_space << IN_COLOR_F_SHIFT);
1030         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1031
1032         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1033         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1034         reg &= ~IN_YC_COEFFI_MASK;
1035         if (ycbcr_coeff)
1036                 reg |= IN_YC_COEFFI_ITU709;
1037         else
1038                 reg |= IN_YC_COEFFI_ITU601;
1039         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1040 }
1041
1042 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1043 {
1044         u32 reg;
1045
1046         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1047         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1048
1049         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1050
1051         if (!(reg & DET_STA)) {
1052                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1053                 return -EINVAL;
1054         }
1055
1056         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1057         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1058
1059         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1060         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1061
1062         if (reg & CHA_STA) {
1063                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1064                 return -EINVAL;
1065         }
1066
1067         return 0;
1068 }
1069
1070 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1071                 enum clock_recovery_m_value_type type,
1072                 u32 m_value,
1073                 u32 n_value)
1074 {
1075         u32 reg;
1076
1077         if (type == REGISTER_M) {
1078                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1079                 reg |= FIX_M_VID;
1080                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1081                 reg = m_value & 0xff;
1082                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1083                 reg = (m_value >> 8) & 0xff;
1084                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1085                 reg = (m_value >> 16) & 0xff;
1086                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1087
1088                 reg = n_value & 0xff;
1089                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1090                 reg = (n_value >> 8) & 0xff;
1091                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1092                 reg = (n_value >> 16) & 0xff;
1093                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1094         } else  {
1095                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1096                 reg &= ~FIX_M_VID;
1097                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1098
1099                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1100                 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1101                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1102         }
1103 }
1104
1105 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1106 {
1107         u32 reg;
1108
1109         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1110                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1111                 reg &= ~FORMAT_SEL;
1112                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1113         } else {
1114                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1115                 reg |= FORMAT_SEL;
1116                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1117         }
1118 }
1119
1120 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1121 {
1122         u32 reg;
1123
1124         if (enable) {
1125                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1126                 reg &= ~VIDEO_MODE_MASK;
1127                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1128                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1129         } else {
1130                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1131                 reg &= ~VIDEO_MODE_MASK;
1132                 reg |= VIDEO_MODE_SLAVE_MODE;
1133                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1134         }
1135 }
1136
1137 void exynos_dp_start_video(struct exynos_dp_device *dp)
1138 {
1139         u32 reg;
1140
1141         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1142         reg |= VIDEO_EN;
1143         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1144 }
1145
1146 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1147 {
1148         u32 reg;
1149
1150         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1151         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1152
1153         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1154         if (!(reg & STRM_VALID)) {
1155                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1156                 return -EINVAL;
1157         }
1158
1159         return 0;
1160 }
1161
1162 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1163                         struct video_info *video_info)
1164 {
1165         u32 reg;
1166
1167         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1168         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1169         reg |= MASTER_VID_FUNC_EN_N;
1170         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1171
1172         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1173         reg &= ~INTERACE_SCAN_CFG;
1174         reg |= (video_info->interlaced << 2);
1175         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1176
1177         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1178         reg &= ~VSYNC_POLARITY_CFG;
1179         reg |= (video_info->v_sync_polarity << 1);
1180         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1181
1182         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1183         reg &= ~HSYNC_POLARITY_CFG;
1184         reg |= (video_info->h_sync_polarity << 0);
1185         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1186
1187         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1188         writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1189 }
1190
1191 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1192 {
1193         u32 reg;
1194
1195         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1196         reg &= ~SCRAMBLING_DISABLE;
1197         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1198 }
1199
1200 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1201 {
1202         u32 reg;
1203
1204         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1205         reg |= SCRAMBLING_DISABLE;
1206         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1207 }