2 * Samsung DP (Display port) register interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <video/exynos_dp.h>
21 #include "exynos_dp_core.h"
22 #include "exynos_dp_reg.h"
24 #define COMMON_INT_MASK_1 (0)
25 #define COMMON_INT_MASK_2 (0)
26 #define COMMON_INT_MASK_3 (0)
27 #define COMMON_INT_MASK_4 (0)
28 #define INT_STA_MASK (0)
30 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
35 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
36 reg |= HDCP_VIDEO_MUTE;
37 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
39 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
40 reg &= ~HDCP_VIDEO_MUTE;
41 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
45 void exynos_dp_stop_video(struct exynos_dp_device *dp)
49 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
51 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
54 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
59 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
60 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
62 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
63 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
65 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
68 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
70 /* Set interrupt pin assertion polarity as high */
71 writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
73 /* Clear pending regisers */
74 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
75 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
76 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
77 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
78 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
80 /* 0:mask,1: unmask */
81 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
82 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
83 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
84 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
85 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
88 void exynos_dp_reset(struct exynos_dp_device *dp)
92 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
94 exynos_dp_stop_video(dp);
95 exynos_dp_enable_video_mute(dp, 0);
97 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
98 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
99 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
100 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
102 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
103 SERDES_FIFO_FUNC_EN_N |
104 LS_CLK_DOMAIN_FUNC_EN_N;
105 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
109 exynos_dp_lane_swap(dp, 0);
111 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
112 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
113 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
114 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
116 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
117 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
119 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
120 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
122 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
124 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
126 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
127 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
129 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
130 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
132 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
134 exynos_dp_init_interrupt(dp);
137 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
141 /* 0: mask, 1: unmask */
142 reg = COMMON_INT_MASK_1;
143 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
145 reg = COMMON_INT_MASK_2;
146 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
148 reg = COMMON_INT_MASK_3;
149 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
151 reg = COMMON_INT_MASK_4;
152 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
155 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
158 u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
162 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
169 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
174 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
176 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
178 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
180 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
184 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
185 enum analog_power_block block,
193 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
195 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
197 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
199 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
204 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
206 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
208 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
210 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
215 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
217 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
219 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
221 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
226 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
228 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
230 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
232 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
237 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
239 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
241 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
243 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
248 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
250 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
252 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
254 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
259 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
261 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
263 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
271 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
275 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
278 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
280 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
281 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
282 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
285 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED)
286 exynos_dp_set_pll_power_down(dp, 0);
288 /* Enable Serdes FIFO function and Link symbol clock domain module */
289 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
290 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
292 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
295 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
299 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
300 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
303 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
305 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
306 reg &= ~(F_HPD | HPD_CTRL);
307 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
310 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
314 /* Disable AUX channel module */
315 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
316 reg |= AUX_FUNC_EN_N;
317 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
320 void exynos_dp_init_aux(struct exynos_dp_device *dp)
324 /* Clear inerrupts related to AUX channel */
325 reg = RPLY_RECEIV | AUX_ERR;
326 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
328 exynos_dp_reset_aux(dp);
330 /* Disable AUX transaction H/W retry */
331 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
332 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
333 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
335 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
336 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
337 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
339 /* Enable AUX channel module */
340 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
341 reg &= ~AUX_FUNC_EN_N;
342 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
345 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
349 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
350 if (reg & HPD_STATUS)
356 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
360 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
361 reg &= ~SW_FUNC_EN_N;
362 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
365 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
370 /* Enable AUX CH operation */
371 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
373 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
375 /* Is AUX CH command reply received? */
376 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
377 while (!(reg & RPLY_RECEIV))
378 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
380 /* Clear interrupt source for AUX CH command reply */
381 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
383 /* Clear interrupt source for AUX CH access error */
384 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
386 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
390 /* Check AUX CH error access status */
391 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
392 if ((reg & AUX_STATUS_MASK) != 0) {
393 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
394 reg & AUX_STATUS_MASK);
401 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
402 unsigned int reg_addr,
409 for (i = 0; i < 3; i++) {
410 /* Clear AUX CH data buffer */
412 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
414 /* Select DPCD device address */
415 reg = AUX_ADDR_7_0(reg_addr);
416 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
417 reg = AUX_ADDR_15_8(reg_addr);
418 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
419 reg = AUX_ADDR_19_16(reg_addr);
420 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
422 /* Write data buffer */
423 reg = (unsigned int)data;
424 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
427 * Set DisplayPort transaction and write 1 byte
428 * If bit 3 is 1, DisplayPort transaction.
429 * If Bit 3 is 0, I2C transaction.
431 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
432 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
434 /* Start AUX transaction */
435 retval = exynos_dp_start_aux_transaction(dp);
439 dev_err(dp->dev, "Aux Transaction fail!\n");
445 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
446 unsigned int reg_addr,
453 for (i = 0; i < 10; i++) {
454 /* Clear AUX CH data buffer */
456 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
458 /* Select DPCD device address */
459 reg = AUX_ADDR_7_0(reg_addr);
460 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
461 reg = AUX_ADDR_15_8(reg_addr);
462 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
463 reg = AUX_ADDR_19_16(reg_addr);
464 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
467 * Set DisplayPort transaction and read 1 byte
468 * If bit 3 is 1, DisplayPort transaction.
469 * If Bit 3 is 0, I2C transaction.
471 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
472 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
474 /* Start AUX transaction */
475 retval = exynos_dp_start_aux_transaction(dp);
479 dev_err(dp->dev, "Aux Transaction fail!\n");
482 /* Read data buffer */
483 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
484 *data = (unsigned char)(reg & 0xff);
489 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
490 unsigned int reg_addr,
492 unsigned char data[])
495 unsigned int start_offset;
496 unsigned int cur_data_count;
497 unsigned int cur_data_idx;
501 /* Clear AUX CH data buffer */
503 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
506 while (start_offset < count) {
507 /* Buffer size of AUX CH is 16 * 4bytes */
508 if ((count - start_offset) > 16)
511 cur_data_count = count - start_offset;
513 for (i = 0; i < 10; i++) {
514 /* Select DPCD device address */
515 reg = AUX_ADDR_7_0(reg_addr + start_offset);
516 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
517 reg = AUX_ADDR_15_8(reg_addr + start_offset);
518 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
519 reg = AUX_ADDR_19_16(reg_addr + start_offset);
520 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
522 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
524 reg = data[start_offset + cur_data_idx];
525 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
530 * Set DisplayPort transaction and write
531 * If bit 3 is 1, DisplayPort transaction.
532 * If Bit 3 is 0, I2C transaction.
534 reg = AUX_LENGTH(cur_data_count) |
535 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
536 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
538 /* Start AUX transaction */
539 retval = exynos_dp_start_aux_transaction(dp);
543 dev_err(dp->dev, "Aux Transaction fail!\n");
546 start_offset += cur_data_count;
552 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
553 unsigned int reg_addr,
555 unsigned char data[])
558 unsigned int start_offset;
559 unsigned int cur_data_count;
560 unsigned int cur_data_idx;
564 /* Clear AUX CH data buffer */
566 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
569 while (start_offset < count) {
570 /* Buffer size of AUX CH is 16 * 4bytes */
571 if ((count - start_offset) > 16)
574 cur_data_count = count - start_offset;
576 /* AUX CH Request Transaction process */
577 for (i = 0; i < 10; i++) {
578 /* Select DPCD device address */
579 reg = AUX_ADDR_7_0(reg_addr + start_offset);
580 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
581 reg = AUX_ADDR_15_8(reg_addr + start_offset);
582 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
583 reg = AUX_ADDR_19_16(reg_addr + start_offset);
584 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
587 * Set DisplayPort transaction and read
588 * If bit 3 is 1, DisplayPort transaction.
589 * If Bit 3 is 0, I2C transaction.
591 reg = AUX_LENGTH(cur_data_count) |
592 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
593 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
595 /* Start AUX transaction */
596 retval = exynos_dp_start_aux_transaction(dp);
600 dev_err(dp->dev, "Aux Transaction fail!\n");
603 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
605 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
607 data[start_offset + cur_data_idx] =
611 start_offset += cur_data_count;
617 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
618 unsigned int device_addr,
619 unsigned int reg_addr)
624 /* Set EDID device address */
626 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
627 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
628 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
630 /* Set offset from base address of EDID device */
631 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
634 * Set I2C transaction and write address
635 * If bit 3 is 1, DisplayPort transaction.
636 * If Bit 3 is 0, I2C transaction.
638 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
640 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
642 /* Start AUX transaction */
643 retval = exynos_dp_start_aux_transaction(dp);
645 dev_err(dp->dev, "Aux Transaction fail!\n");
650 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
651 unsigned int device_addr,
652 unsigned int reg_addr,
659 for (i = 0; i < 10; i++) {
660 /* Clear AUX CH data buffer */
662 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
664 /* Select EDID device */
665 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
667 dev_err(dp->dev, "Select EDID device fail!\n");
672 * Set I2C transaction and read data
673 * If bit 3 is 1, DisplayPort transaction.
674 * If Bit 3 is 0, I2C transaction.
676 reg = AUX_TX_COMM_I2C_TRANSACTION |
678 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
680 /* Start AUX transaction */
681 retval = exynos_dp_start_aux_transaction(dp);
685 dev_err(dp->dev, "Aux Transaction fail!\n");
690 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
695 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
696 unsigned int device_addr,
697 unsigned int reg_addr,
699 unsigned char edid[])
703 unsigned int cur_data_idx;
704 unsigned int defer = 0;
707 for (i = 0; i < count; i += 16) {
708 for (j = 0; j < 100; j++) {
709 /* Clear AUX CH data buffer */
711 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
713 /* Set normal AUX CH command */
714 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
716 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
719 * If Rx sends defer, Tx sends only reads
720 * request without sending addres
723 retval = exynos_dp_select_i2c_device(dp,
724 device_addr, reg_addr + i);
730 * Set I2C transaction and write data
731 * If bit 3 is 1, DisplayPort transaction.
732 * If Bit 3 is 0, I2C transaction.
734 reg = AUX_LENGTH(16) |
735 AUX_TX_COMM_I2C_TRANSACTION |
737 writel(reg, dp->reg_base +
738 EXYNOS_DP_AUX_CH_CTL_1);
740 /* Start AUX transaction */
741 retval = exynos_dp_start_aux_transaction(dp);
745 dev_err(dp->dev, "Aux Transaction fail!\n");
747 /* Check if Rx sends defer */
748 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
749 if (reg == AUX_RX_COMM_AUX_DEFER ||
750 reg == AUX_RX_COMM_I2C_DEFER) {
751 dev_err(dp->dev, "Defer: %d\n\n", reg);
756 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
757 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
759 edid[i + cur_data_idx] = (unsigned char)reg;
766 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
771 if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
772 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
775 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
779 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
783 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
788 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
791 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
795 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
799 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
804 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
806 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
808 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
810 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
814 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
815 enum pattern_set pattern)
821 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
822 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
825 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
826 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
829 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
830 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
833 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
834 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
837 reg = SCRAMBLING_ENABLE |
838 LINK_QUAL_PATTERN_SET_DISABLE |
839 SW_TRAINING_PATTERN_SET_NORMAL;
840 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
847 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
851 reg = level << PRE_EMPHASIS_SET_SHIFT;
852 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
855 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
859 reg = level << PRE_EMPHASIS_SET_SHIFT;
860 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
863 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
867 reg = level << PRE_EMPHASIS_SET_SHIFT;
868 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
871 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
875 reg = level << PRE_EMPHASIS_SET_SHIFT;
876 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
879 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
885 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
888 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
894 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
897 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
903 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
906 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
912 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
915 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
919 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
923 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
927 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
931 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
935 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
939 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
943 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
947 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
951 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
953 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
955 /* 10 us is the minimum reset time. */
959 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
962 int exynos_dp_init_video(struct exynos_dp_device *dp)
966 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
967 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
970 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
972 reg = CHA_CRI(4) | CHA_CTRL;
973 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
976 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
978 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
979 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
984 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
992 /* Configure the input color depth, color space, dynamic range */
993 reg = (dynamic_range << IN_D_RANGE_SHIFT) |
994 (color_depth << IN_BPC_SHIFT) |
995 (color_space << IN_COLOR_F_SHIFT);
996 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
998 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
999 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1000 reg &= ~IN_YC_COEFFI_MASK;
1002 reg |= IN_YC_COEFFI_ITU709;
1004 reg |= IN_YC_COEFFI_ITU601;
1005 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1008 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1012 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1013 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1015 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1017 if (!(reg & DET_STA)) {
1018 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1022 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1023 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1025 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1026 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1028 if (reg & CHA_STA) {
1029 dev_dbg(dp->dev, "Input stream clk is changing\n");
1036 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1037 enum clock_recovery_m_value_type type,
1043 if (type == REGISTER_M) {
1044 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1046 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1047 reg = m_value & 0xff;
1048 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1049 reg = (m_value >> 8) & 0xff;
1050 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1051 reg = (m_value >> 16) & 0xff;
1052 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1054 reg = n_value & 0xff;
1055 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1056 reg = (n_value >> 8) & 0xff;
1057 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1058 reg = (n_value >> 16) & 0xff;
1059 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1061 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1063 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1065 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1066 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1067 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1071 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1075 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1076 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1078 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1080 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1082 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1086 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1091 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1092 reg &= ~VIDEO_MODE_MASK;
1093 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1094 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1096 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1097 reg &= ~VIDEO_MODE_MASK;
1098 reg |= VIDEO_MODE_SLAVE_MODE;
1099 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1103 void exynos_dp_start_video(struct exynos_dp_device *dp)
1107 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1109 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1112 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1116 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1117 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1119 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1120 if (!(reg & STRM_VALID)) {
1121 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1128 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1129 struct video_info *video_info)
1133 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1134 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1135 reg |= MASTER_VID_FUNC_EN_N;
1136 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1138 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1139 reg &= ~INTERACE_SCAN_CFG;
1140 reg |= (video_info->interlaced << 2);
1141 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1143 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1144 reg &= ~VSYNC_POLARITY_CFG;
1145 reg |= (video_info->v_sync_polarity << 1);
1146 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1148 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1149 reg &= ~HSYNC_POLARITY_CFG;
1150 reg |= (video_info->h_sync_polarity << 0);
1151 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1153 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1154 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1157 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1161 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1162 reg &= ~SCRAMBLING_DISABLE;
1163 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1166 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1170 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1171 reg |= SCRAMBLING_DISABLE;
1172 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);