drivers/video/exynos/exynos_dp_reg.c

   1 /*
   2  * Samsung DP (Display port) register interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/device.h>
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16
  17 #include <video/exynos_dp.h>
  18
  19 #include "exynos_dp_core.h"
  20 #include "exynos_dp_reg.h"
  21
  22 #define COMMON_INT_MASK_1 (0)
  23 #define COMMON_INT_MASK_2 (0)
  24 #define COMMON_INT_MASK_3 (0)
  25 #define COMMON_INT_MASK_4 (0)
  26 #define INT_STA_MASK (0)
  27
  28 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
  29 {
  30         u32 reg;
  31
  32         if (enable) {
  33                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  34                 reg |= HDCP_VIDEO_MUTE;
  35                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  36         } else {
  37                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  38                 reg &= ~HDCP_VIDEO_MUTE;
  39                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  40         }
  41 }
  42
  43 void exynos_dp_stop_video(struct exynos_dp_device *dp)
  44 {
  45         u32 reg;
  46
  47         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  48         reg &= ~VIDEO_EN;
  49         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
  50 }
  51
  52 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
  53 {
  54         u32 reg;
  55
  56         if (enable)
  57                 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  58                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  59         else
  60                 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  61                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  62
  63         writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
  64 }
  65
  66 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
  67 {
  68         u32 reg;
  69
  70         reg = TX_TERMINAL_CTRL_50_OHM;
  71         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
  72
  73         reg = SEL_24M | TX_DVDD_BIT_1_0625V;
  74         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
  75
  76         reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
  77         writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
  78
  79         reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
  80                 TX_CUR1_2X | TX_CUR_8_MA;
  81         writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
  82
  83         reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
  84                 CH1_AMP_400_MV | CH0_AMP_400_MV;
  85         writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
  86 }
  87
  88 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
  89 {
  90         /* Set interrupt pin assertion polarity as high */
  91         writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
  92
  93         /* Clear pending regisers */
  94         writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
  95         writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
  96         writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
  97         writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
  98         writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
  99
 100         /* 0:mask,1: unmask */
 101         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
 102         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
 103         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
 104         writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 105         writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 106 }
 107
 108 void exynos_dp_reset(struct exynos_dp_device *dp)
 109 {
 110         u32 reg;
 111
 112         exynos_dp_stop_video(dp);
 113         exynos_dp_enable_video_mute(dp, 0);
 114
 115         reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 116                 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 117                 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 118         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 119
 120         reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 121                 SERDES_FIFO_FUNC_EN_N |
 122                 LS_CLK_DOMAIN_FUNC_EN_N;
 123         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 124
 125         udelay(20);
 126
 127         exynos_dp_lane_swap(dp, 0);
 128
 129         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 130         writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
 131         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 132         writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 133
 134         writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
 135         writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
 136
 137         writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
 138         writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
 139
 140         writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
 141
 142         writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
 143
 144         writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
 145         writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
 146
 147         writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
 148         writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
 149
 150         writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 151
 152         exynos_dp_init_analog_param(dp);
 153         exynos_dp_init_interrupt(dp);
 154 }
 155
 156 void exynos_dp_swreset(struct exynos_dp_device *dp)
 157 {
 158         writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
 159 }
 160
 161 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
 162 {
 163         u32 reg;
 164
 165         /* 0: mask, 1: unmask */
 166         reg = COMMON_INT_MASK_1;
 167         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
 168
 169         reg = COMMON_INT_MASK_2;
 170         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
 171
 172         reg = COMMON_INT_MASK_3;
 173         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
 174
 175         reg = COMMON_INT_MASK_4;
 176         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
 177
 178         reg = INT_STA_MASK;
 179         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 180 }
 181
 182 u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 183 {
 184         u32 reg;
 185
 186         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 187         if (reg & PLL_LOCK)
 188                 return PLL_LOCKED;
 189         else
 190                 return PLL_UNLOCKED;
 191 }
 192
 193 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 194 {
 195         u32 reg;
 196
 197         if (enable) {
 198                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 199                 reg |= DP_PLL_PD;
 200                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 201         } else {
 202                 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
 203                 reg &= ~DP_PLL_PD;
 204                 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
 205         }
 206 }
 207
 208 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 209                                 enum analog_power_block block,
 210                                 bool enable)
 211 {
 212         u32 reg;
 213
 214         switch (block) {
 215         case AUX_BLOCK:
 216                 if (enable) {
 217                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 218                         reg |= AUX_PD;
 219                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 220                 } else {
 221                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 222                         reg &= ~AUX_PD;
 223                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 224                 }
 225                 break;
 226         case CH0_BLOCK:
 227                 if (enable) {
 228                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 229                         reg |= CH0_PD;
 230                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 231                 } else {
 232                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 233                         reg &= ~CH0_PD;
 234                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 235                 }
 236                 break;
 237         case CH1_BLOCK:
 238                 if (enable) {
 239                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 240                         reg |= CH1_PD;
 241                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 242                 } else {
 243                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 244                         reg &= ~CH1_PD;
 245                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 246                 }
 247                 break;
 248         case CH2_BLOCK:
 249                 if (enable) {
 250                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 251                         reg |= CH2_PD;
 252                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 253                 } else {
 254                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 255                         reg &= ~CH2_PD;
 256                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 257                 }
 258                 break;
 259         case CH3_BLOCK:
 260                 if (enable) {
 261                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 262                         reg |= CH3_PD;
 263                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 264                 } else {
 265                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 266                         reg &= ~CH3_PD;
 267                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 268                 }
 269                 break;
 270         case ANALOG_TOTAL:
 271                 if (enable) {
 272                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 273                         reg |= DP_PHY_PD;
 274                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 275                 } else {
 276                         reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
 277                         reg &= ~DP_PHY_PD;
 278                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 279                 }
 280                 break;
 281         case POWER_ALL:
 282                 if (enable) {
 283                         reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 284                                 CH1_PD | CH0_PD;
 285                         writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
 286                 } else {
 287                         writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
 288                 }
 289                 break;
 290         default:
 291                 break;
 292         }
 293 }
 294
 295 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 296 {
 297         u32 reg;
 298         int timeout_loop = 0;
 299
 300         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 301
 302         reg = PLL_LOCK_CHG;
 303         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
 304
 305         reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 306         reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 307         writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 308
 309         /* Power up PLL */
 310         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 311                 exynos_dp_set_pll_power_down(dp, 0);
 312
 313                 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 314                         timeout_loop++;
 315                         if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 316                                 dev_err(dp->dev, "failed to get pll lock status\n");
 317                                 return;
 318                         }
 319                         usleep_range(10, 20);
 320                 }
 321         }
 322
 323         /* Enable Serdes FIFO function and Link symbol clock domain module */
 324         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 325         reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 326                 | AUX_FUNC_EN_N);
 327         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 328 }
 329
 330 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
 331 {
 332         u32 reg;
 333
 334         reg = HOTPLUG_CHG | HPD_LOST | PLUG;
 335         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
 336
 337         reg = INT_HPD;
 338         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 339
 340         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 341         reg &= ~(F_HPD | HPD_CTRL);
 342         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 343 }
 344
 345 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 346 {
 347         u32 reg;
 348
 349         /* Disable AUX channel module */
 350         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 351         reg |= AUX_FUNC_EN_N;
 352         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 353 }
 354
 355 void exynos_dp_init_aux(struct exynos_dp_device *dp)
 356 {
 357         u32 reg;
 358
 359         /* Clear inerrupts related to AUX channel */
 360         reg = RPLY_RECEIV | AUX_ERR;
 361         writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 362
 363         exynos_dp_reset_aux(dp);
 364
 365         /* Disable AUX transaction H/W retry */
 366         reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 367                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 368         writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
 369
 370         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 371         reg = DEFER_CTRL_EN | DEFER_COUNT(1);
 372         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
 373
 374         /* Enable AUX channel module */
 375         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 376         reg &= ~AUX_FUNC_EN_N;
 377         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 378 }
 379
 380 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 381 {
 382         u32 reg;
 383
 384         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 385         if (reg & HPD_STATUS)
 386                 return 0;
 387
 388         return -EINVAL;
 389 }
 390
 391 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 392 {
 393         u32 reg;
 394
 395         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 396         reg &= ~SW_FUNC_EN_N;
 397         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 398 }
 399
 400 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 401 {
 402         int reg;
 403         int retval = 0;
 404
 405         /* Enable AUX CH operation */
 406         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 407         reg |= AUX_EN;
 408         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 409
 410         /* Is AUX CH command reply received? */
 411         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 412         while (!(reg & RPLY_RECEIV))
 413                 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 414
 415         /* Clear interrupt source for AUX CH command reply */
 416         writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
 417
 418         /* Clear interrupt source for AUX CH access error */
 419         reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
 420         if (reg & AUX_ERR) {
 421                 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
 422                 return -EREMOTEIO;
 423         }
 424
 425         /* Check AUX CH error access status */
 426         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
 427         if ((reg & AUX_STATUS_MASK) != 0) {
 428                 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 429                         reg & AUX_STATUS_MASK);
 430                 return -EREMOTEIO;
 431         }
 432
 433         return retval;
 434 }
 435
 436 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 437                                 unsigned int reg_addr,
 438                                 unsigned char data)
 439 {
 440         u32 reg;
 441         int i;
 442         int retval;
 443
 444         for (i = 0; i < 3; i++) {
 445                 /* Clear AUX CH data buffer */
 446                 reg = BUF_CLR;
 447                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 448
 449                 /* Select DPCD device address */
 450                 reg = AUX_ADDR_7_0(reg_addr);
 451                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 452                 reg = AUX_ADDR_15_8(reg_addr);
 453                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 454                 reg = AUX_ADDR_19_16(reg_addr);
 455                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 456
 457                 /* Write data buffer */
 458                 reg = (unsigned int)data;
 459                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 460
 461                 /*
 462                  * Set DisplayPort transaction and write 1 byte
 463                  * If bit 3 is 1, DisplayPort transaction.
 464                  * If Bit 3 is 0, I2C transaction.
 465                  */
 466                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 467                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 468
 469                 /* Start AUX transaction */
 470                 retval = exynos_dp_start_aux_transaction(dp);
 471                 if (retval == 0)
 472                         break;
 473                 else
 474                         dev_err(dp->dev, "Aux Transaction fail!\n");
 475         }
 476
 477         return retval;
 478 }
 479
 480 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 481                                 unsigned int reg_addr,
 482                                 unsigned char *data)
 483 {
 484         u32 reg;
 485         int i;
 486         int retval;
 487
 488         for (i = 0; i < 10; i++) {
 489                 /* Clear AUX CH data buffer */
 490                 reg = BUF_CLR;
 491                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 492
 493                 /* Select DPCD device address */
 494                 reg = AUX_ADDR_7_0(reg_addr);
 495                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 496                 reg = AUX_ADDR_15_8(reg_addr);
 497                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 498                 reg = AUX_ADDR_19_16(reg_addr);
 499                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 500
 501                 /*
 502                  * Set DisplayPort transaction and read 1 byte
 503                  * If bit 3 is 1, DisplayPort transaction.
 504                  * If Bit 3 is 0, I2C transaction.
 505                  */
 506                 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 507                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 508
 509                 /* Start AUX transaction */
 510                 retval = exynos_dp_start_aux_transaction(dp);
 511                 if (retval == 0)
 512                         break;
 513                 else
 514                         dev_err(dp->dev, "Aux Transaction fail!\n");
 515         }
 516
 517         /* Read data buffer */
 518         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 519         *data = (unsigned char)(reg & 0xff);
 520
 521         return retval;
 522 }
 523
 524 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 525                                 unsigned int reg_addr,
 526                                 unsigned int count,
 527                                 unsigned char data[])
 528 {
 529         u32 reg;
 530         unsigned int start_offset;
 531         unsigned int cur_data_count;
 532         unsigned int cur_data_idx;
 533         int i;
 534         int retval = 0;
 535
 536         /* Clear AUX CH data buffer */
 537         reg = BUF_CLR;
 538         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 539
 540         start_offset = 0;
 541         while (start_offset < count) {
 542                 /* Buffer size of AUX CH is 16 * 4bytes */
 543                 if ((count - start_offset) > 16)
 544                         cur_data_count = 16;
 545                 else
 546                         cur_data_count = count - start_offset;
 547
 548                 for (i = 0; i < 10; i++) {
 549                         /* Select DPCD device address */
 550                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 551                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 552                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 553                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 554                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 555                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 556
 557                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 558                              cur_data_idx++) {
 559                                 reg = data[start_offset + cur_data_idx];
 560                                 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
 561                                                           + 4 * cur_data_idx);
 562                         }
 563
 564                         /*
 565                          * Set DisplayPort transaction and write
 566                          * If bit 3 is 1, DisplayPort transaction.
 567                          * If Bit 3 is 0, I2C transaction.
 568                          */
 569                         reg = AUX_LENGTH(cur_data_count) |
 570                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 571                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 572
 573                         /* Start AUX transaction */
 574                         retval = exynos_dp_start_aux_transaction(dp);
 575                         if (retval == 0)
 576                                 break;
 577                         else
 578                                 dev_err(dp->dev, "Aux Transaction fail!\n");
 579                 }
 580
 581                 start_offset += cur_data_count;
 582         }
 583
 584         return retval;
 585 }
 586
 587 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 588                                 unsigned int reg_addr,
 589                                 unsigned int count,
 590                                 unsigned char data[])
 591 {
 592         u32 reg;
 593         unsigned int start_offset;
 594         unsigned int cur_data_count;
 595         unsigned int cur_data_idx;
 596         int i;
 597         int retval = 0;
 598
 599         /* Clear AUX CH data buffer */
 600         reg = BUF_CLR;
 601         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 602
 603         start_offset = 0;
 604         while (start_offset < count) {
 605                 /* Buffer size of AUX CH is 16 * 4bytes */
 606                 if ((count - start_offset) > 16)
 607                         cur_data_count = 16;
 608                 else
 609                         cur_data_count = count - start_offset;
 610
 611                 /* AUX CH Request Transaction process */
 612                 for (i = 0; i < 10; i++) {
 613                         /* Select DPCD device address */
 614                         reg = AUX_ADDR_7_0(reg_addr + start_offset);
 615                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 616                         reg = AUX_ADDR_15_8(reg_addr + start_offset);
 617                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 618                         reg = AUX_ADDR_19_16(reg_addr + start_offset);
 619                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 620
 621                         /*
 622                          * Set DisplayPort transaction and read
 623                          * If bit 3 is 1, DisplayPort transaction.
 624                          * If Bit 3 is 0, I2C transaction.
 625                          */
 626                         reg = AUX_LENGTH(cur_data_count) |
 627                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 628                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 629
 630                         /* Start AUX transaction */
 631                         retval = exynos_dp_start_aux_transaction(dp);
 632                         if (retval == 0)
 633                                 break;
 634                         else
 635                                 dev_err(dp->dev, "Aux Transaction fail!\n");
 636                 }
 637
 638                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 639                     cur_data_idx++) {
 640                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 641                                                  + 4 * cur_data_idx);
 642                         data[start_offset + cur_data_idx] =
 643                                 (unsigned char)reg;
 644                 }
 645
 646                 start_offset += cur_data_count;
 647         }
 648
 649         return retval;
 650 }
 651
 652 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 653                                 unsigned int device_addr,
 654                                 unsigned int reg_addr)
 655 {
 656         u32 reg;
 657         int retval;
 658
 659         /* Set EDID device address */
 660         reg = device_addr;
 661         writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
 662         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
 663         writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
 664
 665         /* Set offset from base address of EDID device */
 666         writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 667
 668         /*
 669          * Set I2C transaction and write address
 670          * If bit 3 is 1, DisplayPort transaction.
 671          * If Bit 3 is 0, I2C transaction.
 672          */
 673         reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 674                 AUX_TX_COMM_WRITE;
 675         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 676
 677         /* Start AUX transaction */
 678         retval = exynos_dp_start_aux_transaction(dp);
 679         if (retval != 0)
 680                 dev_err(dp->dev, "Aux Transaction fail!\n");
 681
 682         return retval;
 683 }
 684
 685 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 686                                 unsigned int device_addr,
 687                                 unsigned int reg_addr,
 688                                 unsigned int *data)
 689 {
 690         u32 reg;
 691         int i;
 692         int retval;
 693
 694         for (i = 0; i < 10; i++) {
 695                 /* Clear AUX CH data buffer */
 696                 reg = BUF_CLR;
 697                 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 698
 699                 /* Select EDID device */
 700                 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
 701                 if (retval != 0) {
 702                         dev_err(dp->dev, "Select EDID device fail!\n");
 703                         continue;
 704                 }
 705
 706                 /*
 707                  * Set I2C transaction and read data
 708                  * If bit 3 is 1, DisplayPort transaction.
 709                  * If Bit 3 is 0, I2C transaction.
 710                  */
 711                 reg = AUX_TX_COMM_I2C_TRANSACTION |
 712                         AUX_TX_COMM_READ;
 713                 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 714
 715                 /* Start AUX transaction */
 716                 retval = exynos_dp_start_aux_transaction(dp);
 717                 if (retval == 0)
 718                         break;
 719                 else
 720                         dev_err(dp->dev, "Aux Transaction fail!\n");
 721         }
 722
 723         /* Read data */
 724         if (retval == 0)
 725                 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
 726
 727         return retval;
 728 }
 729
 730 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 731                                 unsigned int device_addr,
 732                                 unsigned int reg_addr,
 733                                 unsigned int count,
 734                                 unsigned char edid[])
 735 {
 736         u32 reg;
 737         unsigned int i, j;
 738         unsigned int cur_data_idx;
 739         unsigned int defer = 0;
 740         int retval = 0;
 741
 742         for (i = 0; i < count; i += 16) {
 743                 for (j = 0; j < 100; j++) {
 744                         /* Clear AUX CH data buffer */
 745                         reg = BUF_CLR;
 746                         writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 747
 748                         /* Set normal AUX CH command */
 749                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 750                         reg &= ~ADDR_ONLY;
 751                         writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
 752
 753                         /*
 754                          * If Rx sends defer, Tx sends only reads
 755                          * request without sending addres
 756                          */
 757                         if (!defer)
 758                                 retval = exynos_dp_select_i2c_device(dp,
 759                                                 device_addr, reg_addr + i);
 760                         else
 761                                 defer = 0;
 762
 763                         if (retval == 0) {
 764                                 /*
 765                                  * Set I2C transaction and write data
 766                                  * If bit 3 is 1, DisplayPort transaction.
 767                                  * If Bit 3 is 0, I2C transaction.
 768                                  */
 769                                 reg = AUX_LENGTH(16) |
 770                                         AUX_TX_COMM_I2C_TRANSACTION |
 771                                         AUX_TX_COMM_READ;
 772                                 writel(reg, dp->reg_base +
 773                                         EXYNOS_DP_AUX_CH_CTL_1);
 774
 775                                 /* Start AUX transaction */
 776                                 retval = exynos_dp_start_aux_transaction(dp);
 777                                 if (retval == 0)
 778                                         break;
 779                                 else
 780                                         dev_err(dp->dev, "Aux Transaction fail!\n");
 781                         }
 782                         /* Check if Rx sends defer */
 783                         reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
 784                         if (reg == AUX_RX_COMM_AUX_DEFER ||
 785                                 reg == AUX_RX_COMM_I2C_DEFER) {
 786                                 dev_err(dp->dev, "Defer: %d\n\n", reg);
 787                                 defer = 1;
 788                         }
 789                 }
 790
 791                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 792                         reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
 793                                                  + 4 * cur_data_idx);
 794                         edid[i + cur_data_idx] = (unsigned char)reg;
 795                 }
 796         }
 797
 798         return retval;
 799 }
 800
 801 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 802 {
 803         u32 reg;
 804
 805         reg = bwtype;
 806         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 807                 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 808 }
 809
 810 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 811 {
 812         u32 reg;
 813
 814         reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 815         *bwtype = reg;
 816 }
 817
 818 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 819 {
 820         u32 reg;
 821
 822         reg = count;
 823         writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 824 }
 825
 826 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 827 {
 828         u32 reg;
 829
 830         reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 831         *count = reg;
 832 }
 833
 834 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 835 {
 836         u32 reg;
 837
 838         if (enable) {
 839                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 840                 reg |= ENHANCED;
 841                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 842         } else {
 843                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 844                 reg &= ~ENHANCED;
 845                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
 846         }
 847 }
 848
 849 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 850                                  enum pattern_set pattern)
 851 {
 852         u32 reg;
 853
 854         switch (pattern) {
 855         case PRBS7:
 856                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 857                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 858                 break;
 859         case D10_2:
 860                 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 861                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 862                 break;
 863         case TRAINING_PTN1:
 864                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 865                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 866                 break;
 867         case TRAINING_PTN2:
 868                 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 869                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 870                 break;
 871         case DP_NONE:
 872                 reg = SCRAMBLING_ENABLE |
 873                         LINK_QUAL_PATTERN_SET_DISABLE |
 874                         SW_TRAINING_PATTERN_SET_NORMAL;
 875                 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 876                 break;
 877         default:
 878                 break;
 879         }
 880 }
 881
 882 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 883 {
 884         u32 reg;
 885
 886         reg = level << PRE_EMPHASIS_SET_SHIFT;
 887         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 888 }
 889
 890 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 891 {
 892         u32 reg;
 893
 894         reg = level << PRE_EMPHASIS_SET_SHIFT;
 895         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 896 }
 897
 898 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 899 {
 900         u32 reg;
 901
 902         reg = level << PRE_EMPHASIS_SET_SHIFT;
 903         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 904 }
 905
 906 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 907 {
 908         u32 reg;
 909
 910         reg = level << PRE_EMPHASIS_SET_SHIFT;
 911         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 912 }
 913
 914 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 915                                         u32 training_lane)
 916 {
 917         u32 reg;
 918
 919         reg = training_lane;
 920         writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 921 }
 922
 923 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 924                                         u32 training_lane)
 925 {
 926         u32 reg;
 927
 928         reg = training_lane;
 929         writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 930 }
 931
 932 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 933                                         u32 training_lane)
 934 {
 935         u32 reg;
 936
 937         reg = training_lane;
 938         writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 939 }
 940
 941 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 942                                         u32 training_lane)
 943 {
 944         u32 reg;
 945
 946         reg = training_lane;
 947         writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 948 }
 949
 950 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 951 {
 952         u32 reg;
 953
 954         reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 955         return reg;
 956 }
 957
 958 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
 959 {
 960         u32 reg;
 961
 962         reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 963         return reg;
 964 }
 965
 966 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
 967 {
 968         u32 reg;
 969
 970         reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 971         return reg;
 972 }
 973
 974 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
 975 {
 976         u32 reg;
 977
 978         reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 979         return reg;
 980 }
 981
 982 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
 983 {
 984         u32 reg;
 985
 986         reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
 987         reg |= MACRO_RST;
 988         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 989
 990         /* 10 us is the minimum reset time. */
 991         udelay(10);
 992
 993         reg &= ~MACRO_RST;
 994         writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 995 }
 996
 997 int exynos_dp_init_video(struct exynos_dp_device *dp)
 998 {
 999         u32 reg;
1000
1001         reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1002         writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1003
1004         reg = 0x0;
1005         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1006
1007         reg = CHA_CRI(4) | CHA_CTRL;
1008         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1009
1010         reg = 0x0;
1011         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1012
1013         reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1014         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1015
1016         return 0;
1017 }
1018
1019 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
1020                         u32 color_depth,
1021                         u32 color_space,
1022                         u32 dynamic_range,
1023                         u32 ycbcr_coeff)
1024 {
1025         u32 reg;
1026
1027         /* Configure the input color depth, color space, dynamic range */
1028         reg = (dynamic_range << IN_D_RANGE_SHIFT) |
1029                 (color_depth << IN_BPC_SHIFT) |
1030                 (color_space << IN_COLOR_F_SHIFT);
1031         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1032
1033         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1034         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1035         reg &= ~IN_YC_COEFFI_MASK;
1036         if (ycbcr_coeff)
1037                 reg |= IN_YC_COEFFI_ITU709;
1038         else
1039                 reg |= IN_YC_COEFFI_ITU601;
1040         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1041 }
1042
1043 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1044 {
1045         u32 reg;
1046
1047         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1048         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1049
1050         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1051
1052         if (!(reg & DET_STA)) {
1053                 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1054                 return -EINVAL;
1055         }
1056
1057         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1058         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1059
1060         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1061         dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1062
1063         if (reg & CHA_STA) {
1064                 dev_dbg(dp->dev, "Input stream clk is changing\n");
1065                 return -EINVAL;
1066         }
1067
1068         return 0;
1069 }
1070
1071 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1072                 enum clock_recovery_m_value_type type,
1073                 u32 m_value,
1074                 u32 n_value)
1075 {
1076         u32 reg;
1077
1078         if (type == REGISTER_M) {
1079                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1080                 reg |= FIX_M_VID;
1081                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1082                 reg = m_value & 0xff;
1083                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1084                 reg = (m_value >> 8) & 0xff;
1085                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1086                 reg = (m_value >> 16) & 0xff;
1087                 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1088
1089                 reg = n_value & 0xff;
1090                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1091                 reg = (n_value >> 8) & 0xff;
1092                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1093                 reg = (n_value >> 16) & 0xff;
1094                 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1095         } else  {
1096                 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1097                 reg &= ~FIX_M_VID;
1098                 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1099
1100                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1101                 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1102                 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1103         }
1104 }
1105
1106 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1107 {
1108         u32 reg;
1109
1110         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1111                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1112                 reg &= ~FORMAT_SEL;
1113                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1114         } else {
1115                 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1116                 reg |= FORMAT_SEL;
1117                 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1118         }
1119 }
1120
1121 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1122 {
1123         u32 reg;
1124
1125         if (enable) {
1126                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1127                 reg &= ~VIDEO_MODE_MASK;
1128                 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1129                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1130         } else {
1131                 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1132                 reg &= ~VIDEO_MODE_MASK;
1133                 reg |= VIDEO_MODE_SLAVE_MODE;
1134                 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1135         }
1136 }
1137
1138 void exynos_dp_start_video(struct exynos_dp_device *dp)
1139 {
1140         u32 reg;
1141
1142         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1143         reg |= VIDEO_EN;
1144         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1145 }
1146
1147 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1148 {
1149         u32 reg;
1150
1151         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1152         writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1153
1154         reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1155         if (!(reg & STRM_VALID)) {
1156                 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1157                 return -EINVAL;
1158         }
1159
1160         return 0;
1161 }
1162
1163 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1164                         struct video_info *video_info)
1165 {
1166         u32 reg;
1167
1168         reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1169         reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1170         reg |= MASTER_VID_FUNC_EN_N;
1171         writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1172
1173         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1174         reg &= ~INTERACE_SCAN_CFG;
1175         reg |= (video_info->interlaced << 2);
1176         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1177
1178         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1179         reg &= ~VSYNC_POLARITY_CFG;
1180         reg |= (video_info->v_sync_polarity << 1);
1181         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1182
1183         reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1184         reg &= ~HSYNC_POLARITY_CFG;
1185         reg |= (video_info->h_sync_polarity << 0);
1186         writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1187
1188         reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1189         writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1190 }
1191
1192 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1193 {
1194         u32 reg;
1195
1196         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1197         reg &= ~SCRAMBLING_DISABLE;
1198         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1199 }
1200
1201 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1202 {
1203         u32 reg;
1204
1205         reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1206         reg |= SCRAMBLING_DISABLE;
1207         writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1208 }