drivers/video/fbdev/omap2/dss/hdmi5.c

   1 /*
   2  * HDMI driver for OMAP5
   3  *
   4  * Copyright (C) 2014 Texas Instruments Incorporated
   5  *
   6  * Authors:
   7  *      Yong Zhi
   8  *      Mythri pk
   9  *      Archit Taneja <archit@ti.com>
  10  *      Tomi Valkeinen <tomi.valkeinen@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms of the GNU General Public License version 2 as published by
  14  * the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  *
  21  * You should have received a copy of the GNU General Public License along with
  22  * this program.  If not, see <http://www.gnu.org/licenses/>.
  23  */
  24
  25 #define DSS_SUBSYS_NAME "HDMI"
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/err.h>
  30 #include <linux/io.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/mutex.h>
  33 #include <linux/delay.h>
  34 #include <linux/string.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/clk.h>
  38 #include <linux/gpio.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <video/omapdss.h>
  41
  42 #include "hdmi5_core.h"
  43 #include "dss.h"
  44 #include "dss_features.h"
  45
  46 static struct {
  47         struct mutex lock;
  48         struct platform_device *pdev;
  49
  50         struct hdmi_wp_data     wp;
  51         struct hdmi_pll_data    pll;
  52         struct hdmi_phy_data    phy;
  53         struct hdmi_core_data   core;
  54
  55         struct hdmi_config cfg;
  56
  57         struct clk *sys_clk;
  58         struct regulator *vdda_reg;
  59
  60         bool core_enabled;
  61
  62         struct omap_dss_device output;
  63 } hdmi;
  64
  65 static int hdmi_runtime_get(void)
  66 {
  67         int r;
  68
  69         DSSDBG("hdmi_runtime_get\n");
  70
  71         r = pm_runtime_get_sync(&hdmi.pdev->dev);
  72         WARN_ON(r < 0);
  73         if (r < 0)
  74                 return r;
  75
  76         return 0;
  77 }
  78
  79 static void hdmi_runtime_put(void)
  80 {
  81         int r;
  82
  83         DSSDBG("hdmi_runtime_put\n");
  84
  85         r = pm_runtime_put_sync(&hdmi.pdev->dev);
  86         WARN_ON(r < 0 && r != -ENOSYS);
  87 }
  88
  89 static irqreturn_t hdmi_irq_handler(int irq, void *data)
  90 {
  91         struct hdmi_wp_data *wp = data;
  92         u32 irqstatus;
  93
  94         irqstatus = hdmi_wp_get_irqstatus(wp);
  95         hdmi_wp_set_irqstatus(wp, irqstatus);
  96
  97         if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  98                         irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  99                 u32 v;
 100                 /*
 101                  * If we get both connect and disconnect interrupts at the same
 102                  * time, turn off the PHY, clear interrupts, and restart, which
 103                  * raises connect interrupt if a cable is connected, or nothing
 104                  * if cable is not connected.
 105                  */
 106
 107                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
 108
 109                 /*
 110                  * We always get bogus CONNECT & DISCONNECT interrupts when
 111                  * setting the PHY to LDOON. To ignore those, we force the RXDET
 112                  * line to 0 until the PHY power state has been changed.
 113                  */
 114                 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
 115                 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
 116                 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
 117                 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
 118
 119                 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
 120                                 HDMI_IRQ_LINK_DISCONNECT);
 121
 122                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
 123
 124                 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
 125
 126         } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
 127                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
 128         } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
 129                 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
 130         }
 131
 132         return IRQ_HANDLED;
 133 }
 134
 135 static int hdmi_init_regulator(void)
 136 {
 137         int r;
 138         struct regulator *reg;
 139
 140         if (hdmi.vdda_reg != NULL)
 141                 return 0;
 142
 143         reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
 144         if (IS_ERR(reg)) {
 145                 DSSERR("can't get VDDA regulator\n");
 146                 return PTR_ERR(reg);
 147         }
 148
 149         if (regulator_can_change_voltage(reg)) {
 150                 r = regulator_set_voltage(reg, 1800000, 1800000);
 151                 if (r) {
 152                         devm_regulator_put(reg);
 153                         DSSWARN("can't set the regulator voltage\n");
 154                         return r;
 155                 }
 156         }
 157
 158         hdmi.vdda_reg = reg;
 159
 160         return 0;
 161 }
 162
 163 static int hdmi_power_on_core(struct omap_dss_device *dssdev)
 164 {
 165         int r;
 166
 167         r = regulator_enable(hdmi.vdda_reg);
 168         if (r)
 169                 return r;
 170
 171         r = hdmi_runtime_get();
 172         if (r)
 173                 goto err_runtime_get;
 174
 175         /* Make selection of HDMI in DSS */
 176         dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
 177
 178         hdmi.core_enabled = true;
 179
 180         return 0;
 181
 182 err_runtime_get:
 183         regulator_disable(hdmi.vdda_reg);
 184
 185         return r;
 186 }
 187
 188 static void hdmi_power_off_core(struct omap_dss_device *dssdev)
 189 {
 190         hdmi.core_enabled = false;
 191
 192         hdmi_runtime_put();
 193         regulator_disable(hdmi.vdda_reg);
 194 }
 195
 196 static int hdmi_power_on_full(struct omap_dss_device *dssdev)
 197 {
 198         int r;
 199         struct omap_video_timings *p;
 200         struct omap_overlay_manager *mgr = hdmi.output.manager;
 201
 202         r = hdmi_power_on_core(dssdev);
 203         if (r)
 204                 return r;
 205
 206         p = &hdmi.cfg.timings;
 207
 208         DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
 209
 210         hdmi_pll_compute(&hdmi.pll, clk_get_rate(hdmi.sys_clk), p->pixelclock);
 211
 212         /* disable and clear irqs */
 213         hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
 214         hdmi_wp_set_irqstatus(&hdmi.wp,
 215                         hdmi_wp_get_irqstatus(&hdmi.wp));
 216
 217         /* config the PLL and PHY hdmi_set_pll_pwrfirst */
 218         r = hdmi_pll_enable(&hdmi.pll, &hdmi.wp);
 219         if (r) {
 220                 DSSDBG("Failed to lock PLL\n");
 221                 goto err_pll_enable;
 222         }
 223
 224         r = hdmi_phy_configure(&hdmi.phy, hdmi.pll.info.clkdco,
 225                 hdmi.pll.info.clkout);
 226         if (r) {
 227                 DSSDBG("Failed to start PHY\n");
 228                 goto err_phy_cfg;
 229         }
 230
 231         r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
 232         if (r)
 233                 goto err_phy_pwr;
 234
 235         hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
 236
 237         /* bypass TV gamma table */
 238         dispc_enable_gamma_table(0);
 239
 240         /* tv size */
 241         dss_mgr_set_timings(mgr, p);
 242
 243         r = hdmi_wp_video_start(&hdmi.wp);
 244         if (r)
 245                 goto err_vid_enable;
 246
 247         r = dss_mgr_enable(mgr);
 248         if (r)
 249                 goto err_mgr_enable;
 250
 251         hdmi_wp_set_irqenable(&hdmi.wp,
 252                         HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
 253
 254         return 0;
 255
 256 err_mgr_enable:
 257         hdmi_wp_video_stop(&hdmi.wp);
 258 err_vid_enable:
 259         hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
 260 err_phy_pwr:
 261 err_phy_cfg:
 262         hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
 263 err_pll_enable:
 264         hdmi_power_off_core(dssdev);
 265         return -EIO;
 266 }
 267
 268 static void hdmi_power_off_full(struct omap_dss_device *dssdev)
 269 {
 270         struct omap_overlay_manager *mgr = hdmi.output.manager;
 271
 272         hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
 273
 274         dss_mgr_disable(mgr);
 275
 276         hdmi_wp_video_stop(&hdmi.wp);
 277
 278         hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
 279
 280         hdmi_pll_disable(&hdmi.pll, &hdmi.wp);
 281
 282         hdmi_power_off_core(dssdev);
 283 }
 284
 285 static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
 286                                         struct omap_video_timings *timings)
 287 {
 288         struct omap_dss_device *out = &hdmi.output;
 289
 290         /* TODO: proper interlace support */
 291         if (timings->interlace)
 292                 return -EINVAL;
 293
 294         if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
 295                 return -EINVAL;
 296
 297         return 0;
 298 }
 299
 300 static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
 301                 struct omap_video_timings *timings)
 302 {
 303         mutex_lock(&hdmi.lock);
 304
 305         hdmi.cfg.timings = *timings;
 306
 307         dispc_set_tv_pclk(timings->pixelclock);
 308
 309         mutex_unlock(&hdmi.lock);
 310 }
 311
 312 static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
 313                 struct omap_video_timings *timings)
 314 {
 315         *timings = hdmi.cfg.timings;
 316 }
 317
 318 static void hdmi_dump_regs(struct seq_file *s)
 319 {
 320         mutex_lock(&hdmi.lock);
 321
 322         if (hdmi_runtime_get()) {
 323                 mutex_unlock(&hdmi.lock);
 324                 return;
 325         }
 326
 327         hdmi_wp_dump(&hdmi.wp, s);
 328         hdmi_pll_dump(&hdmi.pll, s);
 329         hdmi_phy_dump(&hdmi.phy, s);
 330         hdmi5_core_dump(&hdmi.core, s);
 331
 332         hdmi_runtime_put();
 333         mutex_unlock(&hdmi.lock);
 334 }
 335
 336 static int read_edid(u8 *buf, int len)
 337 {
 338         int r;
 339         int idlemode;
 340
 341         mutex_lock(&hdmi.lock);
 342
 343         r = hdmi_runtime_get();
 344         BUG_ON(r);
 345
 346         idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
 347         /* No-idle mode */
 348         REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
 349
 350         r = hdmi5_read_edid(&hdmi.core,  buf, len);
 351
 352         REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
 353
 354         hdmi_runtime_put();
 355         mutex_unlock(&hdmi.lock);
 356
 357         return r;
 358 }
 359
 360 static int hdmi_display_enable(struct omap_dss_device *dssdev)
 361 {
 362         struct omap_dss_device *out = &hdmi.output;
 363         int r = 0;
 364
 365         DSSDBG("ENTER hdmi_display_enable\n");
 366
 367         mutex_lock(&hdmi.lock);
 368
 369         if (out == NULL || out->manager == NULL) {
 370                 DSSERR("failed to enable display: no output/manager\n");
 371                 r = -ENODEV;
 372                 goto err0;
 373         }
 374
 375         r = hdmi_power_on_full(dssdev);
 376         if (r) {
 377                 DSSERR("failed to power on device\n");
 378                 goto err0;
 379         }
 380
 381         mutex_unlock(&hdmi.lock);
 382         return 0;
 383
 384 err0:
 385         mutex_unlock(&hdmi.lock);
 386         return r;
 387 }
 388
 389 static void hdmi_display_disable(struct omap_dss_device *dssdev)
 390 {
 391         DSSDBG("Enter hdmi_display_disable\n");
 392
 393         mutex_lock(&hdmi.lock);
 394
 395         hdmi_power_off_full(dssdev);
 396
 397         mutex_unlock(&hdmi.lock);
 398 }
 399
 400 static int hdmi_core_enable(struct omap_dss_device *dssdev)
 401 {
 402         int r = 0;
 403
 404         DSSDBG("ENTER omapdss_hdmi_core_enable\n");
 405
 406         mutex_lock(&hdmi.lock);
 407
 408         r = hdmi_power_on_core(dssdev);
 409         if (r) {
 410                 DSSERR("failed to power on device\n");
 411                 goto err0;
 412         }
 413
 414         mutex_unlock(&hdmi.lock);
 415         return 0;
 416
 417 err0:
 418         mutex_unlock(&hdmi.lock);
 419         return r;
 420 }
 421
 422 static void hdmi_core_disable(struct omap_dss_device *dssdev)
 423 {
 424         DSSDBG("Enter omapdss_hdmi_core_disable\n");
 425
 426         mutex_lock(&hdmi.lock);
 427
 428         hdmi_power_off_core(dssdev);
 429
 430         mutex_unlock(&hdmi.lock);
 431 }
 432
 433 static int hdmi_get_clocks(struct platform_device *pdev)
 434 {
 435         struct clk *clk;
 436
 437         clk = devm_clk_get(&pdev->dev, "sys_clk");
 438         if (IS_ERR(clk)) {
 439                 DSSERR("can't get sys_clk\n");
 440                 return PTR_ERR(clk);
 441         }
 442
 443         hdmi.sys_clk = clk;
 444
 445         return 0;
 446 }
 447
 448 static int hdmi_connect(struct omap_dss_device *dssdev,
 449                 struct omap_dss_device *dst)
 450 {
 451         struct omap_overlay_manager *mgr;
 452         int r;
 453
 454         r = hdmi_init_regulator();
 455         if (r)
 456                 return r;
 457
 458         mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
 459         if (!mgr)
 460                 return -ENODEV;
 461
 462         r = dss_mgr_connect(mgr, dssdev);
 463         if (r)
 464                 return r;
 465
 466         r = omapdss_output_set_device(dssdev, dst);
 467         if (r) {
 468                 DSSERR("failed to connect output to new device: %s\n",
 469                                 dst->name);
 470                 dss_mgr_disconnect(mgr, dssdev);
 471                 return r;
 472         }
 473
 474         return 0;
 475 }
 476
 477 static void hdmi_disconnect(struct omap_dss_device *dssdev,
 478                 struct omap_dss_device *dst)
 479 {
 480         WARN_ON(dst != dssdev->dst);
 481
 482         if (dst != dssdev->dst)
 483                 return;
 484
 485         omapdss_output_unset_device(dssdev);
 486
 487         if (dssdev->manager)
 488                 dss_mgr_disconnect(dssdev->manager, dssdev);
 489 }
 490
 491 static int hdmi_read_edid(struct omap_dss_device *dssdev,
 492                 u8 *edid, int len)
 493 {
 494         bool need_enable;
 495         int r;
 496
 497         need_enable = hdmi.core_enabled == false;
 498
 499         if (need_enable) {
 500                 r = hdmi_core_enable(dssdev);
 501                 if (r)
 502                         return r;
 503         }
 504
 505         r = read_edid(edid, len);
 506
 507         if (need_enable)
 508                 hdmi_core_disable(dssdev);
 509
 510         return r;
 511 }
 512
 513 #if defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
 514 static int hdmi_audio_enable(struct omap_dss_device *dssdev)
 515 {
 516         int r;
 517
 518         mutex_lock(&hdmi.lock);
 519
 520         if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) {
 521                 r = -EPERM;
 522                 goto err;
 523         }
 524
 525         r = hdmi_wp_audio_enable(&hdmi.wp, true);
 526         if (r)
 527                 goto err;
 528
 529         mutex_unlock(&hdmi.lock);
 530         return 0;
 531
 532 err:
 533         mutex_unlock(&hdmi.lock);
 534         return r;
 535 }
 536
 537 static void hdmi_audio_disable(struct omap_dss_device *dssdev)
 538 {
 539         hdmi_wp_audio_enable(&hdmi.wp, false);
 540 }
 541
 542 static int hdmi_audio_start(struct omap_dss_device *dssdev)
 543 {
 544         return hdmi_wp_audio_core_req_enable(&hdmi.wp, true);
 545 }
 546
 547 static void hdmi_audio_stop(struct omap_dss_device *dssdev)
 548 {
 549         hdmi_wp_audio_core_req_enable(&hdmi.wp, false);
 550 }
 551
 552 static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
 553 {
 554         bool r;
 555
 556         mutex_lock(&hdmi.lock);
 557
 558         r = hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode);
 559
 560         mutex_unlock(&hdmi.lock);
 561         return r;
 562 }
 563
 564 static int hdmi_audio_config(struct omap_dss_device *dssdev,
 565                 struct omap_dss_audio *audio)
 566 {
 567         int r;
 568         u32 pclk = hdmi.cfg.timings.pixelclock;
 569
 570         mutex_lock(&hdmi.lock);
 571
 572         if (!hdmi_mode_has_audio(hdmi.cfg.hdmi_dvi_mode)) {
 573                 r = -EPERM;
 574                 goto err;
 575         }
 576
 577         r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, audio, pclk);
 578         if (r)
 579                 goto err;
 580
 581         mutex_unlock(&hdmi.lock);
 582         return 0;
 583
 584 err:
 585         mutex_unlock(&hdmi.lock);
 586         return r;
 587 }
 588 #else
 589 static int hdmi_audio_enable(struct omap_dss_device *dssdev)
 590 {
 591         return -EPERM;
 592 }
 593
 594 static void hdmi_audio_disable(struct omap_dss_device *dssdev)
 595 {
 596 }
 597
 598 static int hdmi_audio_start(struct omap_dss_device *dssdev)
 599 {
 600         return -EPERM;
 601 }
 602
 603 static void hdmi_audio_stop(struct omap_dss_device *dssdev)
 604 {
 605 }
 606
 607 static bool hdmi_audio_supported(struct omap_dss_device *dssdev)
 608 {
 609         return false;
 610 }
 611
 612 static int hdmi_audio_config(struct omap_dss_device *dssdev,
 613                 struct omap_dss_audio *audio)
 614 {
 615         return -EPERM;
 616 }
 617 #endif
 618
 619 static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
 620                 const struct hdmi_avi_infoframe *avi)
 621 {
 622         hdmi.cfg.infoframe = *avi;
 623         return 0;
 624 }
 625
 626 static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
 627                 bool hdmi_mode)
 628 {
 629         hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
 630         return 0;
 631 }
 632
 633 static const struct omapdss_hdmi_ops hdmi_ops = {
 634         .connect                = hdmi_connect,
 635         .disconnect             = hdmi_disconnect,
 636
 637         .enable                 = hdmi_display_enable,
 638         .disable                = hdmi_display_disable,
 639
 640         .check_timings          = hdmi_display_check_timing,
 641         .set_timings            = hdmi_display_set_timing,
 642         .get_timings            = hdmi_display_get_timings,
 643
 644         .read_edid              = hdmi_read_edid,
 645         .set_infoframe          = hdmi_set_infoframe,
 646         .set_hdmi_mode          = hdmi_set_hdmi_mode,
 647
 648         .audio_enable           = hdmi_audio_enable,
 649         .audio_disable          = hdmi_audio_disable,
 650         .audio_start            = hdmi_audio_start,
 651         .audio_stop             = hdmi_audio_stop,
 652         .audio_supported        = hdmi_audio_supported,
 653         .audio_config           = hdmi_audio_config,
 654 };
 655
 656 static void hdmi_init_output(struct platform_device *pdev)
 657 {
 658         struct omap_dss_device *out = &hdmi.output;
 659
 660         out->dev = &pdev->dev;
 661         out->id = OMAP_DSS_OUTPUT_HDMI;
 662         out->output_type = OMAP_DISPLAY_TYPE_HDMI;
 663         out->name = "hdmi.0";
 664         out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
 665         out->ops.hdmi = &hdmi_ops;
 666         out->owner = THIS_MODULE;
 667
 668         omapdss_register_output(out);
 669 }
 670
 671 static void __exit hdmi_uninit_output(struct platform_device *pdev)
 672 {
 673         struct omap_dss_device *out = &hdmi.output;
 674
 675         omapdss_unregister_output(out);
 676 }
 677
 678 static int hdmi_probe_of(struct platform_device *pdev)
 679 {
 680         struct device_node *node = pdev->dev.of_node;
 681         struct device_node *ep;
 682         int r;
 683
 684         ep = omapdss_of_get_first_endpoint(node);
 685         if (!ep)
 686                 return 0;
 687
 688         r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
 689         if (r)
 690                 goto err;
 691
 692         of_node_put(ep);
 693         return 0;
 694
 695 err:
 696         of_node_put(ep);
 697         return r;
 698 }
 699
 700 /* HDMI HW IP initialisation */
 701 static int omapdss_hdmihw_probe(struct platform_device *pdev)
 702 {
 703         int r;
 704         int irq;
 705
 706         hdmi.pdev = pdev;
 707
 708         mutex_init(&hdmi.lock);
 709
 710         if (pdev->dev.of_node) {
 711                 r = hdmi_probe_of(pdev);
 712                 if (r)
 713                         return r;
 714         }
 715
 716         r = hdmi_wp_init(pdev, &hdmi.wp);
 717         if (r)
 718                 return r;
 719
 720         r = hdmi_pll_init(pdev, &hdmi.pll);
 721         if (r)
 722                 return r;
 723
 724         r = hdmi_phy_init(pdev, &hdmi.phy);
 725         if (r)
 726                 return r;
 727
 728         r = hdmi5_core_init(pdev, &hdmi.core);
 729         if (r)
 730                 return r;
 731
 732         r = hdmi_get_clocks(pdev);
 733         if (r) {
 734                 DSSERR("can't get clocks\n");
 735                 return r;
 736         }
 737
 738         irq = platform_get_irq(pdev, 0);
 739         if (irq < 0) {
 740                 DSSERR("platform_get_irq failed\n");
 741                 return -ENODEV;
 742         }
 743
 744         r = devm_request_threaded_irq(&pdev->dev, irq,
 745                         NULL, hdmi_irq_handler,
 746                         IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
 747         if (r) {
 748                 DSSERR("HDMI IRQ request failed\n");
 749                 return r;
 750         }
 751
 752         pm_runtime_enable(&pdev->dev);
 753
 754         hdmi_init_output(pdev);
 755
 756         dss_debugfs_create_file("hdmi", hdmi_dump_regs);
 757
 758         return 0;
 759 }
 760
 761 static int __exit omapdss_hdmihw_remove(struct platform_device *pdev)
 762 {
 763         hdmi_uninit_output(pdev);
 764
 765         pm_runtime_disable(&pdev->dev);
 766
 767         return 0;
 768 }
 769
 770 static int hdmi_runtime_suspend(struct device *dev)
 771 {
 772         clk_disable_unprepare(hdmi.sys_clk);
 773
 774         dispc_runtime_put();
 775
 776         return 0;
 777 }
 778
 779 static int hdmi_runtime_resume(struct device *dev)
 780 {
 781         int r;
 782
 783         r = dispc_runtime_get();
 784         if (r < 0)
 785                 return r;
 786
 787         clk_prepare_enable(hdmi.sys_clk);
 788
 789         return 0;
 790 }
 791
 792 static const struct dev_pm_ops hdmi_pm_ops = {
 793         .runtime_suspend = hdmi_runtime_suspend,
 794         .runtime_resume = hdmi_runtime_resume,
 795 };
 796
 797 static const struct of_device_id hdmi_of_match[] = {
 798         { .compatible = "ti,omap5-hdmi", },
 799         {},
 800 };
 801
 802 static struct platform_driver omapdss_hdmihw_driver = {
 803         .probe          = omapdss_hdmihw_probe,
 804         .remove         = __exit_p(omapdss_hdmihw_remove),
 805         .driver         = {
 806                 .name   = "omapdss_hdmi5",
 807                 .owner  = THIS_MODULE,
 808                 .pm     = &hdmi_pm_ops,
 809                 .of_match_table = hdmi_of_match,
 810                 .suppress_bind_attrs = true,
 811         },
 812 };
 813
 814 int __init hdmi5_init_platform_driver(void)
 815 {
 816         return platform_driver_register(&omapdss_hdmihw_driver);
 817 }
 818
 819 void __exit hdmi5_uninit_platform_driver(void)
 820 {
 821         platform_driver_unregister(&omapdss_hdmihw_driver);
 822 }