drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44 #include <plat/clock.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48
  49 /*#define VERBOSE_IRQ*/
  50 #define DSI_CATCH_MISSING_TE
  51
  52 struct dsi_reg { u16 idx; };
  53
  54 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  55
  56 #define DSI_SZ_REGS             SZ_1K
  57 /* DSI Protocol Engine */
  58
  59 #define DSI_REVISION                    DSI_REG(0x0000)
  60 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  61 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  62 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  63 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  64 #define DSI_CTRL                        DSI_REG(0x0040)
  65 #define DSI_GNQ                         DSI_REG(0x0044)
  66 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  67 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  68 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  69 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  70 #define DSI_TIMING1                     DSI_REG(0x0058)
  71 #define DSI_TIMING2                     DSI_REG(0x005C)
  72 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  73 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  74 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  75 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  76 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  77 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  78 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  79 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  80 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  81 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  82 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  83 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  84 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  85 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  86 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  87 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  88 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  89 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  90 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  91 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  92 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  93
  94 /* DSIPHY_SCP */
  95
  96 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  97 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  98 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  99 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
 100 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
 101
 102 /* DSI_PLL_CTRL_SCP */
 103
 104 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 105 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 106 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 107 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 108 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 109
 110 #define REG_GET(dsidev, idx, start, end) \
 111         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 112
 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 114         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 115
 116 /* Global interrupts */
 117 #define DSI_IRQ_VC0             (1 << 0)
 118 #define DSI_IRQ_VC1             (1 << 1)
 119 #define DSI_IRQ_VC2             (1 << 2)
 120 #define DSI_IRQ_VC3             (1 << 3)
 121 #define DSI_IRQ_WAKEUP          (1 << 4)
 122 #define DSI_IRQ_RESYNC          (1 << 5)
 123 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 124 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 125 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 126 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 127 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 128 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 129 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 130 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 131 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 132 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 133 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 134 #define DSI_IRQ_ERROR_MASK \
 135         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 136         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 137 #define DSI_IRQ_CHANNEL_MASK    0xf
 138
 139 /* Virtual channel interrupts */
 140 #define DSI_VC_IRQ_CS           (1 << 0)
 141 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 142 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 143 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 144 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 145 #define DSI_VC_IRQ_BTA          (1 << 5)
 146 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 147 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 149 #define DSI_VC_IRQ_ERROR_MASK \
 150         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 151         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 152         DSI_VC_IRQ_FIFO_TX_UDF)
 153
 154 /* ComplexIO interrupts */
 155 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 156 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 157 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 158 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 159 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 160 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 161 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 162 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 163 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 164 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 165 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 166 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 167 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 168 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 169 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 170 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 171 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 172 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 173 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 174 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 187 #define DSI_CIO_IRQ_ERROR_MASK \
 188         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 189          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 190          DSI_CIO_IRQ_ERRSYNCESC5 | \
 191          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 192          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 193          DSI_CIO_IRQ_ERRESC5 | \
 194          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 195          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 196          DSI_CIO_IRQ_ERRCONTROL5 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 200          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 201          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 202
 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 204
 205 #define DSI_MAX_NR_ISRS                2
 206 #define DSI_MAX_NR_LANES        5
 207
 208 enum dsi_lane_function {
 209         DSI_LANE_UNUSED = 0,
 210         DSI_LANE_CLK,
 211         DSI_LANE_DATA1,
 212         DSI_LANE_DATA2,
 213         DSI_LANE_DATA3,
 214         DSI_LANE_DATA4,
 215 };
 216
 217 struct dsi_lane_config {
 218         enum dsi_lane_function function;
 219         u8 polarity;
 220 };
 221
 222 struct dsi_isr_data {
 223         omap_dsi_isr_t  isr;
 224         void            *arg;
 225         u32             mask;
 226 };
 227
 228 enum fifo_size {
 229         DSI_FIFO_SIZE_0         = 0,
 230         DSI_FIFO_SIZE_32        = 1,
 231         DSI_FIFO_SIZE_64        = 2,
 232         DSI_FIFO_SIZE_96        = 3,
 233         DSI_FIFO_SIZE_128       = 4,
 234 };
 235
 236 enum dsi_vc_source {
 237         DSI_VC_SOURCE_L4 = 0,
 238         DSI_VC_SOURCE_VP,
 239 };
 240
 241 struct dsi_irq_stats {
 242         unsigned long last_reset;
 243         unsigned irq_count;
 244         unsigned dsi_irqs[32];
 245         unsigned vc_irqs[4][32];
 246         unsigned cio_irqs[32];
 247 };
 248
 249 struct dsi_isr_tables {
 250         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 251         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 252         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 253 };
 254
 255 struct dsi_data {
 256         struct platform_device *pdev;
 257         void __iomem    *base;
 258
 259         int module_id;
 260
 261         int irq;
 262
 263         struct clk *dss_clk;
 264         struct clk *sys_clk;
 265
 266         struct dsi_clock_info current_cinfo;
 267
 268         bool vdds_dsi_enabled;
 269         struct regulator *vdds_dsi_reg;
 270
 271         struct {
 272                 enum dsi_vc_source source;
 273                 struct omap_dss_device *dssdev;
 274                 enum fifo_size fifo_size;
 275                 int vc_id;
 276         } vc[4];
 277
 278         struct mutex lock;
 279         struct semaphore bus_lock;
 280
 281         unsigned pll_locked;
 282
 283         spinlock_t irq_lock;
 284         struct dsi_isr_tables isr_tables;
 285         /* space for a copy used by the interrupt handler */
 286         struct dsi_isr_tables isr_tables_copy;
 287
 288         int update_channel;
 289 #ifdef DEBUG
 290         unsigned update_bytes;
 291 #endif
 292
 293         bool te_enabled;
 294         bool ulps_enabled;
 295
 296         void (*framedone_callback)(int, void *);
 297         void *framedone_data;
 298
 299         struct delayed_work framedone_timeout_work;
 300
 301 #ifdef DSI_CATCH_MISSING_TE
 302         struct timer_list te_timer;
 303 #endif
 304
 305         unsigned long cache_req_pck;
 306         unsigned long cache_clk_freq;
 307         struct dsi_clock_info cache_cinfo;
 308
 309         u32             errors;
 310         spinlock_t      errors_lock;
 311 #ifdef DEBUG
 312         ktime_t perf_setup_time;
 313         ktime_t perf_start_time;
 314 #endif
 315         int debug_read;
 316         int debug_write;
 317
 318 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 319         spinlock_t irq_stats_lock;
 320         struct dsi_irq_stats irq_stats;
 321 #endif
 322         /* DSI PLL Parameter Ranges */
 323         unsigned long regm_max, regn_max;
 324         unsigned long  regm_dispc_max, regm_dsi_max;
 325         unsigned long  fint_min, fint_max;
 326         unsigned long lpdiv_max;
 327
 328         unsigned num_lanes_supported;
 329
 330         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 331         unsigned num_lanes_used;
 332
 333         unsigned scp_clk_refcount;
 334 };
 335
 336 struct dsi_packet_sent_handler_data {
 337         struct platform_device *dsidev;
 338         struct completion *completion;
 339 };
 340
 341 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
 342
 343 #ifdef DEBUG
 344 static bool dsi_perf;
 345 module_param(dsi_perf, bool, 0644);
 346 #endif
 347
 348 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 349 {
 350         return dev_get_drvdata(&dsidev->dev);
 351 }
 352
 353 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 354 {
 355         return dsi_pdev_map[dssdev->phy.dsi.module];
 356 }
 357
 358 struct platform_device *dsi_get_dsidev_from_id(int module)
 359 {
 360         return dsi_pdev_map[module];
 361 }
 362
 363 static inline void dsi_write_reg(struct platform_device *dsidev,
 364                 const struct dsi_reg idx, u32 val)
 365 {
 366         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 367
 368         __raw_writel(val, dsi->base + idx.idx);
 369 }
 370
 371 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 372                 const struct dsi_reg idx)
 373 {
 374         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 375
 376         return __raw_readl(dsi->base + idx.idx);
 377 }
 378
 379 void dsi_bus_lock(struct omap_dss_device *dssdev)
 380 {
 381         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 382         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 383
 384         down(&dsi->bus_lock);
 385 }
 386 EXPORT_SYMBOL(dsi_bus_lock);
 387
 388 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 389 {
 390         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 391         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 392
 393         up(&dsi->bus_lock);
 394 }
 395 EXPORT_SYMBOL(dsi_bus_unlock);
 396
 397 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 398 {
 399         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 400
 401         return dsi->bus_lock.count == 0;
 402 }
 403
 404 static void dsi_completion_handler(void *data, u32 mask)
 405 {
 406         complete((struct completion *)data);
 407 }
 408
 409 static inline int wait_for_bit_change(struct platform_device *dsidev,
 410                 const struct dsi_reg idx, int bitnum, int value)
 411 {
 412         unsigned long timeout;
 413         ktime_t wait;
 414         int t;
 415
 416         /* first busyloop to see if the bit changes right away */
 417         t = 100;
 418         while (t-- > 0) {
 419                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 420                         return value;
 421         }
 422
 423         /* then loop for 500ms, sleeping for 1ms in between */
 424         timeout = jiffies + msecs_to_jiffies(500);
 425         while (time_before(jiffies, timeout)) {
 426                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 427                         return value;
 428
 429                 wait = ns_to_ktime(1000 * 1000);
 430                 set_current_state(TASK_UNINTERRUPTIBLE);
 431                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 432         }
 433
 434         return !value;
 435 }
 436
 437 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 438 {
 439         switch (fmt) {
 440         case OMAP_DSS_DSI_FMT_RGB888:
 441         case OMAP_DSS_DSI_FMT_RGB666:
 442                 return 24;
 443         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 444                 return 18;
 445         case OMAP_DSS_DSI_FMT_RGB565:
 446                 return 16;
 447         default:
 448                 BUG();
 449                 return 0;
 450         }
 451 }
 452
 453 #ifdef DEBUG
 454 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 455 {
 456         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 457         dsi->perf_setup_time = ktime_get();
 458 }
 459
 460 static void dsi_perf_mark_start(struct platform_device *dsidev)
 461 {
 462         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 463         dsi->perf_start_time = ktime_get();
 464 }
 465
 466 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 467 {
 468         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 469         ktime_t t, setup_time, trans_time;
 470         u32 total_bytes;
 471         u32 setup_us, trans_us, total_us;
 472
 473         if (!dsi_perf)
 474                 return;
 475
 476         t = ktime_get();
 477
 478         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 479         setup_us = (u32)ktime_to_us(setup_time);
 480         if (setup_us == 0)
 481                 setup_us = 1;
 482
 483         trans_time = ktime_sub(t, dsi->perf_start_time);
 484         trans_us = (u32)ktime_to_us(trans_time);
 485         if (trans_us == 0)
 486                 trans_us = 1;
 487
 488         total_us = setup_us + trans_us;
 489
 490         total_bytes = dsi->update_bytes;
 491
 492         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 493                         "%u bytes, %u kbytes/sec\n",
 494                         name,
 495                         setup_us,
 496                         trans_us,
 497                         total_us,
 498                         1000*1000 / total_us,
 499                         total_bytes,
 500                         total_bytes * 1000 / total_us);
 501 }
 502 #else
 503 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 504 {
 505 }
 506
 507 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 508 {
 509 }
 510
 511 static inline void dsi_perf_show(struct platform_device *dsidev,
 512                 const char *name)
 513 {
 514 }
 515 #endif
 516
 517 static void print_irq_status(u32 status)
 518 {
 519         if (status == 0)
 520                 return;
 521
 522 #ifndef VERBOSE_IRQ
 523         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 524                 return;
 525 #endif
 526         printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
 527
 528 #define PIS(x) \
 529         if (status & DSI_IRQ_##x) \
 530                 printk(#x " ");
 531 #ifdef VERBOSE_IRQ
 532         PIS(VC0);
 533         PIS(VC1);
 534         PIS(VC2);
 535         PIS(VC3);
 536 #endif
 537         PIS(WAKEUP);
 538         PIS(RESYNC);
 539         PIS(PLL_LOCK);
 540         PIS(PLL_UNLOCK);
 541         PIS(PLL_RECALL);
 542         PIS(COMPLEXIO_ERR);
 543         PIS(HS_TX_TIMEOUT);
 544         PIS(LP_RX_TIMEOUT);
 545         PIS(TE_TRIGGER);
 546         PIS(ACK_TRIGGER);
 547         PIS(SYNC_LOST);
 548         PIS(LDO_POWER_GOOD);
 549         PIS(TA_TIMEOUT);
 550 #undef PIS
 551
 552         printk("\n");
 553 }
 554
 555 static void print_irq_status_vc(int channel, u32 status)
 556 {
 557         if (status == 0)
 558                 return;
 559
 560 #ifndef VERBOSE_IRQ
 561         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 562                 return;
 563 #endif
 564         printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
 565
 566 #define PIS(x) \
 567         if (status & DSI_VC_IRQ_##x) \
 568                 printk(#x " ");
 569         PIS(CS);
 570         PIS(ECC_CORR);
 571 #ifdef VERBOSE_IRQ
 572         PIS(PACKET_SENT);
 573 #endif
 574         PIS(FIFO_TX_OVF);
 575         PIS(FIFO_RX_OVF);
 576         PIS(BTA);
 577         PIS(ECC_NO_CORR);
 578         PIS(FIFO_TX_UDF);
 579         PIS(PP_BUSY_CHANGE);
 580 #undef PIS
 581         printk("\n");
 582 }
 583
 584 static void print_irq_status_cio(u32 status)
 585 {
 586         if (status == 0)
 587                 return;
 588
 589         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 590
 591 #define PIS(x) \
 592         if (status & DSI_CIO_IRQ_##x) \
 593                 printk(#x " ");
 594         PIS(ERRSYNCESC1);
 595         PIS(ERRSYNCESC2);
 596         PIS(ERRSYNCESC3);
 597         PIS(ERRESC1);
 598         PIS(ERRESC2);
 599         PIS(ERRESC3);
 600         PIS(ERRCONTROL1);
 601         PIS(ERRCONTROL2);
 602         PIS(ERRCONTROL3);
 603         PIS(STATEULPS1);
 604         PIS(STATEULPS2);
 605         PIS(STATEULPS3);
 606         PIS(ERRCONTENTIONLP0_1);
 607         PIS(ERRCONTENTIONLP1_1);
 608         PIS(ERRCONTENTIONLP0_2);
 609         PIS(ERRCONTENTIONLP1_2);
 610         PIS(ERRCONTENTIONLP0_3);
 611         PIS(ERRCONTENTIONLP1_3);
 612         PIS(ULPSACTIVENOT_ALL0);
 613         PIS(ULPSACTIVENOT_ALL1);
 614 #undef PIS
 615
 616         printk("\n");
 617 }
 618
 619 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 620 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 621                 u32 *vcstatus, u32 ciostatus)
 622 {
 623         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 624         int i;
 625
 626         spin_lock(&dsi->irq_stats_lock);
 627
 628         dsi->irq_stats.irq_count++;
 629         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 630
 631         for (i = 0; i < 4; ++i)
 632                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 633
 634         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 635
 636         spin_unlock(&dsi->irq_stats_lock);
 637 }
 638 #else
 639 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 640 #endif
 641
 642 static int debug_irq;
 643
 644 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 645                 u32 *vcstatus, u32 ciostatus)
 646 {
 647         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 648         int i;
 649
 650         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 651                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 652                 print_irq_status(irqstatus);
 653                 spin_lock(&dsi->errors_lock);
 654                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 655                 spin_unlock(&dsi->errors_lock);
 656         } else if (debug_irq) {
 657                 print_irq_status(irqstatus);
 658         }
 659
 660         for (i = 0; i < 4; ++i) {
 661                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 662                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 663                                        i, vcstatus[i]);
 664                         print_irq_status_vc(i, vcstatus[i]);
 665                 } else if (debug_irq) {
 666                         print_irq_status_vc(i, vcstatus[i]);
 667                 }
 668         }
 669
 670         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 671                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 672                 print_irq_status_cio(ciostatus);
 673         } else if (debug_irq) {
 674                 print_irq_status_cio(ciostatus);
 675         }
 676 }
 677
 678 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 679                 unsigned isr_array_size, u32 irqstatus)
 680 {
 681         struct dsi_isr_data *isr_data;
 682         int i;
 683
 684         for (i = 0; i < isr_array_size; i++) {
 685                 isr_data = &isr_array[i];
 686                 if (isr_data->isr && isr_data->mask & irqstatus)
 687                         isr_data->isr(isr_data->arg, irqstatus);
 688         }
 689 }
 690
 691 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 692                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 693 {
 694         int i;
 695
 696         dsi_call_isrs(isr_tables->isr_table,
 697                         ARRAY_SIZE(isr_tables->isr_table),
 698                         irqstatus);
 699
 700         for (i = 0; i < 4; ++i) {
 701                 if (vcstatus[i] == 0)
 702                         continue;
 703                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 704                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 705                                 vcstatus[i]);
 706         }
 707
 708         if (ciostatus != 0)
 709                 dsi_call_isrs(isr_tables->isr_table_cio,
 710                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 711                                 ciostatus);
 712 }
 713
 714 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 715 {
 716         struct platform_device *dsidev;
 717         struct dsi_data *dsi;
 718         u32 irqstatus, vcstatus[4], ciostatus;
 719         int i;
 720
 721         dsidev = (struct platform_device *) arg;
 722         dsi = dsi_get_dsidrv_data(dsidev);
 723
 724         spin_lock(&dsi->irq_lock);
 725
 726         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 727
 728         /* IRQ is not for us */
 729         if (!irqstatus) {
 730                 spin_unlock(&dsi->irq_lock);
 731                 return IRQ_NONE;
 732         }
 733
 734         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 735         /* flush posted write */
 736         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 737
 738         for (i = 0; i < 4; ++i) {
 739                 if ((irqstatus & (1 << i)) == 0) {
 740                         vcstatus[i] = 0;
 741                         continue;
 742                 }
 743
 744                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 745
 746                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 747                 /* flush posted write */
 748                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 749         }
 750
 751         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 752                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 753
 754                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 755                 /* flush posted write */
 756                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 757         } else {
 758                 ciostatus = 0;
 759         }
 760
 761 #ifdef DSI_CATCH_MISSING_TE
 762         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 763                 del_timer(&dsi->te_timer);
 764 #endif
 765
 766         /* make a copy and unlock, so that isrs can unregister
 767          * themselves */
 768         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 769                 sizeof(dsi->isr_tables));
 770
 771         spin_unlock(&dsi->irq_lock);
 772
 773         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 774
 775         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 776
 777         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 778
 779         return IRQ_HANDLED;
 780 }
 781
 782 /* dsi->irq_lock has to be locked by the caller */
 783 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 784                 struct dsi_isr_data *isr_array,
 785                 unsigned isr_array_size, u32 default_mask,
 786                 const struct dsi_reg enable_reg,
 787                 const struct dsi_reg status_reg)
 788 {
 789         struct dsi_isr_data *isr_data;
 790         u32 mask;
 791         u32 old_mask;
 792         int i;
 793
 794         mask = default_mask;
 795
 796         for (i = 0; i < isr_array_size; i++) {
 797                 isr_data = &isr_array[i];
 798
 799                 if (isr_data->isr == NULL)
 800                         continue;
 801
 802                 mask |= isr_data->mask;
 803         }
 804
 805         old_mask = dsi_read_reg(dsidev, enable_reg);
 806         /* clear the irqstatus for newly enabled irqs */
 807         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 808         dsi_write_reg(dsidev, enable_reg, mask);
 809
 810         /* flush posted writes */
 811         dsi_read_reg(dsidev, enable_reg);
 812         dsi_read_reg(dsidev, status_reg);
 813 }
 814
 815 /* dsi->irq_lock has to be locked by the caller */
 816 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 817 {
 818         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 819         u32 mask = DSI_IRQ_ERROR_MASK;
 820 #ifdef DSI_CATCH_MISSING_TE
 821         mask |= DSI_IRQ_TE_TRIGGER;
 822 #endif
 823         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 824                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 825                         DSI_IRQENABLE, DSI_IRQSTATUS);
 826 }
 827
 828 /* dsi->irq_lock has to be locked by the caller */
 829 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 830 {
 831         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 832
 833         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 834                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 835                         DSI_VC_IRQ_ERROR_MASK,
 836                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 837 }
 838
 839 /* dsi->irq_lock has to be locked by the caller */
 840 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 841 {
 842         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 843
 844         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 845                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 846                         DSI_CIO_IRQ_ERROR_MASK,
 847                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 848 }
 849
 850 static void _dsi_initialize_irq(struct platform_device *dsidev)
 851 {
 852         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 853         unsigned long flags;
 854         int vc;
 855
 856         spin_lock_irqsave(&dsi->irq_lock, flags);
 857
 858         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 859
 860         _omap_dsi_set_irqs(dsidev);
 861         for (vc = 0; vc < 4; ++vc)
 862                 _omap_dsi_set_irqs_vc(dsidev, vc);
 863         _omap_dsi_set_irqs_cio(dsidev);
 864
 865         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 866 }
 867
 868 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 869                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 870 {
 871         struct dsi_isr_data *isr_data;
 872         int free_idx;
 873         int i;
 874
 875         BUG_ON(isr == NULL);
 876
 877         /* check for duplicate entry and find a free slot */
 878         free_idx = -1;
 879         for (i = 0; i < isr_array_size; i++) {
 880                 isr_data = &isr_array[i];
 881
 882                 if (isr_data->isr == isr && isr_data->arg == arg &&
 883                                 isr_data->mask == mask) {
 884                         return -EINVAL;
 885                 }
 886
 887                 if (isr_data->isr == NULL && free_idx == -1)
 888                         free_idx = i;
 889         }
 890
 891         if (free_idx == -1)
 892                 return -EBUSY;
 893
 894         isr_data = &isr_array[free_idx];
 895         isr_data->isr = isr;
 896         isr_data->arg = arg;
 897         isr_data->mask = mask;
 898
 899         return 0;
 900 }
 901
 902 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 903                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 904 {
 905         struct dsi_isr_data *isr_data;
 906         int i;
 907
 908         for (i = 0; i < isr_array_size; i++) {
 909                 isr_data = &isr_array[i];
 910                 if (isr_data->isr != isr || isr_data->arg != arg ||
 911                                 isr_data->mask != mask)
 912                         continue;
 913
 914                 isr_data->isr = NULL;
 915                 isr_data->arg = NULL;
 916                 isr_data->mask = 0;
 917
 918                 return 0;
 919         }
 920
 921         return -EINVAL;
 922 }
 923
 924 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 925                 void *arg, u32 mask)
 926 {
 927         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 928         unsigned long flags;
 929         int r;
 930
 931         spin_lock_irqsave(&dsi->irq_lock, flags);
 932
 933         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 934                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 935
 936         if (r == 0)
 937                 _omap_dsi_set_irqs(dsidev);
 938
 939         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 940
 941         return r;
 942 }
 943
 944 static int dsi_unregister_isr(struct platform_device *dsidev,
 945                 omap_dsi_isr_t isr, void *arg, u32 mask)
 946 {
 947         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 948         unsigned long flags;
 949         int r;
 950
 951         spin_lock_irqsave(&dsi->irq_lock, flags);
 952
 953         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 954                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 955
 956         if (r == 0)
 957                 _omap_dsi_set_irqs(dsidev);
 958
 959         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 960
 961         return r;
 962 }
 963
 964 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 965                 omap_dsi_isr_t isr, void *arg, u32 mask)
 966 {
 967         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 968         unsigned long flags;
 969         int r;
 970
 971         spin_lock_irqsave(&dsi->irq_lock, flags);
 972
 973         r = _dsi_register_isr(isr, arg, mask,
 974                         dsi->isr_tables.isr_table_vc[channel],
 975                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 976
 977         if (r == 0)
 978                 _omap_dsi_set_irqs_vc(dsidev, channel);
 979
 980         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 981
 982         return r;
 983 }
 984
 985 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 986                 omap_dsi_isr_t isr, void *arg, u32 mask)
 987 {
 988         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 989         unsigned long flags;
 990         int r;
 991
 992         spin_lock_irqsave(&dsi->irq_lock, flags);
 993
 994         r = _dsi_unregister_isr(isr, arg, mask,
 995                         dsi->isr_tables.isr_table_vc[channel],
 996                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 997
 998         if (r == 0)
 999                 _omap_dsi_set_irqs_vc(dsidev, channel);
1000
1001         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1002
1003         return r;
1004 }
1005
1006 static int dsi_register_isr_cio(struct platform_device *dsidev,
1007                 omap_dsi_isr_t isr, void *arg, u32 mask)
1008 {
1009         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1010         unsigned long flags;
1011         int r;
1012
1013         spin_lock_irqsave(&dsi->irq_lock, flags);
1014
1015         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1016                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1017
1018         if (r == 0)
1019                 _omap_dsi_set_irqs_cio(dsidev);
1020
1021         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1022
1023         return r;
1024 }
1025
1026 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1027                 omap_dsi_isr_t isr, void *arg, u32 mask)
1028 {
1029         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1030         unsigned long flags;
1031         int r;
1032
1033         spin_lock_irqsave(&dsi->irq_lock, flags);
1034
1035         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1036                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1037
1038         if (r == 0)
1039                 _omap_dsi_set_irqs_cio(dsidev);
1040
1041         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1042
1043         return r;
1044 }
1045
1046 static u32 dsi_get_errors(struct platform_device *dsidev)
1047 {
1048         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1049         unsigned long flags;
1050         u32 e;
1051         spin_lock_irqsave(&dsi->errors_lock, flags);
1052         e = dsi->errors;
1053         dsi->errors = 0;
1054         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1055         return e;
1056 }
1057
1058 int dsi_runtime_get(struct platform_device *dsidev)
1059 {
1060         int r;
1061         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1062
1063         DSSDBG("dsi_runtime_get\n");
1064
1065         r = pm_runtime_get_sync(&dsi->pdev->dev);
1066         WARN_ON(r < 0);
1067         return r < 0 ? r : 0;
1068 }
1069
1070 void dsi_runtime_put(struct platform_device *dsidev)
1071 {
1072         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1073         int r;
1074
1075         DSSDBG("dsi_runtime_put\n");
1076
1077         r = pm_runtime_put_sync(&dsi->pdev->dev);
1078         WARN_ON(r < 0 && r != -ENOSYS);
1079 }
1080
1081 /* source clock for DSI PLL. this could also be PCLKFREE */
1082 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1083                 bool enable)
1084 {
1085         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1086
1087         if (enable)
1088                 clk_enable(dsi->sys_clk);
1089         else
1090                 clk_disable(dsi->sys_clk);
1091
1092         if (enable && dsi->pll_locked) {
1093                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1094                         DSSERR("cannot lock PLL when enabling clocks\n");
1095         }
1096 }
1097
1098 #ifdef DEBUG
1099 static void _dsi_print_reset_status(struct platform_device *dsidev)
1100 {
1101         u32 l;
1102         int b0, b1, b2;
1103
1104         if (!dss_debug)
1105                 return;
1106
1107         /* A dummy read using the SCP interface to any DSIPHY register is
1108          * required after DSIPHY reset to complete the reset of the DSI complex
1109          * I/O. */
1110         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1111
1112         printk(KERN_DEBUG "DSI resets: ");
1113
1114         l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1115         printk("PLL (%d) ", FLD_GET(l, 0, 0));
1116
1117         l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1118         printk("CIO (%d) ", FLD_GET(l, 29, 29));
1119
1120         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1121                 b0 = 28;
1122                 b1 = 27;
1123                 b2 = 26;
1124         } else {
1125                 b0 = 24;
1126                 b1 = 25;
1127                 b2 = 26;
1128         }
1129
1130         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1131         printk("PHY (%x%x%x, %d, %d, %d)\n",
1132                         FLD_GET(l, b0, b0),
1133                         FLD_GET(l, b1, b1),
1134                         FLD_GET(l, b2, b2),
1135                         FLD_GET(l, 29, 29),
1136                         FLD_GET(l, 30, 30),
1137                         FLD_GET(l, 31, 31));
1138 }
1139 #else
1140 #define _dsi_print_reset_status(x)
1141 #endif
1142
1143 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1144 {
1145         DSSDBG("dsi_if_enable(%d)\n", enable);
1146
1147         enable = enable ? 1 : 0;
1148         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1149
1150         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1151                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1152                         return -EIO;
1153         }
1154
1155         return 0;
1156 }
1157
1158 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1159 {
1160         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1161
1162         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1163 }
1164
1165 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1166 {
1167         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1168
1169         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1170 }
1171
1172 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1173 {
1174         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1175
1176         return dsi->current_cinfo.clkin4ddr / 16;
1177 }
1178
1179 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1180 {
1181         unsigned long r;
1182         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1183
1184         if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1185                 /* DSI FCLK source is DSS_CLK_FCK */
1186                 r = clk_get_rate(dsi->dss_clk);
1187         } else {
1188                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1189                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1190         }
1191
1192         return r;
1193 }
1194
1195 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1196 {
1197         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1198         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1199         unsigned long dsi_fclk;
1200         unsigned lp_clk_div;
1201         unsigned long lp_clk;
1202
1203         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1204
1205         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1206                 return -EINVAL;
1207
1208         dsi_fclk = dsi_fclk_rate(dsidev);
1209
1210         lp_clk = dsi_fclk / 2 / lp_clk_div;
1211
1212         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1213         dsi->current_cinfo.lp_clk = lp_clk;
1214         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1215
1216         /* LP_CLK_DIVISOR */
1217         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1218
1219         /* LP_RX_SYNCHRO_ENABLE */
1220         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1221
1222         return 0;
1223 }
1224
1225 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1226 {
1227         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1228
1229         if (dsi->scp_clk_refcount++ == 0)
1230                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1231 }
1232
1233 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1234 {
1235         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1236
1237         WARN_ON(dsi->scp_clk_refcount == 0);
1238         if (--dsi->scp_clk_refcount == 0)
1239                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1240 }
1241
1242 enum dsi_pll_power_state {
1243         DSI_PLL_POWER_OFF       = 0x0,
1244         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1245         DSI_PLL_POWER_ON_ALL    = 0x2,
1246         DSI_PLL_POWER_ON_DIV    = 0x3,
1247 };
1248
1249 static int dsi_pll_power(struct platform_device *dsidev,
1250                 enum dsi_pll_power_state state)
1251 {
1252         int t = 0;
1253
1254         /* DSI-PLL power command 0x3 is not working */
1255         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1256                         state == DSI_PLL_POWER_ON_DIV)
1257                 state = DSI_PLL_POWER_ON_ALL;
1258
1259         /* PLL_PWR_CMD */
1260         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1261
1262         /* PLL_PWR_STATUS */
1263         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1264                 if (++t > 1000) {
1265                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1266                                         state);
1267                         return -ENODEV;
1268                 }
1269                 udelay(1);
1270         }
1271
1272         return 0;
1273 }
1274
1275 /* calculate clock rates using dividers in cinfo */
1276 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1277                 struct dsi_clock_info *cinfo)
1278 {
1279         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1280
1281         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1282                 return -EINVAL;
1283
1284         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1285                 return -EINVAL;
1286
1287         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1288                 return -EINVAL;
1289
1290         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1291                 return -EINVAL;
1292
1293         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1294         cinfo->fint = cinfo->clkin / cinfo->regn;
1295
1296         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1297                 return -EINVAL;
1298
1299         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1300
1301         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1302                 return -EINVAL;
1303
1304         if (cinfo->regm_dispc > 0)
1305                 cinfo->dsi_pll_hsdiv_dispc_clk =
1306                         cinfo->clkin4ddr / cinfo->regm_dispc;
1307         else
1308                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1309
1310         if (cinfo->regm_dsi > 0)
1311                 cinfo->dsi_pll_hsdiv_dsi_clk =
1312                         cinfo->clkin4ddr / cinfo->regm_dsi;
1313         else
1314                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1315
1316         return 0;
1317 }
1318
1319 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1320                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1321                 struct dispc_clock_info *dispc_cinfo)
1322 {
1323         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1324         struct dsi_clock_info cur, best;
1325         struct dispc_clock_info best_dispc;
1326         int min_fck_per_pck;
1327         int match = 0;
1328         unsigned long dss_sys_clk, max_dss_fck;
1329
1330         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1331
1332         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1333
1334         if (req_pck == dsi->cache_req_pck &&
1335                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1336                 DSSDBG("DSI clock info found from cache\n");
1337                 *dsi_cinfo = dsi->cache_cinfo;
1338                 dispc_find_clk_divs(is_tft, req_pck,
1339                         dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1340                 return 0;
1341         }
1342
1343         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1344
1345         if (min_fck_per_pck &&
1346                 req_pck * min_fck_per_pck > max_dss_fck) {
1347                 DSSERR("Requested pixel clock not possible with the current "
1348                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1349                                 "the constraint off.\n");
1350                 min_fck_per_pck = 0;
1351         }
1352
1353         DSSDBG("dsi_pll_calc\n");
1354
1355 retry:
1356         memset(&best, 0, sizeof(best));
1357         memset(&best_dispc, 0, sizeof(best_dispc));
1358
1359         memset(&cur, 0, sizeof(cur));
1360         cur.clkin = dss_sys_clk;
1361
1362         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1363         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1364         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1365                 cur.fint = cur.clkin / cur.regn;
1366
1367                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1368                         continue;
1369
1370                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1371                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1372                         unsigned long a, b;
1373
1374                         a = 2 * cur.regm * (cur.clkin/1000);
1375                         b = cur.regn;
1376                         cur.clkin4ddr = a / b * 1000;
1377
1378                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1379                                 break;
1380
1381                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1382                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1383                         for (cur.regm_dispc = 1; cur.regm_dispc <
1384                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1385                                 struct dispc_clock_info cur_dispc;
1386                                 cur.dsi_pll_hsdiv_dispc_clk =
1387                                         cur.clkin4ddr / cur.regm_dispc;
1388
1389                                 /* this will narrow down the search a bit,
1390                                  * but still give pixclocks below what was
1391                                  * requested */
1392                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1393                                         break;
1394
1395                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1396                                         continue;
1397
1398                                 if (min_fck_per_pck &&
1399                                         cur.dsi_pll_hsdiv_dispc_clk <
1400                                                 req_pck * min_fck_per_pck)
1401                                         continue;
1402
1403                                 match = 1;
1404
1405                                 dispc_find_clk_divs(is_tft, req_pck,
1406                                                 cur.dsi_pll_hsdiv_dispc_clk,
1407                                                 &cur_dispc);
1408
1409                                 if (abs(cur_dispc.pck - req_pck) <
1410                                                 abs(best_dispc.pck - req_pck)) {
1411                                         best = cur;
1412                                         best_dispc = cur_dispc;
1413
1414                                         if (cur_dispc.pck == req_pck)
1415                                                 goto found;
1416                                 }
1417                         }
1418                 }
1419         }
1420 found:
1421         if (!match) {
1422                 if (min_fck_per_pck) {
1423                         DSSERR("Could not find suitable clock settings.\n"
1424                                         "Turning FCK/PCK constraint off and"
1425                                         "trying again.\n");
1426                         min_fck_per_pck = 0;
1427                         goto retry;
1428                 }
1429
1430                 DSSERR("Could not find suitable clock settings.\n");
1431
1432                 return -EINVAL;
1433         }
1434
1435         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1436         best.regm_dsi = 0;
1437         best.dsi_pll_hsdiv_dsi_clk = 0;
1438
1439         if (dsi_cinfo)
1440                 *dsi_cinfo = best;
1441         if (dispc_cinfo)
1442                 *dispc_cinfo = best_dispc;
1443
1444         dsi->cache_req_pck = req_pck;
1445         dsi->cache_clk_freq = 0;
1446         dsi->cache_cinfo = best;
1447
1448         return 0;
1449 }
1450
1451 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1452                 struct dsi_clock_info *cinfo)
1453 {
1454         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1455         int r = 0;
1456         u32 l;
1457         int f = 0;
1458         u8 regn_start, regn_end, regm_start, regm_end;
1459         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1460
1461         DSSDBGF();
1462
1463         dsi->current_cinfo.clkin = cinfo->clkin;
1464         dsi->current_cinfo.fint = cinfo->fint;
1465         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1466         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1467                         cinfo->dsi_pll_hsdiv_dispc_clk;
1468         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1469                         cinfo->dsi_pll_hsdiv_dsi_clk;
1470
1471         dsi->current_cinfo.regn = cinfo->regn;
1472         dsi->current_cinfo.regm = cinfo->regm;
1473         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1474         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1475
1476         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1477
1478         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1479
1480         /* DSIPHY == CLKIN4DDR */
1481         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1482                         cinfo->regm,
1483                         cinfo->regn,
1484                         cinfo->clkin,
1485                         cinfo->clkin4ddr);
1486
1487         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1488                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1489
1490         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1491
1492         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1493                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1494                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1495                 cinfo->dsi_pll_hsdiv_dispc_clk);
1496         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1497                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1498                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1499                 cinfo->dsi_pll_hsdiv_dsi_clk);
1500
1501         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1502         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1503         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1504                         &regm_dispc_end);
1505         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1506                         &regm_dsi_end);
1507
1508         /* DSI_PLL_AUTOMODE = manual */
1509         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1510
1511         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1512         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1513         /* DSI_PLL_REGN */
1514         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1515         /* DSI_PLL_REGM */
1516         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1517         /* DSI_CLOCK_DIV */
1518         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1519                         regm_dispc_start, regm_dispc_end);
1520         /* DSIPROTO_CLOCK_DIV */
1521         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1522                         regm_dsi_start, regm_dsi_end);
1523         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1524
1525         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1526
1527         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1528                 f = cinfo->fint < 1000000 ? 0x3 :
1529                         cinfo->fint < 1250000 ? 0x4 :
1530                         cinfo->fint < 1500000 ? 0x5 :
1531                         cinfo->fint < 1750000 ? 0x6 :
1532                         0x7;
1533         }
1534
1535         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1536
1537         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1538                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1539         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1540         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1541         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1542         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1543
1544         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1545
1546         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1547                 DSSERR("dsi pll go bit not going down.\n");
1548                 r = -EIO;
1549                 goto err;
1550         }
1551
1552         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1553                 DSSERR("cannot lock PLL\n");
1554                 r = -EIO;
1555                 goto err;
1556         }
1557
1558         dsi->pll_locked = 1;
1559
1560         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1561         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1562         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1563         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1564         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1565         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1566         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1567         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1568         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1569         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1570         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1571         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1572         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1573         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1574         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1575         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1576
1577         DSSDBG("PLL config done\n");
1578 err:
1579         return r;
1580 }
1581
1582 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1583                 bool enable_hsdiv)
1584 {
1585         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1586         int r = 0;
1587         enum dsi_pll_power_state pwstate;
1588
1589         DSSDBG("PLL init\n");
1590
1591         if (dsi->vdds_dsi_reg == NULL) {
1592                 struct regulator *vdds_dsi;
1593
1594                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1595
1596                 if (IS_ERR(vdds_dsi)) {
1597                         DSSERR("can't get VDDS_DSI regulator\n");
1598                         return PTR_ERR(vdds_dsi);
1599                 }
1600
1601                 dsi->vdds_dsi_reg = vdds_dsi;
1602         }
1603
1604         dsi_enable_pll_clock(dsidev, 1);
1605         /*
1606          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1607          */
1608         dsi_enable_scp_clk(dsidev);
1609
1610         if (!dsi->vdds_dsi_enabled) {
1611                 r = regulator_enable(dsi->vdds_dsi_reg);
1612                 if (r)
1613                         goto err0;
1614                 dsi->vdds_dsi_enabled = true;
1615         }
1616
1617         /* XXX PLL does not come out of reset without this... */
1618         dispc_pck_free_enable(1);
1619
1620         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1621                 DSSERR("PLL not coming out of reset.\n");
1622                 r = -ENODEV;
1623                 dispc_pck_free_enable(0);
1624                 goto err1;
1625         }
1626
1627         /* XXX ... but if left on, we get problems when planes do not
1628          * fill the whole display. No idea about this */
1629         dispc_pck_free_enable(0);
1630
1631         if (enable_hsclk && enable_hsdiv)
1632                 pwstate = DSI_PLL_POWER_ON_ALL;
1633         else if (enable_hsclk)
1634                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1635         else if (enable_hsdiv)
1636                 pwstate = DSI_PLL_POWER_ON_DIV;
1637         else
1638                 pwstate = DSI_PLL_POWER_OFF;
1639
1640         r = dsi_pll_power(dsidev, pwstate);
1641
1642         if (r)
1643                 goto err1;
1644
1645         DSSDBG("PLL init done\n");
1646
1647         return 0;
1648 err1:
1649         if (dsi->vdds_dsi_enabled) {
1650                 regulator_disable(dsi->vdds_dsi_reg);
1651                 dsi->vdds_dsi_enabled = false;
1652         }
1653 err0:
1654         dsi_disable_scp_clk(dsidev);
1655         dsi_enable_pll_clock(dsidev, 0);
1656         return r;
1657 }
1658
1659 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1660 {
1661         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1662
1663         dsi->pll_locked = 0;
1664         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1665         if (disconnect_lanes) {
1666                 WARN_ON(!dsi->vdds_dsi_enabled);
1667                 regulator_disable(dsi->vdds_dsi_reg);
1668                 dsi->vdds_dsi_enabled = false;
1669         }
1670
1671         dsi_disable_scp_clk(dsidev);
1672         dsi_enable_pll_clock(dsidev, 0);
1673
1674         DSSDBG("PLL uninit done\n");
1675 }
1676
1677 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1678                 struct seq_file *s)
1679 {
1680         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1681         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1682         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1683         int dsi_module = dsi->module_id;
1684
1685         dispc_clk_src = dss_get_dispc_clk_source();
1686         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1687
1688         if (dsi_runtime_get(dsidev))
1689                 return;
1690
1691         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1692
1693         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1694
1695         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1696
1697         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1698                         cinfo->clkin4ddr, cinfo->regm);
1699
1700         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1701                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1702                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1703                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1704                         cinfo->dsi_pll_hsdiv_dispc_clk,
1705                         cinfo->regm_dispc,
1706                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1707                         "off" : "on");
1708
1709         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1710                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1711                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1712                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1713                         cinfo->dsi_pll_hsdiv_dsi_clk,
1714                         cinfo->regm_dsi,
1715                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1716                         "off" : "on");
1717
1718         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1719
1720         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1721                         dss_get_generic_clk_source_name(dsi_clk_src),
1722                         dss_feat_get_clk_source_name(dsi_clk_src));
1723
1724         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1725
1726         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1727                         cinfo->clkin4ddr / 4);
1728
1729         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1730
1731         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1732
1733         dsi_runtime_put(dsidev);
1734 }
1735
1736 void dsi_dump_clocks(struct seq_file *s)
1737 {
1738         struct platform_device *dsidev;
1739         int i;
1740
1741         for  (i = 0; i < MAX_NUM_DSI; i++) {
1742                 dsidev = dsi_get_dsidev_from_id(i);
1743                 if (dsidev)
1744                         dsi_dump_dsidev_clocks(dsidev, s);
1745         }
1746 }
1747
1748 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1749 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1750                 struct seq_file *s)
1751 {
1752         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1753         unsigned long flags;
1754         struct dsi_irq_stats stats;
1755
1756         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1757
1758         stats = dsi->irq_stats;
1759         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1760         dsi->irq_stats.last_reset = jiffies;
1761
1762         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1763
1764         seq_printf(s, "period %u ms\n",
1765                         jiffies_to_msecs(jiffies - stats.last_reset));
1766
1767         seq_printf(s, "irqs %d\n", stats.irq_count);
1768 #define PIS(x) \
1769         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1770
1771         seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1772         PIS(VC0);
1773         PIS(VC1);
1774         PIS(VC2);
1775         PIS(VC3);
1776         PIS(WAKEUP);
1777         PIS(RESYNC);
1778         PIS(PLL_LOCK);
1779         PIS(PLL_UNLOCK);
1780         PIS(PLL_RECALL);
1781         PIS(COMPLEXIO_ERR);
1782         PIS(HS_TX_TIMEOUT);
1783         PIS(LP_RX_TIMEOUT);
1784         PIS(TE_TRIGGER);
1785         PIS(ACK_TRIGGER);
1786         PIS(SYNC_LOST);
1787         PIS(LDO_POWER_GOOD);
1788         PIS(TA_TIMEOUT);
1789 #undef PIS
1790
1791 #define PIS(x) \
1792         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1793                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1794                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1795                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1796                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1797
1798         seq_printf(s, "-- VC interrupts --\n");
1799         PIS(CS);
1800         PIS(ECC_CORR);
1801         PIS(PACKET_SENT);
1802         PIS(FIFO_TX_OVF);
1803         PIS(FIFO_RX_OVF);
1804         PIS(BTA);
1805         PIS(ECC_NO_CORR);
1806         PIS(FIFO_TX_UDF);
1807         PIS(PP_BUSY_CHANGE);
1808 #undef PIS
1809
1810 #define PIS(x) \
1811         seq_printf(s, "%-20s %10d\n", #x, \
1812                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1813
1814         seq_printf(s, "-- CIO interrupts --\n");
1815         PIS(ERRSYNCESC1);
1816         PIS(ERRSYNCESC2);
1817         PIS(ERRSYNCESC3);
1818         PIS(ERRESC1);
1819         PIS(ERRESC2);
1820         PIS(ERRESC3);
1821         PIS(ERRCONTROL1);
1822         PIS(ERRCONTROL2);
1823         PIS(ERRCONTROL3);
1824         PIS(STATEULPS1);
1825         PIS(STATEULPS2);
1826         PIS(STATEULPS3);
1827         PIS(ERRCONTENTIONLP0_1);
1828         PIS(ERRCONTENTIONLP1_1);
1829         PIS(ERRCONTENTIONLP0_2);
1830         PIS(ERRCONTENTIONLP1_2);
1831         PIS(ERRCONTENTIONLP0_3);
1832         PIS(ERRCONTENTIONLP1_3);
1833         PIS(ULPSACTIVENOT_ALL0);
1834         PIS(ULPSACTIVENOT_ALL1);
1835 #undef PIS
1836 }
1837
1838 static void dsi1_dump_irqs(struct seq_file *s)
1839 {
1840         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1841
1842         dsi_dump_dsidev_irqs(dsidev, s);
1843 }
1844
1845 static void dsi2_dump_irqs(struct seq_file *s)
1846 {
1847         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1848
1849         dsi_dump_dsidev_irqs(dsidev, s);
1850 }
1851 #endif
1852
1853 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1854                 struct seq_file *s)
1855 {
1856 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1857
1858         if (dsi_runtime_get(dsidev))
1859                 return;
1860         dsi_enable_scp_clk(dsidev);
1861
1862         DUMPREG(DSI_REVISION);
1863         DUMPREG(DSI_SYSCONFIG);
1864         DUMPREG(DSI_SYSSTATUS);
1865         DUMPREG(DSI_IRQSTATUS);
1866         DUMPREG(DSI_IRQENABLE);
1867         DUMPREG(DSI_CTRL);
1868         DUMPREG(DSI_COMPLEXIO_CFG1);
1869         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1870         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1871         DUMPREG(DSI_CLK_CTRL);
1872         DUMPREG(DSI_TIMING1);
1873         DUMPREG(DSI_TIMING2);
1874         DUMPREG(DSI_VM_TIMING1);
1875         DUMPREG(DSI_VM_TIMING2);
1876         DUMPREG(DSI_VM_TIMING3);
1877         DUMPREG(DSI_CLK_TIMING);
1878         DUMPREG(DSI_TX_FIFO_VC_SIZE);
1879         DUMPREG(DSI_RX_FIFO_VC_SIZE);
1880         DUMPREG(DSI_COMPLEXIO_CFG2);
1881         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1882         DUMPREG(DSI_VM_TIMING4);
1883         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1884         DUMPREG(DSI_VM_TIMING5);
1885         DUMPREG(DSI_VM_TIMING6);
1886         DUMPREG(DSI_VM_TIMING7);
1887         DUMPREG(DSI_STOPCLK_TIMING);
1888
1889         DUMPREG(DSI_VC_CTRL(0));
1890         DUMPREG(DSI_VC_TE(0));
1891         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1892         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1893         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1894         DUMPREG(DSI_VC_IRQSTATUS(0));
1895         DUMPREG(DSI_VC_IRQENABLE(0));
1896
1897         DUMPREG(DSI_VC_CTRL(1));
1898         DUMPREG(DSI_VC_TE(1));
1899         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1900         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1901         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1902         DUMPREG(DSI_VC_IRQSTATUS(1));
1903         DUMPREG(DSI_VC_IRQENABLE(1));
1904
1905         DUMPREG(DSI_VC_CTRL(2));
1906         DUMPREG(DSI_VC_TE(2));
1907         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1908         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1909         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1910         DUMPREG(DSI_VC_IRQSTATUS(2));
1911         DUMPREG(DSI_VC_IRQENABLE(2));
1912
1913         DUMPREG(DSI_VC_CTRL(3));
1914         DUMPREG(DSI_VC_TE(3));
1915         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1916         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1917         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1918         DUMPREG(DSI_VC_IRQSTATUS(3));
1919         DUMPREG(DSI_VC_IRQENABLE(3));
1920
1921         DUMPREG(DSI_DSIPHY_CFG0);
1922         DUMPREG(DSI_DSIPHY_CFG1);
1923         DUMPREG(DSI_DSIPHY_CFG2);
1924         DUMPREG(DSI_DSIPHY_CFG5);
1925
1926         DUMPREG(DSI_PLL_CONTROL);
1927         DUMPREG(DSI_PLL_STATUS);
1928         DUMPREG(DSI_PLL_GO);
1929         DUMPREG(DSI_PLL_CONFIGURATION1);
1930         DUMPREG(DSI_PLL_CONFIGURATION2);
1931
1932         dsi_disable_scp_clk(dsidev);
1933         dsi_runtime_put(dsidev);
1934 #undef DUMPREG
1935 }
1936
1937 static void dsi1_dump_regs(struct seq_file *s)
1938 {
1939         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1940
1941         dsi_dump_dsidev_regs(dsidev, s);
1942 }
1943
1944 static void dsi2_dump_regs(struct seq_file *s)
1945 {
1946         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1947
1948         dsi_dump_dsidev_regs(dsidev, s);
1949 }
1950
1951 enum dsi_cio_power_state {
1952         DSI_COMPLEXIO_POWER_OFF         = 0x0,
1953         DSI_COMPLEXIO_POWER_ON          = 0x1,
1954         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
1955 };
1956
1957 static int dsi_cio_power(struct platform_device *dsidev,
1958                 enum dsi_cio_power_state state)
1959 {
1960         int t = 0;
1961
1962         /* PWR_CMD */
1963         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1964
1965         /* PWR_STATUS */
1966         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1967                         26, 25) != state) {
1968                 if (++t > 1000) {
1969                         DSSERR("failed to set complexio power state to "
1970                                         "%d\n", state);
1971                         return -ENODEV;
1972                 }
1973                 udelay(1);
1974         }
1975
1976         return 0;
1977 }
1978
1979 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1980 {
1981         int val;
1982
1983         /* line buffer on OMAP3 is 1024 x 24bits */
1984         /* XXX: for some reason using full buffer size causes
1985          * considerable TX slowdown with update sizes that fill the
1986          * whole buffer */
1987         if (!dss_has_feature(FEAT_DSI_GNQ))
1988                 return 1023 * 3;
1989
1990         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1991
1992         switch (val) {
1993         case 1:
1994                 return 512 * 3;         /* 512x24 bits */
1995         case 2:
1996                 return 682 * 3;         /* 682x24 bits */
1997         case 3:
1998                 return 853 * 3;         /* 853x24 bits */
1999         case 4:
2000                 return 1024 * 3;        /* 1024x24 bits */
2001         case 5:
2002                 return 1194 * 3;        /* 1194x24 bits */
2003         case 6:
2004                 return 1365 * 3;        /* 1365x24 bits */
2005         default:
2006                 BUG();
2007                 return 0;
2008         }
2009 }
2010
2011 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2012 {
2013         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2014         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2015         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2016         static const enum dsi_lane_function functions[] = {
2017                 DSI_LANE_CLK,
2018                 DSI_LANE_DATA1,
2019                 DSI_LANE_DATA2,
2020                 DSI_LANE_DATA3,
2021                 DSI_LANE_DATA4,
2022         };
2023         u32 r;
2024         int i;
2025
2026         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2027
2028         for (i = 0; i < dsi->num_lanes_used; ++i) {
2029                 unsigned offset = offsets[i];
2030                 unsigned polarity, lane_number;
2031                 unsigned t;
2032
2033                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2034                         if (dsi->lanes[t].function == functions[i])
2035                                 break;
2036
2037                 if (t == dsi->num_lanes_supported)
2038                         return -EINVAL;
2039
2040                 lane_number = t;
2041                 polarity = dsi->lanes[t].polarity;
2042
2043                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2044                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2045         }
2046
2047         /* clear the unused lanes */
2048         for (; i < dsi->num_lanes_supported; ++i) {
2049                 unsigned offset = offsets[i];
2050
2051                 r = FLD_MOD(r, 0, offset + 2, offset);
2052                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2053         }
2054
2055         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2056
2057         return 0;
2058 }
2059
2060 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2061 {
2062         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2063
2064         /* convert time in ns to ddr ticks, rounding up */
2065         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2066         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2067 }
2068
2069 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2070 {
2071         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2072
2073         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2074         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2075 }
2076
2077 static void dsi_cio_timings(struct platform_device *dsidev)
2078 {
2079         u32 r;
2080         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2081         u32 tlpx_half, tclk_trail, tclk_zero;
2082         u32 tclk_prepare;
2083
2084         /* calculate timings */
2085
2086         /* 1 * DDR_CLK = 2 * UI */
2087
2088         /* min 40ns + 4*UI      max 85ns + 6*UI */
2089         ths_prepare = ns2ddr(dsidev, 70) + 2;
2090
2091         /* min 145ns + 10*UI */
2092         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2093
2094         /* min max(8*UI, 60ns+4*UI) */
2095         ths_trail = ns2ddr(dsidev, 60) + 5;
2096
2097         /* min 100ns */
2098         ths_exit = ns2ddr(dsidev, 145);
2099
2100         /* tlpx min 50n */
2101         tlpx_half = ns2ddr(dsidev, 25);
2102
2103         /* min 60ns */
2104         tclk_trail = ns2ddr(dsidev, 60) + 2;
2105
2106         /* min 38ns, max 95ns */
2107         tclk_prepare = ns2ddr(dsidev, 65);
2108
2109         /* min tclk-prepare + tclk-zero = 300ns */
2110         tclk_zero = ns2ddr(dsidev, 260);
2111
2112         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2113                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2114                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2115         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2116                         ths_trail, ddr2ns(dsidev, ths_trail),
2117                         ths_exit, ddr2ns(dsidev, ths_exit));
2118
2119         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2120                         "tclk_zero %u (%uns)\n",
2121                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2122                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2123                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2124         DSSDBG("tclk_prepare %u (%uns)\n",
2125                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2126
2127         /* program timings */
2128
2129         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2130         r = FLD_MOD(r, ths_prepare, 31, 24);
2131         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2132         r = FLD_MOD(r, ths_trail, 15, 8);
2133         r = FLD_MOD(r, ths_exit, 7, 0);
2134         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2135
2136         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2137         r = FLD_MOD(r, tlpx_half, 22, 16);
2138         r = FLD_MOD(r, tclk_trail, 15, 8);
2139         r = FLD_MOD(r, tclk_zero, 7, 0);
2140         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2141
2142         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2143         r = FLD_MOD(r, tclk_prepare, 7, 0);
2144         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2145 }
2146
2147 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2148 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2149                 unsigned mask_p, unsigned mask_n)
2150 {
2151         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2152         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2153         int i;
2154         u32 l;
2155         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2156
2157         l = 0;
2158
2159         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2160                 unsigned p = dsi->lanes[i].polarity;
2161
2162                 if (mask_p & (1 << i))
2163                         l |= 1 << (i * 2 + (p ? 0 : 1));
2164
2165                 if (mask_n & (1 << i))
2166                         l |= 1 << (i * 2 + (p ? 1 : 0));
2167         }
2168
2169         /*
2170          * Bits in REGLPTXSCPDAT4TO0DXDY:
2171          * 17: DY0 18: DX0
2172          * 19: DY1 20: DX1
2173          * 21: DY2 22: DX2
2174          * 23: DY3 24: DX3
2175          * 25: DY4 26: DX4
2176          */
2177
2178         /* Set the lane override configuration */
2179
2180         /* REGLPTXSCPDAT4TO0DXDY */
2181         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2182
2183         /* Enable lane override */
2184
2185         /* ENLPTXSCPDAT */
2186         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2187 }
2188
2189 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2190 {
2191         /* Disable lane override */
2192         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2193         /* Reset the lane override configuration */
2194         /* REGLPTXSCPDAT4TO0DXDY */
2195         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2196 }
2197
2198 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2199 {
2200         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2201         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2202         int t, i;
2203         bool in_use[DSI_MAX_NR_LANES];
2204         static const u8 offsets_old[] = { 28, 27, 26 };
2205         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2206         const u8 *offsets;
2207
2208         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2209                 offsets = offsets_old;
2210         else
2211                 offsets = offsets_new;
2212
2213         for (i = 0; i < dsi->num_lanes_supported; ++i)
2214                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2215
2216         t = 100000;
2217         while (true) {
2218                 u32 l;
2219                 int ok;
2220
2221                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2222
2223                 ok = 0;
2224                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2225                         if (!in_use[i] || (l & (1 << offsets[i])))
2226                                 ok++;
2227                 }
2228
2229                 if (ok == dsi->num_lanes_supported)
2230                         break;
2231
2232                 if (--t == 0) {
2233                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2234                                 if (!in_use[i] || (l & (1 << offsets[i])))
2235                                         continue;
2236
2237                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2238                                                 "out of reset\n", i);
2239                         }
2240                         return -EIO;
2241                 }
2242         }
2243
2244         return 0;
2245 }
2246
2247 /* return bitmask of enabled lanes, lane0 being the lsb */
2248 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2249 {
2250         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2251         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2252         unsigned mask = 0;
2253         int i;
2254
2255         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2256                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2257                         mask |= 1 << i;
2258         }
2259
2260         return mask;
2261 }
2262
2263 static int dsi_cio_init(struct omap_dss_device *dssdev)
2264 {
2265         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2266         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2267         int r;
2268         u32 l;
2269
2270         DSSDBGF();
2271
2272         r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dssdev));
2273         if (r)
2274                 return r;
2275
2276         dsi_enable_scp_clk(dsidev);
2277
2278         /* A dummy read using the SCP interface to any DSIPHY register is
2279          * required after DSIPHY reset to complete the reset of the DSI complex
2280          * I/O. */
2281         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2282
2283         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2284                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2285                 r = -EIO;
2286                 goto err_scp_clk_dom;
2287         }
2288
2289         r = dsi_set_lane_config(dssdev);
2290         if (r)
2291                 goto err_scp_clk_dom;
2292
2293         /* set TX STOP MODE timer to maximum for this operation */
2294         l = dsi_read_reg(dsidev, DSI_TIMING1);
2295         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2296         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2297         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2298         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2299         dsi_write_reg(dsidev, DSI_TIMING1, l);
2300
2301         if (dsi->ulps_enabled) {
2302                 unsigned mask_p;
2303                 int i;
2304
2305                 DSSDBG("manual ulps exit\n");
2306
2307                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2308                  * stop state. DSS HW cannot do this via the normal
2309                  * ULPS exit sequence, as after reset the DSS HW thinks
2310                  * that we are not in ULPS mode, and refuses to send the
2311                  * sequence. So we need to send the ULPS exit sequence
2312                  * manually by setting positive lines high and negative lines
2313                  * low for 1ms.
2314                  */
2315
2316                 mask_p = 0;
2317
2318                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2319                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2320                                 continue;
2321                         mask_p |= 1 << i;
2322                 }
2323
2324                 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2325         }
2326
2327         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2328         if (r)
2329                 goto err_cio_pwr;
2330
2331         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2332                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2333                 r = -ENODEV;
2334                 goto err_cio_pwr_dom;
2335         }
2336
2337         dsi_if_enable(dsidev, true);
2338         dsi_if_enable(dsidev, false);
2339         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2340
2341         r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2342         if (r)
2343                 goto err_tx_clk_esc_rst;
2344
2345         if (dsi->ulps_enabled) {
2346                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2347                 ktime_t wait = ns_to_ktime(1000 * 1000);
2348                 set_current_state(TASK_UNINTERRUPTIBLE);
2349                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2350
2351                 /* Disable the override. The lanes should be set to Mark-11
2352                  * state by the HW */
2353                 dsi_cio_disable_lane_override(dsidev);
2354         }
2355
2356         /* FORCE_TX_STOP_MODE_IO */
2357         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2358
2359         dsi_cio_timings(dsidev);
2360
2361         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2362                 /* DDR_CLK_ALWAYS_ON */
2363                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2364                         dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2365         }
2366
2367         dsi->ulps_enabled = false;
2368
2369         DSSDBG("CIO init done\n");
2370
2371         return 0;
2372
2373 err_tx_clk_esc_rst:
2374         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2375 err_cio_pwr_dom:
2376         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2377 err_cio_pwr:
2378         if (dsi->ulps_enabled)
2379                 dsi_cio_disable_lane_override(dsidev);
2380 err_scp_clk_dom:
2381         dsi_disable_scp_clk(dsidev);
2382         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dssdev));
2383         return r;
2384 }
2385
2386 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2387 {
2388         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2389         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2390
2391         /* DDR_CLK_ALWAYS_ON */
2392         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2393
2394         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2395         dsi_disable_scp_clk(dsidev);
2396         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dssdev));
2397 }
2398
2399 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2400                 enum fifo_size size1, enum fifo_size size2,
2401                 enum fifo_size size3, enum fifo_size size4)
2402 {
2403         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2404         u32 r = 0;
2405         int add = 0;
2406         int i;
2407
2408         dsi->vc[0].fifo_size = size1;
2409         dsi->vc[1].fifo_size = size2;
2410         dsi->vc[2].fifo_size = size3;
2411         dsi->vc[3].fifo_size = size4;
2412
2413         for (i = 0; i < 4; i++) {
2414                 u8 v;
2415                 int size = dsi->vc[i].fifo_size;
2416
2417                 if (add + size > 4) {
2418                         DSSERR("Illegal FIFO configuration\n");
2419                         BUG();
2420                         return;
2421                 }
2422
2423                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2424                 r |= v << (8 * i);
2425                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2426                 add += size;
2427         }
2428
2429         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2430 }
2431
2432 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2433                 enum fifo_size size1, enum fifo_size size2,
2434                 enum fifo_size size3, enum fifo_size size4)
2435 {
2436         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2437         u32 r = 0;
2438         int add = 0;
2439         int i;
2440
2441         dsi->vc[0].fifo_size = size1;
2442         dsi->vc[1].fifo_size = size2;
2443         dsi->vc[2].fifo_size = size3;
2444         dsi->vc[3].fifo_size = size4;
2445
2446         for (i = 0; i < 4; i++) {
2447                 u8 v;
2448                 int size = dsi->vc[i].fifo_size;
2449
2450                 if (add + size > 4) {
2451                         DSSERR("Illegal FIFO configuration\n");
2452                         BUG();
2453                         return;
2454                 }
2455
2456                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2457                 r |= v << (8 * i);
2458                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2459                 add += size;
2460         }
2461
2462         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2463 }
2464
2465 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2466 {
2467         u32 r;
2468
2469         r = dsi_read_reg(dsidev, DSI_TIMING1);
2470         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2471         dsi_write_reg(dsidev, DSI_TIMING1, r);
2472
2473         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2474                 DSSERR("TX_STOP bit not going down\n");
2475                 return -EIO;
2476         }
2477
2478         return 0;
2479 }
2480
2481 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2482 {
2483         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2484 }
2485
2486 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2487 {
2488         struct dsi_packet_sent_handler_data *vp_data =
2489                 (struct dsi_packet_sent_handler_data *) data;
2490         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2491         const int channel = dsi->update_channel;
2492         u8 bit = dsi->te_enabled ? 30 : 31;
2493
2494         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2495                 complete(vp_data->completion);
2496 }
2497
2498 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2499 {
2500         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2501         DECLARE_COMPLETION_ONSTACK(completion);
2502         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2503         int r = 0;
2504         u8 bit;
2505
2506         bit = dsi->te_enabled ? 30 : 31;
2507
2508         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2509                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2510         if (r)
2511                 goto err0;
2512
2513         /* Wait for completion only if TE_EN/TE_START is still set */
2514         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2515                 if (wait_for_completion_timeout(&completion,
2516                                 msecs_to_jiffies(10)) == 0) {
2517                         DSSERR("Failed to complete previous frame transfer\n");
2518                         r = -EIO;
2519                         goto err1;
2520                 }
2521         }
2522
2523         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2524                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2525
2526         return 0;
2527 err1:
2528         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2529                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2530 err0:
2531         return r;
2532 }
2533
2534 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2535 {
2536         struct dsi_packet_sent_handler_data *l4_data =
2537                 (struct dsi_packet_sent_handler_data *) data;
2538         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2539         const int channel = dsi->update_channel;
2540
2541         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2542                 complete(l4_data->completion);
2543 }
2544
2545 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2546 {
2547         DECLARE_COMPLETION_ONSTACK(completion);
2548         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2549         int r = 0;
2550
2551         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2552                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2553         if (r)
2554                 goto err0;
2555
2556         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2557         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2558                 if (wait_for_completion_timeout(&completion,
2559                                 msecs_to_jiffies(10)) == 0) {
2560                         DSSERR("Failed to complete previous l4 transfer\n");
2561                         r = -EIO;
2562                         goto err1;
2563                 }
2564         }
2565
2566         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2567                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2568
2569         return 0;
2570 err1:
2571         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2572                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2573 err0:
2574         return r;
2575 }
2576
2577 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2578 {
2579         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2580
2581         WARN_ON(!dsi_bus_is_locked(dsidev));
2582
2583         WARN_ON(in_interrupt());
2584
2585         if (!dsi_vc_is_enabled(dsidev, channel))
2586                 return 0;
2587
2588         switch (dsi->vc[channel].source) {
2589         case DSI_VC_SOURCE_VP:
2590                 return dsi_sync_vc_vp(dsidev, channel);
2591         case DSI_VC_SOURCE_L4:
2592                 return dsi_sync_vc_l4(dsidev, channel);
2593         default:
2594                 BUG();
2595                 return -EINVAL;
2596         }
2597 }
2598
2599 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2600                 bool enable)
2601 {
2602         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2603                         channel, enable);
2604
2605         enable = enable ? 1 : 0;
2606
2607         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2608
2609         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2610                 0, enable) != enable) {
2611                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2612                         return -EIO;
2613         }
2614
2615         return 0;
2616 }
2617
2618 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2619 {
2620         u32 r;
2621
2622         DSSDBGF("%d", channel);
2623
2624         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2625
2626         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2627                 DSSERR("VC(%d) busy when trying to configure it!\n",
2628                                 channel);
2629
2630         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2631         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2632         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2633         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2634         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2635         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2636         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2637         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2638                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2639
2640         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2641         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2642
2643         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2644 }
2645
2646 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2647                 enum dsi_vc_source source)
2648 {
2649         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2650
2651         if (dsi->vc[channel].source == source)
2652                 return 0;
2653
2654         DSSDBGF("%d", channel);
2655
2656         dsi_sync_vc(dsidev, channel);
2657
2658         dsi_vc_enable(dsidev, channel, 0);
2659
2660         /* VC_BUSY */
2661         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2662                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2663                 return -EIO;
2664         }
2665
2666         /* SOURCE, 0 = L4, 1 = video port */
2667         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2668
2669         /* DCS_CMD_ENABLE */
2670         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2671                 bool enable = source == DSI_VC_SOURCE_VP;
2672                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2673         }
2674
2675         dsi_vc_enable(dsidev, channel, 1);
2676
2677         dsi->vc[channel].source = source;
2678
2679         return 0;
2680 }
2681
2682 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2683                 bool enable)
2684 {
2685         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2686
2687         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2688
2689         WARN_ON(!dsi_bus_is_locked(dsidev));
2690
2691         dsi_vc_enable(dsidev, channel, 0);
2692         dsi_if_enable(dsidev, 0);
2693
2694         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2695
2696         dsi_vc_enable(dsidev, channel, 1);
2697         dsi_if_enable(dsidev, 1);
2698
2699         dsi_force_tx_stop_mode_io(dsidev);
2700
2701         /* start the DDR clock by sending a NULL packet */
2702         if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2703                 dsi_vc_send_null(dssdev, channel);
2704 }
2705 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2706
2707 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2708 {
2709         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2710                 u32 val;
2711                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2712                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2713                                 (val >> 0) & 0xff,
2714                                 (val >> 8) & 0xff,
2715                                 (val >> 16) & 0xff,
2716                                 (val >> 24) & 0xff);
2717         }
2718 }
2719
2720 static void dsi_show_rx_ack_with_err(u16 err)
2721 {
2722         DSSERR("\tACK with ERROR (%#x):\n", err);
2723         if (err & (1 << 0))
2724                 DSSERR("\t\tSoT Error\n");
2725         if (err & (1 << 1))
2726                 DSSERR("\t\tSoT Sync Error\n");
2727         if (err & (1 << 2))
2728                 DSSERR("\t\tEoT Sync Error\n");
2729         if (err & (1 << 3))
2730                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2731         if (err & (1 << 4))
2732                 DSSERR("\t\tLP Transmit Sync Error\n");
2733         if (err & (1 << 5))
2734                 DSSERR("\t\tHS Receive Timeout Error\n");
2735         if (err & (1 << 6))
2736                 DSSERR("\t\tFalse Control Error\n");
2737         if (err & (1 << 7))
2738                 DSSERR("\t\t(reserved7)\n");
2739         if (err & (1 << 8))
2740                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2741         if (err & (1 << 9))
2742                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2743         if (err & (1 << 10))
2744                 DSSERR("\t\tChecksum Error\n");
2745         if (err & (1 << 11))
2746                 DSSERR("\t\tData type not recognized\n");
2747         if (err & (1 << 12))
2748                 DSSERR("\t\tInvalid VC ID\n");
2749         if (err & (1 << 13))
2750                 DSSERR("\t\tInvalid Transmission Length\n");
2751         if (err & (1 << 14))
2752                 DSSERR("\t\t(reserved14)\n");
2753         if (err & (1 << 15))
2754                 DSSERR("\t\tDSI Protocol Violation\n");
2755 }
2756
2757 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2758                 int channel)
2759 {
2760         /* RX_FIFO_NOT_EMPTY */
2761         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2762                 u32 val;
2763                 u8 dt;
2764                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2765                 DSSERR("\trawval %#08x\n", val);
2766                 dt = FLD_GET(val, 5, 0);
2767                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2768                         u16 err = FLD_GET(val, 23, 8);
2769                         dsi_show_rx_ack_with_err(err);
2770                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2771                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2772                                         FLD_GET(val, 23, 8));
2773                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2774                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2775                                         FLD_GET(val, 23, 8));
2776                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2777                         DSSERR("\tDCS long response, len %d\n",
2778                                         FLD_GET(val, 23, 8));
2779                         dsi_vc_flush_long_data(dsidev, channel);
2780                 } else {
2781                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2782                 }
2783         }
2784         return 0;
2785 }
2786
2787 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2788 {
2789         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2790
2791         if (dsi->debug_write || dsi->debug_read)
2792                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2793
2794         WARN_ON(!dsi_bus_is_locked(dsidev));
2795
2796         /* RX_FIFO_NOT_EMPTY */
2797         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2798                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2799                 dsi_vc_flush_receive_data(dsidev, channel);
2800         }
2801
2802         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2803
2804         /* flush posted write */
2805         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2806
2807         return 0;
2808 }
2809
2810 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2811 {
2812         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2813         DECLARE_COMPLETION_ONSTACK(completion);
2814         int r = 0;
2815         u32 err;
2816
2817         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2818                         &completion, DSI_VC_IRQ_BTA);
2819         if (r)
2820                 goto err0;
2821
2822         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2823                         DSI_IRQ_ERROR_MASK);
2824         if (r)
2825                 goto err1;
2826
2827         r = dsi_vc_send_bta(dsidev, channel);
2828         if (r)
2829                 goto err2;
2830
2831         if (wait_for_completion_timeout(&completion,
2832                                 msecs_to_jiffies(500)) == 0) {
2833                 DSSERR("Failed to receive BTA\n");
2834                 r = -EIO;
2835                 goto err2;
2836         }
2837
2838         err = dsi_get_errors(dsidev);
2839         if (err) {
2840                 DSSERR("Error while sending BTA: %x\n", err);
2841                 r = -EIO;
2842                 goto err2;
2843         }
2844 err2:
2845         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2846                         DSI_IRQ_ERROR_MASK);
2847 err1:
2848         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2849                         &completion, DSI_VC_IRQ_BTA);
2850 err0:
2851         return r;
2852 }
2853 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2854
2855 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2856                 int channel, u8 data_type, u16 len, u8 ecc)
2857 {
2858         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2859         u32 val;
2860         u8 data_id;
2861
2862         WARN_ON(!dsi_bus_is_locked(dsidev));
2863
2864         data_id = data_type | dsi->vc[channel].vc_id << 6;
2865
2866         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2867                 FLD_VAL(ecc, 31, 24);
2868
2869         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2870 }
2871
2872 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2873                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2874 {
2875         u32 val;
2876
2877         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2878
2879 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2880                         b1, b2, b3, b4, val); */
2881
2882         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2883 }
2884
2885 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2886                 u8 data_type, u8 *data, u16 len, u8 ecc)
2887 {
2888         /*u32 val; */
2889         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2890         int i;
2891         u8 *p;
2892         int r = 0;
2893         u8 b1, b2, b3, b4;
2894
2895         if (dsi->debug_write)
2896                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2897
2898         /* len + header */
2899         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2900                 DSSERR("unable to send long packet: packet too long.\n");
2901                 return -EINVAL;
2902         }
2903
2904         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2905
2906         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2907
2908         p = data;
2909         for (i = 0; i < len >> 2; i++) {
2910                 if (dsi->debug_write)
2911                         DSSDBG("\tsending full packet %d\n", i);
2912
2913                 b1 = *p++;
2914                 b2 = *p++;
2915                 b3 = *p++;
2916                 b4 = *p++;
2917
2918                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2919         }
2920
2921         i = len % 4;
2922         if (i) {
2923                 b1 = 0; b2 = 0; b3 = 0;
2924
2925                 if (dsi->debug_write)
2926                         DSSDBG("\tsending remainder bytes %d\n", i);
2927
2928                 switch (i) {
2929                 case 3:
2930                         b1 = *p++;
2931                         b2 = *p++;
2932                         b3 = *p++;
2933                         break;
2934                 case 2:
2935                         b1 = *p++;
2936                         b2 = *p++;
2937                         break;
2938                 case 1:
2939                         b1 = *p++;
2940                         break;
2941                 }
2942
2943                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2944         }
2945
2946         return r;
2947 }
2948
2949 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2950                 u8 data_type, u16 data, u8 ecc)
2951 {
2952         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2953         u32 r;
2954         u8 data_id;
2955
2956         WARN_ON(!dsi_bus_is_locked(dsidev));
2957
2958         if (dsi->debug_write)
2959                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2960                                 channel,
2961                                 data_type, data & 0xff, (data >> 8) & 0xff);
2962
2963         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2964
2965         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2966                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2967                 return -EINVAL;
2968         }
2969
2970         data_id = data_type | dsi->vc[channel].vc_id << 6;
2971
2972         r = (data_id << 0) | (data << 8) | (ecc << 24);
2973
2974         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2975
2976         return 0;
2977 }
2978
2979 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2980 {
2981         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2982
2983         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2984                 0, 0);
2985 }
2986 EXPORT_SYMBOL(dsi_vc_send_null);
2987
2988 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
2989                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
2990 {
2991         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2992         int r;
2993
2994         if (len == 0) {
2995                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2996                 r = dsi_vc_send_short(dsidev, channel,
2997                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2998         } else if (len == 1) {
2999                 r = dsi_vc_send_short(dsidev, channel,
3000                                 type == DSS_DSI_CONTENT_GENERIC ?
3001                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3002                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3003         } else if (len == 2) {
3004                 r = dsi_vc_send_short(dsidev, channel,
3005                                 type == DSS_DSI_CONTENT_GENERIC ?
3006                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3007                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3008                                 data[0] | (data[1] << 8), 0);
3009         } else {
3010                 r = dsi_vc_send_long(dsidev, channel,
3011                                 type == DSS_DSI_CONTENT_GENERIC ?
3012                                 MIPI_DSI_GENERIC_LONG_WRITE :
3013                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3014         }
3015
3016         return r;
3017 }
3018
3019 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3020                 u8 *data, int len)
3021 {
3022         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3023                         DSS_DSI_CONTENT_DCS);
3024 }
3025 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3026
3027 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3028                 u8 *data, int len)
3029 {
3030         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3031                         DSS_DSI_CONTENT_GENERIC);
3032 }
3033 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3034
3035 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3036                 u8 *data, int len, enum dss_dsi_content_type type)
3037 {
3038         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3039         int r;
3040
3041         r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3042         if (r)
3043                 goto err;
3044
3045         r = dsi_vc_send_bta_sync(dssdev, channel);
3046         if (r)
3047                 goto err;
3048
3049         /* RX_FIFO_NOT_EMPTY */
3050         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3051                 DSSERR("rx fifo not empty after write, dumping data:\n");
3052                 dsi_vc_flush_receive_data(dsidev, channel);
3053                 r = -EIO;
3054                 goto err;
3055         }
3056
3057         return 0;
3058 err:
3059         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3060                         channel, data[0], len);
3061         return r;
3062 }
3063
3064 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3065                 int len)
3066 {
3067         return dsi_vc_write_common(dssdev, channel, data, len,
3068                         DSS_DSI_CONTENT_DCS);
3069 }
3070 EXPORT_SYMBOL(dsi_vc_dcs_write);
3071
3072 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3073                 int len)
3074 {
3075         return dsi_vc_write_common(dssdev, channel, data, len,
3076                         DSS_DSI_CONTENT_GENERIC);
3077 }
3078 EXPORT_SYMBOL(dsi_vc_generic_write);
3079
3080 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3081 {
3082         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3083 }
3084 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3085
3086 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3087 {
3088         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3089 }
3090 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3091
3092 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3093                 u8 param)
3094 {
3095         u8 buf[2];
3096         buf[0] = dcs_cmd;
3097         buf[1] = param;
3098         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3099 }
3100 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3101
3102 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3103                 u8 param)
3104 {
3105         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3106 }
3107 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3108
3109 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3110                 u8 param1, u8 param2)
3111 {
3112         u8 buf[2];
3113         buf[0] = param1;
3114         buf[1] = param2;
3115         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3116 }
3117 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3118
3119 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3120                 int channel, u8 dcs_cmd)
3121 {
3122         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3123         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3124         int r;
3125
3126         if (dsi->debug_read)
3127                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3128                         channel, dcs_cmd);
3129
3130         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3131         if (r) {
3132                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3133                         " failed\n", channel, dcs_cmd);
3134                 return r;
3135         }
3136
3137         return 0;
3138 }
3139
3140 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3141                 int channel, u8 *reqdata, int reqlen)
3142 {
3143         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3144         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3145         u16 data;
3146         u8 data_type;
3147         int r;
3148
3149         if (dsi->debug_read)
3150                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3151                         channel, reqlen);
3152
3153         if (reqlen == 0) {
3154                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3155                 data = 0;
3156         } else if (reqlen == 1) {
3157                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3158                 data = reqdata[0];
3159         } else if (reqlen == 2) {
3160                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3161                 data = reqdata[0] | (reqdata[1] << 8);
3162         } else {
3163                 BUG();
3164                 return -EINVAL;
3165         }
3166
3167         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3168         if (r) {
3169                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3170                         " failed\n", channel, reqlen);
3171                 return r;
3172         }
3173
3174         return 0;
3175 }
3176
3177 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3178                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3179 {
3180         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3181         u32 val;
3182         u8 dt;
3183         int r;
3184
3185         /* RX_FIFO_NOT_EMPTY */
3186         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3187                 DSSERR("RX fifo empty when trying to read.\n");
3188                 r = -EIO;
3189                 goto err;
3190         }
3191
3192         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3193         if (dsi->debug_read)
3194                 DSSDBG("\theader: %08x\n", val);
3195         dt = FLD_GET(val, 5, 0);
3196         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3197                 u16 err = FLD_GET(val, 23, 8);
3198                 dsi_show_rx_ack_with_err(err);
3199                 r = -EIO;
3200                 goto err;
3201
3202         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3203                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3204                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3205                 u8 data = FLD_GET(val, 15, 8);
3206                 if (dsi->debug_read)
3207                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3208                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3209                                 "DCS", data);
3210
3211                 if (buflen < 1) {
3212                         r = -EIO;
3213                         goto err;
3214                 }
3215
3216                 buf[0] = data;
3217
3218                 return 1;
3219         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3220                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3221                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3222                 u16 data = FLD_GET(val, 23, 8);
3223                 if (dsi->debug_read)
3224                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3225                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3226                                 "DCS", data);
3227
3228                 if (buflen < 2) {
3229                         r = -EIO;
3230                         goto err;
3231                 }
3232
3233                 buf[0] = data & 0xff;
3234                 buf[1] = (data >> 8) & 0xff;
3235
3236                 return 2;
3237         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3238                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3239                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3240                 int w;
3241                 int len = FLD_GET(val, 23, 8);
3242                 if (dsi->debug_read)
3243                         DSSDBG("\t%s long response, len %d\n",
3244                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3245                                 "DCS", len);
3246
3247                 if (len > buflen) {
3248                         r = -EIO;
3249                         goto err;
3250                 }
3251
3252                 /* two byte checksum ends the packet, not included in len */
3253                 for (w = 0; w < len + 2;) {
3254                         int b;
3255                         val = dsi_read_reg(dsidev,
3256                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3257                         if (dsi->debug_read)
3258                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3259                                                 (val >> 0) & 0xff,
3260                                                 (val >> 8) & 0xff,
3261                                                 (val >> 16) & 0xff,
3262                                                 (val >> 24) & 0xff);
3263
3264                         for (b = 0; b < 4; ++b) {
3265                                 if (w < len)
3266                                         buf[w] = (val >> (b * 8)) & 0xff;
3267                                 /* we discard the 2 byte checksum */
3268                                 ++w;
3269                         }
3270                 }
3271
3272                 return len;
3273         } else {
3274                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3275                 r = -EIO;
3276                 goto err;
3277         }
3278
3279 err:
3280         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3281                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3282
3283         return r;
3284 }
3285
3286 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3287                 u8 *buf, int buflen)
3288 {
3289         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3290         int r;
3291
3292         r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3293         if (r)
3294                 goto err;
3295
3296         r = dsi_vc_send_bta_sync(dssdev, channel);
3297         if (r)
3298                 goto err;
3299
3300         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3301                 DSS_DSI_CONTENT_DCS);
3302         if (r < 0)
3303                 goto err;
3304
3305         if (r != buflen) {
3306                 r = -EIO;
3307                 goto err;
3308         }
3309
3310         return 0;
3311 err:
3312         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3313         return r;
3314 }
3315 EXPORT_SYMBOL(dsi_vc_dcs_read);
3316
3317 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3318                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3319 {
3320         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3321         int r;
3322
3323         r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3324         if (r)
3325                 return r;
3326
3327         r = dsi_vc_send_bta_sync(dssdev, channel);
3328         if (r)
3329                 return r;
3330
3331         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3332                 DSS_DSI_CONTENT_GENERIC);
3333         if (r < 0)
3334                 return r;
3335
3336         if (r != buflen) {
3337                 r = -EIO;
3338                 return r;
3339         }
3340
3341         return 0;
3342 }
3343
3344 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3345                 int buflen)
3346 {
3347         int r;
3348
3349         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3350         if (r) {
3351                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3352                 return r;
3353         }
3354
3355         return 0;
3356 }
3357 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3358
3359 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3360                 u8 *buf, int buflen)
3361 {
3362         int r;
3363
3364         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3365         if (r) {
3366                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3367                 return r;
3368         }
3369
3370         return 0;
3371 }
3372 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3373
3374 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3375                 u8 param1, u8 param2, u8 *buf, int buflen)
3376 {
3377         int r;
3378         u8 reqdata[2];
3379
3380         reqdata[0] = param1;
3381         reqdata[1] = param2;
3382
3383         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3384         if (r) {
3385                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3386                 return r;
3387         }
3388
3389         return 0;
3390 }
3391 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3392
3393 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3394                 u16 len)
3395 {
3396         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3397
3398         return dsi_vc_send_short(dsidev, channel,
3399                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3400 }
3401 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3402
3403 static int dsi_enter_ulps(struct platform_device *dsidev)
3404 {
3405         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3406         DECLARE_COMPLETION_ONSTACK(completion);
3407         int r, i;
3408         unsigned mask;
3409
3410         DSSDBGF();
3411
3412         WARN_ON(!dsi_bus_is_locked(dsidev));
3413
3414         WARN_ON(dsi->ulps_enabled);
3415
3416         if (dsi->ulps_enabled)
3417                 return 0;
3418
3419         /* DDR_CLK_ALWAYS_ON */
3420         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3421                 dsi_if_enable(dsidev, 0);
3422                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3423                 dsi_if_enable(dsidev, 1);
3424         }
3425
3426         dsi_sync_vc(dsidev, 0);
3427         dsi_sync_vc(dsidev, 1);
3428         dsi_sync_vc(dsidev, 2);
3429         dsi_sync_vc(dsidev, 3);
3430
3431         dsi_force_tx_stop_mode_io(dsidev);
3432
3433         dsi_vc_enable(dsidev, 0, false);
3434         dsi_vc_enable(dsidev, 1, false);
3435         dsi_vc_enable(dsidev, 2, false);
3436         dsi_vc_enable(dsidev, 3, false);
3437
3438         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3439                 DSSERR("HS busy when enabling ULPS\n");
3440                 return -EIO;
3441         }
3442
3443         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3444                 DSSERR("LP busy when enabling ULPS\n");
3445                 return -EIO;
3446         }
3447
3448         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3449                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3450         if (r)
3451                 return r;
3452
3453         mask = 0;
3454
3455         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3456                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3457                         continue;
3458                 mask |= 1 << i;
3459         }
3460         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3461         /* LANEx_ULPS_SIG2 */
3462         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3463
3464         /* flush posted write and wait for SCP interface to finish the write */
3465         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3466
3467         if (wait_for_completion_timeout(&completion,
3468                                 msecs_to_jiffies(1000)) == 0) {
3469                 DSSERR("ULPS enable timeout\n");
3470                 r = -EIO;
3471                 goto err;
3472         }
3473
3474         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3475                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3476
3477         /* Reset LANEx_ULPS_SIG2 */
3478         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3479
3480         /* flush posted write and wait for SCP interface to finish the write */
3481         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3482
3483         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3484
3485         dsi_if_enable(dsidev, false);
3486
3487         dsi->ulps_enabled = true;
3488
3489         return 0;
3490
3491 err:
3492         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3493                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3494         return r;
3495 }
3496
3497 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3498                 unsigned ticks, bool x4, bool x16)
3499 {
3500         unsigned long fck;
3501         unsigned long total_ticks;
3502         u32 r;
3503
3504         BUG_ON(ticks > 0x1fff);
3505
3506         /* ticks in DSI_FCK */
3507         fck = dsi_fclk_rate(dsidev);
3508
3509         r = dsi_read_reg(dsidev, DSI_TIMING2);
3510         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3511         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3512         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3513         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3514         dsi_write_reg(dsidev, DSI_TIMING2, r);
3515
3516         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3517
3518         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3519                         total_ticks,
3520                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3521                         (total_ticks * 1000) / (fck / 1000 / 1000));
3522 }
3523
3524 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3525                 bool x8, bool x16)
3526 {
3527         unsigned long fck;
3528         unsigned long total_ticks;
3529         u32 r;
3530
3531         BUG_ON(ticks > 0x1fff);
3532
3533         /* ticks in DSI_FCK */
3534         fck = dsi_fclk_rate(dsidev);
3535
3536         r = dsi_read_reg(dsidev, DSI_TIMING1);
3537         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3538         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3539         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3540         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3541         dsi_write_reg(dsidev, DSI_TIMING1, r);
3542
3543         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3544
3545         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3546                         total_ticks,
3547                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3548                         (total_ticks * 1000) / (fck / 1000 / 1000));
3549 }
3550
3551 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3552                 unsigned ticks, bool x4, bool x16)
3553 {
3554         unsigned long fck;
3555         unsigned long total_ticks;
3556         u32 r;
3557
3558         BUG_ON(ticks > 0x1fff);
3559
3560         /* ticks in DSI_FCK */
3561         fck = dsi_fclk_rate(dsidev);
3562
3563         r = dsi_read_reg(dsidev, DSI_TIMING1);
3564         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3565         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3566         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3567         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3568         dsi_write_reg(dsidev, DSI_TIMING1, r);
3569
3570         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3571
3572         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3573                         total_ticks,
3574                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3575                         (total_ticks * 1000) / (fck / 1000 / 1000));
3576 }
3577
3578 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3579                 unsigned ticks, bool x4, bool x16)
3580 {
3581         unsigned long fck;
3582         unsigned long total_ticks;
3583         u32 r;
3584
3585         BUG_ON(ticks > 0x1fff);
3586
3587         /* ticks in TxByteClkHS */
3588         fck = dsi_get_txbyteclkhs(dsidev);
3589
3590         r = dsi_read_reg(dsidev, DSI_TIMING2);
3591         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3592         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3593         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3594         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3595         dsi_write_reg(dsidev, DSI_TIMING2, r);
3596
3597         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3598
3599         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3600                         total_ticks,
3601                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3602                         (total_ticks * 1000) / (fck / 1000 / 1000));
3603 }
3604
3605 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3606 {
3607         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3608         int num_line_buffers;
3609
3610         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3611                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3612                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3613                 struct omap_video_timings *timings = &dssdev->panel.timings;
3614                 /*
3615                  * Don't use line buffers if width is greater than the video
3616                  * port's line buffer size
3617                  */
3618                 if (line_buf_size <= timings->x_res * bpp / 8)
3619                         num_line_buffers = 0;
3620                 else
3621                         num_line_buffers = 2;
3622         } else {
3623                 /* Use maximum number of line buffers in command mode */
3624                 num_line_buffers = 2;
3625         }
3626
3627         /* LINE_BUFFER */
3628         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3629 }
3630
3631 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3632 {
3633         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3634         int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3635         int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3636         int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3637         bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3638         bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3639         u32 r;
3640
3641         r = dsi_read_reg(dsidev, DSI_CTRL);
3642         r = FLD_MOD(r, de_pol, 9, 9);           /* VP_DE_POL */
3643         r = FLD_MOD(r, hsync_pol, 10, 10);      /* VP_HSYNC_POL */
3644         r = FLD_MOD(r, vsync_pol, 11, 11);      /* VP_VSYNC_POL */
3645         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3646         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3647         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3648         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3649         dsi_write_reg(dsidev, DSI_CTRL, r);
3650 }
3651
3652 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3653 {
3654         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3655         int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3656         int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3657         int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3658         int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3659         u32 r;
3660
3661         /*
3662          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3663          * 1 = Long blanking packets are sent in corresponding blanking periods
3664          */
3665         r = dsi_read_reg(dsidev, DSI_CTRL);
3666         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3667         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3668         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3669         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3670         dsi_write_reg(dsidev, DSI_CTRL, r);
3671 }
3672
3673 /*
3674  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3675  * results in maximum transition time for data and clock lanes to enter and
3676  * exit HS mode. Hence, this is the scenario where the least amount of command
3677  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3678  * clock cycles that can be used to interleave command mode data in HS so that
3679  * all scenarios are satisfied.
3680  */
3681 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3682                 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3683 {
3684         int transition;
3685
3686         /*
3687          * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3688          * time of data lanes only, if it isn't set, we need to consider HS
3689          * transition time of both data and clock lanes. HS transition time
3690          * of Scenario 3 is considered.
3691          */
3692         if (ddr_alwon) {
3693                 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3694         } else {
3695                 int trans1, trans2;
3696                 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3697                 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3698                                 enter_hs + 1;
3699                 transition = max(trans1, trans2);
3700         }
3701
3702         return blank > transition ? blank - transition : 0;
3703 }
3704
3705 /*
3706  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3707  * results in maximum transition time for data lanes to enter and exit LP mode.
3708  * Hence, this is the scenario where the least amount of command mode data can
3709  * be interleaved. We program the minimum amount of bytes that can be
3710  * interleaved in LP so that all scenarios are satisfied.
3711  */
3712 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3713                 int lp_clk_div, int tdsi_fclk)
3714 {
3715         int trans_lp;   /* time required for a LP transition, in TXBYTECLKHS */
3716         int tlp_avail;  /* time left for interleaving commands, in CLKIN4DDR */
3717         int ttxclkesc;  /* period of LP transmit escape clock, in CLKIN4DDR */
3718         int thsbyte_clk = 16;   /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3719         int lp_inter;   /* cmd mode data that can be interleaved, in bytes */
3720
3721         /* maximum LP transition time according to Scenario 1 */
3722         trans_lp = exit_hs + max(enter_hs, 2) + 1;
3723
3724         /* CLKIN4DDR = 16 * TXBYTECLKHS */
3725         tlp_avail = thsbyte_clk * (blank - trans_lp);
3726
3727         ttxclkesc = tdsi_fclk * lp_clk_div;
3728
3729         lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3730                         26) / 16;
3731
3732         return max(lp_inter, 0);
3733 }
3734
3735 static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev)
3736 {
3737         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3738         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3739         int blanking_mode;
3740         int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3741         int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3742         int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3743         int tclk_trail, ths_exit, exiths_clk;
3744         bool ddr_alwon;
3745         struct omap_video_timings *timings = &dssdev->panel.timings;
3746         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3747         int ndl = dsi->num_lanes_used - 1;
3748         int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1;
3749         int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3750         int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3751         int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3752         int bl_interleave_hs = 0, bl_interleave_lp = 0;
3753         u32 r;
3754
3755         r = dsi_read_reg(dsidev, DSI_CTRL);
3756         blanking_mode = FLD_GET(r, 20, 20);
3757         hfp_blanking_mode = FLD_GET(r, 21, 21);
3758         hbp_blanking_mode = FLD_GET(r, 22, 22);
3759         hsa_blanking_mode = FLD_GET(r, 23, 23);
3760
3761         r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3762         hbp = FLD_GET(r, 11, 0);
3763         hfp = FLD_GET(r, 23, 12);
3764         hsa = FLD_GET(r, 31, 24);
3765
3766         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3767         ddr_clk_post = FLD_GET(r, 7, 0);
3768         ddr_clk_pre = FLD_GET(r, 15, 8);
3769
3770         r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3771         exit_hs_mode_lat = FLD_GET(r, 15, 0);
3772         enter_hs_mode_lat = FLD_GET(r, 31, 16);
3773
3774         r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3775         lp_clk_div = FLD_GET(r, 12, 0);
3776         ddr_alwon = FLD_GET(r, 13, 13);
3777
3778         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3779         ths_exit = FLD_GET(r, 7, 0);
3780
3781         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3782         tclk_trail = FLD_GET(r, 15, 8);
3783
3784         exiths_clk = ths_exit + tclk_trail;
3785
3786         width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3787         bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3788
3789         if (!hsa_blanking_mode) {
3790                 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3791                                         enter_hs_mode_lat, exit_hs_mode_lat,
3792                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3793                 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3794                                         enter_hs_mode_lat, exit_hs_mode_lat,
3795                                         lp_clk_div, dsi_fclk_hsdiv);
3796         }
3797
3798         if (!hfp_blanking_mode) {
3799                 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3800                                         enter_hs_mode_lat, exit_hs_mode_lat,
3801                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3802                 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3803                                         enter_hs_mode_lat, exit_hs_mode_lat,
3804                                         lp_clk_div, dsi_fclk_hsdiv);
3805         }
3806
3807         if (!hbp_blanking_mode) {
3808                 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3809                                         enter_hs_mode_lat, exit_hs_mode_lat,
3810                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3811
3812                 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3813                                         enter_hs_mode_lat, exit_hs_mode_lat,
3814                                         lp_clk_div, dsi_fclk_hsdiv);
3815         }
3816
3817         if (!blanking_mode) {
3818                 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3819                                         enter_hs_mode_lat, exit_hs_mode_lat,
3820                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3821
3822                 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3823                                         enter_hs_mode_lat, exit_hs_mode_lat,
3824                                         lp_clk_div, dsi_fclk_hsdiv);
3825         }
3826
3827         DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3828                 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3829                 bl_interleave_hs);
3830
3831         DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3832                 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3833                 bl_interleave_lp);
3834
3835         r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3836         r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3837         r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3838         r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3839         dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3840
3841         r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3842         r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3843         r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3844         r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3845         dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3846
3847         r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3848         r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3849         r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3850         dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3851 }
3852
3853 static int dsi_proto_config(struct omap_dss_device *dssdev)
3854 {
3855         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3856         u32 r;
3857         int buswidth = 0;
3858
3859         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3860                         DSI_FIFO_SIZE_32,
3861                         DSI_FIFO_SIZE_32,
3862                         DSI_FIFO_SIZE_32);
3863
3864         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3865                         DSI_FIFO_SIZE_32,
3866                         DSI_FIFO_SIZE_32,
3867                         DSI_FIFO_SIZE_32);
3868
3869         /* XXX what values for the timeouts? */
3870         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3871         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3872         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3873         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3874
3875         switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3876         case 16:
3877                 buswidth = 0;
3878                 break;
3879         case 18:
3880                 buswidth = 1;
3881                 break;
3882         case 24:
3883                 buswidth = 2;
3884                 break;
3885         default:
3886                 BUG();
3887                 return -EINVAL;
3888         }
3889
3890         r = dsi_read_reg(dsidev, DSI_CTRL);
3891         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
3892         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
3893         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
3894         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
3895         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3896         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
3897         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
3898         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
3899         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3900                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
3901                 /* DCS_CMD_CODE, 1=start, 0=continue */
3902                 r = FLD_MOD(r, 0, 25, 25);
3903         }
3904
3905         dsi_write_reg(dsidev, DSI_CTRL, r);
3906
3907         dsi_config_vp_num_line_buffers(dssdev);
3908
3909         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3910                 dsi_config_vp_sync_events(dssdev);
3911                 dsi_config_blanking_modes(dssdev);
3912                 dsi_config_cmd_mode_interleaving(dssdev);
3913         }
3914
3915         dsi_vc_initial_config(dsidev, 0);
3916         dsi_vc_initial_config(dsidev, 1);
3917         dsi_vc_initial_config(dsidev, 2);
3918         dsi_vc_initial_config(dsidev, 3);
3919
3920         return 0;
3921 }
3922
3923 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3924 {
3925         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3926         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3927         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3928         unsigned tclk_pre, tclk_post;
3929         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3930         unsigned ths_trail, ths_exit;
3931         unsigned ddr_clk_pre, ddr_clk_post;
3932         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3933         unsigned ths_eot;
3934         int ndl = dsi->num_lanes_used - 1;
3935         u32 r;
3936
3937         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3938         ths_prepare = FLD_GET(r, 31, 24);
3939         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3940         ths_zero = ths_prepare_ths_zero - ths_prepare;
3941         ths_trail = FLD_GET(r, 15, 8);
3942         ths_exit = FLD_GET(r, 7, 0);
3943
3944         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3945         tlpx = FLD_GET(r, 22, 16) * 2;
3946         tclk_trail = FLD_GET(r, 15, 8);
3947         tclk_zero = FLD_GET(r, 7, 0);
3948
3949         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3950         tclk_prepare = FLD_GET(r, 7, 0);
3951
3952         /* min 8*UI */
3953         tclk_pre = 20;
3954         /* min 60ns + 52*UI */
3955         tclk_post = ns2ddr(dsidev, 60) + 26;
3956
3957         ths_eot = DIV_ROUND_UP(4, ndl);
3958
3959         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3960                         4);
3961         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3962
3963         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3964         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3965
3966         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3967         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3968         r = FLD_MOD(r, ddr_clk_post, 7, 0);
3969         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3970
3971         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3972                         ddr_clk_pre,
3973                         ddr_clk_post);
3974
3975         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3976                 DIV_ROUND_UP(ths_prepare, 4) +
3977                 DIV_ROUND_UP(ths_zero + 3, 4);
3978
3979         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3980
3981         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3982                 FLD_VAL(exit_hs_mode_lat, 15, 0);
3983         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3984
3985         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3986                         enter_hs_mode_lat, exit_hs_mode_lat);
3987
3988          if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3989                 /* TODO: Implement a video mode check_timings function */
3990                 int hsa = dssdev->panel.dsi_vm_data.hsa;
3991                 int hfp = dssdev->panel.dsi_vm_data.hfp;
3992                 int hbp = dssdev->panel.dsi_vm_data.hbp;
3993                 int vsa = dssdev->panel.dsi_vm_data.vsa;
3994                 int vfp = dssdev->panel.dsi_vm_data.vfp;
3995                 int vbp = dssdev->panel.dsi_vm_data.vbp;
3996                 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3997                 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3998                 struct omap_video_timings *timings = &dssdev->panel.timings;
3999                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4000                 int tl, t_he, width_bytes;
4001
4002                 t_he = hsync_end ?
4003                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4004
4005                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4006
4007                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4008                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4009                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4010
4011                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4012                         hfp, hsync_end ? hsa : 0, tl);
4013                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4014                         vsa, timings->y_res);
4015
4016                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4017                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
4018                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
4019                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
4020                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4021
4022                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4023                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
4024                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
4025                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
4026                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
4027                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4028
4029                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4030                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
4031                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
4032                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4033         }
4034 }
4035
4036 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4037                 const struct omap_dsi_pin_config *pin_cfg)
4038 {
4039         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4040         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4041         int num_pins;
4042         const int *pins;
4043         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4044         int num_lanes;
4045         int i;
4046
4047         static const enum dsi_lane_function functions[] = {
4048                 DSI_LANE_CLK,
4049                 DSI_LANE_DATA1,
4050                 DSI_LANE_DATA2,
4051                 DSI_LANE_DATA3,
4052                 DSI_LANE_DATA4,
4053         };
4054
4055         num_pins = pin_cfg->num_pins;
4056         pins = pin_cfg->pins;
4057
4058         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4059                         || num_pins % 2 != 0)
4060                 return -EINVAL;
4061
4062         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4063                 lanes[i].function = DSI_LANE_UNUSED;
4064
4065         num_lanes = 0;
4066
4067         for (i = 0; i < num_pins; i += 2) {
4068                 u8 lane, pol;
4069                 int dx, dy;
4070
4071                 dx = pins[i];
4072                 dy = pins[i + 1];
4073
4074                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4075                         return -EINVAL;
4076
4077                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4078                         return -EINVAL;
4079
4080                 if (dx & 1) {
4081                         if (dy != dx - 1)
4082                                 return -EINVAL;
4083                         pol = 1;
4084                 } else {
4085                         if (dy != dx + 1)
4086                                 return -EINVAL;
4087                         pol = 0;
4088                 }
4089
4090                 lane = dx / 2;
4091
4092                 lanes[lane].function = functions[i / 2];
4093                 lanes[lane].polarity = pol;
4094                 num_lanes++;
4095         }
4096
4097         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4098         dsi->num_lanes_used = num_lanes;
4099
4100         return 0;
4101 }
4102 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4103
4104 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4105 {
4106         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4107         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4108         u8 data_type;
4109         u16 word_count;
4110         int r;
4111
4112         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4113                 switch (dssdev->panel.dsi_pix_fmt) {
4114                 case OMAP_DSS_DSI_FMT_RGB888:
4115                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4116                         break;
4117                 case OMAP_DSS_DSI_FMT_RGB666:
4118                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4119                         break;
4120                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4121                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4122                         break;
4123                 case OMAP_DSS_DSI_FMT_RGB565:
4124                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4125                         break;
4126                 default:
4127                         BUG();
4128                         return -EINVAL;
4129                 };
4130
4131                 dsi_if_enable(dsidev, false);
4132                 dsi_vc_enable(dsidev, channel, false);
4133
4134                 /* MODE, 1 = video mode */
4135                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4136
4137                 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
4138
4139                 dsi_vc_write_long_header(dsidev, channel, data_type,
4140                                 word_count, 0);
4141
4142                 dsi_vc_enable(dsidev, channel, true);
4143                 dsi_if_enable(dsidev, true);
4144         }
4145
4146         r = dss_mgr_enable(dssdev->manager);
4147         if (r) {
4148                 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4149                         dsi_if_enable(dsidev, false);
4150                         dsi_vc_enable(dsidev, channel, false);
4151                 }
4152
4153                 return r;
4154         }
4155
4156         return 0;
4157 }
4158 EXPORT_SYMBOL(dsi_enable_video_output);
4159
4160 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4161 {
4162         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4163
4164         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4165                 dsi_if_enable(dsidev, false);
4166                 dsi_vc_enable(dsidev, channel, false);
4167
4168                 /* MODE, 0 = command mode */
4169                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4170
4171                 dsi_vc_enable(dsidev, channel, true);
4172                 dsi_if_enable(dsidev, true);
4173         }
4174
4175         dss_mgr_disable(dssdev->manager);
4176 }
4177 EXPORT_SYMBOL(dsi_disable_video_output);
4178
4179 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4180                 u16 w, u16 h)
4181 {
4182         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4183         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4184         unsigned bytespp;
4185         unsigned bytespl;
4186         unsigned bytespf;
4187         unsigned total_len;
4188         unsigned packet_payload;
4189         unsigned packet_len;
4190         u32 l;
4191         int r;
4192         const unsigned channel = dsi->update_channel;
4193         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4194
4195         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4196
4197         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4198
4199         bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4200         bytespl = w * bytespp;
4201         bytespf = bytespl * h;
4202
4203         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4204          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4205
4206         if (bytespf < line_buf_size)
4207                 packet_payload = bytespf;
4208         else
4209                 packet_payload = (line_buf_size) / bytespl * bytespl;
4210
4211         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4212         total_len = (bytespf / packet_payload) * packet_len;
4213
4214         if (bytespf % packet_payload)
4215                 total_len += (bytespf % packet_payload) + 1;
4216
4217         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4218         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4219
4220         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4221                 packet_len, 0);
4222
4223         if (dsi->te_enabled)
4224                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4225         else
4226                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4227         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4228
4229         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4230          * because DSS interrupts are not capable of waking up the CPU and the
4231          * framedone interrupt could be delayed for quite a long time. I think
4232          * the same goes for any DSS interrupts, but for some reason I have not
4233          * seen the problem anywhere else than here.
4234          */
4235         dispc_disable_sidle();
4236
4237         dsi_perf_mark_start(dsidev);
4238
4239         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4240                 msecs_to_jiffies(250));
4241         BUG_ON(r == 0);
4242
4243         dss_mgr_start_update(dssdev->manager);
4244
4245         if (dsi->te_enabled) {
4246                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4247                  * for TE is longer than the timer allows */
4248                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4249
4250                 dsi_vc_send_bta(dsidev, channel);
4251
4252 #ifdef DSI_CATCH_MISSING_TE
4253                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4254 #endif
4255         }
4256 }
4257
4258 #ifdef DSI_CATCH_MISSING_TE
4259 static void dsi_te_timeout(unsigned long arg)
4260 {
4261         DSSERR("TE not received for 250ms!\n");
4262 }
4263 #endif
4264
4265 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4266 {
4267         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4268
4269         /* SIDLEMODE back to smart-idle */
4270         dispc_enable_sidle();
4271
4272         if (dsi->te_enabled) {
4273                 /* enable LP_RX_TO again after the TE */
4274                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4275         }
4276
4277         dsi->framedone_callback(error, dsi->framedone_data);
4278
4279         if (!error)
4280                 dsi_perf_show(dsidev, "DISPC");
4281 }
4282
4283 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4284 {
4285         struct dsi_data *dsi = container_of(work, struct dsi_data,
4286                         framedone_timeout_work.work);
4287         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4288          * 250ms which would conflict with this timeout work. What should be
4289          * done is first cancel the transfer on the HW, and then cancel the
4290          * possibly scheduled framedone work. However, cancelling the transfer
4291          * on the HW is buggy, and would probably require resetting the whole
4292          * DSI */
4293
4294         DSSERR("Framedone not received for 250ms!\n");
4295
4296         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4297 }
4298
4299 static void dsi_framedone_irq_callback(void *data, u32 mask)
4300 {
4301         struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4302         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4303         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4304
4305         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4306          * turns itself off. However, DSI still has the pixels in its buffers,
4307          * and is sending the data.
4308          */
4309
4310         __cancel_delayed_work(&dsi->framedone_timeout_work);
4311
4312         dsi_handle_framedone(dsidev, 0);
4313 }
4314
4315 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4316                 void (*callback)(int, void *), void *data)
4317 {
4318         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4319         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4320         u16 dw, dh;
4321
4322         dsi_perf_mark_setup(dsidev);
4323
4324         dsi->update_channel = channel;
4325
4326         dsi->framedone_callback = callback;
4327         dsi->framedone_data = data;
4328
4329         dssdev->driver->get_resolution(dssdev, &dw, &dh);
4330
4331 #ifdef DEBUG
4332         dsi->update_bytes = dw * dh *
4333                 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4334 #endif
4335         dsi_update_screen_dispc(dssdev, dw, dh);
4336
4337         return 0;
4338 }
4339 EXPORT_SYMBOL(omap_dsi_update);
4340
4341 /* Display funcs */
4342
4343 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4344 {
4345         int r;
4346
4347         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4348                 u16 dw, dh;
4349                 u32 irq;
4350                 struct omap_video_timings timings = {
4351                         .hsw            = 1,
4352                         .hfp            = 1,
4353                         .hbp            = 1,
4354                         .vsw            = 1,
4355                         .vfp            = 0,
4356                         .vbp            = 0,
4357                 };
4358
4359                 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4360                 timings.x_res = dw;
4361                 timings.y_res = dh;
4362
4363                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4364                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4365
4366                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4367                         (void *) dssdev, irq);
4368                 if (r) {
4369                         DSSERR("can't get FRAMEDONE irq\n");
4370                         return r;
4371                 }
4372
4373                 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4374                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4375
4376                 dss_mgr_set_timings(dssdev->manager, &timings);
4377         } else {
4378                 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4379                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4380
4381                 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
4382         }
4383
4384                 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4385                         OMAP_DSS_LCD_DISPLAY_TFT);
4386                 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4387                         dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4388         return 0;
4389 }
4390
4391 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4392 {
4393         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4394                 u32 irq;
4395
4396                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4397                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4398
4399                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4400                         (void *) dssdev, irq);
4401         }
4402 }
4403
4404 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4405 {
4406         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4407         struct dsi_clock_info cinfo;
4408         int r;
4409
4410         cinfo.regn  = dssdev->clocks.dsi.regn;
4411         cinfo.regm  = dssdev->clocks.dsi.regm;
4412         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4413         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4414         r = dsi_calc_clock_rates(dsidev, &cinfo);
4415         if (r) {
4416                 DSSERR("Failed to calc dsi clocks\n");
4417                 return r;
4418         }
4419
4420         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4421         if (r) {
4422                 DSSERR("Failed to set dsi clocks\n");
4423                 return r;
4424         }
4425
4426         return 0;
4427 }
4428
4429 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4430 {
4431         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4432         struct dispc_clock_info dispc_cinfo;
4433         int r;
4434         unsigned long long fck;
4435
4436         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4437
4438         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4439         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4440
4441         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4442         if (r) {
4443                 DSSERR("Failed to calc dispc clocks\n");
4444                 return r;
4445         }
4446
4447         r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4448         if (r) {
4449                 DSSERR("Failed to set dispc clocks\n");
4450                 return r;
4451         }
4452
4453         return 0;
4454 }
4455
4456 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4457 {
4458         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4459         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4460         int r;
4461
4462         r = dsi_pll_init(dsidev, true, true);
4463         if (r)
4464                 goto err0;
4465
4466         r = dsi_configure_dsi_clocks(dssdev);
4467         if (r)
4468                 goto err1;
4469
4470         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4471         dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src);
4472         dss_select_lcd_clk_source(dssdev->manager->id,
4473                         dssdev->clocks.dispc.channel.lcd_clk_src);
4474
4475         DSSDBG("PLL OK\n");
4476
4477         r = dsi_configure_dispc_clocks(dssdev);
4478         if (r)
4479                 goto err2;
4480
4481         r = dsi_cio_init(dssdev);
4482         if (r)
4483                 goto err2;
4484
4485         _dsi_print_reset_status(dsidev);
4486
4487         dsi_proto_timings(dssdev);
4488         dsi_set_lp_clk_divisor(dssdev);
4489
4490         if (1)
4491                 _dsi_print_reset_status(dsidev);
4492
4493         r = dsi_proto_config(dssdev);
4494         if (r)
4495                 goto err3;
4496
4497         /* enable interface */
4498         dsi_vc_enable(dsidev, 0, 1);
4499         dsi_vc_enable(dsidev, 1, 1);
4500         dsi_vc_enable(dsidev, 2, 1);
4501         dsi_vc_enable(dsidev, 3, 1);
4502         dsi_if_enable(dsidev, 1);
4503         dsi_force_tx_stop_mode_io(dsidev);
4504
4505         return 0;
4506 err3:
4507         dsi_cio_uninit(dssdev);
4508 err2:
4509         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4510         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4511         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4512
4513 err1:
4514         dsi_pll_uninit(dsidev, true);
4515 err0:
4516         return r;
4517 }
4518
4519 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4520                 bool disconnect_lanes, bool enter_ulps)
4521 {
4522         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4523         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4524
4525         if (enter_ulps && !dsi->ulps_enabled)
4526                 dsi_enter_ulps(dsidev);
4527
4528         /* disable interface */
4529         dsi_if_enable(dsidev, 0);
4530         dsi_vc_enable(dsidev, 0, 0);
4531         dsi_vc_enable(dsidev, 1, 0);
4532         dsi_vc_enable(dsidev, 2, 0);
4533         dsi_vc_enable(dsidev, 3, 0);
4534
4535         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4536         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4537         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4538         dsi_cio_uninit(dssdev);
4539         dsi_pll_uninit(dsidev, disconnect_lanes);
4540 }
4541
4542 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4543 {
4544         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4545         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4546         int r = 0;
4547
4548         DSSDBG("dsi_display_enable\n");
4549
4550         WARN_ON(!dsi_bus_is_locked(dsidev));
4551
4552         mutex_lock(&dsi->lock);
4553
4554         if (dssdev->manager == NULL) {
4555                 DSSERR("failed to enable display: no manager\n");
4556                 r = -ENODEV;
4557                 goto err_start_dev;
4558         }
4559
4560         r = omap_dss_start_device(dssdev);
4561         if (r) {
4562                 DSSERR("failed to start device\n");
4563                 goto err_start_dev;
4564         }
4565
4566         r = dsi_runtime_get(dsidev);
4567         if (r)
4568                 goto err_get_dsi;
4569
4570         dsi_enable_pll_clock(dsidev, 1);
4571
4572         _dsi_initialize_irq(dsidev);
4573
4574         r = dsi_display_init_dispc(dssdev);
4575         if (r)
4576                 goto err_init_dispc;
4577
4578         r = dsi_display_init_dsi(dssdev);
4579         if (r)
4580                 goto err_init_dsi;
4581
4582         mutex_unlock(&dsi->lock);
4583
4584         return 0;
4585
4586 err_init_dsi:
4587         dsi_display_uninit_dispc(dssdev);
4588 err_init_dispc:
4589         dsi_enable_pll_clock(dsidev, 0);
4590         dsi_runtime_put(dsidev);
4591 err_get_dsi:
4592         omap_dss_stop_device(dssdev);
4593 err_start_dev:
4594         mutex_unlock(&dsi->lock);
4595         DSSDBG("dsi_display_enable FAILED\n");
4596         return r;
4597 }
4598 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4599
4600 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4601                 bool disconnect_lanes, bool enter_ulps)
4602 {
4603         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4604         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4605
4606         DSSDBG("dsi_display_disable\n");
4607
4608         WARN_ON(!dsi_bus_is_locked(dsidev));
4609
4610         mutex_lock(&dsi->lock);
4611
4612         dsi_sync_vc(dsidev, 0);
4613         dsi_sync_vc(dsidev, 1);
4614         dsi_sync_vc(dsidev, 2);
4615         dsi_sync_vc(dsidev, 3);
4616
4617         dsi_display_uninit_dispc(dssdev);
4618
4619         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4620
4621         dsi_runtime_put(dsidev);
4622         dsi_enable_pll_clock(dsidev, 0);
4623
4624         omap_dss_stop_device(dssdev);
4625
4626         mutex_unlock(&dsi->lock);
4627 }
4628 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4629
4630 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4631 {
4632         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4633         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4634
4635         dsi->te_enabled = enable;
4636         return 0;
4637 }
4638 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4639
4640 static int __init dsi_init_display(struct omap_dss_device *dssdev)
4641 {
4642         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4643         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4644
4645         DSSDBG("DSI init\n");
4646
4647         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4648                 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4649                         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4650         }
4651
4652         if (dsi->vdds_dsi_reg == NULL) {
4653                 struct regulator *vdds_dsi;
4654
4655                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4656
4657                 if (IS_ERR(vdds_dsi)) {
4658                         DSSERR("can't get VDDS_DSI regulator\n");
4659                         return PTR_ERR(vdds_dsi);
4660                 }
4661
4662                 dsi->vdds_dsi_reg = vdds_dsi;
4663         }
4664
4665         return 0;
4666 }
4667
4668 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4669 {
4670         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4671         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4672         int i;
4673
4674         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4675                 if (!dsi->vc[i].dssdev) {
4676                         dsi->vc[i].dssdev = dssdev;
4677                         *channel = i;
4678                         return 0;
4679                 }
4680         }
4681
4682         DSSERR("cannot get VC for display %s", dssdev->name);
4683         return -ENOSPC;
4684 }
4685 EXPORT_SYMBOL(omap_dsi_request_vc);
4686
4687 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4688 {
4689         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4690         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4691
4692         if (vc_id < 0 || vc_id > 3) {
4693                 DSSERR("VC ID out of range\n");
4694                 return -EINVAL;
4695         }
4696
4697         if (channel < 0 || channel > 3) {
4698                 DSSERR("Virtual Channel out of range\n");
4699                 return -EINVAL;
4700         }
4701
4702         if (dsi->vc[channel].dssdev != dssdev) {
4703                 DSSERR("Virtual Channel not allocated to display %s\n",
4704                         dssdev->name);
4705                 return -EINVAL;
4706         }
4707
4708         dsi->vc[channel].vc_id = vc_id;
4709
4710         return 0;
4711 }
4712 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4713
4714 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4715 {
4716         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4717         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4718
4719         if ((channel >= 0 && channel <= 3) &&
4720                 dsi->vc[channel].dssdev == dssdev) {
4721                 dsi->vc[channel].dssdev = NULL;
4722                 dsi->vc[channel].vc_id = 0;
4723         }
4724 }
4725 EXPORT_SYMBOL(omap_dsi_release_vc);
4726
4727 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4728 {
4729         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4730                 DSSERR("%s (%s) not active\n",
4731                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4732                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4733 }
4734
4735 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4736 {
4737         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4738                 DSSERR("%s (%s) not active\n",
4739                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4740                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4741 }
4742
4743 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4744 {
4745         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4746
4747         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4748         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4749         dsi->regm_dispc_max =
4750                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4751         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4752         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4753         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4754         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4755 }
4756
4757 static int dsi_get_clocks(struct platform_device *dsidev)
4758 {
4759         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4760         struct clk *clk;
4761
4762         clk = clk_get(&dsidev->dev, "fck");
4763         if (IS_ERR(clk)) {
4764                 DSSERR("can't get fck\n");
4765                 return PTR_ERR(clk);
4766         }
4767
4768         dsi->dss_clk = clk;
4769
4770         clk = clk_get(&dsidev->dev, "sys_clk");
4771         if (IS_ERR(clk)) {
4772                 DSSERR("can't get sys_clk\n");
4773                 clk_put(dsi->dss_clk);
4774                 dsi->dss_clk = NULL;
4775                 return PTR_ERR(clk);
4776         }
4777
4778         dsi->sys_clk = clk;
4779
4780         return 0;
4781 }
4782
4783 static void dsi_put_clocks(struct platform_device *dsidev)
4784 {
4785         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4786
4787         if (dsi->dss_clk)
4788                 clk_put(dsi->dss_clk);
4789         if (dsi->sys_clk)
4790                 clk_put(dsi->sys_clk);
4791 }
4792
4793 static void __init dsi_probe_pdata(struct platform_device *dsidev)
4794 {
4795         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4796         struct omap_dss_board_info *pdata = dsidev->dev.platform_data;
4797         int i, r;
4798
4799         for (i = 0; i < pdata->num_devices; ++i) {
4800                 struct omap_dss_device *dssdev = pdata->devices[i];
4801
4802                 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
4803                         continue;
4804
4805                 if (dssdev->phy.dsi.module != dsi->module_id)
4806                         continue;
4807
4808                 r = dsi_init_display(dssdev);
4809                 if (r) {
4810                         DSSERR("device %s init failed: %d\n", dssdev->name, r);
4811                         continue;
4812                 }
4813
4814                 r = omap_dss_register_device(dssdev, &dsidev->dev, i);
4815                 if (r)
4816                         DSSERR("device %s register failed: %d\n",
4817                                         dssdev->name, r);
4818         }
4819 }
4820
4821 /* DSI1 HW IP initialisation */
4822 static int __init omap_dsihw_probe(struct platform_device *dsidev)
4823 {
4824         u32 rev;
4825         int r, i;
4826         struct resource *dsi_mem;
4827         struct dsi_data *dsi;
4828
4829         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
4830         if (!dsi)
4831                 return -ENOMEM;
4832
4833         dsi->module_id = dsidev->id;
4834         dsi->pdev = dsidev;
4835         dsi_pdev_map[dsi->module_id] = dsidev;
4836         dev_set_drvdata(&dsidev->dev, dsi);
4837
4838         spin_lock_init(&dsi->irq_lock);
4839         spin_lock_init(&dsi->errors_lock);
4840         dsi->errors = 0;
4841
4842 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4843         spin_lock_init(&dsi->irq_stats_lock);
4844         dsi->irq_stats.last_reset = jiffies;
4845 #endif
4846
4847         mutex_init(&dsi->lock);
4848         sema_init(&dsi->bus_lock, 1);
4849
4850         INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4851                         dsi_framedone_timeout_work_callback);
4852
4853 #ifdef DSI_CATCH_MISSING_TE
4854         init_timer(&dsi->te_timer);
4855         dsi->te_timer.function = dsi_te_timeout;
4856         dsi->te_timer.data = 0;
4857 #endif
4858         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4859         if (!dsi_mem) {
4860                 DSSERR("can't get IORESOURCE_MEM DSI\n");
4861                 return -EINVAL;
4862         }
4863
4864         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
4865                                  resource_size(dsi_mem));
4866         if (!dsi->base) {
4867                 DSSERR("can't ioremap DSI\n");
4868                 return -ENOMEM;
4869         }
4870
4871         dsi->irq = platform_get_irq(dsi->pdev, 0);
4872         if (dsi->irq < 0) {
4873                 DSSERR("platform_get_irq failed\n");
4874                 return -ENODEV;
4875         }
4876
4877         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
4878                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
4879         if (r < 0) {
4880                 DSSERR("request_irq failed\n");
4881                 return r;
4882         }
4883
4884         /* DSI VCs initialization */
4885         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4886                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4887                 dsi->vc[i].dssdev = NULL;
4888                 dsi->vc[i].vc_id = 0;
4889         }
4890
4891         dsi_calc_clock_param_ranges(dsidev);
4892
4893         r = dsi_get_clocks(dsidev);
4894         if (r)
4895                 return r;
4896
4897         pm_runtime_enable(&dsidev->dev);
4898
4899         r = dsi_runtime_get(dsidev);
4900         if (r)
4901                 goto err_runtime_get;
4902
4903         rev = dsi_read_reg(dsidev, DSI_REVISION);
4904         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4905                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4906
4907         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4908          * of data to 3 by default */
4909         if (dss_has_feature(FEAT_DSI_GNQ))
4910                 /* NB_DATA_LANES */
4911                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4912         else
4913                 dsi->num_lanes_supported = 3;
4914
4915         dsi_probe_pdata(dsidev);
4916
4917         dsi_runtime_put(dsidev);
4918
4919         if (dsi->module_id == 0)
4920                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
4921         else if (dsi->module_id == 1)
4922                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
4923
4924 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4925         if (dsi->module_id == 0)
4926                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
4927         else if (dsi->module_id == 1)
4928                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
4929 #endif
4930         return 0;
4931
4932 err_runtime_get:
4933         pm_runtime_disable(&dsidev->dev);
4934         dsi_put_clocks(dsidev);
4935         return r;
4936 }
4937
4938 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
4939 {
4940         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4941
4942         WARN_ON(dsi->scp_clk_refcount > 0);
4943
4944         omap_dss_unregister_child_devices(&dsidev->dev);
4945
4946         pm_runtime_disable(&dsidev->dev);
4947
4948         dsi_put_clocks(dsidev);
4949
4950         if (dsi->vdds_dsi_reg != NULL) {
4951                 if (dsi->vdds_dsi_enabled) {
4952                         regulator_disable(dsi->vdds_dsi_reg);
4953                         dsi->vdds_dsi_enabled = false;
4954                 }
4955
4956                 regulator_put(dsi->vdds_dsi_reg);
4957                 dsi->vdds_dsi_reg = NULL;
4958         }
4959
4960         return 0;
4961 }
4962
4963 static int dsi_runtime_suspend(struct device *dev)
4964 {
4965         dispc_runtime_put();
4966
4967         return 0;
4968 }
4969
4970 static int dsi_runtime_resume(struct device *dev)
4971 {
4972         int r;
4973
4974         r = dispc_runtime_get();
4975         if (r)
4976                 return r;
4977
4978         return 0;
4979 }
4980
4981 static const struct dev_pm_ops dsi_pm_ops = {
4982         .runtime_suspend = dsi_runtime_suspend,
4983         .runtime_resume = dsi_runtime_resume,
4984 };
4985
4986 static struct platform_driver omap_dsihw_driver = {
4987         .remove         = __exit_p(omap_dsihw_remove),
4988         .driver         = {
4989                 .name   = "omapdss_dsi",
4990                 .owner  = THIS_MODULE,
4991                 .pm     = &dsi_pm_ops,
4992         },
4993 };
4994
4995 int __init dsi_init_platform_driver(void)
4996 {
4997         return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
4998 }
4999
5000 void __exit dsi_uninit_platform_driver(void)
5001 {
5002         platform_driver_unregister(&omap_dsihw_driver);
5003 }