drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44 #include <plat/clock.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48
  49 /*#define VERBOSE_IRQ*/
  50 #define DSI_CATCH_MISSING_TE
  51
  52 struct dsi_reg { u16 idx; };
  53
  54 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  55
  56 #define DSI_SZ_REGS             SZ_1K
  57 /* DSI Protocol Engine */
  58
  59 #define DSI_REVISION                    DSI_REG(0x0000)
  60 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  61 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  62 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  63 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  64 #define DSI_CTRL                        DSI_REG(0x0040)
  65 #define DSI_GNQ                         DSI_REG(0x0044)
  66 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  67 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  68 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  69 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  70 #define DSI_TIMING1                     DSI_REG(0x0058)
  71 #define DSI_TIMING2                     DSI_REG(0x005C)
  72 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  73 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  74 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  75 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  76 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  77 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  78 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  79 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  80 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  81 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  82 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  83 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  84 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  85 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  86 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  87 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  88 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  89 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  90 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  91 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  92 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  93
  94 /* DSIPHY_SCP */
  95
  96 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  97 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  98 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  99 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
 100 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
 101
 102 /* DSI_PLL_CTRL_SCP */
 103
 104 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 105 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 106 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 107 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 108 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 109
 110 #define REG_GET(dsidev, idx, start, end) \
 111         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 112
 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 114         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 115
 116 /* Global interrupts */
 117 #define DSI_IRQ_VC0             (1 << 0)
 118 #define DSI_IRQ_VC1             (1 << 1)
 119 #define DSI_IRQ_VC2             (1 << 2)
 120 #define DSI_IRQ_VC3             (1 << 3)
 121 #define DSI_IRQ_WAKEUP          (1 << 4)
 122 #define DSI_IRQ_RESYNC          (1 << 5)
 123 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 124 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 125 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 126 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 127 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 128 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 129 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 130 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 131 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 132 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 133 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 134 #define DSI_IRQ_ERROR_MASK \
 135         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 136         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 137 #define DSI_IRQ_CHANNEL_MASK    0xf
 138
 139 /* Virtual channel interrupts */
 140 #define DSI_VC_IRQ_CS           (1 << 0)
 141 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 142 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 143 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 144 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 145 #define DSI_VC_IRQ_BTA          (1 << 5)
 146 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 147 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 149 #define DSI_VC_IRQ_ERROR_MASK \
 150         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 151         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 152         DSI_VC_IRQ_FIFO_TX_UDF)
 153
 154 /* ComplexIO interrupts */
 155 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 156 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 157 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 158 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 159 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 160 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 161 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 162 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 163 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 164 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 165 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 166 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 167 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 168 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 169 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 170 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 171 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 172 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 173 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 174 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 187 #define DSI_CIO_IRQ_ERROR_MASK \
 188         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 189          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 190          DSI_CIO_IRQ_ERRSYNCESC5 | \
 191          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 192          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 193          DSI_CIO_IRQ_ERRESC5 | \
 194          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 195          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 196          DSI_CIO_IRQ_ERRCONTROL5 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 200          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 201          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 202
 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 204
 205 #define DSI_MAX_NR_ISRS                2
 206 #define DSI_MAX_NR_LANES        5
 207
 208 enum dsi_lane_function {
 209         DSI_LANE_UNUSED = 0,
 210         DSI_LANE_CLK,
 211         DSI_LANE_DATA1,
 212         DSI_LANE_DATA2,
 213         DSI_LANE_DATA3,
 214         DSI_LANE_DATA4,
 215 };
 216
 217 struct dsi_lane_config {
 218         enum dsi_lane_function function;
 219         u8 polarity;
 220 };
 221
 222 struct dsi_isr_data {
 223         omap_dsi_isr_t  isr;
 224         void            *arg;
 225         u32             mask;
 226 };
 227
 228 enum fifo_size {
 229         DSI_FIFO_SIZE_0         = 0,
 230         DSI_FIFO_SIZE_32        = 1,
 231         DSI_FIFO_SIZE_64        = 2,
 232         DSI_FIFO_SIZE_96        = 3,
 233         DSI_FIFO_SIZE_128       = 4,
 234 };
 235
 236 enum dsi_vc_source {
 237         DSI_VC_SOURCE_L4 = 0,
 238         DSI_VC_SOURCE_VP,
 239 };
 240
 241 struct dsi_irq_stats {
 242         unsigned long last_reset;
 243         unsigned irq_count;
 244         unsigned dsi_irqs[32];
 245         unsigned vc_irqs[4][32];
 246         unsigned cio_irqs[32];
 247 };
 248
 249 struct dsi_isr_tables {
 250         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 251         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 252         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 253 };
 254
 255 struct dsi_data {
 256         struct platform_device *pdev;
 257         void __iomem    *base;
 258
 259         int module_id;
 260
 261         int irq;
 262
 263         struct clk *dss_clk;
 264         struct clk *sys_clk;
 265
 266         struct dsi_clock_info current_cinfo;
 267
 268         bool vdds_dsi_enabled;
 269         struct regulator *vdds_dsi_reg;
 270
 271         struct {
 272                 enum dsi_vc_source source;
 273                 struct omap_dss_device *dssdev;
 274                 enum fifo_size fifo_size;
 275                 int vc_id;
 276         } vc[4];
 277
 278         struct mutex lock;
 279         struct semaphore bus_lock;
 280
 281         unsigned pll_locked;
 282
 283         spinlock_t irq_lock;
 284         struct dsi_isr_tables isr_tables;
 285         /* space for a copy used by the interrupt handler */
 286         struct dsi_isr_tables isr_tables_copy;
 287
 288         int update_channel;
 289 #ifdef DEBUG
 290         unsigned update_bytes;
 291 #endif
 292
 293         bool te_enabled;
 294         bool ulps_enabled;
 295
 296         void (*framedone_callback)(int, void *);
 297         void *framedone_data;
 298
 299         struct delayed_work framedone_timeout_work;
 300
 301 #ifdef DSI_CATCH_MISSING_TE
 302         struct timer_list te_timer;
 303 #endif
 304
 305         unsigned long cache_req_pck;
 306         unsigned long cache_clk_freq;
 307         struct dsi_clock_info cache_cinfo;
 308
 309         u32             errors;
 310         spinlock_t      errors_lock;
 311 #ifdef DEBUG
 312         ktime_t perf_setup_time;
 313         ktime_t perf_start_time;
 314 #endif
 315         int debug_read;
 316         int debug_write;
 317
 318 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 319         spinlock_t irq_stats_lock;
 320         struct dsi_irq_stats irq_stats;
 321 #endif
 322         /* DSI PLL Parameter Ranges */
 323         unsigned long regm_max, regn_max;
 324         unsigned long  regm_dispc_max, regm_dsi_max;
 325         unsigned long  fint_min, fint_max;
 326         unsigned long lpdiv_max;
 327
 328         unsigned num_lanes_supported;
 329
 330         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 331         unsigned num_lanes_used;
 332
 333         unsigned scp_clk_refcount;
 334
 335         struct dss_lcd_mgr_config mgr_config;
 336 };
 337
 338 struct dsi_packet_sent_handler_data {
 339         struct platform_device *dsidev;
 340         struct completion *completion;
 341 };
 342
 343 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
 344
 345 #ifdef DEBUG
 346 static bool dsi_perf;
 347 module_param(dsi_perf, bool, 0644);
 348 #endif
 349
 350 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 351 {
 352         return dev_get_drvdata(&dsidev->dev);
 353 }
 354
 355 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 356 {
 357         return dsi_pdev_map[dssdev->phy.dsi.module];
 358 }
 359
 360 struct platform_device *dsi_get_dsidev_from_id(int module)
 361 {
 362         return dsi_pdev_map[module];
 363 }
 364
 365 static inline void dsi_write_reg(struct platform_device *dsidev,
 366                 const struct dsi_reg idx, u32 val)
 367 {
 368         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 369
 370         __raw_writel(val, dsi->base + idx.idx);
 371 }
 372
 373 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 374                 const struct dsi_reg idx)
 375 {
 376         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 377
 378         return __raw_readl(dsi->base + idx.idx);
 379 }
 380
 381 void dsi_bus_lock(struct omap_dss_device *dssdev)
 382 {
 383         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 384         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 385
 386         down(&dsi->bus_lock);
 387 }
 388 EXPORT_SYMBOL(dsi_bus_lock);
 389
 390 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 391 {
 392         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 393         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 394
 395         up(&dsi->bus_lock);
 396 }
 397 EXPORT_SYMBOL(dsi_bus_unlock);
 398
 399 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 400 {
 401         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 402
 403         return dsi->bus_lock.count == 0;
 404 }
 405
 406 static void dsi_completion_handler(void *data, u32 mask)
 407 {
 408         complete((struct completion *)data);
 409 }
 410
 411 static inline int wait_for_bit_change(struct platform_device *dsidev,
 412                 const struct dsi_reg idx, int bitnum, int value)
 413 {
 414         unsigned long timeout;
 415         ktime_t wait;
 416         int t;
 417
 418         /* first busyloop to see if the bit changes right away */
 419         t = 100;
 420         while (t-- > 0) {
 421                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 422                         return value;
 423         }
 424
 425         /* then loop for 500ms, sleeping for 1ms in between */
 426         timeout = jiffies + msecs_to_jiffies(500);
 427         while (time_before(jiffies, timeout)) {
 428                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 429                         return value;
 430
 431                 wait = ns_to_ktime(1000 * 1000);
 432                 set_current_state(TASK_UNINTERRUPTIBLE);
 433                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 434         }
 435
 436         return !value;
 437 }
 438
 439 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 440 {
 441         switch (fmt) {
 442         case OMAP_DSS_DSI_FMT_RGB888:
 443         case OMAP_DSS_DSI_FMT_RGB666:
 444                 return 24;
 445         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 446                 return 18;
 447         case OMAP_DSS_DSI_FMT_RGB565:
 448                 return 16;
 449         default:
 450                 BUG();
 451                 return 0;
 452         }
 453 }
 454
 455 #ifdef DEBUG
 456 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 457 {
 458         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 459         dsi->perf_setup_time = ktime_get();
 460 }
 461
 462 static void dsi_perf_mark_start(struct platform_device *dsidev)
 463 {
 464         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 465         dsi->perf_start_time = ktime_get();
 466 }
 467
 468 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 469 {
 470         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 471         ktime_t t, setup_time, trans_time;
 472         u32 total_bytes;
 473         u32 setup_us, trans_us, total_us;
 474
 475         if (!dsi_perf)
 476                 return;
 477
 478         t = ktime_get();
 479
 480         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 481         setup_us = (u32)ktime_to_us(setup_time);
 482         if (setup_us == 0)
 483                 setup_us = 1;
 484
 485         trans_time = ktime_sub(t, dsi->perf_start_time);
 486         trans_us = (u32)ktime_to_us(trans_time);
 487         if (trans_us == 0)
 488                 trans_us = 1;
 489
 490         total_us = setup_us + trans_us;
 491
 492         total_bytes = dsi->update_bytes;
 493
 494         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 495                         "%u bytes, %u kbytes/sec\n",
 496                         name,
 497                         setup_us,
 498                         trans_us,
 499                         total_us,
 500                         1000*1000 / total_us,
 501                         total_bytes,
 502                         total_bytes * 1000 / total_us);
 503 }
 504 #else
 505 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 506 {
 507 }
 508
 509 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 510 {
 511 }
 512
 513 static inline void dsi_perf_show(struct platform_device *dsidev,
 514                 const char *name)
 515 {
 516 }
 517 #endif
 518
 519 static void print_irq_status(u32 status)
 520 {
 521         if (status == 0)
 522                 return;
 523
 524 #ifndef VERBOSE_IRQ
 525         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 526                 return;
 527 #endif
 528         printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
 529
 530 #define PIS(x) \
 531         if (status & DSI_IRQ_##x) \
 532                 printk(#x " ");
 533 #ifdef VERBOSE_IRQ
 534         PIS(VC0);
 535         PIS(VC1);
 536         PIS(VC2);
 537         PIS(VC3);
 538 #endif
 539         PIS(WAKEUP);
 540         PIS(RESYNC);
 541         PIS(PLL_LOCK);
 542         PIS(PLL_UNLOCK);
 543         PIS(PLL_RECALL);
 544         PIS(COMPLEXIO_ERR);
 545         PIS(HS_TX_TIMEOUT);
 546         PIS(LP_RX_TIMEOUT);
 547         PIS(TE_TRIGGER);
 548         PIS(ACK_TRIGGER);
 549         PIS(SYNC_LOST);
 550         PIS(LDO_POWER_GOOD);
 551         PIS(TA_TIMEOUT);
 552 #undef PIS
 553
 554         printk("\n");
 555 }
 556
 557 static void print_irq_status_vc(int channel, u32 status)
 558 {
 559         if (status == 0)
 560                 return;
 561
 562 #ifndef VERBOSE_IRQ
 563         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 564                 return;
 565 #endif
 566         printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
 567
 568 #define PIS(x) \
 569         if (status & DSI_VC_IRQ_##x) \
 570                 printk(#x " ");
 571         PIS(CS);
 572         PIS(ECC_CORR);
 573 #ifdef VERBOSE_IRQ
 574         PIS(PACKET_SENT);
 575 #endif
 576         PIS(FIFO_TX_OVF);
 577         PIS(FIFO_RX_OVF);
 578         PIS(BTA);
 579         PIS(ECC_NO_CORR);
 580         PIS(FIFO_TX_UDF);
 581         PIS(PP_BUSY_CHANGE);
 582 #undef PIS
 583         printk("\n");
 584 }
 585
 586 static void print_irq_status_cio(u32 status)
 587 {
 588         if (status == 0)
 589                 return;
 590
 591         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 592
 593 #define PIS(x) \
 594         if (status & DSI_CIO_IRQ_##x) \
 595                 printk(#x " ");
 596         PIS(ERRSYNCESC1);
 597         PIS(ERRSYNCESC2);
 598         PIS(ERRSYNCESC3);
 599         PIS(ERRESC1);
 600         PIS(ERRESC2);
 601         PIS(ERRESC3);
 602         PIS(ERRCONTROL1);
 603         PIS(ERRCONTROL2);
 604         PIS(ERRCONTROL3);
 605         PIS(STATEULPS1);
 606         PIS(STATEULPS2);
 607         PIS(STATEULPS3);
 608         PIS(ERRCONTENTIONLP0_1);
 609         PIS(ERRCONTENTIONLP1_1);
 610         PIS(ERRCONTENTIONLP0_2);
 611         PIS(ERRCONTENTIONLP1_2);
 612         PIS(ERRCONTENTIONLP0_3);
 613         PIS(ERRCONTENTIONLP1_3);
 614         PIS(ULPSACTIVENOT_ALL0);
 615         PIS(ULPSACTIVENOT_ALL1);
 616 #undef PIS
 617
 618         printk("\n");
 619 }
 620
 621 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 622 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 623                 u32 *vcstatus, u32 ciostatus)
 624 {
 625         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 626         int i;
 627
 628         spin_lock(&dsi->irq_stats_lock);
 629
 630         dsi->irq_stats.irq_count++;
 631         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 632
 633         for (i = 0; i < 4; ++i)
 634                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 635
 636         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 637
 638         spin_unlock(&dsi->irq_stats_lock);
 639 }
 640 #else
 641 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 642 #endif
 643
 644 static int debug_irq;
 645
 646 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 647                 u32 *vcstatus, u32 ciostatus)
 648 {
 649         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 650         int i;
 651
 652         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 653                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 654                 print_irq_status(irqstatus);
 655                 spin_lock(&dsi->errors_lock);
 656                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 657                 spin_unlock(&dsi->errors_lock);
 658         } else if (debug_irq) {
 659                 print_irq_status(irqstatus);
 660         }
 661
 662         for (i = 0; i < 4; ++i) {
 663                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 664                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 665                                        i, vcstatus[i]);
 666                         print_irq_status_vc(i, vcstatus[i]);
 667                 } else if (debug_irq) {
 668                         print_irq_status_vc(i, vcstatus[i]);
 669                 }
 670         }
 671
 672         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 673                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 674                 print_irq_status_cio(ciostatus);
 675         } else if (debug_irq) {
 676                 print_irq_status_cio(ciostatus);
 677         }
 678 }
 679
 680 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 681                 unsigned isr_array_size, u32 irqstatus)
 682 {
 683         struct dsi_isr_data *isr_data;
 684         int i;
 685
 686         for (i = 0; i < isr_array_size; i++) {
 687                 isr_data = &isr_array[i];
 688                 if (isr_data->isr && isr_data->mask & irqstatus)
 689                         isr_data->isr(isr_data->arg, irqstatus);
 690         }
 691 }
 692
 693 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 694                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 695 {
 696         int i;
 697
 698         dsi_call_isrs(isr_tables->isr_table,
 699                         ARRAY_SIZE(isr_tables->isr_table),
 700                         irqstatus);
 701
 702         for (i = 0; i < 4; ++i) {
 703                 if (vcstatus[i] == 0)
 704                         continue;
 705                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 706                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 707                                 vcstatus[i]);
 708         }
 709
 710         if (ciostatus != 0)
 711                 dsi_call_isrs(isr_tables->isr_table_cio,
 712                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 713                                 ciostatus);
 714 }
 715
 716 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 717 {
 718         struct platform_device *dsidev;
 719         struct dsi_data *dsi;
 720         u32 irqstatus, vcstatus[4], ciostatus;
 721         int i;
 722
 723         dsidev = (struct platform_device *) arg;
 724         dsi = dsi_get_dsidrv_data(dsidev);
 725
 726         spin_lock(&dsi->irq_lock);
 727
 728         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 729
 730         /* IRQ is not for us */
 731         if (!irqstatus) {
 732                 spin_unlock(&dsi->irq_lock);
 733                 return IRQ_NONE;
 734         }
 735
 736         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 737         /* flush posted write */
 738         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 739
 740         for (i = 0; i < 4; ++i) {
 741                 if ((irqstatus & (1 << i)) == 0) {
 742                         vcstatus[i] = 0;
 743                         continue;
 744                 }
 745
 746                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 747
 748                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 749                 /* flush posted write */
 750                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 751         }
 752
 753         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 754                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 755
 756                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 757                 /* flush posted write */
 758                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 759         } else {
 760                 ciostatus = 0;
 761         }
 762
 763 #ifdef DSI_CATCH_MISSING_TE
 764         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 765                 del_timer(&dsi->te_timer);
 766 #endif
 767
 768         /* make a copy and unlock, so that isrs can unregister
 769          * themselves */
 770         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 771                 sizeof(dsi->isr_tables));
 772
 773         spin_unlock(&dsi->irq_lock);
 774
 775         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 776
 777         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 778
 779         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 780
 781         return IRQ_HANDLED;
 782 }
 783
 784 /* dsi->irq_lock has to be locked by the caller */
 785 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 786                 struct dsi_isr_data *isr_array,
 787                 unsigned isr_array_size, u32 default_mask,
 788                 const struct dsi_reg enable_reg,
 789                 const struct dsi_reg status_reg)
 790 {
 791         struct dsi_isr_data *isr_data;
 792         u32 mask;
 793         u32 old_mask;
 794         int i;
 795
 796         mask = default_mask;
 797
 798         for (i = 0; i < isr_array_size; i++) {
 799                 isr_data = &isr_array[i];
 800
 801                 if (isr_data->isr == NULL)
 802                         continue;
 803
 804                 mask |= isr_data->mask;
 805         }
 806
 807         old_mask = dsi_read_reg(dsidev, enable_reg);
 808         /* clear the irqstatus for newly enabled irqs */
 809         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 810         dsi_write_reg(dsidev, enable_reg, mask);
 811
 812         /* flush posted writes */
 813         dsi_read_reg(dsidev, enable_reg);
 814         dsi_read_reg(dsidev, status_reg);
 815 }
 816
 817 /* dsi->irq_lock has to be locked by the caller */
 818 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 819 {
 820         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 821         u32 mask = DSI_IRQ_ERROR_MASK;
 822 #ifdef DSI_CATCH_MISSING_TE
 823         mask |= DSI_IRQ_TE_TRIGGER;
 824 #endif
 825         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 826                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 827                         DSI_IRQENABLE, DSI_IRQSTATUS);
 828 }
 829
 830 /* dsi->irq_lock has to be locked by the caller */
 831 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 832 {
 833         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 834
 835         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 836                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 837                         DSI_VC_IRQ_ERROR_MASK,
 838                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 839 }
 840
 841 /* dsi->irq_lock has to be locked by the caller */
 842 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 843 {
 844         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 845
 846         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 847                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 848                         DSI_CIO_IRQ_ERROR_MASK,
 849                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 850 }
 851
 852 static void _dsi_initialize_irq(struct platform_device *dsidev)
 853 {
 854         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 855         unsigned long flags;
 856         int vc;
 857
 858         spin_lock_irqsave(&dsi->irq_lock, flags);
 859
 860         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 861
 862         _omap_dsi_set_irqs(dsidev);
 863         for (vc = 0; vc < 4; ++vc)
 864                 _omap_dsi_set_irqs_vc(dsidev, vc);
 865         _omap_dsi_set_irqs_cio(dsidev);
 866
 867         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 868 }
 869
 870 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 871                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 872 {
 873         struct dsi_isr_data *isr_data;
 874         int free_idx;
 875         int i;
 876
 877         BUG_ON(isr == NULL);
 878
 879         /* check for duplicate entry and find a free slot */
 880         free_idx = -1;
 881         for (i = 0; i < isr_array_size; i++) {
 882                 isr_data = &isr_array[i];
 883
 884                 if (isr_data->isr == isr && isr_data->arg == arg &&
 885                                 isr_data->mask == mask) {
 886                         return -EINVAL;
 887                 }
 888
 889                 if (isr_data->isr == NULL && free_idx == -1)
 890                         free_idx = i;
 891         }
 892
 893         if (free_idx == -1)
 894                 return -EBUSY;
 895
 896         isr_data = &isr_array[free_idx];
 897         isr_data->isr = isr;
 898         isr_data->arg = arg;
 899         isr_data->mask = mask;
 900
 901         return 0;
 902 }
 903
 904 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 905                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 906 {
 907         struct dsi_isr_data *isr_data;
 908         int i;
 909
 910         for (i = 0; i < isr_array_size; i++) {
 911                 isr_data = &isr_array[i];
 912                 if (isr_data->isr != isr || isr_data->arg != arg ||
 913                                 isr_data->mask != mask)
 914                         continue;
 915
 916                 isr_data->isr = NULL;
 917                 isr_data->arg = NULL;
 918                 isr_data->mask = 0;
 919
 920                 return 0;
 921         }
 922
 923         return -EINVAL;
 924 }
 925
 926 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 927                 void *arg, u32 mask)
 928 {
 929         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 930         unsigned long flags;
 931         int r;
 932
 933         spin_lock_irqsave(&dsi->irq_lock, flags);
 934
 935         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 936                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 937
 938         if (r == 0)
 939                 _omap_dsi_set_irqs(dsidev);
 940
 941         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 942
 943         return r;
 944 }
 945
 946 static int dsi_unregister_isr(struct platform_device *dsidev,
 947                 omap_dsi_isr_t isr, void *arg, u32 mask)
 948 {
 949         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 950         unsigned long flags;
 951         int r;
 952
 953         spin_lock_irqsave(&dsi->irq_lock, flags);
 954
 955         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 956                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 957
 958         if (r == 0)
 959                 _omap_dsi_set_irqs(dsidev);
 960
 961         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 962
 963         return r;
 964 }
 965
 966 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 967                 omap_dsi_isr_t isr, void *arg, u32 mask)
 968 {
 969         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 970         unsigned long flags;
 971         int r;
 972
 973         spin_lock_irqsave(&dsi->irq_lock, flags);
 974
 975         r = _dsi_register_isr(isr, arg, mask,
 976                         dsi->isr_tables.isr_table_vc[channel],
 977                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 978
 979         if (r == 0)
 980                 _omap_dsi_set_irqs_vc(dsidev, channel);
 981
 982         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 983
 984         return r;
 985 }
 986
 987 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 988                 omap_dsi_isr_t isr, void *arg, u32 mask)
 989 {
 990         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 991         unsigned long flags;
 992         int r;
 993
 994         spin_lock_irqsave(&dsi->irq_lock, flags);
 995
 996         r = _dsi_unregister_isr(isr, arg, mask,
 997                         dsi->isr_tables.isr_table_vc[channel],
 998                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 999
1000         if (r == 0)
1001                 _omap_dsi_set_irqs_vc(dsidev, channel);
1002
1003         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1004
1005         return r;
1006 }
1007
1008 static int dsi_register_isr_cio(struct platform_device *dsidev,
1009                 omap_dsi_isr_t isr, void *arg, u32 mask)
1010 {
1011         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1012         unsigned long flags;
1013         int r;
1014
1015         spin_lock_irqsave(&dsi->irq_lock, flags);
1016
1017         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1018                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1019
1020         if (r == 0)
1021                 _omap_dsi_set_irqs_cio(dsidev);
1022
1023         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1024
1025         return r;
1026 }
1027
1028 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1029                 omap_dsi_isr_t isr, void *arg, u32 mask)
1030 {
1031         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1032         unsigned long flags;
1033         int r;
1034
1035         spin_lock_irqsave(&dsi->irq_lock, flags);
1036
1037         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1038                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1039
1040         if (r == 0)
1041                 _omap_dsi_set_irqs_cio(dsidev);
1042
1043         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1044
1045         return r;
1046 }
1047
1048 static u32 dsi_get_errors(struct platform_device *dsidev)
1049 {
1050         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1051         unsigned long flags;
1052         u32 e;
1053         spin_lock_irqsave(&dsi->errors_lock, flags);
1054         e = dsi->errors;
1055         dsi->errors = 0;
1056         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1057         return e;
1058 }
1059
1060 int dsi_runtime_get(struct platform_device *dsidev)
1061 {
1062         int r;
1063         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1064
1065         DSSDBG("dsi_runtime_get\n");
1066
1067         r = pm_runtime_get_sync(&dsi->pdev->dev);
1068         WARN_ON(r < 0);
1069         return r < 0 ? r : 0;
1070 }
1071
1072 void dsi_runtime_put(struct platform_device *dsidev)
1073 {
1074         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1075         int r;
1076
1077         DSSDBG("dsi_runtime_put\n");
1078
1079         r = pm_runtime_put_sync(&dsi->pdev->dev);
1080         WARN_ON(r < 0 && r != -ENOSYS);
1081 }
1082
1083 /* source clock for DSI PLL. this could also be PCLKFREE */
1084 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1085                 bool enable)
1086 {
1087         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1088
1089         if (enable)
1090                 clk_prepare_enable(dsi->sys_clk);
1091         else
1092                 clk_disable_unprepare(dsi->sys_clk);
1093
1094         if (enable && dsi->pll_locked) {
1095                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1096                         DSSERR("cannot lock PLL when enabling clocks\n");
1097         }
1098 }
1099
1100 #ifdef DEBUG
1101 static void _dsi_print_reset_status(struct platform_device *dsidev)
1102 {
1103         u32 l;
1104         int b0, b1, b2;
1105
1106         if (!dss_debug)
1107                 return;
1108
1109         /* A dummy read using the SCP interface to any DSIPHY register is
1110          * required after DSIPHY reset to complete the reset of the DSI complex
1111          * I/O. */
1112         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1113
1114         printk(KERN_DEBUG "DSI resets: ");
1115
1116         l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1117         printk("PLL (%d) ", FLD_GET(l, 0, 0));
1118
1119         l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1120         printk("CIO (%d) ", FLD_GET(l, 29, 29));
1121
1122         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1123                 b0 = 28;
1124                 b1 = 27;
1125                 b2 = 26;
1126         } else {
1127                 b0 = 24;
1128                 b1 = 25;
1129                 b2 = 26;
1130         }
1131
1132         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1133         printk("PHY (%x%x%x, %d, %d, %d)\n",
1134                         FLD_GET(l, b0, b0),
1135                         FLD_GET(l, b1, b1),
1136                         FLD_GET(l, b2, b2),
1137                         FLD_GET(l, 29, 29),
1138                         FLD_GET(l, 30, 30),
1139                         FLD_GET(l, 31, 31));
1140 }
1141 #else
1142 #define _dsi_print_reset_status(x)
1143 #endif
1144
1145 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1146 {
1147         DSSDBG("dsi_if_enable(%d)\n", enable);
1148
1149         enable = enable ? 1 : 0;
1150         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1151
1152         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1153                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1154                         return -EIO;
1155         }
1156
1157         return 0;
1158 }
1159
1160 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1161 {
1162         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1163
1164         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1165 }
1166
1167 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1168 {
1169         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1170
1171         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1172 }
1173
1174 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1175 {
1176         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1177
1178         return dsi->current_cinfo.clkin4ddr / 16;
1179 }
1180
1181 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1182 {
1183         unsigned long r;
1184         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1185
1186         if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1187                 /* DSI FCLK source is DSS_CLK_FCK */
1188                 r = clk_get_rate(dsi->dss_clk);
1189         } else {
1190                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1191                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1192         }
1193
1194         return r;
1195 }
1196
1197 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1198 {
1199         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1200         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1201         unsigned long dsi_fclk;
1202         unsigned lp_clk_div;
1203         unsigned long lp_clk;
1204
1205         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1206
1207         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1208                 return -EINVAL;
1209
1210         dsi_fclk = dsi_fclk_rate(dsidev);
1211
1212         lp_clk = dsi_fclk / 2 / lp_clk_div;
1213
1214         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1215         dsi->current_cinfo.lp_clk = lp_clk;
1216         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1217
1218         /* LP_CLK_DIVISOR */
1219         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1220
1221         /* LP_RX_SYNCHRO_ENABLE */
1222         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1223
1224         return 0;
1225 }
1226
1227 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1228 {
1229         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1230
1231         if (dsi->scp_clk_refcount++ == 0)
1232                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1233 }
1234
1235 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1236 {
1237         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1238
1239         WARN_ON(dsi->scp_clk_refcount == 0);
1240         if (--dsi->scp_clk_refcount == 0)
1241                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1242 }
1243
1244 enum dsi_pll_power_state {
1245         DSI_PLL_POWER_OFF       = 0x0,
1246         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1247         DSI_PLL_POWER_ON_ALL    = 0x2,
1248         DSI_PLL_POWER_ON_DIV    = 0x3,
1249 };
1250
1251 static int dsi_pll_power(struct platform_device *dsidev,
1252                 enum dsi_pll_power_state state)
1253 {
1254         int t = 0;
1255
1256         /* DSI-PLL power command 0x3 is not working */
1257         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1258                         state == DSI_PLL_POWER_ON_DIV)
1259                 state = DSI_PLL_POWER_ON_ALL;
1260
1261         /* PLL_PWR_CMD */
1262         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1263
1264         /* PLL_PWR_STATUS */
1265         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1266                 if (++t > 1000) {
1267                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1268                                         state);
1269                         return -ENODEV;
1270                 }
1271                 udelay(1);
1272         }
1273
1274         return 0;
1275 }
1276
1277 /* calculate clock rates using dividers in cinfo */
1278 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1279                 struct dsi_clock_info *cinfo)
1280 {
1281         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1282
1283         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1284                 return -EINVAL;
1285
1286         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1287                 return -EINVAL;
1288
1289         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1290                 return -EINVAL;
1291
1292         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1293                 return -EINVAL;
1294
1295         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1296         cinfo->fint = cinfo->clkin / cinfo->regn;
1297
1298         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1299                 return -EINVAL;
1300
1301         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1302
1303         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1304                 return -EINVAL;
1305
1306         if (cinfo->regm_dispc > 0)
1307                 cinfo->dsi_pll_hsdiv_dispc_clk =
1308                         cinfo->clkin4ddr / cinfo->regm_dispc;
1309         else
1310                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1311
1312         if (cinfo->regm_dsi > 0)
1313                 cinfo->dsi_pll_hsdiv_dsi_clk =
1314                         cinfo->clkin4ddr / cinfo->regm_dsi;
1315         else
1316                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1317
1318         return 0;
1319 }
1320
1321 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
1322                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1323                 struct dispc_clock_info *dispc_cinfo)
1324 {
1325         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1326         struct dsi_clock_info cur, best;
1327         struct dispc_clock_info best_dispc;
1328         int min_fck_per_pck;
1329         int match = 0;
1330         unsigned long dss_sys_clk, max_dss_fck;
1331
1332         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1333
1334         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1335
1336         if (req_pck == dsi->cache_req_pck &&
1337                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1338                 DSSDBG("DSI clock info found from cache\n");
1339                 *dsi_cinfo = dsi->cache_cinfo;
1340                 dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk,
1341                         dispc_cinfo);
1342                 return 0;
1343         }
1344
1345         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1346
1347         if (min_fck_per_pck &&
1348                 req_pck * min_fck_per_pck > max_dss_fck) {
1349                 DSSERR("Requested pixel clock not possible with the current "
1350                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1351                                 "the constraint off.\n");
1352                 min_fck_per_pck = 0;
1353         }
1354
1355         DSSDBG("dsi_pll_calc\n");
1356
1357 retry:
1358         memset(&best, 0, sizeof(best));
1359         memset(&best_dispc, 0, sizeof(best_dispc));
1360
1361         memset(&cur, 0, sizeof(cur));
1362         cur.clkin = dss_sys_clk;
1363
1364         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1365         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1366         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1367                 cur.fint = cur.clkin / cur.regn;
1368
1369                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1370                         continue;
1371
1372                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1373                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1374                         unsigned long a, b;
1375
1376                         a = 2 * cur.regm * (cur.clkin/1000);
1377                         b = cur.regn;
1378                         cur.clkin4ddr = a / b * 1000;
1379
1380                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1381                                 break;
1382
1383                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1384                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1385                         for (cur.regm_dispc = 1; cur.regm_dispc <
1386                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1387                                 struct dispc_clock_info cur_dispc;
1388                                 cur.dsi_pll_hsdiv_dispc_clk =
1389                                         cur.clkin4ddr / cur.regm_dispc;
1390
1391                                 /* this will narrow down the search a bit,
1392                                  * but still give pixclocks below what was
1393                                  * requested */
1394                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1395                                         break;
1396
1397                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1398                                         continue;
1399
1400                                 if (min_fck_per_pck &&
1401                                         cur.dsi_pll_hsdiv_dispc_clk <
1402                                                 req_pck * min_fck_per_pck)
1403                                         continue;
1404
1405                                 match = 1;
1406
1407                                 dispc_find_clk_divs(req_pck,
1408                                                 cur.dsi_pll_hsdiv_dispc_clk,
1409                                                 &cur_dispc);
1410
1411                                 if (abs(cur_dispc.pck - req_pck) <
1412                                                 abs(best_dispc.pck - req_pck)) {
1413                                         best = cur;
1414                                         best_dispc = cur_dispc;
1415
1416                                         if (cur_dispc.pck == req_pck)
1417                                                 goto found;
1418                                 }
1419                         }
1420                 }
1421         }
1422 found:
1423         if (!match) {
1424                 if (min_fck_per_pck) {
1425                         DSSERR("Could not find suitable clock settings.\n"
1426                                         "Turning FCK/PCK constraint off and"
1427                                         "trying again.\n");
1428                         min_fck_per_pck = 0;
1429                         goto retry;
1430                 }
1431
1432                 DSSERR("Could not find suitable clock settings.\n");
1433
1434                 return -EINVAL;
1435         }
1436
1437         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1438         best.regm_dsi = 0;
1439         best.dsi_pll_hsdiv_dsi_clk = 0;
1440
1441         if (dsi_cinfo)
1442                 *dsi_cinfo = best;
1443         if (dispc_cinfo)
1444                 *dispc_cinfo = best_dispc;
1445
1446         dsi->cache_req_pck = req_pck;
1447         dsi->cache_clk_freq = 0;
1448         dsi->cache_cinfo = best;
1449
1450         return 0;
1451 }
1452
1453 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1454                 struct dsi_clock_info *cinfo)
1455 {
1456         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1457         int r = 0;
1458         u32 l;
1459         int f = 0;
1460         u8 regn_start, regn_end, regm_start, regm_end;
1461         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1462
1463         DSSDBGF();
1464
1465         dsi->current_cinfo.clkin = cinfo->clkin;
1466         dsi->current_cinfo.fint = cinfo->fint;
1467         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1468         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1469                         cinfo->dsi_pll_hsdiv_dispc_clk;
1470         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1471                         cinfo->dsi_pll_hsdiv_dsi_clk;
1472
1473         dsi->current_cinfo.regn = cinfo->regn;
1474         dsi->current_cinfo.regm = cinfo->regm;
1475         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1476         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1477
1478         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1479
1480         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1481
1482         /* DSIPHY == CLKIN4DDR */
1483         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1484                         cinfo->regm,
1485                         cinfo->regn,
1486                         cinfo->clkin,
1487                         cinfo->clkin4ddr);
1488
1489         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1490                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1491
1492         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1493
1494         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1495                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1496                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1497                 cinfo->dsi_pll_hsdiv_dispc_clk);
1498         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1499                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1500                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1501                 cinfo->dsi_pll_hsdiv_dsi_clk);
1502
1503         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1504         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1505         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1506                         &regm_dispc_end);
1507         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1508                         &regm_dsi_end);
1509
1510         /* DSI_PLL_AUTOMODE = manual */
1511         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1512
1513         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1514         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1515         /* DSI_PLL_REGN */
1516         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1517         /* DSI_PLL_REGM */
1518         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1519         /* DSI_CLOCK_DIV */
1520         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1521                         regm_dispc_start, regm_dispc_end);
1522         /* DSIPROTO_CLOCK_DIV */
1523         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1524                         regm_dsi_start, regm_dsi_end);
1525         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1526
1527         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1528
1529         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1530                 f = cinfo->fint < 1000000 ? 0x3 :
1531                         cinfo->fint < 1250000 ? 0x4 :
1532                         cinfo->fint < 1500000 ? 0x5 :
1533                         cinfo->fint < 1750000 ? 0x6 :
1534                         0x7;
1535         }
1536
1537         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1538
1539         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1540                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1541         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1542         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1543         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1544         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1545
1546         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1547
1548         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1549                 DSSERR("dsi pll go bit not going down.\n");
1550                 r = -EIO;
1551                 goto err;
1552         }
1553
1554         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1555                 DSSERR("cannot lock PLL\n");
1556                 r = -EIO;
1557                 goto err;
1558         }
1559
1560         dsi->pll_locked = 1;
1561
1562         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1563         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1564         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1565         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1566         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1567         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1568         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1569         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1570         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1571         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1572         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1573         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1574         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1575         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1576         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1577         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1578
1579         DSSDBG("PLL config done\n");
1580 err:
1581         return r;
1582 }
1583
1584 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1585                 bool enable_hsdiv)
1586 {
1587         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1588         int r = 0;
1589         enum dsi_pll_power_state pwstate;
1590
1591         DSSDBG("PLL init\n");
1592
1593         if (dsi->vdds_dsi_reg == NULL) {
1594                 struct regulator *vdds_dsi;
1595
1596                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1597
1598                 if (IS_ERR(vdds_dsi)) {
1599                         DSSERR("can't get VDDS_DSI regulator\n");
1600                         return PTR_ERR(vdds_dsi);
1601                 }
1602
1603                 dsi->vdds_dsi_reg = vdds_dsi;
1604         }
1605
1606         dsi_enable_pll_clock(dsidev, 1);
1607         /*
1608          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1609          */
1610         dsi_enable_scp_clk(dsidev);
1611
1612         if (!dsi->vdds_dsi_enabled) {
1613                 r = regulator_enable(dsi->vdds_dsi_reg);
1614                 if (r)
1615                         goto err0;
1616                 dsi->vdds_dsi_enabled = true;
1617         }
1618
1619         /* XXX PLL does not come out of reset without this... */
1620         dispc_pck_free_enable(1);
1621
1622         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1623                 DSSERR("PLL not coming out of reset.\n");
1624                 r = -ENODEV;
1625                 dispc_pck_free_enable(0);
1626                 goto err1;
1627         }
1628
1629         /* XXX ... but if left on, we get problems when planes do not
1630          * fill the whole display. No idea about this */
1631         dispc_pck_free_enable(0);
1632
1633         if (enable_hsclk && enable_hsdiv)
1634                 pwstate = DSI_PLL_POWER_ON_ALL;
1635         else if (enable_hsclk)
1636                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1637         else if (enable_hsdiv)
1638                 pwstate = DSI_PLL_POWER_ON_DIV;
1639         else
1640                 pwstate = DSI_PLL_POWER_OFF;
1641
1642         r = dsi_pll_power(dsidev, pwstate);
1643
1644         if (r)
1645                 goto err1;
1646
1647         DSSDBG("PLL init done\n");
1648
1649         return 0;
1650 err1:
1651         if (dsi->vdds_dsi_enabled) {
1652                 regulator_disable(dsi->vdds_dsi_reg);
1653                 dsi->vdds_dsi_enabled = false;
1654         }
1655 err0:
1656         dsi_disable_scp_clk(dsidev);
1657         dsi_enable_pll_clock(dsidev, 0);
1658         return r;
1659 }
1660
1661 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1662 {
1663         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1664
1665         dsi->pll_locked = 0;
1666         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1667         if (disconnect_lanes) {
1668                 WARN_ON(!dsi->vdds_dsi_enabled);
1669                 regulator_disable(dsi->vdds_dsi_reg);
1670                 dsi->vdds_dsi_enabled = false;
1671         }
1672
1673         dsi_disable_scp_clk(dsidev);
1674         dsi_enable_pll_clock(dsidev, 0);
1675
1676         DSSDBG("PLL uninit done\n");
1677 }
1678
1679 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1680                 struct seq_file *s)
1681 {
1682         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1683         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1684         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1685         int dsi_module = dsi->module_id;
1686
1687         dispc_clk_src = dss_get_dispc_clk_source();
1688         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1689
1690         if (dsi_runtime_get(dsidev))
1691                 return;
1692
1693         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1694
1695         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1696
1697         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1698
1699         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1700                         cinfo->clkin4ddr, cinfo->regm);
1701
1702         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1703                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1704                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1705                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1706                         cinfo->dsi_pll_hsdiv_dispc_clk,
1707                         cinfo->regm_dispc,
1708                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1709                         "off" : "on");
1710
1711         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1712                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1713                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1714                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1715                         cinfo->dsi_pll_hsdiv_dsi_clk,
1716                         cinfo->regm_dsi,
1717                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1718                         "off" : "on");
1719
1720         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1721
1722         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1723                         dss_get_generic_clk_source_name(dsi_clk_src),
1724                         dss_feat_get_clk_source_name(dsi_clk_src));
1725
1726         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1727
1728         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1729                         cinfo->clkin4ddr / 4);
1730
1731         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1732
1733         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1734
1735         dsi_runtime_put(dsidev);
1736 }
1737
1738 void dsi_dump_clocks(struct seq_file *s)
1739 {
1740         struct platform_device *dsidev;
1741         int i;
1742
1743         for  (i = 0; i < MAX_NUM_DSI; i++) {
1744                 dsidev = dsi_get_dsidev_from_id(i);
1745                 if (dsidev)
1746                         dsi_dump_dsidev_clocks(dsidev, s);
1747         }
1748 }
1749
1750 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1751 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1752                 struct seq_file *s)
1753 {
1754         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1755         unsigned long flags;
1756         struct dsi_irq_stats stats;
1757
1758         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1759
1760         stats = dsi->irq_stats;
1761         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1762         dsi->irq_stats.last_reset = jiffies;
1763
1764         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1765
1766         seq_printf(s, "period %u ms\n",
1767                         jiffies_to_msecs(jiffies - stats.last_reset));
1768
1769         seq_printf(s, "irqs %d\n", stats.irq_count);
1770 #define PIS(x) \
1771         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1772
1773         seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1774         PIS(VC0);
1775         PIS(VC1);
1776         PIS(VC2);
1777         PIS(VC3);
1778         PIS(WAKEUP);
1779         PIS(RESYNC);
1780         PIS(PLL_LOCK);
1781         PIS(PLL_UNLOCK);
1782         PIS(PLL_RECALL);
1783         PIS(COMPLEXIO_ERR);
1784         PIS(HS_TX_TIMEOUT);
1785         PIS(LP_RX_TIMEOUT);
1786         PIS(TE_TRIGGER);
1787         PIS(ACK_TRIGGER);
1788         PIS(SYNC_LOST);
1789         PIS(LDO_POWER_GOOD);
1790         PIS(TA_TIMEOUT);
1791 #undef PIS
1792
1793 #define PIS(x) \
1794         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1795                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1796                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1797                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1798                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1799
1800         seq_printf(s, "-- VC interrupts --\n");
1801         PIS(CS);
1802         PIS(ECC_CORR);
1803         PIS(PACKET_SENT);
1804         PIS(FIFO_TX_OVF);
1805         PIS(FIFO_RX_OVF);
1806         PIS(BTA);
1807         PIS(ECC_NO_CORR);
1808         PIS(FIFO_TX_UDF);
1809         PIS(PP_BUSY_CHANGE);
1810 #undef PIS
1811
1812 #define PIS(x) \
1813         seq_printf(s, "%-20s %10d\n", #x, \
1814                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1815
1816         seq_printf(s, "-- CIO interrupts --\n");
1817         PIS(ERRSYNCESC1);
1818         PIS(ERRSYNCESC2);
1819         PIS(ERRSYNCESC3);
1820         PIS(ERRESC1);
1821         PIS(ERRESC2);
1822         PIS(ERRESC3);
1823         PIS(ERRCONTROL1);
1824         PIS(ERRCONTROL2);
1825         PIS(ERRCONTROL3);
1826         PIS(STATEULPS1);
1827         PIS(STATEULPS2);
1828         PIS(STATEULPS3);
1829         PIS(ERRCONTENTIONLP0_1);
1830         PIS(ERRCONTENTIONLP1_1);
1831         PIS(ERRCONTENTIONLP0_2);
1832         PIS(ERRCONTENTIONLP1_2);
1833         PIS(ERRCONTENTIONLP0_3);
1834         PIS(ERRCONTENTIONLP1_3);
1835         PIS(ULPSACTIVENOT_ALL0);
1836         PIS(ULPSACTIVENOT_ALL1);
1837 #undef PIS
1838 }
1839
1840 static void dsi1_dump_irqs(struct seq_file *s)
1841 {
1842         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1843
1844         dsi_dump_dsidev_irqs(dsidev, s);
1845 }
1846
1847 static void dsi2_dump_irqs(struct seq_file *s)
1848 {
1849         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1850
1851         dsi_dump_dsidev_irqs(dsidev, s);
1852 }
1853 #endif
1854
1855 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1856                 struct seq_file *s)
1857 {
1858 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1859
1860         if (dsi_runtime_get(dsidev))
1861                 return;
1862         dsi_enable_scp_clk(dsidev);
1863
1864         DUMPREG(DSI_REVISION);
1865         DUMPREG(DSI_SYSCONFIG);
1866         DUMPREG(DSI_SYSSTATUS);
1867         DUMPREG(DSI_IRQSTATUS);
1868         DUMPREG(DSI_IRQENABLE);
1869         DUMPREG(DSI_CTRL);
1870         DUMPREG(DSI_COMPLEXIO_CFG1);
1871         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1872         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1873         DUMPREG(DSI_CLK_CTRL);
1874         DUMPREG(DSI_TIMING1);
1875         DUMPREG(DSI_TIMING2);
1876         DUMPREG(DSI_VM_TIMING1);
1877         DUMPREG(DSI_VM_TIMING2);
1878         DUMPREG(DSI_VM_TIMING3);
1879         DUMPREG(DSI_CLK_TIMING);
1880         DUMPREG(DSI_TX_FIFO_VC_SIZE);
1881         DUMPREG(DSI_RX_FIFO_VC_SIZE);
1882         DUMPREG(DSI_COMPLEXIO_CFG2);
1883         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1884         DUMPREG(DSI_VM_TIMING4);
1885         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1886         DUMPREG(DSI_VM_TIMING5);
1887         DUMPREG(DSI_VM_TIMING6);
1888         DUMPREG(DSI_VM_TIMING7);
1889         DUMPREG(DSI_STOPCLK_TIMING);
1890
1891         DUMPREG(DSI_VC_CTRL(0));
1892         DUMPREG(DSI_VC_TE(0));
1893         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1894         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1895         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1896         DUMPREG(DSI_VC_IRQSTATUS(0));
1897         DUMPREG(DSI_VC_IRQENABLE(0));
1898
1899         DUMPREG(DSI_VC_CTRL(1));
1900         DUMPREG(DSI_VC_TE(1));
1901         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1902         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1903         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1904         DUMPREG(DSI_VC_IRQSTATUS(1));
1905         DUMPREG(DSI_VC_IRQENABLE(1));
1906
1907         DUMPREG(DSI_VC_CTRL(2));
1908         DUMPREG(DSI_VC_TE(2));
1909         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1910         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1911         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1912         DUMPREG(DSI_VC_IRQSTATUS(2));
1913         DUMPREG(DSI_VC_IRQENABLE(2));
1914
1915         DUMPREG(DSI_VC_CTRL(3));
1916         DUMPREG(DSI_VC_TE(3));
1917         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1918         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1919         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1920         DUMPREG(DSI_VC_IRQSTATUS(3));
1921         DUMPREG(DSI_VC_IRQENABLE(3));
1922
1923         DUMPREG(DSI_DSIPHY_CFG0);
1924         DUMPREG(DSI_DSIPHY_CFG1);
1925         DUMPREG(DSI_DSIPHY_CFG2);
1926         DUMPREG(DSI_DSIPHY_CFG5);
1927
1928         DUMPREG(DSI_PLL_CONTROL);
1929         DUMPREG(DSI_PLL_STATUS);
1930         DUMPREG(DSI_PLL_GO);
1931         DUMPREG(DSI_PLL_CONFIGURATION1);
1932         DUMPREG(DSI_PLL_CONFIGURATION2);
1933
1934         dsi_disable_scp_clk(dsidev);
1935         dsi_runtime_put(dsidev);
1936 #undef DUMPREG
1937 }
1938
1939 static void dsi1_dump_regs(struct seq_file *s)
1940 {
1941         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1942
1943         dsi_dump_dsidev_regs(dsidev, s);
1944 }
1945
1946 static void dsi2_dump_regs(struct seq_file *s)
1947 {
1948         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1949
1950         dsi_dump_dsidev_regs(dsidev, s);
1951 }
1952
1953 enum dsi_cio_power_state {
1954         DSI_COMPLEXIO_POWER_OFF         = 0x0,
1955         DSI_COMPLEXIO_POWER_ON          = 0x1,
1956         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
1957 };
1958
1959 static int dsi_cio_power(struct platform_device *dsidev,
1960                 enum dsi_cio_power_state state)
1961 {
1962         int t = 0;
1963
1964         /* PWR_CMD */
1965         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1966
1967         /* PWR_STATUS */
1968         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1969                         26, 25) != state) {
1970                 if (++t > 1000) {
1971                         DSSERR("failed to set complexio power state to "
1972                                         "%d\n", state);
1973                         return -ENODEV;
1974                 }
1975                 udelay(1);
1976         }
1977
1978         return 0;
1979 }
1980
1981 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1982 {
1983         int val;
1984
1985         /* line buffer on OMAP3 is 1024 x 24bits */
1986         /* XXX: for some reason using full buffer size causes
1987          * considerable TX slowdown with update sizes that fill the
1988          * whole buffer */
1989         if (!dss_has_feature(FEAT_DSI_GNQ))
1990                 return 1023 * 3;
1991
1992         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1993
1994         switch (val) {
1995         case 1:
1996                 return 512 * 3;         /* 512x24 bits */
1997         case 2:
1998                 return 682 * 3;         /* 682x24 bits */
1999         case 3:
2000                 return 853 * 3;         /* 853x24 bits */
2001         case 4:
2002                 return 1024 * 3;        /* 1024x24 bits */
2003         case 5:
2004                 return 1194 * 3;        /* 1194x24 bits */
2005         case 6:
2006                 return 1365 * 3;        /* 1365x24 bits */
2007         default:
2008                 BUG();
2009                 return 0;
2010         }
2011 }
2012
2013 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2014 {
2015         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2016         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2017         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2018         static const enum dsi_lane_function functions[] = {
2019                 DSI_LANE_CLK,
2020                 DSI_LANE_DATA1,
2021                 DSI_LANE_DATA2,
2022                 DSI_LANE_DATA3,
2023                 DSI_LANE_DATA4,
2024         };
2025         u32 r;
2026         int i;
2027
2028         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2029
2030         for (i = 0; i < dsi->num_lanes_used; ++i) {
2031                 unsigned offset = offsets[i];
2032                 unsigned polarity, lane_number;
2033                 unsigned t;
2034
2035                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2036                         if (dsi->lanes[t].function == functions[i])
2037                                 break;
2038
2039                 if (t == dsi->num_lanes_supported)
2040                         return -EINVAL;
2041
2042                 lane_number = t;
2043                 polarity = dsi->lanes[t].polarity;
2044
2045                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2046                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2047         }
2048
2049         /* clear the unused lanes */
2050         for (; i < dsi->num_lanes_supported; ++i) {
2051                 unsigned offset = offsets[i];
2052
2053                 r = FLD_MOD(r, 0, offset + 2, offset);
2054                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2055         }
2056
2057         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2058
2059         return 0;
2060 }
2061
2062 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2063 {
2064         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2065
2066         /* convert time in ns to ddr ticks, rounding up */
2067         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2068         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2069 }
2070
2071 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2072 {
2073         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2074
2075         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2076         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2077 }
2078
2079 static void dsi_cio_timings(struct platform_device *dsidev)
2080 {
2081         u32 r;
2082         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2083         u32 tlpx_half, tclk_trail, tclk_zero;
2084         u32 tclk_prepare;
2085
2086         /* calculate timings */
2087
2088         /* 1 * DDR_CLK = 2 * UI */
2089
2090         /* min 40ns + 4*UI      max 85ns + 6*UI */
2091         ths_prepare = ns2ddr(dsidev, 70) + 2;
2092
2093         /* min 145ns + 10*UI */
2094         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2095
2096         /* min max(8*UI, 60ns+4*UI) */
2097         ths_trail = ns2ddr(dsidev, 60) + 5;
2098
2099         /* min 100ns */
2100         ths_exit = ns2ddr(dsidev, 145);
2101
2102         /* tlpx min 50n */
2103         tlpx_half = ns2ddr(dsidev, 25);
2104
2105         /* min 60ns */
2106         tclk_trail = ns2ddr(dsidev, 60) + 2;
2107
2108         /* min 38ns, max 95ns */
2109         tclk_prepare = ns2ddr(dsidev, 65);
2110
2111         /* min tclk-prepare + tclk-zero = 300ns */
2112         tclk_zero = ns2ddr(dsidev, 260);
2113
2114         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2115                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2116                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2117         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2118                         ths_trail, ddr2ns(dsidev, ths_trail),
2119                         ths_exit, ddr2ns(dsidev, ths_exit));
2120
2121         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2122                         "tclk_zero %u (%uns)\n",
2123                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2124                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2125                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2126         DSSDBG("tclk_prepare %u (%uns)\n",
2127                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2128
2129         /* program timings */
2130
2131         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2132         r = FLD_MOD(r, ths_prepare, 31, 24);
2133         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2134         r = FLD_MOD(r, ths_trail, 15, 8);
2135         r = FLD_MOD(r, ths_exit, 7, 0);
2136         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2137
2138         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2139         r = FLD_MOD(r, tlpx_half, 22, 16);
2140         r = FLD_MOD(r, tclk_trail, 15, 8);
2141         r = FLD_MOD(r, tclk_zero, 7, 0);
2142         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2143
2144         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2145         r = FLD_MOD(r, tclk_prepare, 7, 0);
2146         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2147 }
2148
2149 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2150 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2151                 unsigned mask_p, unsigned mask_n)
2152 {
2153         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2154         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2155         int i;
2156         u32 l;
2157         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2158
2159         l = 0;
2160
2161         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2162                 unsigned p = dsi->lanes[i].polarity;
2163
2164                 if (mask_p & (1 << i))
2165                         l |= 1 << (i * 2 + (p ? 0 : 1));
2166
2167                 if (mask_n & (1 << i))
2168                         l |= 1 << (i * 2 + (p ? 1 : 0));
2169         }
2170
2171         /*
2172          * Bits in REGLPTXSCPDAT4TO0DXDY:
2173          * 17: DY0 18: DX0
2174          * 19: DY1 20: DX1
2175          * 21: DY2 22: DX2
2176          * 23: DY3 24: DX3
2177          * 25: DY4 26: DX4
2178          */
2179
2180         /* Set the lane override configuration */
2181
2182         /* REGLPTXSCPDAT4TO0DXDY */
2183         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2184
2185         /* Enable lane override */
2186
2187         /* ENLPTXSCPDAT */
2188         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2189 }
2190
2191 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2192 {
2193         /* Disable lane override */
2194         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2195         /* Reset the lane override configuration */
2196         /* REGLPTXSCPDAT4TO0DXDY */
2197         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2198 }
2199
2200 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2201 {
2202         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2203         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2204         int t, i;
2205         bool in_use[DSI_MAX_NR_LANES];
2206         static const u8 offsets_old[] = { 28, 27, 26 };
2207         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2208         const u8 *offsets;
2209
2210         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2211                 offsets = offsets_old;
2212         else
2213                 offsets = offsets_new;
2214
2215         for (i = 0; i < dsi->num_lanes_supported; ++i)
2216                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2217
2218         t = 100000;
2219         while (true) {
2220                 u32 l;
2221                 int ok;
2222
2223                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2224
2225                 ok = 0;
2226                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2227                         if (!in_use[i] || (l & (1 << offsets[i])))
2228                                 ok++;
2229                 }
2230
2231                 if (ok == dsi->num_lanes_supported)
2232                         break;
2233
2234                 if (--t == 0) {
2235                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2236                                 if (!in_use[i] || (l & (1 << offsets[i])))
2237                                         continue;
2238
2239                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2240                                                 "out of reset\n", i);
2241                         }
2242                         return -EIO;
2243                 }
2244         }
2245
2246         return 0;
2247 }
2248
2249 /* return bitmask of enabled lanes, lane0 being the lsb */
2250 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2251 {
2252         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2253         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2254         unsigned mask = 0;
2255         int i;
2256
2257         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2258                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2259                         mask |= 1 << i;
2260         }
2261
2262         return mask;
2263 }
2264
2265 static int dsi_cio_init(struct omap_dss_device *dssdev)
2266 {
2267         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2268         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2269         int r;
2270         u32 l;
2271
2272         DSSDBGF();
2273
2274         r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dssdev));
2275         if (r)
2276                 return r;
2277
2278         dsi_enable_scp_clk(dsidev);
2279
2280         /* A dummy read using the SCP interface to any DSIPHY register is
2281          * required after DSIPHY reset to complete the reset of the DSI complex
2282          * I/O. */
2283         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2284
2285         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2286                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2287                 r = -EIO;
2288                 goto err_scp_clk_dom;
2289         }
2290
2291         r = dsi_set_lane_config(dssdev);
2292         if (r)
2293                 goto err_scp_clk_dom;
2294
2295         /* set TX STOP MODE timer to maximum for this operation */
2296         l = dsi_read_reg(dsidev, DSI_TIMING1);
2297         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2298         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2299         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2300         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2301         dsi_write_reg(dsidev, DSI_TIMING1, l);
2302
2303         if (dsi->ulps_enabled) {
2304                 unsigned mask_p;
2305                 int i;
2306
2307                 DSSDBG("manual ulps exit\n");
2308
2309                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2310                  * stop state. DSS HW cannot do this via the normal
2311                  * ULPS exit sequence, as after reset the DSS HW thinks
2312                  * that we are not in ULPS mode, and refuses to send the
2313                  * sequence. So we need to send the ULPS exit sequence
2314                  * manually by setting positive lines high and negative lines
2315                  * low for 1ms.
2316                  */
2317
2318                 mask_p = 0;
2319
2320                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2321                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2322                                 continue;
2323                         mask_p |= 1 << i;
2324                 }
2325
2326                 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2327         }
2328
2329         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2330         if (r)
2331                 goto err_cio_pwr;
2332
2333         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2334                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2335                 r = -ENODEV;
2336                 goto err_cio_pwr_dom;
2337         }
2338
2339         dsi_if_enable(dsidev, true);
2340         dsi_if_enable(dsidev, false);
2341         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2342
2343         r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2344         if (r)
2345                 goto err_tx_clk_esc_rst;
2346
2347         if (dsi->ulps_enabled) {
2348                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2349                 ktime_t wait = ns_to_ktime(1000 * 1000);
2350                 set_current_state(TASK_UNINTERRUPTIBLE);
2351                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2352
2353                 /* Disable the override. The lanes should be set to Mark-11
2354                  * state by the HW */
2355                 dsi_cio_disable_lane_override(dsidev);
2356         }
2357
2358         /* FORCE_TX_STOP_MODE_IO */
2359         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2360
2361         dsi_cio_timings(dsidev);
2362
2363         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2364                 /* DDR_CLK_ALWAYS_ON */
2365                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2366                         dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2367         }
2368
2369         dsi->ulps_enabled = false;
2370
2371         DSSDBG("CIO init done\n");
2372
2373         return 0;
2374
2375 err_tx_clk_esc_rst:
2376         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2377 err_cio_pwr_dom:
2378         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2379 err_cio_pwr:
2380         if (dsi->ulps_enabled)
2381                 dsi_cio_disable_lane_override(dsidev);
2382 err_scp_clk_dom:
2383         dsi_disable_scp_clk(dsidev);
2384         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dssdev));
2385         return r;
2386 }
2387
2388 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2389 {
2390         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2391         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2392
2393         /* DDR_CLK_ALWAYS_ON */
2394         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2395
2396         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2397         dsi_disable_scp_clk(dsidev);
2398         dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dssdev));
2399 }
2400
2401 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2402                 enum fifo_size size1, enum fifo_size size2,
2403                 enum fifo_size size3, enum fifo_size size4)
2404 {
2405         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2406         u32 r = 0;
2407         int add = 0;
2408         int i;
2409
2410         dsi->vc[0].fifo_size = size1;
2411         dsi->vc[1].fifo_size = size2;
2412         dsi->vc[2].fifo_size = size3;
2413         dsi->vc[3].fifo_size = size4;
2414
2415         for (i = 0; i < 4; i++) {
2416                 u8 v;
2417                 int size = dsi->vc[i].fifo_size;
2418
2419                 if (add + size > 4) {
2420                         DSSERR("Illegal FIFO configuration\n");
2421                         BUG();
2422                         return;
2423                 }
2424
2425                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2426                 r |= v << (8 * i);
2427                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2428                 add += size;
2429         }
2430
2431         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2432 }
2433
2434 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2435                 enum fifo_size size1, enum fifo_size size2,
2436                 enum fifo_size size3, enum fifo_size size4)
2437 {
2438         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2439         u32 r = 0;
2440         int add = 0;
2441         int i;
2442
2443         dsi->vc[0].fifo_size = size1;
2444         dsi->vc[1].fifo_size = size2;
2445         dsi->vc[2].fifo_size = size3;
2446         dsi->vc[3].fifo_size = size4;
2447
2448         for (i = 0; i < 4; i++) {
2449                 u8 v;
2450                 int size = dsi->vc[i].fifo_size;
2451
2452                 if (add + size > 4) {
2453                         DSSERR("Illegal FIFO configuration\n");
2454                         BUG();
2455                         return;
2456                 }
2457
2458                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2459                 r |= v << (8 * i);
2460                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2461                 add += size;
2462         }
2463
2464         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2465 }
2466
2467 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2468 {
2469         u32 r;
2470
2471         r = dsi_read_reg(dsidev, DSI_TIMING1);
2472         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2473         dsi_write_reg(dsidev, DSI_TIMING1, r);
2474
2475         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2476                 DSSERR("TX_STOP bit not going down\n");
2477                 return -EIO;
2478         }
2479
2480         return 0;
2481 }
2482
2483 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2484 {
2485         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2486 }
2487
2488 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2489 {
2490         struct dsi_packet_sent_handler_data *vp_data =
2491                 (struct dsi_packet_sent_handler_data *) data;
2492         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2493         const int channel = dsi->update_channel;
2494         u8 bit = dsi->te_enabled ? 30 : 31;
2495
2496         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2497                 complete(vp_data->completion);
2498 }
2499
2500 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2501 {
2502         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2503         DECLARE_COMPLETION_ONSTACK(completion);
2504         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2505         int r = 0;
2506         u8 bit;
2507
2508         bit = dsi->te_enabled ? 30 : 31;
2509
2510         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2511                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2512         if (r)
2513                 goto err0;
2514
2515         /* Wait for completion only if TE_EN/TE_START is still set */
2516         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2517                 if (wait_for_completion_timeout(&completion,
2518                                 msecs_to_jiffies(10)) == 0) {
2519                         DSSERR("Failed to complete previous frame transfer\n");
2520                         r = -EIO;
2521                         goto err1;
2522                 }
2523         }
2524
2525         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2526                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2527
2528         return 0;
2529 err1:
2530         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2531                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2532 err0:
2533         return r;
2534 }
2535
2536 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2537 {
2538         struct dsi_packet_sent_handler_data *l4_data =
2539                 (struct dsi_packet_sent_handler_data *) data;
2540         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2541         const int channel = dsi->update_channel;
2542
2543         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2544                 complete(l4_data->completion);
2545 }
2546
2547 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2548 {
2549         DECLARE_COMPLETION_ONSTACK(completion);
2550         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2551         int r = 0;
2552
2553         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2554                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2555         if (r)
2556                 goto err0;
2557
2558         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2559         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2560                 if (wait_for_completion_timeout(&completion,
2561                                 msecs_to_jiffies(10)) == 0) {
2562                         DSSERR("Failed to complete previous l4 transfer\n");
2563                         r = -EIO;
2564                         goto err1;
2565                 }
2566         }
2567
2568         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2569                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2570
2571         return 0;
2572 err1:
2573         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2574                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2575 err0:
2576         return r;
2577 }
2578
2579 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2580 {
2581         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2582
2583         WARN_ON(!dsi_bus_is_locked(dsidev));
2584
2585         WARN_ON(in_interrupt());
2586
2587         if (!dsi_vc_is_enabled(dsidev, channel))
2588                 return 0;
2589
2590         switch (dsi->vc[channel].source) {
2591         case DSI_VC_SOURCE_VP:
2592                 return dsi_sync_vc_vp(dsidev, channel);
2593         case DSI_VC_SOURCE_L4:
2594                 return dsi_sync_vc_l4(dsidev, channel);
2595         default:
2596                 BUG();
2597                 return -EINVAL;
2598         }
2599 }
2600
2601 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2602                 bool enable)
2603 {
2604         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2605                         channel, enable);
2606
2607         enable = enable ? 1 : 0;
2608
2609         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2610
2611         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2612                 0, enable) != enable) {
2613                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2614                         return -EIO;
2615         }
2616
2617         return 0;
2618 }
2619
2620 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2621 {
2622         u32 r;
2623
2624         DSSDBGF("%d", channel);
2625
2626         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2627
2628         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2629                 DSSERR("VC(%d) busy when trying to configure it!\n",
2630                                 channel);
2631
2632         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2633         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2634         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2635         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2636         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2637         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2638         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2639         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2640                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2641
2642         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2643         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2644
2645         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2646 }
2647
2648 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2649                 enum dsi_vc_source source)
2650 {
2651         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2652
2653         if (dsi->vc[channel].source == source)
2654                 return 0;
2655
2656         DSSDBGF("%d", channel);
2657
2658         dsi_sync_vc(dsidev, channel);
2659
2660         dsi_vc_enable(dsidev, channel, 0);
2661
2662         /* VC_BUSY */
2663         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2664                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2665                 return -EIO;
2666         }
2667
2668         /* SOURCE, 0 = L4, 1 = video port */
2669         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2670
2671         /* DCS_CMD_ENABLE */
2672         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2673                 bool enable = source == DSI_VC_SOURCE_VP;
2674                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2675         }
2676
2677         dsi_vc_enable(dsidev, channel, 1);
2678
2679         dsi->vc[channel].source = source;
2680
2681         return 0;
2682 }
2683
2684 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2685                 bool enable)
2686 {
2687         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2688
2689         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2690
2691         WARN_ON(!dsi_bus_is_locked(dsidev));
2692
2693         dsi_vc_enable(dsidev, channel, 0);
2694         dsi_if_enable(dsidev, 0);
2695
2696         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2697
2698         dsi_vc_enable(dsidev, channel, 1);
2699         dsi_if_enable(dsidev, 1);
2700
2701         dsi_force_tx_stop_mode_io(dsidev);
2702
2703         /* start the DDR clock by sending a NULL packet */
2704         if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2705                 dsi_vc_send_null(dssdev, channel);
2706 }
2707 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2708
2709 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2710 {
2711         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2712                 u32 val;
2713                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2714                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2715                                 (val >> 0) & 0xff,
2716                                 (val >> 8) & 0xff,
2717                                 (val >> 16) & 0xff,
2718                                 (val >> 24) & 0xff);
2719         }
2720 }
2721
2722 static void dsi_show_rx_ack_with_err(u16 err)
2723 {
2724         DSSERR("\tACK with ERROR (%#x):\n", err);
2725         if (err & (1 << 0))
2726                 DSSERR("\t\tSoT Error\n");
2727         if (err & (1 << 1))
2728                 DSSERR("\t\tSoT Sync Error\n");
2729         if (err & (1 << 2))
2730                 DSSERR("\t\tEoT Sync Error\n");
2731         if (err & (1 << 3))
2732                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2733         if (err & (1 << 4))
2734                 DSSERR("\t\tLP Transmit Sync Error\n");
2735         if (err & (1 << 5))
2736                 DSSERR("\t\tHS Receive Timeout Error\n");
2737         if (err & (1 << 6))
2738                 DSSERR("\t\tFalse Control Error\n");
2739         if (err & (1 << 7))
2740                 DSSERR("\t\t(reserved7)\n");
2741         if (err & (1 << 8))
2742                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2743         if (err & (1 << 9))
2744                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2745         if (err & (1 << 10))
2746                 DSSERR("\t\tChecksum Error\n");
2747         if (err & (1 << 11))
2748                 DSSERR("\t\tData type not recognized\n");
2749         if (err & (1 << 12))
2750                 DSSERR("\t\tInvalid VC ID\n");
2751         if (err & (1 << 13))
2752                 DSSERR("\t\tInvalid Transmission Length\n");
2753         if (err & (1 << 14))
2754                 DSSERR("\t\t(reserved14)\n");
2755         if (err & (1 << 15))
2756                 DSSERR("\t\tDSI Protocol Violation\n");
2757 }
2758
2759 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2760                 int channel)
2761 {
2762         /* RX_FIFO_NOT_EMPTY */
2763         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2764                 u32 val;
2765                 u8 dt;
2766                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2767                 DSSERR("\trawval %#08x\n", val);
2768                 dt = FLD_GET(val, 5, 0);
2769                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2770                         u16 err = FLD_GET(val, 23, 8);
2771                         dsi_show_rx_ack_with_err(err);
2772                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2773                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2774                                         FLD_GET(val, 23, 8));
2775                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2776                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2777                                         FLD_GET(val, 23, 8));
2778                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2779                         DSSERR("\tDCS long response, len %d\n",
2780                                         FLD_GET(val, 23, 8));
2781                         dsi_vc_flush_long_data(dsidev, channel);
2782                 } else {
2783                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2784                 }
2785         }
2786         return 0;
2787 }
2788
2789 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2790 {
2791         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2792
2793         if (dsi->debug_write || dsi->debug_read)
2794                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2795
2796         WARN_ON(!dsi_bus_is_locked(dsidev));
2797
2798         /* RX_FIFO_NOT_EMPTY */
2799         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2800                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2801                 dsi_vc_flush_receive_data(dsidev, channel);
2802         }
2803
2804         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2805
2806         /* flush posted write */
2807         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2808
2809         return 0;
2810 }
2811
2812 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2813 {
2814         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2815         DECLARE_COMPLETION_ONSTACK(completion);
2816         int r = 0;
2817         u32 err;
2818
2819         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2820                         &completion, DSI_VC_IRQ_BTA);
2821         if (r)
2822                 goto err0;
2823
2824         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2825                         DSI_IRQ_ERROR_MASK);
2826         if (r)
2827                 goto err1;
2828
2829         r = dsi_vc_send_bta(dsidev, channel);
2830         if (r)
2831                 goto err2;
2832
2833         if (wait_for_completion_timeout(&completion,
2834                                 msecs_to_jiffies(500)) == 0) {
2835                 DSSERR("Failed to receive BTA\n");
2836                 r = -EIO;
2837                 goto err2;
2838         }
2839
2840         err = dsi_get_errors(dsidev);
2841         if (err) {
2842                 DSSERR("Error while sending BTA: %x\n", err);
2843                 r = -EIO;
2844                 goto err2;
2845         }
2846 err2:
2847         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2848                         DSI_IRQ_ERROR_MASK);
2849 err1:
2850         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2851                         &completion, DSI_VC_IRQ_BTA);
2852 err0:
2853         return r;
2854 }
2855 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2856
2857 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2858                 int channel, u8 data_type, u16 len, u8 ecc)
2859 {
2860         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2861         u32 val;
2862         u8 data_id;
2863
2864         WARN_ON(!dsi_bus_is_locked(dsidev));
2865
2866         data_id = data_type | dsi->vc[channel].vc_id << 6;
2867
2868         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2869                 FLD_VAL(ecc, 31, 24);
2870
2871         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2872 }
2873
2874 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2875                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2876 {
2877         u32 val;
2878
2879         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2880
2881 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2882                         b1, b2, b3, b4, val); */
2883
2884         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2885 }
2886
2887 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2888                 u8 data_type, u8 *data, u16 len, u8 ecc)
2889 {
2890         /*u32 val; */
2891         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2892         int i;
2893         u8 *p;
2894         int r = 0;
2895         u8 b1, b2, b3, b4;
2896
2897         if (dsi->debug_write)
2898                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2899
2900         /* len + header */
2901         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2902                 DSSERR("unable to send long packet: packet too long.\n");
2903                 return -EINVAL;
2904         }
2905
2906         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2907
2908         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2909
2910         p = data;
2911         for (i = 0; i < len >> 2; i++) {
2912                 if (dsi->debug_write)
2913                         DSSDBG("\tsending full packet %d\n", i);
2914
2915                 b1 = *p++;
2916                 b2 = *p++;
2917                 b3 = *p++;
2918                 b4 = *p++;
2919
2920                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2921         }
2922
2923         i = len % 4;
2924         if (i) {
2925                 b1 = 0; b2 = 0; b3 = 0;
2926
2927                 if (dsi->debug_write)
2928                         DSSDBG("\tsending remainder bytes %d\n", i);
2929
2930                 switch (i) {
2931                 case 3:
2932                         b1 = *p++;
2933                         b2 = *p++;
2934                         b3 = *p++;
2935                         break;
2936                 case 2:
2937                         b1 = *p++;
2938                         b2 = *p++;
2939                         break;
2940                 case 1:
2941                         b1 = *p++;
2942                         break;
2943                 }
2944
2945                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2946         }
2947
2948         return r;
2949 }
2950
2951 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2952                 u8 data_type, u16 data, u8 ecc)
2953 {
2954         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2955         u32 r;
2956         u8 data_id;
2957
2958         WARN_ON(!dsi_bus_is_locked(dsidev));
2959
2960         if (dsi->debug_write)
2961                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2962                                 channel,
2963                                 data_type, data & 0xff, (data >> 8) & 0xff);
2964
2965         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2966
2967         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2968                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2969                 return -EINVAL;
2970         }
2971
2972         data_id = data_type | dsi->vc[channel].vc_id << 6;
2973
2974         r = (data_id << 0) | (data << 8) | (ecc << 24);
2975
2976         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2977
2978         return 0;
2979 }
2980
2981 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2982 {
2983         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2984
2985         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2986                 0, 0);
2987 }
2988 EXPORT_SYMBOL(dsi_vc_send_null);
2989
2990 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
2991                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
2992 {
2993         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2994         int r;
2995
2996         if (len == 0) {
2997                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2998                 r = dsi_vc_send_short(dsidev, channel,
2999                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3000         } else if (len == 1) {
3001                 r = dsi_vc_send_short(dsidev, channel,
3002                                 type == DSS_DSI_CONTENT_GENERIC ?
3003                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3004                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3005         } else if (len == 2) {
3006                 r = dsi_vc_send_short(dsidev, channel,
3007                                 type == DSS_DSI_CONTENT_GENERIC ?
3008                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3009                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3010                                 data[0] | (data[1] << 8), 0);
3011         } else {
3012                 r = dsi_vc_send_long(dsidev, channel,
3013                                 type == DSS_DSI_CONTENT_GENERIC ?
3014                                 MIPI_DSI_GENERIC_LONG_WRITE :
3015                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3016         }
3017
3018         return r;
3019 }
3020
3021 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3022                 u8 *data, int len)
3023 {
3024         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3025                         DSS_DSI_CONTENT_DCS);
3026 }
3027 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3028
3029 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3030                 u8 *data, int len)
3031 {
3032         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3033                         DSS_DSI_CONTENT_GENERIC);
3034 }
3035 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3036
3037 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3038                 u8 *data, int len, enum dss_dsi_content_type type)
3039 {
3040         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3041         int r;
3042
3043         r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3044         if (r)
3045                 goto err;
3046
3047         r = dsi_vc_send_bta_sync(dssdev, channel);
3048         if (r)
3049                 goto err;
3050
3051         /* RX_FIFO_NOT_EMPTY */
3052         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3053                 DSSERR("rx fifo not empty after write, dumping data:\n");
3054                 dsi_vc_flush_receive_data(dsidev, channel);
3055                 r = -EIO;
3056                 goto err;
3057         }
3058
3059         return 0;
3060 err:
3061         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3062                         channel, data[0], len);
3063         return r;
3064 }
3065
3066 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3067                 int len)
3068 {
3069         return dsi_vc_write_common(dssdev, channel, data, len,
3070                         DSS_DSI_CONTENT_DCS);
3071 }
3072 EXPORT_SYMBOL(dsi_vc_dcs_write);
3073
3074 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3075                 int len)
3076 {
3077         return dsi_vc_write_common(dssdev, channel, data, len,
3078                         DSS_DSI_CONTENT_GENERIC);
3079 }
3080 EXPORT_SYMBOL(dsi_vc_generic_write);
3081
3082 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3083 {
3084         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3085 }
3086 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3087
3088 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3089 {
3090         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3091 }
3092 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3093
3094 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3095                 u8 param)
3096 {
3097         u8 buf[2];
3098         buf[0] = dcs_cmd;
3099         buf[1] = param;
3100         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3101 }
3102 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3103
3104 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3105                 u8 param)
3106 {
3107         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3108 }
3109 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3110
3111 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3112                 u8 param1, u8 param2)
3113 {
3114         u8 buf[2];
3115         buf[0] = param1;
3116         buf[1] = param2;
3117         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3118 }
3119 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3120
3121 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3122                 int channel, u8 dcs_cmd)
3123 {
3124         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3125         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3126         int r;
3127
3128         if (dsi->debug_read)
3129                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3130                         channel, dcs_cmd);
3131
3132         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3133         if (r) {
3134                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3135                         " failed\n", channel, dcs_cmd);
3136                 return r;
3137         }
3138
3139         return 0;
3140 }
3141
3142 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3143                 int channel, u8 *reqdata, int reqlen)
3144 {
3145         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3146         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3147         u16 data;
3148         u8 data_type;
3149         int r;
3150
3151         if (dsi->debug_read)
3152                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3153                         channel, reqlen);
3154
3155         if (reqlen == 0) {
3156                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3157                 data = 0;
3158         } else if (reqlen == 1) {
3159                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3160                 data = reqdata[0];
3161         } else if (reqlen == 2) {
3162                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3163                 data = reqdata[0] | (reqdata[1] << 8);
3164         } else {
3165                 BUG();
3166                 return -EINVAL;
3167         }
3168
3169         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3170         if (r) {
3171                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3172                         " failed\n", channel, reqlen);
3173                 return r;
3174         }
3175
3176         return 0;
3177 }
3178
3179 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3180                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3181 {
3182         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3183         u32 val;
3184         u8 dt;
3185         int r;
3186
3187         /* RX_FIFO_NOT_EMPTY */
3188         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3189                 DSSERR("RX fifo empty when trying to read.\n");
3190                 r = -EIO;
3191                 goto err;
3192         }
3193
3194         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3195         if (dsi->debug_read)
3196                 DSSDBG("\theader: %08x\n", val);
3197         dt = FLD_GET(val, 5, 0);
3198         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3199                 u16 err = FLD_GET(val, 23, 8);
3200                 dsi_show_rx_ack_with_err(err);
3201                 r = -EIO;
3202                 goto err;
3203
3204         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3205                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3206                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3207                 u8 data = FLD_GET(val, 15, 8);
3208                 if (dsi->debug_read)
3209                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3210                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3211                                 "DCS", data);
3212
3213                 if (buflen < 1) {
3214                         r = -EIO;
3215                         goto err;
3216                 }
3217
3218                 buf[0] = data;
3219
3220                 return 1;
3221         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3222                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3223                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3224                 u16 data = FLD_GET(val, 23, 8);
3225                 if (dsi->debug_read)
3226                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3227                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3228                                 "DCS", data);
3229
3230                 if (buflen < 2) {
3231                         r = -EIO;
3232                         goto err;
3233                 }
3234
3235                 buf[0] = data & 0xff;
3236                 buf[1] = (data >> 8) & 0xff;
3237
3238                 return 2;
3239         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3240                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3241                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3242                 int w;
3243                 int len = FLD_GET(val, 23, 8);
3244                 if (dsi->debug_read)
3245                         DSSDBG("\t%s long response, len %d\n",
3246                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3247                                 "DCS", len);
3248
3249                 if (len > buflen) {
3250                         r = -EIO;
3251                         goto err;
3252                 }
3253
3254                 /* two byte checksum ends the packet, not included in len */
3255                 for (w = 0; w < len + 2;) {
3256                         int b;
3257                         val = dsi_read_reg(dsidev,
3258                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3259                         if (dsi->debug_read)
3260                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3261                                                 (val >> 0) & 0xff,
3262                                                 (val >> 8) & 0xff,
3263                                                 (val >> 16) & 0xff,
3264                                                 (val >> 24) & 0xff);
3265
3266                         for (b = 0; b < 4; ++b) {
3267                                 if (w < len)
3268                                         buf[w] = (val >> (b * 8)) & 0xff;
3269                                 /* we discard the 2 byte checksum */
3270                                 ++w;
3271                         }
3272                 }
3273
3274                 return len;
3275         } else {
3276                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3277                 r = -EIO;
3278                 goto err;
3279         }
3280
3281 err:
3282         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3283                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3284
3285         return r;
3286 }
3287
3288 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3289                 u8 *buf, int buflen)
3290 {
3291         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3292         int r;
3293
3294         r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3295         if (r)
3296                 goto err;
3297
3298         r = dsi_vc_send_bta_sync(dssdev, channel);
3299         if (r)
3300                 goto err;
3301
3302         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3303                 DSS_DSI_CONTENT_DCS);
3304         if (r < 0)
3305                 goto err;
3306
3307         if (r != buflen) {
3308                 r = -EIO;
3309                 goto err;
3310         }
3311
3312         return 0;
3313 err:
3314         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3315         return r;
3316 }
3317 EXPORT_SYMBOL(dsi_vc_dcs_read);
3318
3319 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3320                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3321 {
3322         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3323         int r;
3324
3325         r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3326         if (r)
3327                 return r;
3328
3329         r = dsi_vc_send_bta_sync(dssdev, channel);
3330         if (r)
3331                 return r;
3332
3333         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3334                 DSS_DSI_CONTENT_GENERIC);
3335         if (r < 0)
3336                 return r;
3337
3338         if (r != buflen) {
3339                 r = -EIO;
3340                 return r;
3341         }
3342
3343         return 0;
3344 }
3345
3346 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3347                 int buflen)
3348 {
3349         int r;
3350
3351         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3352         if (r) {
3353                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3354                 return r;
3355         }
3356
3357         return 0;
3358 }
3359 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3360
3361 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3362                 u8 *buf, int buflen)
3363 {
3364         int r;
3365
3366         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3367         if (r) {
3368                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3369                 return r;
3370         }
3371
3372         return 0;
3373 }
3374 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3375
3376 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3377                 u8 param1, u8 param2, u8 *buf, int buflen)
3378 {
3379         int r;
3380         u8 reqdata[2];
3381
3382         reqdata[0] = param1;
3383         reqdata[1] = param2;
3384
3385         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3386         if (r) {
3387                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3388                 return r;
3389         }
3390
3391         return 0;
3392 }
3393 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3394
3395 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3396                 u16 len)
3397 {
3398         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3399
3400         return dsi_vc_send_short(dsidev, channel,
3401                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3402 }
3403 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3404
3405 static int dsi_enter_ulps(struct platform_device *dsidev)
3406 {
3407         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3408         DECLARE_COMPLETION_ONSTACK(completion);
3409         int r, i;
3410         unsigned mask;
3411
3412         DSSDBGF();
3413
3414         WARN_ON(!dsi_bus_is_locked(dsidev));
3415
3416         WARN_ON(dsi->ulps_enabled);
3417
3418         if (dsi->ulps_enabled)
3419                 return 0;
3420
3421         /* DDR_CLK_ALWAYS_ON */
3422         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3423                 dsi_if_enable(dsidev, 0);
3424                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3425                 dsi_if_enable(dsidev, 1);
3426         }
3427
3428         dsi_sync_vc(dsidev, 0);
3429         dsi_sync_vc(dsidev, 1);
3430         dsi_sync_vc(dsidev, 2);
3431         dsi_sync_vc(dsidev, 3);
3432
3433         dsi_force_tx_stop_mode_io(dsidev);
3434
3435         dsi_vc_enable(dsidev, 0, false);
3436         dsi_vc_enable(dsidev, 1, false);
3437         dsi_vc_enable(dsidev, 2, false);
3438         dsi_vc_enable(dsidev, 3, false);
3439
3440         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3441                 DSSERR("HS busy when enabling ULPS\n");
3442                 return -EIO;
3443         }
3444
3445         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3446                 DSSERR("LP busy when enabling ULPS\n");
3447                 return -EIO;
3448         }
3449
3450         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3451                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3452         if (r)
3453                 return r;
3454
3455         mask = 0;
3456
3457         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3458                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3459                         continue;
3460                 mask |= 1 << i;
3461         }
3462         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3463         /* LANEx_ULPS_SIG2 */
3464         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3465
3466         /* flush posted write and wait for SCP interface to finish the write */
3467         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3468
3469         if (wait_for_completion_timeout(&completion,
3470                                 msecs_to_jiffies(1000)) == 0) {
3471                 DSSERR("ULPS enable timeout\n");
3472                 r = -EIO;
3473                 goto err;
3474         }
3475
3476         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3477                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3478
3479         /* Reset LANEx_ULPS_SIG2 */
3480         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3481
3482         /* flush posted write and wait for SCP interface to finish the write */
3483         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3484
3485         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3486
3487         dsi_if_enable(dsidev, false);
3488
3489         dsi->ulps_enabled = true;
3490
3491         return 0;
3492
3493 err:
3494         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3495                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3496         return r;
3497 }
3498
3499 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3500                 unsigned ticks, bool x4, bool x16)
3501 {
3502         unsigned long fck;
3503         unsigned long total_ticks;
3504         u32 r;
3505
3506         BUG_ON(ticks > 0x1fff);
3507
3508         /* ticks in DSI_FCK */
3509         fck = dsi_fclk_rate(dsidev);
3510
3511         r = dsi_read_reg(dsidev, DSI_TIMING2);
3512         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3513         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3514         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3515         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3516         dsi_write_reg(dsidev, DSI_TIMING2, r);
3517
3518         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3519
3520         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3521                         total_ticks,
3522                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3523                         (total_ticks * 1000) / (fck / 1000 / 1000));
3524 }
3525
3526 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3527                 bool x8, bool x16)
3528 {
3529         unsigned long fck;
3530         unsigned long total_ticks;
3531         u32 r;
3532
3533         BUG_ON(ticks > 0x1fff);
3534
3535         /* ticks in DSI_FCK */
3536         fck = dsi_fclk_rate(dsidev);
3537
3538         r = dsi_read_reg(dsidev, DSI_TIMING1);
3539         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3540         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3541         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3542         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3543         dsi_write_reg(dsidev, DSI_TIMING1, r);
3544
3545         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3546
3547         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3548                         total_ticks,
3549                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3550                         (total_ticks * 1000) / (fck / 1000 / 1000));
3551 }
3552
3553 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3554                 unsigned ticks, bool x4, bool x16)
3555 {
3556         unsigned long fck;
3557         unsigned long total_ticks;
3558         u32 r;
3559
3560         BUG_ON(ticks > 0x1fff);
3561
3562         /* ticks in DSI_FCK */
3563         fck = dsi_fclk_rate(dsidev);
3564
3565         r = dsi_read_reg(dsidev, DSI_TIMING1);
3566         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3567         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3568         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3569         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3570         dsi_write_reg(dsidev, DSI_TIMING1, r);
3571
3572         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3573
3574         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3575                         total_ticks,
3576                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3577                         (total_ticks * 1000) / (fck / 1000 / 1000));
3578 }
3579
3580 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3581                 unsigned ticks, bool x4, bool x16)
3582 {
3583         unsigned long fck;
3584         unsigned long total_ticks;
3585         u32 r;
3586
3587         BUG_ON(ticks > 0x1fff);
3588
3589         /* ticks in TxByteClkHS */
3590         fck = dsi_get_txbyteclkhs(dsidev);
3591
3592         r = dsi_read_reg(dsidev, DSI_TIMING2);
3593         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3594         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3595         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3596         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3597         dsi_write_reg(dsidev, DSI_TIMING2, r);
3598
3599         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3600
3601         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3602                         total_ticks,
3603                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3604                         (total_ticks * 1000) / (fck / 1000 / 1000));
3605 }
3606
3607 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3608 {
3609         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3610         int num_line_buffers;
3611
3612         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3613                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3614                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3615                 struct omap_video_timings *timings = &dssdev->panel.timings;
3616                 /*
3617                  * Don't use line buffers if width is greater than the video
3618                  * port's line buffer size
3619                  */
3620                 if (line_buf_size <= timings->x_res * bpp / 8)
3621                         num_line_buffers = 0;
3622                 else
3623                         num_line_buffers = 2;
3624         } else {
3625                 /* Use maximum number of line buffers in command mode */
3626                 num_line_buffers = 2;
3627         }
3628
3629         /* LINE_BUFFER */
3630         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3631 }
3632
3633 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3634 {
3635         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3636         bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3637         bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3638         u32 r;
3639
3640         r = dsi_read_reg(dsidev, DSI_CTRL);
3641         r = FLD_MOD(r, 1, 9, 9);                /* VP_DE_POL */
3642         r = FLD_MOD(r, 1, 10, 10);              /* VP_HSYNC_POL */
3643         r = FLD_MOD(r, 1, 11, 11);              /* VP_VSYNC_POL */
3644         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3645         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3646         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3647         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3648         dsi_write_reg(dsidev, DSI_CTRL, r);
3649 }
3650
3651 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3652 {
3653         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3654         int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3655         int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3656         int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3657         int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3658         u32 r;
3659
3660         /*
3661          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3662          * 1 = Long blanking packets are sent in corresponding blanking periods
3663          */
3664         r = dsi_read_reg(dsidev, DSI_CTRL);
3665         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3666         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3667         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3668         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3669         dsi_write_reg(dsidev, DSI_CTRL, r);
3670 }
3671
3672 /*
3673  * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3674  * results in maximum transition time for data and clock lanes to enter and
3675  * exit HS mode. Hence, this is the scenario where the least amount of command
3676  * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3677  * clock cycles that can be used to interleave command mode data in HS so that
3678  * all scenarios are satisfied.
3679  */
3680 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3681                 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3682 {
3683         int transition;
3684
3685         /*
3686          * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3687          * time of data lanes only, if it isn't set, we need to consider HS
3688          * transition time of both data and clock lanes. HS transition time
3689          * of Scenario 3 is considered.
3690          */
3691         if (ddr_alwon) {
3692                 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3693         } else {
3694                 int trans1, trans2;
3695                 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3696                 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3697                                 enter_hs + 1;
3698                 transition = max(trans1, trans2);
3699         }
3700
3701         return blank > transition ? blank - transition : 0;
3702 }
3703
3704 /*
3705  * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3706  * results in maximum transition time for data lanes to enter and exit LP mode.
3707  * Hence, this is the scenario where the least amount of command mode data can
3708  * be interleaved. We program the minimum amount of bytes that can be
3709  * interleaved in LP so that all scenarios are satisfied.
3710  */
3711 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3712                 int lp_clk_div, int tdsi_fclk)
3713 {
3714         int trans_lp;   /* time required for a LP transition, in TXBYTECLKHS */
3715         int tlp_avail;  /* time left for interleaving commands, in CLKIN4DDR */
3716         int ttxclkesc;  /* period of LP transmit escape clock, in CLKIN4DDR */
3717         int thsbyte_clk = 16;   /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3718         int lp_inter;   /* cmd mode data that can be interleaved, in bytes */
3719
3720         /* maximum LP transition time according to Scenario 1 */
3721         trans_lp = exit_hs + max(enter_hs, 2) + 1;
3722
3723         /* CLKIN4DDR = 16 * TXBYTECLKHS */
3724         tlp_avail = thsbyte_clk * (blank - trans_lp);
3725
3726         ttxclkesc = tdsi_fclk * lp_clk_div;
3727
3728         lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3729                         26) / 16;
3730
3731         return max(lp_inter, 0);
3732 }
3733
3734 static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev)
3735 {
3736         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3737         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3738         int blanking_mode;
3739         int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3740         int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3741         int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3742         int tclk_trail, ths_exit, exiths_clk;
3743         bool ddr_alwon;
3744         struct omap_video_timings *timings = &dssdev->panel.timings;
3745         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3746         int ndl = dsi->num_lanes_used - 1;
3747         int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1;
3748         int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3749         int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3750         int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3751         int bl_interleave_hs = 0, bl_interleave_lp = 0;
3752         u32 r;
3753
3754         r = dsi_read_reg(dsidev, DSI_CTRL);
3755         blanking_mode = FLD_GET(r, 20, 20);
3756         hfp_blanking_mode = FLD_GET(r, 21, 21);
3757         hbp_blanking_mode = FLD_GET(r, 22, 22);
3758         hsa_blanking_mode = FLD_GET(r, 23, 23);
3759
3760         r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3761         hbp = FLD_GET(r, 11, 0);
3762         hfp = FLD_GET(r, 23, 12);
3763         hsa = FLD_GET(r, 31, 24);
3764
3765         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3766         ddr_clk_post = FLD_GET(r, 7, 0);
3767         ddr_clk_pre = FLD_GET(r, 15, 8);
3768
3769         r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3770         exit_hs_mode_lat = FLD_GET(r, 15, 0);
3771         enter_hs_mode_lat = FLD_GET(r, 31, 16);
3772
3773         r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3774         lp_clk_div = FLD_GET(r, 12, 0);
3775         ddr_alwon = FLD_GET(r, 13, 13);
3776
3777         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3778         ths_exit = FLD_GET(r, 7, 0);
3779
3780         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3781         tclk_trail = FLD_GET(r, 15, 8);
3782
3783         exiths_clk = ths_exit + tclk_trail;
3784
3785         width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3786         bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3787
3788         if (!hsa_blanking_mode) {
3789                 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3790                                         enter_hs_mode_lat, exit_hs_mode_lat,
3791                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3792                 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3793                                         enter_hs_mode_lat, exit_hs_mode_lat,
3794                                         lp_clk_div, dsi_fclk_hsdiv);
3795         }
3796
3797         if (!hfp_blanking_mode) {
3798                 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3799                                         enter_hs_mode_lat, exit_hs_mode_lat,
3800                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3801                 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3802                                         enter_hs_mode_lat, exit_hs_mode_lat,
3803                                         lp_clk_div, dsi_fclk_hsdiv);
3804         }
3805
3806         if (!hbp_blanking_mode) {
3807                 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3808                                         enter_hs_mode_lat, exit_hs_mode_lat,
3809                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3810
3811                 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3812                                         enter_hs_mode_lat, exit_hs_mode_lat,
3813                                         lp_clk_div, dsi_fclk_hsdiv);
3814         }
3815
3816         if (!blanking_mode) {
3817                 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3818                                         enter_hs_mode_lat, exit_hs_mode_lat,
3819                                         exiths_clk, ddr_clk_pre, ddr_clk_post);
3820
3821                 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3822                                         enter_hs_mode_lat, exit_hs_mode_lat,
3823                                         lp_clk_div, dsi_fclk_hsdiv);
3824         }
3825
3826         DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3827                 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3828                 bl_interleave_hs);
3829
3830         DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3831                 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3832                 bl_interleave_lp);
3833
3834         r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3835         r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3836         r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3837         r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3838         dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3839
3840         r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3841         r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3842         r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3843         r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3844         dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3845
3846         r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3847         r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3848         r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3849         dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3850 }
3851
3852 static int dsi_proto_config(struct omap_dss_device *dssdev)
3853 {
3854         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3855         u32 r;
3856         int buswidth = 0;
3857
3858         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3859                         DSI_FIFO_SIZE_32,
3860                         DSI_FIFO_SIZE_32,
3861                         DSI_FIFO_SIZE_32);
3862
3863         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3864                         DSI_FIFO_SIZE_32,
3865                         DSI_FIFO_SIZE_32,
3866                         DSI_FIFO_SIZE_32);
3867
3868         /* XXX what values for the timeouts? */
3869         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3870         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3871         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3872         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3873
3874         switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3875         case 16:
3876                 buswidth = 0;
3877                 break;
3878         case 18:
3879                 buswidth = 1;
3880                 break;
3881         case 24:
3882                 buswidth = 2;
3883                 break;
3884         default:
3885                 BUG();
3886                 return -EINVAL;
3887         }
3888
3889         r = dsi_read_reg(dsidev, DSI_CTRL);
3890         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
3891         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
3892         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
3893         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
3894         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3895         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
3896         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
3897         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
3898         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3899                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
3900                 /* DCS_CMD_CODE, 1=start, 0=continue */
3901                 r = FLD_MOD(r, 0, 25, 25);
3902         }
3903
3904         dsi_write_reg(dsidev, DSI_CTRL, r);
3905
3906         dsi_config_vp_num_line_buffers(dssdev);
3907
3908         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3909                 dsi_config_vp_sync_events(dssdev);
3910                 dsi_config_blanking_modes(dssdev);
3911                 dsi_config_cmd_mode_interleaving(dssdev);
3912         }
3913
3914         dsi_vc_initial_config(dsidev, 0);
3915         dsi_vc_initial_config(dsidev, 1);
3916         dsi_vc_initial_config(dsidev, 2);
3917         dsi_vc_initial_config(dsidev, 3);
3918
3919         return 0;
3920 }
3921
3922 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3923 {
3924         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3925         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3926         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3927         unsigned tclk_pre, tclk_post;
3928         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3929         unsigned ths_trail, ths_exit;
3930         unsigned ddr_clk_pre, ddr_clk_post;
3931         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3932         unsigned ths_eot;
3933         int ndl = dsi->num_lanes_used - 1;
3934         u32 r;
3935
3936         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3937         ths_prepare = FLD_GET(r, 31, 24);
3938         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3939         ths_zero = ths_prepare_ths_zero - ths_prepare;
3940         ths_trail = FLD_GET(r, 15, 8);
3941         ths_exit = FLD_GET(r, 7, 0);
3942
3943         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3944         tlpx = FLD_GET(r, 22, 16) * 2;
3945         tclk_trail = FLD_GET(r, 15, 8);
3946         tclk_zero = FLD_GET(r, 7, 0);
3947
3948         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3949         tclk_prepare = FLD_GET(r, 7, 0);
3950
3951         /* min 8*UI */
3952         tclk_pre = 20;
3953         /* min 60ns + 52*UI */
3954         tclk_post = ns2ddr(dsidev, 60) + 26;
3955
3956         ths_eot = DIV_ROUND_UP(4, ndl);
3957
3958         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3959                         4);
3960         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3961
3962         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3963         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3964
3965         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3966         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3967         r = FLD_MOD(r, ddr_clk_post, 7, 0);
3968         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3969
3970         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3971                         ddr_clk_pre,
3972                         ddr_clk_post);
3973
3974         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3975                 DIV_ROUND_UP(ths_prepare, 4) +
3976                 DIV_ROUND_UP(ths_zero + 3, 4);
3977
3978         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3979
3980         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3981                 FLD_VAL(exit_hs_mode_lat, 15, 0);
3982         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3983
3984         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3985                         enter_hs_mode_lat, exit_hs_mode_lat);
3986
3987          if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3988                 /* TODO: Implement a video mode check_timings function */
3989                 int hsa = dssdev->panel.dsi_vm_data.hsa;
3990                 int hfp = dssdev->panel.dsi_vm_data.hfp;
3991                 int hbp = dssdev->panel.dsi_vm_data.hbp;
3992                 int vsa = dssdev->panel.dsi_vm_data.vsa;
3993                 int vfp = dssdev->panel.dsi_vm_data.vfp;
3994                 int vbp = dssdev->panel.dsi_vm_data.vbp;
3995                 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3996                 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3997                 struct omap_video_timings *timings = &dssdev->panel.timings;
3998                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3999                 int tl, t_he, width_bytes;
4000
4001                 t_he = hsync_end ?
4002                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4003
4004                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4005
4006                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4007                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4008                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4009
4010                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4011                         hfp, hsync_end ? hsa : 0, tl);
4012                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4013                         vsa, timings->y_res);
4014
4015                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4016                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
4017                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
4018                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
4019                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4020
4021                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4022                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
4023                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
4024                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
4025                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
4026                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4027
4028                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4029                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
4030                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
4031                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4032         }
4033 }
4034
4035 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4036                 const struct omap_dsi_pin_config *pin_cfg)
4037 {
4038         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4039         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4040         int num_pins;
4041         const int *pins;
4042         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4043         int num_lanes;
4044         int i;
4045
4046         static const enum dsi_lane_function functions[] = {
4047                 DSI_LANE_CLK,
4048                 DSI_LANE_DATA1,
4049                 DSI_LANE_DATA2,
4050                 DSI_LANE_DATA3,
4051                 DSI_LANE_DATA4,
4052         };
4053
4054         num_pins = pin_cfg->num_pins;
4055         pins = pin_cfg->pins;
4056
4057         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4058                         || num_pins % 2 != 0)
4059                 return -EINVAL;
4060
4061         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4062                 lanes[i].function = DSI_LANE_UNUSED;
4063
4064         num_lanes = 0;
4065
4066         for (i = 0; i < num_pins; i += 2) {
4067                 u8 lane, pol;
4068                 int dx, dy;
4069
4070                 dx = pins[i];
4071                 dy = pins[i + 1];
4072
4073                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4074                         return -EINVAL;
4075
4076                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4077                         return -EINVAL;
4078
4079                 if (dx & 1) {
4080                         if (dy != dx - 1)
4081                                 return -EINVAL;
4082                         pol = 1;
4083                 } else {
4084                         if (dy != dx + 1)
4085                                 return -EINVAL;
4086                         pol = 0;
4087                 }
4088
4089                 lane = dx / 2;
4090
4091                 lanes[lane].function = functions[i / 2];
4092                 lanes[lane].polarity = pol;
4093                 num_lanes++;
4094         }
4095
4096         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4097         dsi->num_lanes_used = num_lanes;
4098
4099         return 0;
4100 }
4101 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4102
4103 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4104 {
4105         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4106         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4107         u8 data_type;
4108         u16 word_count;
4109         int r;
4110
4111         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4112                 switch (dssdev->panel.dsi_pix_fmt) {
4113                 case OMAP_DSS_DSI_FMT_RGB888:
4114                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4115                         break;
4116                 case OMAP_DSS_DSI_FMT_RGB666:
4117                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4118                         break;
4119                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4120                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4121                         break;
4122                 case OMAP_DSS_DSI_FMT_RGB565:
4123                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4124                         break;
4125                 default:
4126                         BUG();
4127                         return -EINVAL;
4128                 };
4129
4130                 dsi_if_enable(dsidev, false);
4131                 dsi_vc_enable(dsidev, channel, false);
4132
4133                 /* MODE, 1 = video mode */
4134                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4135
4136                 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
4137
4138                 dsi_vc_write_long_header(dsidev, channel, data_type,
4139                                 word_count, 0);
4140
4141                 dsi_vc_enable(dsidev, channel, true);
4142                 dsi_if_enable(dsidev, true);
4143         }
4144
4145         r = dss_mgr_enable(dssdev->manager);
4146         if (r) {
4147                 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4148                         dsi_if_enable(dsidev, false);
4149                         dsi_vc_enable(dsidev, channel, false);
4150                 }
4151
4152                 return r;
4153         }
4154
4155         return 0;
4156 }
4157 EXPORT_SYMBOL(dsi_enable_video_output);
4158
4159 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4160 {
4161         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4162
4163         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4164                 dsi_if_enable(dsidev, false);
4165                 dsi_vc_enable(dsidev, channel, false);
4166
4167                 /* MODE, 0 = command mode */
4168                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4169
4170                 dsi_vc_enable(dsidev, channel, true);
4171                 dsi_if_enable(dsidev, true);
4172         }
4173
4174         dss_mgr_disable(dssdev->manager);
4175 }
4176 EXPORT_SYMBOL(dsi_disable_video_output);
4177
4178 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4179                 u16 w, u16 h)
4180 {
4181         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4182         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4183         unsigned bytespp;
4184         unsigned bytespl;
4185         unsigned bytespf;
4186         unsigned total_len;
4187         unsigned packet_payload;
4188         unsigned packet_len;
4189         u32 l;
4190         int r;
4191         const unsigned channel = dsi->update_channel;
4192         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4193
4194         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4195
4196         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4197
4198         bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4199         bytespl = w * bytespp;
4200         bytespf = bytespl * h;
4201
4202         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4203          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4204
4205         if (bytespf < line_buf_size)
4206                 packet_payload = bytespf;
4207         else
4208                 packet_payload = (line_buf_size) / bytespl * bytespl;
4209
4210         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4211         total_len = (bytespf / packet_payload) * packet_len;
4212
4213         if (bytespf % packet_payload)
4214                 total_len += (bytespf % packet_payload) + 1;
4215
4216         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4217         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4218
4219         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4220                 packet_len, 0);
4221
4222         if (dsi->te_enabled)
4223                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4224         else
4225                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4226         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4227
4228         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4229          * because DSS interrupts are not capable of waking up the CPU and the
4230          * framedone interrupt could be delayed for quite a long time. I think
4231          * the same goes for any DSS interrupts, but for some reason I have not
4232          * seen the problem anywhere else than here.
4233          */
4234         dispc_disable_sidle();
4235
4236         dsi_perf_mark_start(dsidev);
4237
4238         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4239                 msecs_to_jiffies(250));
4240         BUG_ON(r == 0);
4241
4242         dss_mgr_start_update(dssdev->manager);
4243
4244         if (dsi->te_enabled) {
4245                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4246                  * for TE is longer than the timer allows */
4247                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4248
4249                 dsi_vc_send_bta(dsidev, channel);
4250
4251 #ifdef DSI_CATCH_MISSING_TE
4252                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4253 #endif
4254         }
4255 }
4256
4257 #ifdef DSI_CATCH_MISSING_TE
4258 static void dsi_te_timeout(unsigned long arg)
4259 {
4260         DSSERR("TE not received for 250ms!\n");
4261 }
4262 #endif
4263
4264 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4265 {
4266         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4267
4268         /* SIDLEMODE back to smart-idle */
4269         dispc_enable_sidle();
4270
4271         if (dsi->te_enabled) {
4272                 /* enable LP_RX_TO again after the TE */
4273                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4274         }
4275
4276         dsi->framedone_callback(error, dsi->framedone_data);
4277
4278         if (!error)
4279                 dsi_perf_show(dsidev, "DISPC");
4280 }
4281
4282 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4283 {
4284         struct dsi_data *dsi = container_of(work, struct dsi_data,
4285                         framedone_timeout_work.work);
4286         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4287          * 250ms which would conflict with this timeout work. What should be
4288          * done is first cancel the transfer on the HW, and then cancel the
4289          * possibly scheduled framedone work. However, cancelling the transfer
4290          * on the HW is buggy, and would probably require resetting the whole
4291          * DSI */
4292
4293         DSSERR("Framedone not received for 250ms!\n");
4294
4295         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4296 }
4297
4298 static void dsi_framedone_irq_callback(void *data, u32 mask)
4299 {
4300         struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4301         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4302         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4303
4304         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4305          * turns itself off. However, DSI still has the pixels in its buffers,
4306          * and is sending the data.
4307          */
4308
4309         __cancel_delayed_work(&dsi->framedone_timeout_work);
4310
4311         dsi_handle_framedone(dsidev, 0);
4312 }
4313
4314 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4315                 void (*callback)(int, void *), void *data)
4316 {
4317         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4318         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4319         u16 dw, dh;
4320
4321         dsi_perf_mark_setup(dsidev);
4322
4323         dsi->update_channel = channel;
4324
4325         dsi->framedone_callback = callback;
4326         dsi->framedone_data = data;
4327
4328         dssdev->driver->get_resolution(dssdev, &dw, &dh);
4329
4330 #ifdef DEBUG
4331         dsi->update_bytes = dw * dh *
4332                 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4333 #endif
4334         dsi_update_screen_dispc(dssdev, dw, dh);
4335
4336         return 0;
4337 }
4338 EXPORT_SYMBOL(omap_dsi_update);
4339
4340 /* Display funcs */
4341
4342 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4343 {
4344         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4345         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4346         struct dispc_clock_info dispc_cinfo;
4347         int r;
4348         unsigned long long fck;
4349
4350         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4351
4352         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4353         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4354
4355         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4356         if (r) {
4357                 DSSERR("Failed to calc dispc clocks\n");
4358                 return r;
4359         }
4360
4361         dsi->mgr_config.clock_info = dispc_cinfo;
4362
4363         return 0;
4364 }
4365
4366 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4367 {
4368         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4369         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4370         struct omap_video_timings timings;
4371         int r;
4372         u32 irq = 0;
4373
4374         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4375                 u16 dw, dh;
4376
4377                 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4378
4379                 timings.x_res = dw;
4380                 timings.y_res = dh;
4381                 timings.hsw = 1;
4382                 timings.hfp = 1;
4383                 timings.hbp = 1;
4384                 timings.vsw = 1;
4385                 timings.vfp = 0;
4386                 timings.vbp = 0;
4387
4388                 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
4389
4390                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4391                         (void *) dssdev, irq);
4392                 if (r) {
4393                         DSSERR("can't get FRAMEDONE irq\n");
4394                         goto err;
4395                 }
4396
4397                 dsi->mgr_config.stallmode = true;
4398                 dsi->mgr_config.fifohandcheck = true;
4399         } else {
4400                 timings = dssdev->panel.timings;
4401
4402                 dsi->mgr_config.stallmode = false;
4403                 dsi->mgr_config.fifohandcheck = false;
4404         }
4405
4406         /*
4407          * override interlace, logic level and edge related parameters in
4408          * omap_video_timings with default values
4409          */
4410         timings.interlace = false;
4411         timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4412         timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4413         timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4414         timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4415         timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4416
4417         dss_mgr_set_timings(dssdev->manager, &timings);
4418
4419         r = dsi_configure_dispc_clocks(dssdev);
4420         if (r)
4421                 goto err1;
4422
4423         dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4424         dsi->mgr_config.video_port_width =
4425                         dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
4426         dsi->mgr_config.lcden_sig_polarity = 0;
4427
4428         dss_mgr_set_lcd_config(dssdev->manager, &dsi->mgr_config);
4429
4430         return 0;
4431 err1:
4432         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE)
4433                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4434                         (void *) dssdev, irq);
4435 err:
4436         return r;
4437 }
4438
4439 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4440 {
4441         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4442                 u32 irq;
4443
4444                 irq = dispc_mgr_get_framedone_irq(dssdev->manager->id);
4445
4446                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4447                         (void *) dssdev, irq);
4448         }
4449 }
4450
4451 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4452 {
4453         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4454         struct dsi_clock_info cinfo;
4455         int r;
4456
4457         cinfo.regn  = dssdev->clocks.dsi.regn;
4458         cinfo.regm  = dssdev->clocks.dsi.regm;
4459         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4460         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4461         r = dsi_calc_clock_rates(dsidev, &cinfo);
4462         if (r) {
4463                 DSSERR("Failed to calc dsi clocks\n");
4464                 return r;
4465         }
4466
4467         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4468         if (r) {
4469                 DSSERR("Failed to set dsi clocks\n");
4470                 return r;
4471         }
4472
4473         return 0;
4474 }
4475
4476 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4477 {
4478         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4479         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4480         int r;
4481
4482         r = dsi_pll_init(dsidev, true, true);
4483         if (r)
4484                 goto err0;
4485
4486         r = dsi_configure_dsi_clocks(dssdev);
4487         if (r)
4488                 goto err1;
4489
4490         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4491         dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src);
4492         dss_select_lcd_clk_source(dssdev->manager->id,
4493                         dssdev->clocks.dispc.channel.lcd_clk_src);
4494
4495         DSSDBG("PLL OK\n");
4496
4497         r = dsi_cio_init(dssdev);
4498         if (r)
4499                 goto err2;
4500
4501         _dsi_print_reset_status(dsidev);
4502
4503         dsi_proto_timings(dssdev);
4504         dsi_set_lp_clk_divisor(dssdev);
4505
4506         if (1)
4507                 _dsi_print_reset_status(dsidev);
4508
4509         r = dsi_proto_config(dssdev);
4510         if (r)
4511                 goto err3;
4512
4513         /* enable interface */
4514         dsi_vc_enable(dsidev, 0, 1);
4515         dsi_vc_enable(dsidev, 1, 1);
4516         dsi_vc_enable(dsidev, 2, 1);
4517         dsi_vc_enable(dsidev, 3, 1);
4518         dsi_if_enable(dsidev, 1);
4519         dsi_force_tx_stop_mode_io(dsidev);
4520
4521         return 0;
4522 err3:
4523         dsi_cio_uninit(dssdev);
4524 err2:
4525         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4526         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4527         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4528
4529 err1:
4530         dsi_pll_uninit(dsidev, true);
4531 err0:
4532         return r;
4533 }
4534
4535 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4536                 bool disconnect_lanes, bool enter_ulps)
4537 {
4538         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4539         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4540
4541         if (enter_ulps && !dsi->ulps_enabled)
4542                 dsi_enter_ulps(dsidev);
4543
4544         /* disable interface */
4545         dsi_if_enable(dsidev, 0);
4546         dsi_vc_enable(dsidev, 0, 0);
4547         dsi_vc_enable(dsidev, 1, 0);
4548         dsi_vc_enable(dsidev, 2, 0);
4549         dsi_vc_enable(dsidev, 3, 0);
4550
4551         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4552         dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4553         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4554         dsi_cio_uninit(dssdev);
4555         dsi_pll_uninit(dsidev, disconnect_lanes);
4556 }
4557
4558 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4559 {
4560         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4561         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4562         int r = 0;
4563
4564         DSSDBG("dsi_display_enable\n");
4565
4566         WARN_ON(!dsi_bus_is_locked(dsidev));
4567
4568         mutex_lock(&dsi->lock);
4569
4570         if (dssdev->manager == NULL) {
4571                 DSSERR("failed to enable display: no manager\n");
4572                 r = -ENODEV;
4573                 goto err_start_dev;
4574         }
4575
4576         r = omap_dss_start_device(dssdev);
4577         if (r) {
4578                 DSSERR("failed to start device\n");
4579                 goto err_start_dev;
4580         }
4581
4582         r = dsi_runtime_get(dsidev);
4583         if (r)
4584                 goto err_get_dsi;
4585
4586         dsi_enable_pll_clock(dsidev, 1);
4587
4588         _dsi_initialize_irq(dsidev);
4589
4590         r = dsi_display_init_dispc(dssdev);
4591         if (r)
4592                 goto err_init_dispc;
4593
4594         r = dsi_display_init_dsi(dssdev);
4595         if (r)
4596                 goto err_init_dsi;
4597
4598         mutex_unlock(&dsi->lock);
4599
4600         return 0;
4601
4602 err_init_dsi:
4603         dsi_display_uninit_dispc(dssdev);
4604 err_init_dispc:
4605         dsi_enable_pll_clock(dsidev, 0);
4606         dsi_runtime_put(dsidev);
4607 err_get_dsi:
4608         omap_dss_stop_device(dssdev);
4609 err_start_dev:
4610         mutex_unlock(&dsi->lock);
4611         DSSDBG("dsi_display_enable FAILED\n");
4612         return r;
4613 }
4614 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4615
4616 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4617                 bool disconnect_lanes, bool enter_ulps)
4618 {
4619         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4620         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4621
4622         DSSDBG("dsi_display_disable\n");
4623
4624         WARN_ON(!dsi_bus_is_locked(dsidev));
4625
4626         mutex_lock(&dsi->lock);
4627
4628         dsi_sync_vc(dsidev, 0);
4629         dsi_sync_vc(dsidev, 1);
4630         dsi_sync_vc(dsidev, 2);
4631         dsi_sync_vc(dsidev, 3);
4632
4633         dsi_display_uninit_dispc(dssdev);
4634
4635         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4636
4637         dsi_runtime_put(dsidev);
4638         dsi_enable_pll_clock(dsidev, 0);
4639
4640         omap_dss_stop_device(dssdev);
4641
4642         mutex_unlock(&dsi->lock);
4643 }
4644 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4645
4646 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4647 {
4648         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4649         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4650
4651         dsi->te_enabled = enable;
4652         return 0;
4653 }
4654 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4655
4656 static int __init dsi_init_display(struct omap_dss_device *dssdev)
4657 {
4658         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4659         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4660
4661         DSSDBG("DSI init\n");
4662
4663         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4664                 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4665                         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4666         }
4667
4668         if (dsi->vdds_dsi_reg == NULL) {
4669                 struct regulator *vdds_dsi;
4670
4671                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4672
4673                 if (IS_ERR(vdds_dsi)) {
4674                         DSSERR("can't get VDDS_DSI regulator\n");
4675                         return PTR_ERR(vdds_dsi);
4676                 }
4677
4678                 dsi->vdds_dsi_reg = vdds_dsi;
4679         }
4680
4681         return 0;
4682 }
4683
4684 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4685 {
4686         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4687         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4688         int i;
4689
4690         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4691                 if (!dsi->vc[i].dssdev) {
4692                         dsi->vc[i].dssdev = dssdev;
4693                         *channel = i;
4694                         return 0;
4695                 }
4696         }
4697
4698         DSSERR("cannot get VC for display %s", dssdev->name);
4699         return -ENOSPC;
4700 }
4701 EXPORT_SYMBOL(omap_dsi_request_vc);
4702
4703 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4704 {
4705         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4706         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4707
4708         if (vc_id < 0 || vc_id > 3) {
4709                 DSSERR("VC ID out of range\n");
4710                 return -EINVAL;
4711         }
4712
4713         if (channel < 0 || channel > 3) {
4714                 DSSERR("Virtual Channel out of range\n");
4715                 return -EINVAL;
4716         }
4717
4718         if (dsi->vc[channel].dssdev != dssdev) {
4719                 DSSERR("Virtual Channel not allocated to display %s\n",
4720                         dssdev->name);
4721                 return -EINVAL;
4722         }
4723
4724         dsi->vc[channel].vc_id = vc_id;
4725
4726         return 0;
4727 }
4728 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4729
4730 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4731 {
4732         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4733         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4734
4735         if ((channel >= 0 && channel <= 3) &&
4736                 dsi->vc[channel].dssdev == dssdev) {
4737                 dsi->vc[channel].dssdev = NULL;
4738                 dsi->vc[channel].vc_id = 0;
4739         }
4740 }
4741 EXPORT_SYMBOL(omap_dsi_release_vc);
4742
4743 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4744 {
4745         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4746                 DSSERR("%s (%s) not active\n",
4747                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4748                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4749 }
4750
4751 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4752 {
4753         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4754                 DSSERR("%s (%s) not active\n",
4755                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4756                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4757 }
4758
4759 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4760 {
4761         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4762
4763         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4764         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4765         dsi->regm_dispc_max =
4766                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4767         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4768         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4769         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4770         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4771 }
4772
4773 static int dsi_get_clocks(struct platform_device *dsidev)
4774 {
4775         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4776         struct clk *clk;
4777
4778         clk = clk_get(&dsidev->dev, "fck");
4779         if (IS_ERR(clk)) {
4780                 DSSERR("can't get fck\n");
4781                 return PTR_ERR(clk);
4782         }
4783
4784         dsi->dss_clk = clk;
4785
4786         clk = clk_get(&dsidev->dev, "sys_clk");
4787         if (IS_ERR(clk)) {
4788                 DSSERR("can't get sys_clk\n");
4789                 clk_put(dsi->dss_clk);
4790                 dsi->dss_clk = NULL;
4791                 return PTR_ERR(clk);
4792         }
4793
4794         dsi->sys_clk = clk;
4795
4796         return 0;
4797 }
4798
4799 static void dsi_put_clocks(struct platform_device *dsidev)
4800 {
4801         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4802
4803         if (dsi->dss_clk)
4804                 clk_put(dsi->dss_clk);
4805         if (dsi->sys_clk)
4806                 clk_put(dsi->sys_clk);
4807 }
4808
4809 static void __init dsi_probe_pdata(struct platform_device *dsidev)
4810 {
4811         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4812         struct omap_dss_board_info *pdata = dsidev->dev.platform_data;
4813         int i, r;
4814
4815         for (i = 0; i < pdata->num_devices; ++i) {
4816                 struct omap_dss_device *dssdev = pdata->devices[i];
4817
4818                 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
4819                         continue;
4820
4821                 if (dssdev->phy.dsi.module != dsi->module_id)
4822                         continue;
4823
4824                 r = dsi_init_display(dssdev);
4825                 if (r) {
4826                         DSSERR("device %s init failed: %d\n", dssdev->name, r);
4827                         continue;
4828                 }
4829
4830                 r = omap_dss_register_device(dssdev, &dsidev->dev, i);
4831                 if (r)
4832                         DSSERR("device %s register failed: %d\n",
4833                                         dssdev->name, r);
4834         }
4835 }
4836
4837 /* DSI1 HW IP initialisation */
4838 static int __init omap_dsihw_probe(struct platform_device *dsidev)
4839 {
4840         u32 rev;
4841         int r, i;
4842         struct resource *dsi_mem;
4843         struct dsi_data *dsi;
4844
4845         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
4846         if (!dsi)
4847                 return -ENOMEM;
4848
4849         dsi->module_id = dsidev->id;
4850         dsi->pdev = dsidev;
4851         dsi_pdev_map[dsi->module_id] = dsidev;
4852         dev_set_drvdata(&dsidev->dev, dsi);
4853
4854         spin_lock_init(&dsi->irq_lock);
4855         spin_lock_init(&dsi->errors_lock);
4856         dsi->errors = 0;
4857
4858 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4859         spin_lock_init(&dsi->irq_stats_lock);
4860         dsi->irq_stats.last_reset = jiffies;
4861 #endif
4862
4863         mutex_init(&dsi->lock);
4864         sema_init(&dsi->bus_lock, 1);
4865
4866         INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4867                         dsi_framedone_timeout_work_callback);
4868
4869 #ifdef DSI_CATCH_MISSING_TE
4870         init_timer(&dsi->te_timer);
4871         dsi->te_timer.function = dsi_te_timeout;
4872         dsi->te_timer.data = 0;
4873 #endif
4874         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4875         if (!dsi_mem) {
4876                 DSSERR("can't get IORESOURCE_MEM DSI\n");
4877                 return -EINVAL;
4878         }
4879
4880         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
4881                                  resource_size(dsi_mem));
4882         if (!dsi->base) {
4883                 DSSERR("can't ioremap DSI\n");
4884                 return -ENOMEM;
4885         }
4886
4887         dsi->irq = platform_get_irq(dsi->pdev, 0);
4888         if (dsi->irq < 0) {
4889                 DSSERR("platform_get_irq failed\n");
4890                 return -ENODEV;
4891         }
4892
4893         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
4894                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
4895         if (r < 0) {
4896                 DSSERR("request_irq failed\n");
4897                 return r;
4898         }
4899
4900         /* DSI VCs initialization */
4901         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4902                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4903                 dsi->vc[i].dssdev = NULL;
4904                 dsi->vc[i].vc_id = 0;
4905         }
4906
4907         dsi_calc_clock_param_ranges(dsidev);
4908
4909         r = dsi_get_clocks(dsidev);
4910         if (r)
4911                 return r;
4912
4913         pm_runtime_enable(&dsidev->dev);
4914
4915         r = dsi_runtime_get(dsidev);
4916         if (r)
4917                 goto err_runtime_get;
4918
4919         rev = dsi_read_reg(dsidev, DSI_REVISION);
4920         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4921                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4922
4923         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4924          * of data to 3 by default */
4925         if (dss_has_feature(FEAT_DSI_GNQ))
4926                 /* NB_DATA_LANES */
4927                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4928         else
4929                 dsi->num_lanes_supported = 3;
4930
4931         dsi_probe_pdata(dsidev);
4932
4933         dsi_runtime_put(dsidev);
4934
4935         if (dsi->module_id == 0)
4936                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
4937         else if (dsi->module_id == 1)
4938                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
4939
4940 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4941         if (dsi->module_id == 0)
4942                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
4943         else if (dsi->module_id == 1)
4944                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
4945 #endif
4946         return 0;
4947
4948 err_runtime_get:
4949         pm_runtime_disable(&dsidev->dev);
4950         dsi_put_clocks(dsidev);
4951         return r;
4952 }
4953
4954 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
4955 {
4956         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4957
4958         WARN_ON(dsi->scp_clk_refcount > 0);
4959
4960         omap_dss_unregister_child_devices(&dsidev->dev);
4961
4962         pm_runtime_disable(&dsidev->dev);
4963
4964         dsi_put_clocks(dsidev);
4965
4966         if (dsi->vdds_dsi_reg != NULL) {
4967                 if (dsi->vdds_dsi_enabled) {
4968                         regulator_disable(dsi->vdds_dsi_reg);
4969                         dsi->vdds_dsi_enabled = false;
4970                 }
4971
4972                 regulator_put(dsi->vdds_dsi_reg);
4973                 dsi->vdds_dsi_reg = NULL;
4974         }
4975
4976         return 0;
4977 }
4978
4979 static int dsi_runtime_suspend(struct device *dev)
4980 {
4981         dispc_runtime_put();
4982
4983         return 0;
4984 }
4985
4986 static int dsi_runtime_resume(struct device *dev)
4987 {
4988         int r;
4989
4990         r = dispc_runtime_get();
4991         if (r)
4992                 return r;
4993
4994         return 0;
4995 }
4996
4997 static const struct dev_pm_ops dsi_pm_ops = {
4998         .runtime_suspend = dsi_runtime_suspend,
4999         .runtime_resume = dsi_runtime_resume,
5000 };
5001
5002 static struct platform_driver omap_dsihw_driver = {
5003         .remove         = __exit_p(omap_dsihw_remove),
5004         .driver         = {
5005                 .name   = "omapdss_dsi",
5006                 .owner  = THIS_MODULE,
5007                 .pm     = &dsi_pm_ops,
5008         },
5009 };
5010
5011 int __init dsi_init_platform_driver(void)
5012 {
5013         return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
5014 }
5015
5016 void __exit dsi_uninit_platform_driver(void)
5017 {
5018         platform_driver_unregister(&omap_dsihw_driver);
5019 }