drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/export.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/gfp.h>
  35 #include <linux/sizes.h>
  36
  37 #include <video/omapdss.h>
  38
  39 #include "dss.h"
  40 #include "dss_features.h"
  41
  42 #define DSS_SZ_REGS                     SZ_512
  43
  44 struct dss_reg {
  45         u16 idx;
  46 };
  47
  48 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  49
  50 #define DSS_REVISION                    DSS_REG(0x0000)
  51 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  52 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  53 #define DSS_CONTROL                     DSS_REG(0x0040)
  54 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  55 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  56 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  57
  58 #define REG_GET(idx, start, end) \
  59         FLD_GET(dss_read_reg(idx), start, end)
  60
  61 #define REG_FLD_MOD(idx, val, start, end) \
  62         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  63
  64 static int dss_runtime_get(void);
  65 static void dss_runtime_put(void);
  66
  67 struct dss_features {
  68         u8 fck_div_max;
  69         u8 dss_fck_multiplier;
  70         const char *parent_clk_name;
  71         int (*dpi_select_source)(enum omap_channel channel);
  72 };
  73
  74 static struct {
  75         struct platform_device *pdev;
  76         void __iomem    *base;
  77
  78         struct clk      *parent_clk;
  79         struct clk      *dss_clk;
  80         unsigned long   dss_clk_rate;
  81
  82         unsigned long   cache_req_pck;
  83         unsigned long   cache_prate;
  84         struct dispc_clock_info cache_dispc_cinfo;
  85
  86         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  87         enum omap_dss_clk_source dispc_clk_source;
  88         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  89
  90         bool            ctx_valid;
  91         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  92
  93         const struct dss_features *feat;
  94 } dss;
  95
  96 static const char * const dss_generic_clk_source_names[] = {
  97         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  98         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  99         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 100         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
 101         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DSI_PLL2_HSDIV_DSI",
 102 };
 103
 104 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 105 {
 106         __raw_writel(val, dss.base + idx.idx);
 107 }
 108
 109 static inline u32 dss_read_reg(const struct dss_reg idx)
 110 {
 111         return __raw_readl(dss.base + idx.idx);
 112 }
 113
 114 #define SR(reg) \
 115         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 116 #define RR(reg) \
 117         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 118
 119 static void dss_save_context(void)
 120 {
 121         DSSDBG("dss_save_context\n");
 122
 123         SR(CONTROL);
 124
 125         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 126                         OMAP_DISPLAY_TYPE_SDI) {
 127                 SR(SDI_CONTROL);
 128                 SR(PLL_CONTROL);
 129         }
 130
 131         dss.ctx_valid = true;
 132
 133         DSSDBG("context saved\n");
 134 }
 135
 136 static void dss_restore_context(void)
 137 {
 138         DSSDBG("dss_restore_context\n");
 139
 140         if (!dss.ctx_valid)
 141                 return;
 142
 143         RR(CONTROL);
 144
 145         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 146                         OMAP_DISPLAY_TYPE_SDI) {
 147                 RR(SDI_CONTROL);
 148                 RR(PLL_CONTROL);
 149         }
 150
 151         DSSDBG("context restored\n");
 152 }
 153
 154 #undef SR
 155 #undef RR
 156
 157 int dss_get_ctx_loss_count(void)
 158 {
 159         struct platform_device *core_pdev = dss_get_core_pdev();
 160         struct omap_dss_board_info *board_data = core_pdev->dev.platform_data;
 161         int cnt;
 162
 163         if (!board_data->get_context_loss_count)
 164                 return -ENOENT;
 165
 166         cnt = board_data->get_context_loss_count(&dss.pdev->dev);
 167
 168         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 169
 170         return cnt;
 171 }
 172
 173 void dss_sdi_init(int datapairs)
 174 {
 175         u32 l;
 176
 177         BUG_ON(datapairs > 3 || datapairs < 1);
 178
 179         l = dss_read_reg(DSS_SDI_CONTROL);
 180         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 181         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 182         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 183         dss_write_reg(DSS_SDI_CONTROL, l);
 184
 185         l = dss_read_reg(DSS_PLL_CONTROL);
 186         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 187         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 188         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 189         dss_write_reg(DSS_PLL_CONTROL, l);
 190 }
 191
 192 int dss_sdi_enable(void)
 193 {
 194         unsigned long timeout;
 195
 196         dispc_pck_free_enable(1);
 197
 198         /* Reset SDI PLL */
 199         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 200         udelay(1);      /* wait 2x PCLK */
 201
 202         /* Lock SDI PLL */
 203         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 204
 205         /* Waiting for PLL lock request to complete */
 206         timeout = jiffies + msecs_to_jiffies(500);
 207         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 208                 if (time_after_eq(jiffies, timeout)) {
 209                         DSSERR("PLL lock request timed out\n");
 210                         goto err1;
 211                 }
 212         }
 213
 214         /* Clearing PLL_GO bit */
 215         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 216
 217         /* Waiting for PLL to lock */
 218         timeout = jiffies + msecs_to_jiffies(500);
 219         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 220                 if (time_after_eq(jiffies, timeout)) {
 221                         DSSERR("PLL lock timed out\n");
 222                         goto err1;
 223                 }
 224         }
 225
 226         dispc_lcd_enable_signal(1);
 227
 228         /* Waiting for SDI reset to complete */
 229         timeout = jiffies + msecs_to_jiffies(500);
 230         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 231                 if (time_after_eq(jiffies, timeout)) {
 232                         DSSERR("SDI reset timed out\n");
 233                         goto err2;
 234                 }
 235         }
 236
 237         return 0;
 238
 239  err2:
 240         dispc_lcd_enable_signal(0);
 241  err1:
 242         /* Reset SDI PLL */
 243         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 244
 245         dispc_pck_free_enable(0);
 246
 247         return -ETIMEDOUT;
 248 }
 249
 250 void dss_sdi_disable(void)
 251 {
 252         dispc_lcd_enable_signal(0);
 253
 254         dispc_pck_free_enable(0);
 255
 256         /* Reset SDI PLL */
 257         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 258 }
 259
 260 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 261 {
 262         return dss_generic_clk_source_names[clk_src];
 263 }
 264
 265 void dss_dump_clocks(struct seq_file *s)
 266 {
 267         const char *fclk_name, *fclk_real_name;
 268         unsigned long fclk_rate;
 269
 270         if (dss_runtime_get())
 271                 return;
 272
 273         seq_printf(s, "- DSS -\n");
 274
 275         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 276         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 277         fclk_rate = clk_get_rate(dss.dss_clk);
 278
 279         seq_printf(s, "%s (%s) = %lu\n",
 280                         fclk_name, fclk_real_name,
 281                         fclk_rate);
 282
 283         dss_runtime_put();
 284 }
 285
 286 static void dss_dump_regs(struct seq_file *s)
 287 {
 288 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 289
 290         if (dss_runtime_get())
 291                 return;
 292
 293         DUMPREG(DSS_REVISION);
 294         DUMPREG(DSS_SYSCONFIG);
 295         DUMPREG(DSS_SYSSTATUS);
 296         DUMPREG(DSS_CONTROL);
 297
 298         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 299                         OMAP_DISPLAY_TYPE_SDI) {
 300                 DUMPREG(DSS_SDI_CONTROL);
 301                 DUMPREG(DSS_PLL_CONTROL);
 302                 DUMPREG(DSS_SDI_STATUS);
 303         }
 304
 305         dss_runtime_put();
 306 #undef DUMPREG
 307 }
 308
 309 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 310 {
 311         struct platform_device *dsidev;
 312         int b;
 313         u8 start, end;
 314
 315         switch (clk_src) {
 316         case OMAP_DSS_CLK_SRC_FCK:
 317                 b = 0;
 318                 break;
 319         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 320                 b = 1;
 321                 dsidev = dsi_get_dsidev_from_id(0);
 322                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 323                 break;
 324         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 325                 b = 2;
 326                 dsidev = dsi_get_dsidev_from_id(1);
 327                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 328                 break;
 329         default:
 330                 BUG();
 331                 return;
 332         }
 333
 334         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 335
 336         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 337
 338         dss.dispc_clk_source = clk_src;
 339 }
 340
 341 void dss_select_dsi_clk_source(int dsi_module,
 342                 enum omap_dss_clk_source clk_src)
 343 {
 344         struct platform_device *dsidev;
 345         int b, pos;
 346
 347         switch (clk_src) {
 348         case OMAP_DSS_CLK_SRC_FCK:
 349                 b = 0;
 350                 break;
 351         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 352                 BUG_ON(dsi_module != 0);
 353                 b = 1;
 354                 dsidev = dsi_get_dsidev_from_id(0);
 355                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 356                 break;
 357         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 358                 BUG_ON(dsi_module != 1);
 359                 b = 1;
 360                 dsidev = dsi_get_dsidev_from_id(1);
 361                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 362                 break;
 363         default:
 364                 BUG();
 365                 return;
 366         }
 367
 368         pos = dsi_module == 0 ? 1 : 10;
 369         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 370
 371         dss.dsi_clk_source[dsi_module] = clk_src;
 372 }
 373
 374 void dss_select_lcd_clk_source(enum omap_channel channel,
 375                 enum omap_dss_clk_source clk_src)
 376 {
 377         struct platform_device *dsidev;
 378         int b, ix, pos;
 379
 380         if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
 381                 dss_select_dispc_clk_source(clk_src);
 382                 return;
 383         }
 384
 385         switch (clk_src) {
 386         case OMAP_DSS_CLK_SRC_FCK:
 387                 b = 0;
 388                 break;
 389         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 390                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 391                 b = 1;
 392                 dsidev = dsi_get_dsidev_from_id(0);
 393                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 394                 break;
 395         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 396                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 397                        channel != OMAP_DSS_CHANNEL_LCD3);
 398                 b = 1;
 399                 dsidev = dsi_get_dsidev_from_id(1);
 400                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 401                 break;
 402         default:
 403                 BUG();
 404                 return;
 405         }
 406
 407         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 408              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 409         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 410
 411         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 412             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 413         dss.lcd_clk_source[ix] = clk_src;
 414 }
 415
 416 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 417 {
 418         return dss.dispc_clk_source;
 419 }
 420
 421 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 422 {
 423         return dss.dsi_clk_source[dsi_module];
 424 }
 425
 426 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 427 {
 428         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 429                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 430                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 431                 return dss.lcd_clk_source[ix];
 432         } else {
 433                 /* LCD_CLK source is the same as DISPC_FCLK source for
 434                  * OMAP2 and OMAP3 */
 435                 return dss.dispc_clk_source;
 436         }
 437 }
 438
 439 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 440                 dss_div_calc_func func, void *data)
 441 {
 442         int fckd, fckd_start, fckd_stop;
 443         unsigned long fck;
 444         unsigned long fck_hw_max;
 445         unsigned long fckd_hw_max;
 446         unsigned long prate;
 447         unsigned m;
 448
 449         if (dss.parent_clk == NULL) {
 450                 fck = clk_get_rate(dss.dss_clk);
 451                 return func(fck, data);
 452         }
 453
 454         fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 455         fckd_hw_max = dss.feat->fck_div_max;
 456
 457         m = dss.feat->dss_fck_multiplier;
 458         prate = clk_get_rate(dss.parent_clk);
 459
 460         fck_min = fck_min ? fck_min : 1;
 461
 462         fckd_start = min(prate * m / fck_min, fckd_hw_max);
 463         fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
 464
 465         for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
 466                 fck = prate / fckd * m;
 467
 468                 if (func(fck, data))
 469                         return true;
 470         }
 471
 472         return false;
 473 }
 474
 475 int dss_set_fck_rate(unsigned long rate)
 476 {
 477         int r;
 478
 479         DSSDBG("set fck to %lu\n", rate);
 480
 481         r = clk_set_rate(dss.dss_clk, rate);
 482         if (r)
 483                 return r;
 484
 485         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 486
 487         WARN_ONCE(dss.dss_clk_rate != rate,
 488                         "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
 489                         rate);
 490
 491         return 0;
 492 }
 493
 494 unsigned long dss_get_dispc_clk_rate(void)
 495 {
 496         return dss.dss_clk_rate;
 497 }
 498
 499 static int dss_setup_default_clock(void)
 500 {
 501         unsigned long max_dss_fck, prate;
 502         unsigned long fck;
 503         unsigned fck_div;
 504         int r;
 505
 506         if (dss.parent_clk == NULL)
 507                 return 0;
 508
 509         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 510
 511         prate = clk_get_rate(dss.parent_clk);
 512
 513         fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
 514                         max_dss_fck);
 515         fck = prate / fck_div * dss.feat->dss_fck_multiplier;
 516
 517         r = dss_set_fck_rate(fck);
 518         if (r)
 519                 return r;
 520
 521         return 0;
 522 }
 523
 524 void dss_set_venc_output(enum omap_dss_venc_type type)
 525 {
 526         int l = 0;
 527
 528         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 529                 l = 0;
 530         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 531                 l = 1;
 532         else
 533                 BUG();
 534
 535         /* venc out selection. 0 = comp, 1 = svideo */
 536         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 537 }
 538
 539 void dss_set_dac_pwrdn_bgz(bool enable)
 540 {
 541         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 542 }
 543
 544 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 545 {
 546         enum omap_display_type dp;
 547         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 548
 549         /* Complain about invalid selections */
 550         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 551         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 552
 553         /* Select only if we have options */
 554         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 555                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 556 }
 557
 558 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 559 {
 560         enum omap_display_type displays;
 561
 562         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 563         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 564                 return DSS_VENC_TV_CLK;
 565
 566         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 567                 return DSS_HDMI_M_PCLK;
 568
 569         return REG_GET(DSS_CONTROL, 15, 15);
 570 }
 571
 572 static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
 573 {
 574         if (channel != OMAP_DSS_CHANNEL_LCD)
 575                 return -EINVAL;
 576
 577         return 0;
 578 }
 579
 580 static int dss_dpi_select_source_omap4(enum omap_channel channel)
 581 {
 582         int val;
 583
 584         switch (channel) {
 585         case OMAP_DSS_CHANNEL_LCD2:
 586                 val = 0;
 587                 break;
 588         case OMAP_DSS_CHANNEL_DIGIT:
 589                 val = 1;
 590                 break;
 591         default:
 592                 return -EINVAL;
 593         }
 594
 595         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
 596
 597         return 0;
 598 }
 599
 600 static int dss_dpi_select_source_omap5(enum omap_channel channel)
 601 {
 602         int val;
 603
 604         switch (channel) {
 605         case OMAP_DSS_CHANNEL_LCD:
 606                 val = 1;
 607                 break;
 608         case OMAP_DSS_CHANNEL_LCD2:
 609                 val = 2;
 610                 break;
 611         case OMAP_DSS_CHANNEL_LCD3:
 612                 val = 3;
 613                 break;
 614         case OMAP_DSS_CHANNEL_DIGIT:
 615                 val = 0;
 616                 break;
 617         default:
 618                 return -EINVAL;
 619         }
 620
 621         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
 622
 623         return 0;
 624 }
 625
 626 int dss_dpi_select_source(enum omap_channel channel)
 627 {
 628         return dss.feat->dpi_select_source(channel);
 629 }
 630
 631 static int dss_get_clocks(void)
 632 {
 633         struct clk *clk;
 634
 635         clk = devm_clk_get(&dss.pdev->dev, "fck");
 636         if (IS_ERR(clk)) {
 637                 DSSERR("can't get clock fck\n");
 638                 return PTR_ERR(clk);
 639         }
 640
 641         dss.dss_clk = clk;
 642
 643         if (dss.feat->parent_clk_name) {
 644                 clk = clk_get(NULL, dss.feat->parent_clk_name);
 645                 if (IS_ERR(clk)) {
 646                         DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
 647                         return PTR_ERR(clk);
 648                 }
 649         } else {
 650                 clk = NULL;
 651         }
 652
 653         dss.parent_clk = clk;
 654
 655         return 0;
 656 }
 657
 658 static void dss_put_clocks(void)
 659 {
 660         if (dss.parent_clk)
 661                 clk_put(dss.parent_clk);
 662 }
 663
 664 static int dss_runtime_get(void)
 665 {
 666         int r;
 667
 668         DSSDBG("dss_runtime_get\n");
 669
 670         r = pm_runtime_get_sync(&dss.pdev->dev);
 671         WARN_ON(r < 0);
 672         return r < 0 ? r : 0;
 673 }
 674
 675 static void dss_runtime_put(void)
 676 {
 677         int r;
 678
 679         DSSDBG("dss_runtime_put\n");
 680
 681         r = pm_runtime_put_sync(&dss.pdev->dev);
 682         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 683 }
 684
 685 /* DEBUGFS */
 686 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 687 void dss_debug_dump_clocks(struct seq_file *s)
 688 {
 689         dss_dump_clocks(s);
 690         dispc_dump_clocks(s);
 691 #ifdef CONFIG_OMAP2_DSS_DSI
 692         dsi_dump_clocks(s);
 693 #endif
 694 }
 695 #endif
 696
 697 static const struct dss_features omap24xx_dss_feats __initconst = {
 698         /*
 699          * fck div max is really 16, but the divider range has gaps. The range
 700          * from 1 to 6 has no gaps, so let's use that as a max.
 701          */
 702         .fck_div_max            =       6,
 703         .dss_fck_multiplier     =       2,
 704         .parent_clk_name        =       "core_ck",
 705         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 706 };
 707
 708 static const struct dss_features omap34xx_dss_feats __initconst = {
 709         .fck_div_max            =       16,
 710         .dss_fck_multiplier     =       2,
 711         .parent_clk_name        =       "dpll4_ck",
 712         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 713 };
 714
 715 static const struct dss_features omap3630_dss_feats __initconst = {
 716         .fck_div_max            =       32,
 717         .dss_fck_multiplier     =       1,
 718         .parent_clk_name        =       "dpll4_ck",
 719         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 720 };
 721
 722 static const struct dss_features omap44xx_dss_feats __initconst = {
 723         .fck_div_max            =       32,
 724         .dss_fck_multiplier     =       1,
 725         .parent_clk_name        =       "dpll_per_x2_ck",
 726         .dpi_select_source      =       &dss_dpi_select_source_omap4,
 727 };
 728
 729 static const struct dss_features omap54xx_dss_feats __initconst = {
 730         .fck_div_max            =       64,
 731         .dss_fck_multiplier     =       1,
 732         .parent_clk_name        =       "dpll_per_x2_ck",
 733         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 734 };
 735
 736 static int __init dss_init_features(struct platform_device *pdev)
 737 {
 738         const struct dss_features *src;
 739         struct dss_features *dst;
 740
 741         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
 742         if (!dst) {
 743                 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
 744                 return -ENOMEM;
 745         }
 746
 747         switch (omapdss_get_version()) {
 748         case OMAPDSS_VER_OMAP24xx:
 749                 src = &omap24xx_dss_feats;
 750                 break;
 751
 752         case OMAPDSS_VER_OMAP34xx_ES1:
 753         case OMAPDSS_VER_OMAP34xx_ES3:
 754         case OMAPDSS_VER_AM35xx:
 755                 src = &omap34xx_dss_feats;
 756                 break;
 757
 758         case OMAPDSS_VER_OMAP3630:
 759                 src = &omap3630_dss_feats;
 760                 break;
 761
 762         case OMAPDSS_VER_OMAP4430_ES1:
 763         case OMAPDSS_VER_OMAP4430_ES2:
 764         case OMAPDSS_VER_OMAP4:
 765                 src = &omap44xx_dss_feats;
 766                 break;
 767
 768         case OMAPDSS_VER_OMAP5:
 769                 src = &omap54xx_dss_feats;
 770                 break;
 771
 772         default:
 773                 return -ENODEV;
 774         }
 775
 776         memcpy(dst, src, sizeof(*dst));
 777         dss.feat = dst;
 778
 779         return 0;
 780 }
 781
 782 /* DSS HW IP initialisation */
 783 static int __init omap_dsshw_probe(struct platform_device *pdev)
 784 {
 785         struct resource *dss_mem;
 786         u32 rev;
 787         int r;
 788
 789         dss.pdev = pdev;
 790
 791         r = dss_init_features(dss.pdev);
 792         if (r)
 793                 return r;
 794
 795         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 796         if (!dss_mem) {
 797                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 798                 return -EINVAL;
 799         }
 800
 801         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
 802                                 resource_size(dss_mem));
 803         if (!dss.base) {
 804                 DSSERR("can't ioremap DSS\n");
 805                 return -ENOMEM;
 806         }
 807
 808         r = dss_get_clocks();
 809         if (r)
 810                 return r;
 811
 812         r = dss_setup_default_clock();
 813         if (r)
 814                 goto err_setup_clocks;
 815
 816         pm_runtime_enable(&pdev->dev);
 817
 818         r = dss_runtime_get();
 819         if (r)
 820                 goto err_runtime_get;
 821
 822         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 823
 824         /* Select DPLL */
 825         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 826
 827         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
 828
 829 #ifdef CONFIG_OMAP2_DSS_VENC
 830         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 831         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 832         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 833 #endif
 834         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 835         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 836         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 837         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 838         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 839
 840         rev = dss_read_reg(DSS_REVISION);
 841         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 842                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 843
 844         dss_runtime_put();
 845
 846         dss_debugfs_create_file("dss", dss_dump_regs);
 847
 848         return 0;
 849
 850 err_runtime_get:
 851         pm_runtime_disable(&pdev->dev);
 852 err_setup_clocks:
 853         dss_put_clocks();
 854         return r;
 855 }
 856
 857 static int __exit omap_dsshw_remove(struct platform_device *pdev)
 858 {
 859         pm_runtime_disable(&pdev->dev);
 860
 861         dss_put_clocks();
 862
 863         return 0;
 864 }
 865
 866 static int dss_runtime_suspend(struct device *dev)
 867 {
 868         dss_save_context();
 869         dss_set_min_bus_tput(dev, 0);
 870         return 0;
 871 }
 872
 873 static int dss_runtime_resume(struct device *dev)
 874 {
 875         int r;
 876         /*
 877          * Set an arbitrarily high tput request to ensure OPP100.
 878          * What we should really do is to make a request to stay in OPP100,
 879          * without any tput requirements, but that is not currently possible
 880          * via the PM layer.
 881          */
 882
 883         r = dss_set_min_bus_tput(dev, 1000000000);
 884         if (r)
 885                 return r;
 886
 887         dss_restore_context();
 888         return 0;
 889 }
 890
 891 static const struct dev_pm_ops dss_pm_ops = {
 892         .runtime_suspend = dss_runtime_suspend,
 893         .runtime_resume = dss_runtime_resume,
 894 };
 895
 896 static struct platform_driver omap_dsshw_driver = {
 897         .remove         = __exit_p(omap_dsshw_remove),
 898         .driver         = {
 899                 .name   = "omapdss_dss",
 900                 .owner  = THIS_MODULE,
 901                 .pm     = &dss_pm_ops,
 902         },
 903 };
 904
 905 int __init dss_init_platform_driver(void)
 906 {
 907         return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
 908 }
 909
 910 void dss_uninit_platform_driver(void)
 911 {
 912         platform_driver_unregister(&omap_dsshw_driver);
 913 }