drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/export.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/gfp.h>
  35 #include <linux/sizes.h>
  36
  37 #include <video/omapdss.h>
  38
  39 #include "dss.h"
  40 #include "dss_features.h"
  41
  42 #define DSS_SZ_REGS                     SZ_512
  43
  44 struct dss_reg {
  45         u16 idx;
  46 };
  47
  48 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  49
  50 #define DSS_REVISION                    DSS_REG(0x0000)
  51 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  52 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  53 #define DSS_CONTROL                     DSS_REG(0x0040)
  54 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  55 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  56 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  57
  58 #define REG_GET(idx, start, end) \
  59         FLD_GET(dss_read_reg(idx), start, end)
  60
  61 #define REG_FLD_MOD(idx, val, start, end) \
  62         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  63
  64 static int dss_runtime_get(void);
  65 static void dss_runtime_put(void);
  66
  67 struct dss_features {
  68         u8 fck_div_max;
  69         u8 dss_fck_multiplier;
  70         const char *parent_clk_name;
  71         int (*dpi_select_source)(enum omap_channel channel);
  72 };
  73
  74 static struct {
  75         struct platform_device *pdev;
  76         void __iomem    *base;
  77
  78         struct clk      *parent_clk;
  79         struct clk      *dss_clk;
  80         unsigned long   dss_clk_rate;
  81
  82         unsigned long   cache_req_pck;
  83         unsigned long   cache_prate;
  84         struct dispc_clock_info cache_dispc_cinfo;
  85
  86         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  87         enum omap_dss_clk_source dispc_clk_source;
  88         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  89
  90         bool            ctx_valid;
  91         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  92
  93         const struct dss_features *feat;
  94 } dss;
  95
  96 static const char * const dss_generic_clk_source_names[] = {
  97         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  98         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  99         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
 100         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC",
 101         [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI]   = "DSI_PLL2_HSDIV_DSI",
 102 };
 103
 104 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
 105 {
 106         __raw_writel(val, dss.base + idx.idx);
 107 }
 108
 109 static inline u32 dss_read_reg(const struct dss_reg idx)
 110 {
 111         return __raw_readl(dss.base + idx.idx);
 112 }
 113
 114 #define SR(reg) \
 115         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 116 #define RR(reg) \
 117         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 118
 119 static void dss_save_context(void)
 120 {
 121         DSSDBG("dss_save_context\n");
 122
 123         SR(CONTROL);
 124
 125         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 126                         OMAP_DISPLAY_TYPE_SDI) {
 127                 SR(SDI_CONTROL);
 128                 SR(PLL_CONTROL);
 129         }
 130
 131         dss.ctx_valid = true;
 132
 133         DSSDBG("context saved\n");
 134 }
 135
 136 static void dss_restore_context(void)
 137 {
 138         DSSDBG("dss_restore_context\n");
 139
 140         if (!dss.ctx_valid)
 141                 return;
 142
 143         RR(CONTROL);
 144
 145         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 146                         OMAP_DISPLAY_TYPE_SDI) {
 147                 RR(SDI_CONTROL);
 148                 RR(PLL_CONTROL);
 149         }
 150
 151         DSSDBG("context restored\n");
 152 }
 153
 154 #undef SR
 155 #undef RR
 156
 157 void dss_sdi_init(int datapairs)
 158 {
 159         u32 l;
 160
 161         BUG_ON(datapairs > 3 || datapairs < 1);
 162
 163         l = dss_read_reg(DSS_SDI_CONTROL);
 164         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 165         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 166         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 167         dss_write_reg(DSS_SDI_CONTROL, l);
 168
 169         l = dss_read_reg(DSS_PLL_CONTROL);
 170         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 171         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 172         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 173         dss_write_reg(DSS_PLL_CONTROL, l);
 174 }
 175
 176 int dss_sdi_enable(void)
 177 {
 178         unsigned long timeout;
 179
 180         dispc_pck_free_enable(1);
 181
 182         /* Reset SDI PLL */
 183         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 184         udelay(1);      /* wait 2x PCLK */
 185
 186         /* Lock SDI PLL */
 187         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 188
 189         /* Waiting for PLL lock request to complete */
 190         timeout = jiffies + msecs_to_jiffies(500);
 191         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 192                 if (time_after_eq(jiffies, timeout)) {
 193                         DSSERR("PLL lock request timed out\n");
 194                         goto err1;
 195                 }
 196         }
 197
 198         /* Clearing PLL_GO bit */
 199         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 200
 201         /* Waiting for PLL to lock */
 202         timeout = jiffies + msecs_to_jiffies(500);
 203         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 204                 if (time_after_eq(jiffies, timeout)) {
 205                         DSSERR("PLL lock timed out\n");
 206                         goto err1;
 207                 }
 208         }
 209
 210         dispc_lcd_enable_signal(1);
 211
 212         /* Waiting for SDI reset to complete */
 213         timeout = jiffies + msecs_to_jiffies(500);
 214         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 215                 if (time_after_eq(jiffies, timeout)) {
 216                         DSSERR("SDI reset timed out\n");
 217                         goto err2;
 218                 }
 219         }
 220
 221         return 0;
 222
 223  err2:
 224         dispc_lcd_enable_signal(0);
 225  err1:
 226         /* Reset SDI PLL */
 227         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 228
 229         dispc_pck_free_enable(0);
 230
 231         return -ETIMEDOUT;
 232 }
 233
 234 void dss_sdi_disable(void)
 235 {
 236         dispc_lcd_enable_signal(0);
 237
 238         dispc_pck_free_enable(0);
 239
 240         /* Reset SDI PLL */
 241         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 242 }
 243
 244 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 245 {
 246         return dss_generic_clk_source_names[clk_src];
 247 }
 248
 249 void dss_dump_clocks(struct seq_file *s)
 250 {
 251         const char *fclk_name, *fclk_real_name;
 252         unsigned long fclk_rate;
 253
 254         if (dss_runtime_get())
 255                 return;
 256
 257         seq_printf(s, "- DSS -\n");
 258
 259         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 260         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 261         fclk_rate = clk_get_rate(dss.dss_clk);
 262
 263         seq_printf(s, "%s (%s) = %lu\n",
 264                         fclk_name, fclk_real_name,
 265                         fclk_rate);
 266
 267         dss_runtime_put();
 268 }
 269
 270 static void dss_dump_regs(struct seq_file *s)
 271 {
 272 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 273
 274         if (dss_runtime_get())
 275                 return;
 276
 277         DUMPREG(DSS_REVISION);
 278         DUMPREG(DSS_SYSCONFIG);
 279         DUMPREG(DSS_SYSSTATUS);
 280         DUMPREG(DSS_CONTROL);
 281
 282         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 283                         OMAP_DISPLAY_TYPE_SDI) {
 284                 DUMPREG(DSS_SDI_CONTROL);
 285                 DUMPREG(DSS_PLL_CONTROL);
 286                 DUMPREG(DSS_SDI_STATUS);
 287         }
 288
 289         dss_runtime_put();
 290 #undef DUMPREG
 291 }
 292
 293 static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 294 {
 295         struct platform_device *dsidev;
 296         int b;
 297         u8 start, end;
 298
 299         switch (clk_src) {
 300         case OMAP_DSS_CLK_SRC_FCK:
 301                 b = 0;
 302                 break;
 303         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 304                 b = 1;
 305                 dsidev = dsi_get_dsidev_from_id(0);
 306                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 307                 break;
 308         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 309                 b = 2;
 310                 dsidev = dsi_get_dsidev_from_id(1);
 311                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 312                 break;
 313         default:
 314                 BUG();
 315                 return;
 316         }
 317
 318         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 319
 320         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 321
 322         dss.dispc_clk_source = clk_src;
 323 }
 324
 325 void dss_select_dsi_clk_source(int dsi_module,
 326                 enum omap_dss_clk_source clk_src)
 327 {
 328         struct platform_device *dsidev;
 329         int b, pos;
 330
 331         switch (clk_src) {
 332         case OMAP_DSS_CLK_SRC_FCK:
 333                 b = 0;
 334                 break;
 335         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 336                 BUG_ON(dsi_module != 0);
 337                 b = 1;
 338                 dsidev = dsi_get_dsidev_from_id(0);
 339                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 340                 break;
 341         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 342                 BUG_ON(dsi_module != 1);
 343                 b = 1;
 344                 dsidev = dsi_get_dsidev_from_id(1);
 345                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 346                 break;
 347         default:
 348                 BUG();
 349                 return;
 350         }
 351
 352         pos = dsi_module == 0 ? 1 : 10;
 353         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 354
 355         dss.dsi_clk_source[dsi_module] = clk_src;
 356 }
 357
 358 void dss_select_lcd_clk_source(enum omap_channel channel,
 359                 enum omap_dss_clk_source clk_src)
 360 {
 361         struct platform_device *dsidev;
 362         int b, ix, pos;
 363
 364         if (!dss_has_feature(FEAT_LCD_CLK_SRC)) {
 365                 dss_select_dispc_clk_source(clk_src);
 366                 return;
 367         }
 368
 369         switch (clk_src) {
 370         case OMAP_DSS_CLK_SRC_FCK:
 371                 b = 0;
 372                 break;
 373         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 374                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 375                 b = 1;
 376                 dsidev = dsi_get_dsidev_from_id(0);
 377                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 378                 break;
 379         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 380                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 &&
 381                        channel != OMAP_DSS_CHANNEL_LCD3);
 382                 b = 1;
 383                 dsidev = dsi_get_dsidev_from_id(1);
 384                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 385                 break;
 386         default:
 387                 BUG();
 388                 return;
 389         }
 390
 391         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 392              (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19);
 393         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 394
 395         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 396             (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 397         dss.lcd_clk_source[ix] = clk_src;
 398 }
 399
 400 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 401 {
 402         return dss.dispc_clk_source;
 403 }
 404
 405 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 406 {
 407         return dss.dsi_clk_source[dsi_module];
 408 }
 409
 410 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 411 {
 412         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 413                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 :
 414                         (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2);
 415                 return dss.lcd_clk_source[ix];
 416         } else {
 417                 /* LCD_CLK source is the same as DISPC_FCLK source for
 418                  * OMAP2 and OMAP3 */
 419                 return dss.dispc_clk_source;
 420         }
 421 }
 422
 423 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
 424                 dss_div_calc_func func, void *data)
 425 {
 426         int fckd, fckd_start, fckd_stop;
 427         unsigned long fck;
 428         unsigned long fck_hw_max;
 429         unsigned long fckd_hw_max;
 430         unsigned long prate;
 431         unsigned m;
 432
 433         fck_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 434
 435         if (dss.parent_clk == NULL) {
 436                 unsigned pckd;
 437
 438                 pckd = fck_hw_max / pck;
 439
 440                 fck = pck * pckd;
 441
 442                 fck = clk_round_rate(dss.dss_clk, fck);
 443
 444                 return func(fck, data);
 445         }
 446
 447         fckd_hw_max = dss.feat->fck_div_max;
 448
 449         m = dss.feat->dss_fck_multiplier;
 450         prate = clk_get_rate(dss.parent_clk);
 451
 452         fck_min = fck_min ? fck_min : 1;
 453
 454         fckd_start = min(prate * m / fck_min, fckd_hw_max);
 455         fckd_stop = max(DIV_ROUND_UP(prate * m, fck_hw_max), 1ul);
 456
 457         for (fckd = fckd_start; fckd >= fckd_stop; --fckd) {
 458                 fck = prate / fckd * m;
 459
 460                 if (func(fck, data))
 461                         return true;
 462         }
 463
 464         return false;
 465 }
 466
 467 int dss_set_fck_rate(unsigned long rate)
 468 {
 469         int r;
 470
 471         DSSDBG("set fck to %lu\n", rate);
 472
 473         r = clk_set_rate(dss.dss_clk, rate);
 474         if (r)
 475                 return r;
 476
 477         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 478
 479         WARN_ONCE(dss.dss_clk_rate != rate,
 480                         "clk rate mismatch: %lu != %lu", dss.dss_clk_rate,
 481                         rate);
 482
 483         return 0;
 484 }
 485
 486 unsigned long dss_get_dispc_clk_rate(void)
 487 {
 488         return dss.dss_clk_rate;
 489 }
 490
 491 static int dss_setup_default_clock(void)
 492 {
 493         unsigned long max_dss_fck, prate;
 494         unsigned long fck;
 495         unsigned fck_div;
 496         int r;
 497
 498         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 499
 500         if (dss.parent_clk == NULL) {
 501                 fck = clk_round_rate(dss.dss_clk, max_dss_fck);
 502         } else {
 503                 prate = clk_get_rate(dss.parent_clk);
 504
 505                 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier,
 506                                 max_dss_fck);
 507                 fck = prate / fck_div * dss.feat->dss_fck_multiplier;
 508         }
 509
 510         r = dss_set_fck_rate(fck);
 511         if (r)
 512                 return r;
 513
 514         return 0;
 515 }
 516
 517 void dss_set_venc_output(enum omap_dss_venc_type type)
 518 {
 519         int l = 0;
 520
 521         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 522                 l = 0;
 523         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 524                 l = 1;
 525         else
 526                 BUG();
 527
 528         /* venc out selection. 0 = comp, 1 = svideo */
 529         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 530 }
 531
 532 void dss_set_dac_pwrdn_bgz(bool enable)
 533 {
 534         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 535 }
 536
 537 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
 538 {
 539         enum omap_display_type dp;
 540         dp = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 541
 542         /* Complain about invalid selections */
 543         WARN_ON((src == DSS_VENC_TV_CLK) && !(dp & OMAP_DISPLAY_TYPE_VENC));
 544         WARN_ON((src == DSS_HDMI_M_PCLK) && !(dp & OMAP_DISPLAY_TYPE_HDMI));
 545
 546         /* Select only if we have options */
 547         if ((dp & OMAP_DISPLAY_TYPE_VENC) && (dp & OMAP_DISPLAY_TYPE_HDMI))
 548                 REG_FLD_MOD(DSS_CONTROL, src, 15, 15);  /* VENC_HDMI_SWITCH */
 549 }
 550
 551 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 552 {
 553         enum omap_display_type displays;
 554
 555         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 556         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 557                 return DSS_VENC_TV_CLK;
 558
 559         if ((displays & OMAP_DISPLAY_TYPE_VENC) == 0)
 560                 return DSS_HDMI_M_PCLK;
 561
 562         return REG_GET(DSS_CONTROL, 15, 15);
 563 }
 564
 565 static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
 566 {
 567         if (channel != OMAP_DSS_CHANNEL_LCD)
 568                 return -EINVAL;
 569
 570         return 0;
 571 }
 572
 573 static int dss_dpi_select_source_omap4(enum omap_channel channel)
 574 {
 575         int val;
 576
 577         switch (channel) {
 578         case OMAP_DSS_CHANNEL_LCD2:
 579                 val = 0;
 580                 break;
 581         case OMAP_DSS_CHANNEL_DIGIT:
 582                 val = 1;
 583                 break;
 584         default:
 585                 return -EINVAL;
 586         }
 587
 588         REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
 589
 590         return 0;
 591 }
 592
 593 static int dss_dpi_select_source_omap5(enum omap_channel channel)
 594 {
 595         int val;
 596
 597         switch (channel) {
 598         case OMAP_DSS_CHANNEL_LCD:
 599                 val = 1;
 600                 break;
 601         case OMAP_DSS_CHANNEL_LCD2:
 602                 val = 2;
 603                 break;
 604         case OMAP_DSS_CHANNEL_LCD3:
 605                 val = 3;
 606                 break;
 607         case OMAP_DSS_CHANNEL_DIGIT:
 608                 val = 0;
 609                 break;
 610         default:
 611                 return -EINVAL;
 612         }
 613
 614         REG_FLD_MOD(DSS_CONTROL, val, 17, 16);
 615
 616         return 0;
 617 }
 618
 619 int dss_dpi_select_source(enum omap_channel channel)
 620 {
 621         return dss.feat->dpi_select_source(channel);
 622 }
 623
 624 static int dss_get_clocks(void)
 625 {
 626         struct clk *clk;
 627
 628         clk = devm_clk_get(&dss.pdev->dev, "fck");
 629         if (IS_ERR(clk)) {
 630                 DSSERR("can't get clock fck\n");
 631                 return PTR_ERR(clk);
 632         }
 633
 634         dss.dss_clk = clk;
 635
 636         if (dss.feat->parent_clk_name) {
 637                 clk = clk_get(NULL, dss.feat->parent_clk_name);
 638                 if (IS_ERR(clk)) {
 639                         DSSERR("Failed to get %s\n", dss.feat->parent_clk_name);
 640                         return PTR_ERR(clk);
 641                 }
 642         } else {
 643                 clk = NULL;
 644         }
 645
 646         dss.parent_clk = clk;
 647
 648         return 0;
 649 }
 650
 651 static void dss_put_clocks(void)
 652 {
 653         if (dss.parent_clk)
 654                 clk_put(dss.parent_clk);
 655 }
 656
 657 static int dss_runtime_get(void)
 658 {
 659         int r;
 660
 661         DSSDBG("dss_runtime_get\n");
 662
 663         r = pm_runtime_get_sync(&dss.pdev->dev);
 664         WARN_ON(r < 0);
 665         return r < 0 ? r : 0;
 666 }
 667
 668 static void dss_runtime_put(void)
 669 {
 670         int r;
 671
 672         DSSDBG("dss_runtime_put\n");
 673
 674         r = pm_runtime_put_sync(&dss.pdev->dev);
 675         WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
 676 }
 677
 678 /* DEBUGFS */
 679 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
 680 void dss_debug_dump_clocks(struct seq_file *s)
 681 {
 682         dss_dump_clocks(s);
 683         dispc_dump_clocks(s);
 684 #ifdef CONFIG_OMAP2_DSS_DSI
 685         dsi_dump_clocks(s);
 686 #endif
 687 }
 688 #endif
 689
 690 static const struct dss_features omap24xx_dss_feats __initconst = {
 691         /*
 692          * fck div max is really 16, but the divider range has gaps. The range
 693          * from 1 to 6 has no gaps, so let's use that as a max.
 694          */
 695         .fck_div_max            =       6,
 696         .dss_fck_multiplier     =       2,
 697         .parent_clk_name        =       "core_ck",
 698         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 699 };
 700
 701 static const struct dss_features omap34xx_dss_feats __initconst = {
 702         .fck_div_max            =       16,
 703         .dss_fck_multiplier     =       2,
 704         .parent_clk_name        =       "dpll4_ck",
 705         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 706 };
 707
 708 static const struct dss_features omap3630_dss_feats __initconst = {
 709         .fck_div_max            =       32,
 710         .dss_fck_multiplier     =       1,
 711         .parent_clk_name        =       "dpll4_ck",
 712         .dpi_select_source      =       &dss_dpi_select_source_omap2_omap3,
 713 };
 714
 715 static const struct dss_features omap44xx_dss_feats __initconst = {
 716         .fck_div_max            =       32,
 717         .dss_fck_multiplier     =       1,
 718         .parent_clk_name        =       "dpll_per_x2_ck",
 719         .dpi_select_source      =       &dss_dpi_select_source_omap4,
 720 };
 721
 722 static const struct dss_features omap54xx_dss_feats __initconst = {
 723         .fck_div_max            =       64,
 724         .dss_fck_multiplier     =       1,
 725         .parent_clk_name        =       "dpll_per_x2_ck",
 726         .dpi_select_source      =       &dss_dpi_select_source_omap5,
 727 };
 728
 729 static int __init dss_init_features(struct platform_device *pdev)
 730 {
 731         const struct dss_features *src;
 732         struct dss_features *dst;
 733
 734         dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
 735         if (!dst) {
 736                 dev_err(&pdev->dev, "Failed to allocate local DSS Features\n");
 737                 return -ENOMEM;
 738         }
 739
 740         switch (omapdss_get_version()) {
 741         case OMAPDSS_VER_OMAP24xx:
 742                 src = &omap24xx_dss_feats;
 743                 break;
 744
 745         case OMAPDSS_VER_OMAP34xx_ES1:
 746         case OMAPDSS_VER_OMAP34xx_ES3:
 747         case OMAPDSS_VER_AM35xx:
 748                 src = &omap34xx_dss_feats;
 749                 break;
 750
 751         case OMAPDSS_VER_OMAP3630:
 752                 src = &omap3630_dss_feats;
 753                 break;
 754
 755         case OMAPDSS_VER_OMAP4430_ES1:
 756         case OMAPDSS_VER_OMAP4430_ES2:
 757         case OMAPDSS_VER_OMAP4:
 758                 src = &omap44xx_dss_feats;
 759                 break;
 760
 761         case OMAPDSS_VER_OMAP5:
 762                 src = &omap54xx_dss_feats;
 763                 break;
 764
 765         default:
 766                 return -ENODEV;
 767         }
 768
 769         memcpy(dst, src, sizeof(*dst));
 770         dss.feat = dst;
 771
 772         return 0;
 773 }
 774
 775 /* DSS HW IP initialisation */
 776 static int __init omap_dsshw_probe(struct platform_device *pdev)
 777 {
 778         struct resource *dss_mem;
 779         u32 rev;
 780         int r;
 781
 782         dss.pdev = pdev;
 783
 784         r = dss_init_features(dss.pdev);
 785         if (r)
 786                 return r;
 787
 788         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 789         if (!dss_mem) {
 790                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 791                 return -EINVAL;
 792         }
 793
 794         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
 795                                 resource_size(dss_mem));
 796         if (!dss.base) {
 797                 DSSERR("can't ioremap DSS\n");
 798                 return -ENOMEM;
 799         }
 800
 801         r = dss_get_clocks();
 802         if (r)
 803                 return r;
 804
 805         r = dss_setup_default_clock();
 806         if (r)
 807                 goto err_setup_clocks;
 808
 809         pm_runtime_enable(&pdev->dev);
 810
 811         r = dss_runtime_get();
 812         if (r)
 813                 goto err_runtime_get;
 814
 815         dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
 816
 817         /* Select DPLL */
 818         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 819
 820         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
 821
 822 #ifdef CONFIG_OMAP2_DSS_VENC
 823         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 824         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 825         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 826 #endif
 827         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 828         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 829         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 830         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 831         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 832
 833         rev = dss_read_reg(DSS_REVISION);
 834         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 835                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 836
 837         dss_runtime_put();
 838
 839         dss_debugfs_create_file("dss", dss_dump_regs);
 840
 841         return 0;
 842
 843 err_runtime_get:
 844         pm_runtime_disable(&pdev->dev);
 845 err_setup_clocks:
 846         dss_put_clocks();
 847         return r;
 848 }
 849
 850 static int __exit omap_dsshw_remove(struct platform_device *pdev)
 851 {
 852         pm_runtime_disable(&pdev->dev);
 853
 854         dss_put_clocks();
 855
 856         return 0;
 857 }
 858
 859 static int dss_runtime_suspend(struct device *dev)
 860 {
 861         dss_save_context();
 862         dss_set_min_bus_tput(dev, 0);
 863         return 0;
 864 }
 865
 866 static int dss_runtime_resume(struct device *dev)
 867 {
 868         int r;
 869         /*
 870          * Set an arbitrarily high tput request to ensure OPP100.
 871          * What we should really do is to make a request to stay in OPP100,
 872          * without any tput requirements, but that is not currently possible
 873          * via the PM layer.
 874          */
 875
 876         r = dss_set_min_bus_tput(dev, 1000000000);
 877         if (r)
 878                 return r;
 879
 880         dss_restore_context();
 881         return 0;
 882 }
 883
 884 static const struct dev_pm_ops dss_pm_ops = {
 885         .runtime_suspend = dss_runtime_suspend,
 886         .runtime_resume = dss_runtime_resume,
 887 };
 888
 889 static struct platform_driver omap_dsshw_driver = {
 890         .remove         = __exit_p(omap_dsshw_remove),
 891         .driver         = {
 892                 .name   = "omapdss_dss",
 893                 .owner  = THIS_MODULE,
 894                 .pm     = &dss_pm_ops,
 895         },
 896 };
 897
 898 int __init dss_init_platform_driver(void)
 899 {
 900         return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
 901 }
 902
 903 void dss_uninit_platform_driver(void)
 904 {
 905         platform_driver_unregister(&omap_dsshw_driver);
 906 }