2 * linux/drivers/video/omap2/dss/sdi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "SDI"
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/export.h>
27 #include <linux/platform_device.h>
28 #include <linux/string.h>
30 #include <video/omapdss.h>
35 struct regulator *vdds_sdi_reg;
37 struct dss_lcd_mgr_config mgr_config;
38 struct omap_video_timings timings;
41 struct omap_dss_output output;
44 struct sdi_clk_calc_ctx {
45 unsigned long pck_min, pck_max;
47 struct dss_clock_info dss_cinfo;
48 struct dispc_clock_info dispc_cinfo;
51 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
52 unsigned long pck, void *data)
54 struct sdi_clk_calc_ctx *ctx = data;
56 ctx->dispc_cinfo.lck_div = lckd;
57 ctx->dispc_cinfo.pck_div = pckd;
58 ctx->dispc_cinfo.lck = lck;
59 ctx->dispc_cinfo.pck = pck;
64 static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
66 struct sdi_clk_calc_ctx *ctx = data;
68 ctx->dss_cinfo.fck = fck;
69 ctx->dss_cinfo.fck_div = fckd;
71 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
72 dpi_calc_dispc_cb, ctx);
75 static int sdi_calc_clock_div(unsigned long pclk,
76 struct dss_clock_info *dss_cinfo,
77 struct dispc_clock_info *dispc_cinfo)
80 struct sdi_clk_calc_ctx ctx;
83 * DSS fclk gives us very few possibilities, so finding a good pixel
84 * clock may not be possible. We try multiple times to find the clock,
85 * each time widening the pixel clock range we look for, up to
89 for (i = 0; i < 10; ++i) {
92 memset(&ctx, 0, sizeof(ctx));
93 if (pclk > 1000 * i * i * i)
94 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
97 ctx.pck_max = pclk + 1000 * i * i * i;
99 ok = dss_div_calc(ctx.pck_min, dpi_calc_dss_cb, &ctx);
101 *dss_cinfo = ctx.dss_cinfo;
102 *dispc_cinfo = ctx.dispc_cinfo;
110 static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
112 struct omap_overlay_manager *mgr = dssdev->output->manager;
114 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
116 sdi.mgr_config.stallmode = false;
117 sdi.mgr_config.fifohandcheck = false;
119 sdi.mgr_config.video_port_width = 24;
120 sdi.mgr_config.lcden_sig_polarity = 1;
122 dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
125 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
127 struct omap_dss_output *out = dssdev->output;
128 struct omap_video_timings *t = &sdi.timings;
129 struct dss_clock_info dss_cinfo;
130 struct dispc_clock_info dispc_cinfo;
134 if (out == NULL || out->manager == NULL) {
135 DSSERR("failed to enable display: no output/manager\n");
139 r = omap_dss_start_device(dssdev);
141 DSSERR("failed to start device\n");
145 r = regulator_enable(sdi.vdds_sdi_reg);
149 r = dispc_runtime_get();
154 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
155 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
157 r = sdi_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
159 goto err_calc_clock_div;
161 sdi.mgr_config.clock_info = dispc_cinfo;
163 pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
165 if (pck != t->pixel_clock) {
166 DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
168 t->pixel_clock, pck);
170 t->pixel_clock = pck;
174 dss_mgr_set_timings(out->manager, t);
176 r = dss_set_clock_div(&dss_cinfo);
178 goto err_set_dss_clock_div;
180 sdi_config_lcd_manager(dssdev);
183 * LCLK and PCLK divisors are located in shadow registers, and we
184 * normally write them to DISPC registers when enabling the output.
185 * However, SDI uses pck-free as source clock for its PLL, and pck-free
186 * is affected by the divisors. And as we need the PLL before enabling
187 * the output, we need to write the divisors early.
189 * It seems just writing to the DISPC register is enough, and we don't
190 * need to care about the shadow register mechanism for pck-free. The
191 * exact reason for this is unknown.
193 dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
195 dss_sdi_init(sdi.datapairs);
196 r = dss_sdi_enable();
201 r = dss_mgr_enable(out->manager);
210 err_set_dss_clock_div:
214 regulator_disable(sdi.vdds_sdi_reg);
216 omap_dss_stop_device(dssdev);
220 EXPORT_SYMBOL(omapdss_sdi_display_enable);
222 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
224 struct omap_overlay_manager *mgr = dssdev->output->manager;
226 dss_mgr_disable(mgr);
232 regulator_disable(sdi.vdds_sdi_reg);
234 omap_dss_stop_device(dssdev);
236 EXPORT_SYMBOL(omapdss_sdi_display_disable);
238 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
239 struct omap_video_timings *timings)
241 sdi.timings = *timings;
243 EXPORT_SYMBOL(omapdss_sdi_set_timings);
245 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
247 sdi.datapairs = datapairs;
249 EXPORT_SYMBOL(omapdss_sdi_set_datapairs);
251 static int sdi_init_display(struct omap_dss_device *dssdev)
253 DSSDBG("SDI init\n");
255 if (sdi.vdds_sdi_reg == NULL) {
256 struct regulator *vdds_sdi;
258 vdds_sdi = dss_get_vdds_sdi();
260 if (IS_ERR(vdds_sdi)) {
261 DSSERR("can't get VDDS_SDI regulator\n");
262 return PTR_ERR(vdds_sdi);
265 sdi.vdds_sdi_reg = vdds_sdi;
271 static struct omap_dss_device *sdi_find_dssdev(struct platform_device *pdev)
273 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
274 const char *def_disp_name = omapdss_get_default_display_name();
275 struct omap_dss_device *def_dssdev;
280 for (i = 0; i < pdata->num_devices; ++i) {
281 struct omap_dss_device *dssdev = pdata->devices[i];
283 if (dssdev->type != OMAP_DISPLAY_TYPE_SDI)
286 if (def_dssdev == NULL)
289 if (def_disp_name != NULL &&
290 strcmp(dssdev->name, def_disp_name) == 0) {
299 static int sdi_probe_pdata(struct platform_device *sdidev)
301 struct omap_dss_device *plat_dssdev;
302 struct omap_dss_device *dssdev;
305 plat_dssdev = sdi_find_dssdev(sdidev);
310 dssdev = dss_alloc_and_init_device(&sdidev->dev);
314 dss_copy_device_pdata(dssdev, plat_dssdev);
316 r = sdi_init_display(dssdev);
318 DSSERR("device %s init failed: %d\n", dssdev->name, r);
319 dss_put_device(dssdev);
323 r = omapdss_output_set_device(&sdi.output, dssdev);
325 DSSERR("failed to connect output to new device: %s\n",
327 dss_put_device(dssdev);
331 r = dss_add_device(dssdev);
333 DSSERR("device %s register failed: %d\n", dssdev->name, r);
334 omapdss_output_unset_device(&sdi.output);
335 dss_put_device(dssdev);
342 static void sdi_init_output(struct platform_device *pdev)
344 struct omap_dss_output *out = &sdi.output;
347 out->id = OMAP_DSS_OUTPUT_SDI;
348 out->type = OMAP_DISPLAY_TYPE_SDI;
350 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
352 dss_register_output(out);
355 static void __exit sdi_uninit_output(struct platform_device *pdev)
357 struct omap_dss_output *out = &sdi.output;
359 dss_unregister_output(out);
362 static int omap_sdi_probe(struct platform_device *pdev)
366 sdi_init_output(pdev);
368 r = sdi_probe_pdata(pdev);
370 sdi_uninit_output(pdev);
377 static int __exit omap_sdi_remove(struct platform_device *pdev)
379 dss_unregister_child_devices(&pdev->dev);
381 sdi_uninit_output(pdev);
386 static struct platform_driver omap_sdi_driver = {
387 .probe = omap_sdi_probe,
388 .remove = __exit_p(omap_sdi_remove),
390 .name = "omapdss_sdi",
391 .owner = THIS_MODULE,
395 int __init sdi_init_platform_driver(void)
397 return platform_driver_register(&omap_sdi_driver);
400 void __exit sdi_uninit_platform_driver(void)
402 platform_driver_unregister(&omap_sdi_driver);