drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c

   1 /*
   2  * ti_hdmi_4xxx_ip.c
   3  *
   4  * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
   6  * Authors: Yong Zhi
   7  *      Mythri pk <mythripk@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along with
  19  * this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/err.h>
  25 #include <linux/io.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mutex.h>
  28 #include <linux/delay.h>
  29 #include <linux/string.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/gpio.h>
  32 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
  33 #include <sound/asound.h>
  34 #include <sound/asoundef.h>
  35 #endif
  36
  37 #include "ti_hdmi_4xxx_ip.h"
  38 #include "dss.h"
  39 #include "dss_features.h"
  40
  41 static inline void hdmi_write_reg(void __iomem *base_addr,
  42                                 const u16 idx, u32 val)
  43 {
  44         __raw_writel(val, base_addr + idx);
  45 }
  46
  47 static inline u32 hdmi_read_reg(void __iomem *base_addr,
  48                                 const u16 idx)
  49 {
  50         return __raw_readl(base_addr + idx);
  51 }
  52
  53 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
  54 {
  55         return ip_data->base_wp;
  56 }
  57
  58 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
  59 {
  60         return ip_data->base_wp + ip_data->phy_offset;
  61 }
  62
  63 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
  64 {
  65         return ip_data->base_wp + ip_data->pll_offset;
  66 }
  67
  68 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
  69 {
  70         return ip_data->base_wp + ip_data->core_av_offset;
  71 }
  72
  73 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
  74 {
  75         return ip_data->base_wp + ip_data->core_sys_offset;
  76 }
  77
  78 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
  79                                 const u16 idx,
  80                                 int b2, int b1, u32 val)
  81 {
  82         u32 t = 0;
  83         while (val != REG_GET(base_addr, idx, b2, b1)) {
  84                 udelay(1);
  85                 if (t++ > 10000)
  86                         return !val;
  87         }
  88         return val;
  89 }
  90
  91 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
  92 {
  93         u32 r;
  94         void __iomem *pll_base = hdmi_pll_base(ip_data);
  95         struct hdmi_pll_info *fmt = &ip_data->pll_data;
  96
  97         /* PLL start always use manual mode */
  98         REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
  99
 100         r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
 101         r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
 102         r = FLD_MOD(r, fmt->regn - 1, 8, 1);  /* CFG1_PLL_REGN */
 103
 104         hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
 105
 106         r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
 107
 108         r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
 109         r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
 110         r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
 111         r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
 112
 113         if (fmt->dcofreq) {
 114                 /* divider programming for frequency beyond 1000Mhz */
 115                 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
 116                 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
 117         } else {
 118                 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
 119         }
 120
 121         hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
 122
 123         r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
 124         r = FLD_MOD(r, fmt->regm2, 24, 18);
 125         r = FLD_MOD(r, fmt->regmf, 17, 0);
 126
 127         hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
 128
 129         /* go now */
 130         REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
 131
 132         /* wait for bit change */
 133         if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
 134                                                         0, 0, 1) != 1) {
 135                 pr_err("PLL GO bit not set\n");
 136                 return -ETIMEDOUT;
 137         }
 138
 139         /* Wait till the lock bit is set in PLL status */
 140         if (hdmi_wait_for_bit_change(pll_base,
 141                                 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
 142                 pr_err("cannot lock PLL\n");
 143                 pr_err("CFG1 0x%x\n",
 144                         hdmi_read_reg(pll_base, PLLCTRL_CFG1));
 145                 pr_err("CFG2 0x%x\n",
 146                         hdmi_read_reg(pll_base, PLLCTRL_CFG2));
 147                 pr_err("CFG4 0x%x\n",
 148                         hdmi_read_reg(pll_base, PLLCTRL_CFG4));
 149                 return -ETIMEDOUT;
 150         }
 151
 152         pr_debug("PLL locked!\n");
 153
 154         return 0;
 155 }
 156
 157 /* PHY_PWR_CMD */
 158 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
 159 {
 160         /* Command for power control of HDMI PHY */
 161         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
 162
 163         /* Status of the power control of HDMI PHY */
 164         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
 165                                 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
 166                 pr_err("Failed to set PHY power mode to %d\n", val);
 167                 return -ETIMEDOUT;
 168         }
 169
 170         return 0;
 171 }
 172
 173 /* PLL_PWR_CMD */
 174 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
 175 {
 176         /* Command for power control of HDMI PLL */
 177         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
 178
 179         /* wait till PHY_PWR_STATUS is set */
 180         if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
 181                                                 1, 0, val) != val) {
 182                 pr_err("Failed to set PLL_PWR_STATUS\n");
 183                 return -ETIMEDOUT;
 184         }
 185
 186         return 0;
 187 }
 188
 189 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
 190 {
 191         /* SYSRESET  controlled by power FSM */
 192         REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
 193
 194         /* READ 0x0 reset is in progress */
 195         if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
 196                                 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
 197                 pr_err("Failed to sysreset PLL\n");
 198                 return -ETIMEDOUT;
 199         }
 200
 201         return 0;
 202 }
 203
 204 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
 205 {
 206         u16 r = 0;
 207
 208         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 209         if (r)
 210                 return r;
 211
 212         r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
 213         if (r)
 214                 return r;
 215
 216         r = hdmi_pll_reset(ip_data);
 217         if (r)
 218                 return r;
 219
 220         r = hdmi_pll_init(ip_data);
 221         if (r)
 222                 return r;
 223
 224         return 0;
 225 }
 226
 227 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
 228 {
 229         hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
 230 }
 231
 232 static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
 233 {
 234         unsigned long flags;
 235         bool hpd;
 236         int r;
 237         /* this should be in ti_hdmi_4xxx_ip private data */
 238         static DEFINE_SPINLOCK(phy_tx_lock);
 239
 240         spin_lock_irqsave(&phy_tx_lock, flags);
 241
 242         hpd = gpio_get_value(ip_data->hpd_gpio);
 243
 244         if (hpd == ip_data->phy_tx_enabled) {
 245                 spin_unlock_irqrestore(&phy_tx_lock, flags);
 246                 return 0;
 247         }
 248
 249         if (hpd)
 250                 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
 251         else
 252                 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
 253
 254         if (r) {
 255                 DSSERR("Failed to %s PHY TX power\n",
 256                                 hpd ? "enable" : "disable");
 257                 goto err;
 258         }
 259
 260         ip_data->phy_tx_enabled = hpd;
 261 err:
 262         spin_unlock_irqrestore(&phy_tx_lock, flags);
 263         return r;
 264 }
 265
 266 static irqreturn_t hpd_irq_handler(int irq, void *data)
 267 {
 268         struct hdmi_ip_data *ip_data = data;
 269
 270         hdmi_check_hpd_state(ip_data);
 271
 272         return IRQ_HANDLED;
 273 }
 274
 275 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
 276 {
 277         u16 r = 0;
 278         void __iomem *phy_base = hdmi_phy_base(ip_data);
 279
 280         r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
 281         if (r)
 282                 return r;
 283
 284         /*
 285          * Read address 0 in order to get the SCP reset done completed
 286          * Dummy access performed to make sure reset is done
 287          */
 288         hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
 289
 290         /*
 291          * Write to phy address 0 to configure the clock
 292          * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
 293          */
 294         REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
 295
 296         /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
 297         hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
 298
 299         /* Setup max LDO voltage */
 300         REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
 301
 302         /* Write to phy address 3 to change the polarity control */
 303         REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
 304
 305         r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio),
 306                                  NULL, hpd_irq_handler,
 307                                  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
 308                                  IRQF_ONESHOT, "hpd", ip_data);
 309         if (r) {
 310                 DSSERR("HPD IRQ request failed\n");
 311                 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 312                 return r;
 313         }
 314
 315         r = hdmi_check_hpd_state(ip_data);
 316         if (r) {
 317                 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
 318                 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 319                 return r;
 320         }
 321
 322         return 0;
 323 }
 324
 325 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
 326 {
 327         free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
 328
 329         hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
 330         ip_data->phy_tx_enabled = false;
 331 }
 332
 333 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
 334 {
 335         void __iomem *base = hdmi_core_sys_base(ip_data);
 336
 337         /* Turn on CLK for DDC */
 338         REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
 339
 340         /* IN_PROG */
 341         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
 342                 /* Abort transaction */
 343                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
 344                 /* IN_PROG */
 345                 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 346                                         4, 4, 0) != 0) {
 347                         DSSERR("Timeout aborting DDC transaction\n");
 348                         return -ETIMEDOUT;
 349                 }
 350         }
 351
 352         /* Clk SCL Devices */
 353         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
 354
 355         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 356         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 357                                 4, 4, 0) != 0) {
 358                 DSSERR("Timeout starting SCL clock\n");
 359                 return -ETIMEDOUT;
 360         }
 361
 362         /* Clear FIFO */
 363         REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
 364
 365         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 366         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 367                                 4, 4, 0) != 0) {
 368                 DSSERR("Timeout clearing DDC fifo\n");
 369                 return -ETIMEDOUT;
 370         }
 371
 372         return 0;
 373 }
 374
 375 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
 376                 u8 *pedid, int ext)
 377 {
 378         void __iomem *base = hdmi_core_sys_base(ip_data);
 379         u32 i;
 380         char checksum;
 381         u32 offset = 0;
 382
 383         /* HDMI_CORE_DDC_STATUS_IN_PROG */
 384         if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
 385                                 4, 4, 0) != 0) {
 386                 DSSERR("Timeout waiting DDC to be ready\n");
 387                 return -ETIMEDOUT;
 388         }
 389
 390         if (ext % 2 != 0)
 391                 offset = 0x80;
 392
 393         /* Load Segment Address Register */
 394         REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
 395
 396         /* Load Slave Address Register */
 397         REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
 398
 399         /* Load Offset Address Register */
 400         REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
 401
 402         /* Load Byte Count */
 403         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
 404         REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
 405
 406         /* Set DDC_CMD */
 407         if (ext)
 408                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
 409         else
 410                 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
 411
 412         /* HDMI_CORE_DDC_STATUS_BUS_LOW */
 413         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
 414                 pr_err("I2C Bus Low?\n");
 415                 return -EIO;
 416         }
 417         /* HDMI_CORE_DDC_STATUS_NO_ACK */
 418         if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
 419                 pr_err("I2C No Ack\n");
 420                 return -EIO;
 421         }
 422
 423         for (i = 0; i < 0x80; ++i) {
 424                 int t;
 425
 426                 /* IN_PROG */
 427                 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
 428                         DSSERR("operation stopped when reading edid\n");
 429                         return -EIO;
 430                 }
 431
 432                 t = 0;
 433                 /* FIFO_EMPTY */
 434                 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
 435                         if (t++ > 10000) {
 436                                 DSSERR("timeout reading edid\n");
 437                                 return -ETIMEDOUT;
 438                         }
 439                         udelay(1);
 440                 }
 441
 442                 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
 443         }
 444
 445         checksum = 0;
 446         for (i = 0; i < 0x80; ++i)
 447                 checksum += pedid[i];
 448
 449         if (checksum != 0) {
 450                 pr_err("E-EDID checksum failed!!\n");
 451                 return -EIO;
 452         }
 453
 454         return 0;
 455 }
 456
 457 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
 458                                 u8 *edid, int len)
 459 {
 460         int r, l;
 461
 462         if (len < 128)
 463                 return -EINVAL;
 464
 465         r = hdmi_core_ddc_init(ip_data);
 466         if (r)
 467                 return r;
 468
 469         r = hdmi_core_ddc_edid(ip_data, edid, 0);
 470         if (r)
 471                 return r;
 472
 473         l = 128;
 474
 475         if (len >= 128 * 2 && edid[0x7e] > 0) {
 476                 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
 477                 if (r)
 478                         return r;
 479                 l += 128;
 480         }
 481
 482         return l;
 483 }
 484
 485 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
 486 {
 487         return gpio_get_value(ip_data->hpd_gpio);
 488 }
 489
 490 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
 491                         struct hdmi_core_infoframe_avi *avi_cfg,
 492                         struct hdmi_core_packet_enable_repeat *repeat_cfg)
 493 {
 494         pr_debug("Enter hdmi_core_init\n");
 495
 496         /* video core */
 497         video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
 498         video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
 499         video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
 500         video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
 501         video_cfg->hdmi_dvi = HDMI_DVI;
 502         video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
 503
 504         /* info frame */
 505         avi_cfg->db1_format = 0;
 506         avi_cfg->db1_active_info = 0;
 507         avi_cfg->db1_bar_info_dv = 0;
 508         avi_cfg->db1_scan_info = 0;
 509         avi_cfg->db2_colorimetry = 0;
 510         avi_cfg->db2_aspect_ratio = 0;
 511         avi_cfg->db2_active_fmt_ar = 0;
 512         avi_cfg->db3_itc = 0;
 513         avi_cfg->db3_ec = 0;
 514         avi_cfg->db3_q_range = 0;
 515         avi_cfg->db3_nup_scaling = 0;
 516         avi_cfg->db4_videocode = 0;
 517         avi_cfg->db5_pixel_repeat = 0;
 518         avi_cfg->db6_7_line_eoftop = 0 ;
 519         avi_cfg->db8_9_line_sofbottom = 0;
 520         avi_cfg->db10_11_pixel_eofleft = 0;
 521         avi_cfg->db12_13_pixel_sofright = 0;
 522
 523         /* packet enable and repeat */
 524         repeat_cfg->audio_pkt = 0;
 525         repeat_cfg->audio_pkt_repeat = 0;
 526         repeat_cfg->avi_infoframe = 0;
 527         repeat_cfg->avi_infoframe_repeat = 0;
 528         repeat_cfg->gen_cntrl_pkt = 0;
 529         repeat_cfg->gen_cntrl_pkt_repeat = 0;
 530         repeat_cfg->generic_pkt = 0;
 531         repeat_cfg->generic_pkt_repeat = 0;
 532 }
 533
 534 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
 535 {
 536         pr_debug("Enter hdmi_core_powerdown_disable\n");
 537         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
 538 }
 539
 540 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
 541 {
 542         pr_debug("Enter hdmi_core_swreset_release\n");
 543         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
 544 }
 545
 546 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
 547 {
 548         pr_debug("Enter hdmi_core_swreset_assert\n");
 549         REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
 550 }
 551
 552 /* HDMI_CORE_VIDEO_CONFIG */
 553 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
 554                                 struct hdmi_core_video_config *cfg)
 555 {
 556         u32 r = 0;
 557         void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
 558
 559         /* sys_ctrl1 default configuration not tunable */
 560         r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
 561         r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
 562         r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
 563         r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
 564         r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
 565         hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
 566
 567         REG_FLD_MOD(core_sys_base,
 568                         HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
 569
 570         /* Vid_Mode */
 571         r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
 572
 573         /* dither truncation configuration */
 574         if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
 575                 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
 576                 r = FLD_MOD(r, 1, 5, 5);
 577         } else {
 578                 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
 579                 r = FLD_MOD(r, 0, 5, 5);
 580         }
 581         hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
 582
 583         /* HDMI_Ctrl */
 584         r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
 585         r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
 586         r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
 587         r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
 588         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
 589
 590         /* TMDS_CTRL */
 591         REG_FLD_MOD(core_sys_base,
 592                         HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
 593 }
 594
 595 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
 596 {
 597         u32 val;
 598         char sum = 0, checksum = 0;
 599         void __iomem *av_base = hdmi_av_base(ip_data);
 600         struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
 601
 602         sum += 0x82 + 0x002 + 0x00D;
 603         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
 604         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
 605         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
 606
 607         val = (info_avi.db1_format << 5) |
 608                 (info_avi.db1_active_info << 4) |
 609                 (info_avi.db1_bar_info_dv << 2) |
 610                 (info_avi.db1_scan_info);
 611         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
 612         sum += val;
 613
 614         val = (info_avi.db2_colorimetry << 6) |
 615                 (info_avi.db2_aspect_ratio << 4) |
 616                 (info_avi.db2_active_fmt_ar);
 617         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
 618         sum += val;
 619
 620         val = (info_avi.db3_itc << 7) |
 621                 (info_avi.db3_ec << 4) |
 622                 (info_avi.db3_q_range << 2) |
 623                 (info_avi.db3_nup_scaling);
 624         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
 625         sum += val;
 626
 627         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
 628                                         info_avi.db4_videocode);
 629         sum += info_avi.db4_videocode;
 630
 631         val = info_avi.db5_pixel_repeat;
 632         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
 633         sum += val;
 634
 635         val = info_avi.db6_7_line_eoftop & 0x00FF;
 636         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
 637         sum += val;
 638
 639         val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
 640         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
 641         sum += val;
 642
 643         val = info_avi.db8_9_line_sofbottom & 0x00FF;
 644         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
 645         sum += val;
 646
 647         val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
 648         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
 649         sum += val;
 650
 651         val = info_avi.db10_11_pixel_eofleft & 0x00FF;
 652         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
 653         sum += val;
 654
 655         val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
 656         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
 657         sum += val;
 658
 659         val = info_avi.db12_13_pixel_sofright & 0x00FF;
 660         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
 661         sum += val;
 662
 663         val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
 664         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
 665         sum += val;
 666
 667         checksum = 0x100 - sum;
 668         hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
 669 }
 670
 671 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
 672                 struct hdmi_core_packet_enable_repeat repeat_cfg)
 673 {
 674         /* enable/repeat the infoframe */
 675         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
 676                 (repeat_cfg.audio_pkt << 5) |
 677                 (repeat_cfg.audio_pkt_repeat << 4) |
 678                 (repeat_cfg.avi_infoframe << 1) |
 679                 (repeat_cfg.avi_infoframe_repeat));
 680
 681         /* enable/repeat the packet */
 682         hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
 683                 (repeat_cfg.gen_cntrl_pkt << 3) |
 684                 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
 685                 (repeat_cfg.generic_pkt << 1) |
 686                 (repeat_cfg.generic_pkt_repeat));
 687 }
 688
 689 static void hdmi_wp_init(struct omap_video_timings *timings,
 690                         struct hdmi_video_format *video_fmt)
 691 {
 692         pr_debug("Enter hdmi_wp_init\n");
 693
 694         timings->hbp = 0;
 695         timings->hfp = 0;
 696         timings->hsw = 0;
 697         timings->vbp = 0;
 698         timings->vfp = 0;
 699         timings->vsw = 0;
 700
 701         video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
 702         video_fmt->y_res = 0;
 703         video_fmt->x_res = 0;
 704
 705 }
 706
 707 int ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data)
 708 {
 709         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, true, 31, 31);
 710         return 0;
 711 }
 712
 713 void ti_hdmi_4xxx_wp_video_stop(struct hdmi_ip_data *ip_data)
 714 {
 715         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, false, 31, 31);
 716 }
 717
 718 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
 719         struct omap_video_timings *timings, struct hdmi_config *param)
 720 {
 721         pr_debug("Enter hdmi_wp_video_init_format\n");
 722
 723         video_fmt->y_res = param->timings.y_res;
 724         video_fmt->x_res = param->timings.x_res;
 725
 726         timings->hbp = param->timings.hbp;
 727         timings->hfp = param->timings.hfp;
 728         timings->hsw = param->timings.hsw;
 729         timings->vbp = param->timings.vbp;
 730         timings->vfp = param->timings.vfp;
 731         timings->vsw = param->timings.vsw;
 732 }
 733
 734 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
 735                 struct hdmi_video_format *video_fmt)
 736 {
 737         u32 l = 0;
 738
 739         REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
 740                         video_fmt->packing_mode, 10, 8);
 741
 742         l |= FLD_VAL(video_fmt->y_res, 31, 16);
 743         l |= FLD_VAL(video_fmt->x_res, 15, 0);
 744         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
 745 }
 746
 747 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
 748 {
 749         u32 r;
 750         pr_debug("Enter hdmi_wp_video_config_interface\n");
 751
 752         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
 753         r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7);
 754         r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6);
 755         r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
 756         r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
 757         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
 758 }
 759
 760 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
 761                 struct omap_video_timings *timings)
 762 {
 763         u32 timing_h = 0;
 764         u32 timing_v = 0;
 765
 766         pr_debug("Enter hdmi_wp_video_config_timing\n");
 767
 768         timing_h |= FLD_VAL(timings->hbp, 31, 20);
 769         timing_h |= FLD_VAL(timings->hfp, 19, 8);
 770         timing_h |= FLD_VAL(timings->hsw, 7, 0);
 771         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
 772
 773         timing_v |= FLD_VAL(timings->vbp, 31, 20);
 774         timing_v |= FLD_VAL(timings->vfp, 19, 8);
 775         timing_v |= FLD_VAL(timings->vsw, 7, 0);
 776         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
 777 }
 778
 779 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
 780 {
 781         /* HDMI */
 782         struct omap_video_timings video_timing;
 783         struct hdmi_video_format video_format;
 784         /* HDMI core */
 785         struct hdmi_core_infoframe_avi avi_cfg = ip_data->avi_cfg;
 786         struct hdmi_core_video_config v_core_cfg;
 787         struct hdmi_core_packet_enable_repeat repeat_cfg;
 788         struct hdmi_config *cfg = &ip_data->cfg;
 789
 790         hdmi_wp_init(&video_timing, &video_format);
 791
 792         hdmi_core_init(&v_core_cfg,
 793                 &avi_cfg,
 794                 &repeat_cfg);
 795
 796         hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
 797
 798         hdmi_wp_video_config_timing(ip_data, &video_timing);
 799
 800         /* video config */
 801         video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
 802
 803         hdmi_wp_video_config_format(ip_data, &video_format);
 804
 805         hdmi_wp_video_config_interface(ip_data);
 806
 807         /*
 808          * configure core video part
 809          * set software reset in the core
 810          */
 811         hdmi_core_swreset_assert(ip_data);
 812
 813         /* power down off */
 814         hdmi_core_powerdown_disable(ip_data);
 815
 816         v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
 817         v_core_cfg.hdmi_dvi = cfg->cm.mode;
 818
 819         hdmi_core_video_config(ip_data, &v_core_cfg);
 820
 821         /* release software reset in the core */
 822         hdmi_core_swreset_release(ip_data);
 823
 824         /*
 825          * configure packet
 826          * info frame video see doc CEA861-D page 65
 827          */
 828         avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
 829         avi_cfg.db1_active_info =
 830                 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
 831         avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
 832         avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
 833         avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
 834         avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
 835         avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
 836         avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
 837         avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
 838         avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
 839         avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
 840         avi_cfg.db4_videocode = cfg->cm.code;
 841         avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
 842         avi_cfg.db6_7_line_eoftop = 0;
 843         avi_cfg.db8_9_line_sofbottom = 0;
 844         avi_cfg.db10_11_pixel_eofleft = 0;
 845         avi_cfg.db12_13_pixel_sofright = 0;
 846
 847         hdmi_core_aux_infoframe_avi_config(ip_data);
 848
 849         /* enable/repeat the infoframe */
 850         repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
 851         repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
 852         /* wakeup */
 853         repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
 854         repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
 855         hdmi_core_av_packet_config(ip_data, repeat_cfg);
 856 }
 857
 858 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 859 {
 860 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
 861                 hdmi_read_reg(hdmi_wp_base(ip_data), r))
 862
 863         DUMPREG(HDMI_WP_REVISION);
 864         DUMPREG(HDMI_WP_SYSCONFIG);
 865         DUMPREG(HDMI_WP_IRQSTATUS_RAW);
 866         DUMPREG(HDMI_WP_IRQSTATUS);
 867         DUMPREG(HDMI_WP_PWR_CTRL);
 868         DUMPREG(HDMI_WP_IRQENABLE_SET);
 869         DUMPREG(HDMI_WP_VIDEO_CFG);
 870         DUMPREG(HDMI_WP_VIDEO_SIZE);
 871         DUMPREG(HDMI_WP_VIDEO_TIMING_H);
 872         DUMPREG(HDMI_WP_VIDEO_TIMING_V);
 873         DUMPREG(HDMI_WP_WP_CLK);
 874         DUMPREG(HDMI_WP_AUDIO_CFG);
 875         DUMPREG(HDMI_WP_AUDIO_CFG2);
 876         DUMPREG(HDMI_WP_AUDIO_CTRL);
 877         DUMPREG(HDMI_WP_AUDIO_DATA);
 878 }
 879
 880 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 881 {
 882 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
 883                 hdmi_read_reg(hdmi_pll_base(ip_data), r))
 884
 885         DUMPPLL(PLLCTRL_PLL_CONTROL);
 886         DUMPPLL(PLLCTRL_PLL_STATUS);
 887         DUMPPLL(PLLCTRL_PLL_GO);
 888         DUMPPLL(PLLCTRL_CFG1);
 889         DUMPPLL(PLLCTRL_CFG2);
 890         DUMPPLL(PLLCTRL_CFG3);
 891         DUMPPLL(PLLCTRL_CFG4);
 892 }
 893
 894 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
 895 {
 896         int i;
 897
 898 #define CORE_REG(i, name) name(i)
 899 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
 900                 hdmi_read_reg(hdmi_core_sys_base(ip_data), r))
 901 #define DUMPCOREAV(r) seq_printf(s, "%-35s %08x\n", #r,\
 902                 hdmi_read_reg(hdmi_av_base(ip_data), r))
 903 #define DUMPCOREAV2(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
 904                 (i < 10) ? 32 - strlen(#r) : 31 - strlen(#r), " ", \
 905                 hdmi_read_reg(hdmi_av_base(ip_data), CORE_REG(i, r)))
 906
 907         DUMPCORE(HDMI_CORE_SYS_VND_IDL);
 908         DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
 909         DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
 910         DUMPCORE(HDMI_CORE_SYS_DEV_REV);
 911         DUMPCORE(HDMI_CORE_SYS_SRST);
 912         DUMPCORE(HDMI_CORE_CTRL1);
 913         DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
 914         DUMPCORE(HDMI_CORE_SYS_DE_DLY);
 915         DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
 916         DUMPCORE(HDMI_CORE_SYS_DE_TOP);
 917         DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
 918         DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
 919         DUMPCORE(HDMI_CORE_SYS_DE_LINL);
 920         DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
 921         DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
 922         DUMPCORE(HDMI_CORE_SYS_VID_MODE);
 923         DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
 924         DUMPCORE(HDMI_CORE_SYS_INTR1);
 925         DUMPCORE(HDMI_CORE_SYS_INTR2);
 926         DUMPCORE(HDMI_CORE_SYS_INTR3);
 927         DUMPCORE(HDMI_CORE_SYS_INTR4);
 928         DUMPCORE(HDMI_CORE_SYS_UMASK1);
 929         DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
 930
 931         DUMPCORE(HDMI_CORE_DDC_ADDR);
 932         DUMPCORE(HDMI_CORE_DDC_SEGM);
 933         DUMPCORE(HDMI_CORE_DDC_OFFSET);
 934         DUMPCORE(HDMI_CORE_DDC_COUNT1);
 935         DUMPCORE(HDMI_CORE_DDC_COUNT2);
 936         DUMPCORE(HDMI_CORE_DDC_STATUS);
 937         DUMPCORE(HDMI_CORE_DDC_CMD);
 938         DUMPCORE(HDMI_CORE_DDC_DATA);
 939
 940         DUMPCOREAV(HDMI_CORE_AV_ACR_CTRL);
 941         DUMPCOREAV(HDMI_CORE_AV_FREQ_SVAL);
 942         DUMPCOREAV(HDMI_CORE_AV_N_SVAL1);
 943         DUMPCOREAV(HDMI_CORE_AV_N_SVAL2);
 944         DUMPCOREAV(HDMI_CORE_AV_N_SVAL3);
 945         DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL1);
 946         DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL2);
 947         DUMPCOREAV(HDMI_CORE_AV_CTS_SVAL3);
 948         DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL1);
 949         DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL2);
 950         DUMPCOREAV(HDMI_CORE_AV_CTS_HVAL3);
 951         DUMPCOREAV(HDMI_CORE_AV_AUD_MODE);
 952         DUMPCOREAV(HDMI_CORE_AV_SPDIF_CTRL);
 953         DUMPCOREAV(HDMI_CORE_AV_HW_SPDIF_FS);
 954         DUMPCOREAV(HDMI_CORE_AV_SWAP_I2S);
 955         DUMPCOREAV(HDMI_CORE_AV_SPDIF_ERTH);
 956         DUMPCOREAV(HDMI_CORE_AV_I2S_IN_MAP);
 957         DUMPCOREAV(HDMI_CORE_AV_I2S_IN_CTRL);
 958         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST0);
 959         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST1);
 960         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST2);
 961         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST4);
 962         DUMPCOREAV(HDMI_CORE_AV_I2S_CHST5);
 963         DUMPCOREAV(HDMI_CORE_AV_ASRC);
 964         DUMPCOREAV(HDMI_CORE_AV_I2S_IN_LEN);
 965         DUMPCOREAV(HDMI_CORE_AV_HDMI_CTRL);
 966         DUMPCOREAV(HDMI_CORE_AV_AUDO_TXSTAT);
 967         DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
 968         DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
 969         DUMPCOREAV(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
 970         DUMPCOREAV(HDMI_CORE_AV_TEST_TXCTRL);
 971         DUMPCOREAV(HDMI_CORE_AV_DPD);
 972         DUMPCOREAV(HDMI_CORE_AV_PB_CTRL1);
 973         DUMPCOREAV(HDMI_CORE_AV_PB_CTRL2);
 974         DUMPCOREAV(HDMI_CORE_AV_AVI_TYPE);
 975         DUMPCOREAV(HDMI_CORE_AV_AVI_VERS);
 976         DUMPCOREAV(HDMI_CORE_AV_AVI_LEN);
 977         DUMPCOREAV(HDMI_CORE_AV_AVI_CHSUM);
 978
 979         for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
 980                 DUMPCOREAV2(i, HDMI_CORE_AV_AVI_DBYTE);
 981
 982         DUMPCOREAV(HDMI_CORE_AV_SPD_TYPE);
 983         DUMPCOREAV(HDMI_CORE_AV_SPD_VERS);
 984         DUMPCOREAV(HDMI_CORE_AV_SPD_LEN);
 985         DUMPCOREAV(HDMI_CORE_AV_SPD_CHSUM);
 986
 987         for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
 988                 DUMPCOREAV2(i, HDMI_CORE_AV_SPD_DBYTE);
 989
 990         DUMPCOREAV(HDMI_CORE_AV_AUDIO_TYPE);
 991         DUMPCOREAV(HDMI_CORE_AV_AUDIO_VERS);
 992         DUMPCOREAV(HDMI_CORE_AV_AUDIO_LEN);
 993         DUMPCOREAV(HDMI_CORE_AV_AUDIO_CHSUM);
 994
 995         for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
 996                 DUMPCOREAV2(i, HDMI_CORE_AV_AUD_DBYTE);
 997
 998         DUMPCOREAV(HDMI_CORE_AV_MPEG_TYPE);
 999         DUMPCOREAV(HDMI_CORE_AV_MPEG_VERS);
1000         DUMPCOREAV(HDMI_CORE_AV_MPEG_LEN);
1001         DUMPCOREAV(HDMI_CORE_AV_MPEG_CHSUM);
1002
1003         for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
1004                 DUMPCOREAV2(i, HDMI_CORE_AV_MPEG_DBYTE);
1005
1006         for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
1007                 DUMPCOREAV2(i, HDMI_CORE_AV_GEN_DBYTE);
1008
1009         DUMPCOREAV(HDMI_CORE_AV_CP_BYTE1);
1010
1011         for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
1012                 DUMPCOREAV2(i, HDMI_CORE_AV_GEN2_DBYTE);
1013
1014         DUMPCOREAV(HDMI_CORE_AV_CEC_ADDR_ID);
1015 }
1016
1017 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1018 {
1019 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1020                 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1021
1022         DUMPPHY(HDMI_TXPHY_TX_CTRL);
1023         DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1024         DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1025         DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1026 }
1027
1028 #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
1029 static void ti_hdmi_4xxx_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1030                                         struct hdmi_audio_format *aud_fmt)
1031 {
1032         u32 r;
1033
1034         DSSDBG("Enter hdmi_wp_audio_config_format\n");
1035
1036         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1037         r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1038         r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1039         r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1040         r = FLD_MOD(r, aud_fmt->type, 4, 4);
1041         r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1042         r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1043         r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1044         r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1045         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1046 }
1047
1048 static void ti_hdmi_4xxx_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1049                                         struct hdmi_audio_dma *aud_dma)
1050 {
1051         u32 r;
1052
1053         DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1054
1055         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1056         r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1057         r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1058         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1059
1060         r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1061         r = FLD_MOD(r, aud_dma->mode, 9, 9);
1062         r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1063         hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1064 }
1065
1066 static void ti_hdmi_4xxx_core_audio_config(struct hdmi_ip_data *ip_data,
1067                                         struct hdmi_core_audio_config *cfg)
1068 {
1069         u32 r;
1070         void __iomem *av_base = hdmi_av_base(ip_data);
1071
1072         /*
1073          * Parameters for generation of Audio Clock Recovery packets
1074          */
1075         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1076         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1077         REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1078
1079         if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1080                 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1081                 REG_FLD_MOD(av_base,
1082                                 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1083                 REG_FLD_MOD(av_base,
1084                                 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1085         } else {
1086                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1087                                 cfg->aud_par_busclk, 7, 0);
1088                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1089                                 (cfg->aud_par_busclk >> 8), 7, 0);
1090                 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1091                                 (cfg->aud_par_busclk >> 16), 7, 0);
1092         }
1093
1094         /* Set ACR clock divisor */
1095         REG_FLD_MOD(av_base,
1096                         HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1097
1098         r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1099         /*
1100          * Use TMDS clock for ACR packets. For devices that use
1101          * the MCLK, this is the first part of the MCLK initialization.
1102          */
1103         r = FLD_MOD(r, 0, 2, 2);
1104
1105         r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1106         r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1107         hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1108
1109         /* For devices using MCLK, this completes its initialization. */
1110         if (cfg->use_mclk)
1111                 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
1112
1113         /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1114         REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1115                                                 cfg->fs_override, 1, 1);
1116
1117         /*
1118          * Set IEC-60958-3 channel status word. It is passed to the IP
1119          * just as it is received. The user of the driver is responsible
1120          * for its contents.
1121          */
1122         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST0,
1123                        cfg->iec60958_cfg->status[0]);
1124         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST1,
1125                        cfg->iec60958_cfg->status[1]);
1126         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST2,
1127                        cfg->iec60958_cfg->status[2]);
1128         /* yes, this is correct: status[3] goes to CHST4 register */
1129         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST4,
1130                        cfg->iec60958_cfg->status[3]);
1131         /* yes, this is correct: status[4] goes to CHST5 register */
1132         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5,
1133                        cfg->iec60958_cfg->status[4]);
1134
1135         /* set I2S parameters */
1136         r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1137         r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1138         r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1139         r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1140         r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1141         r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1142         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1143
1144         REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1145                         cfg->i2s_cfg.in_length_bits, 3, 0);
1146
1147         /* Audio channels and mode parameters */
1148         REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1149         r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1150         r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1151         r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1152         r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1153         r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1154         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1155
1156         /* Audio channel mappings */
1157         /* TODO: Make channel mapping dynamic. For now, map channels
1158          * in the ALSA order: FL/FR/RL/RR/C/LFE/SL/SR. Remapping is needed as
1159          * HDMI speaker order is different. See CEA-861 Section 6.6.2.
1160          */
1161         hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_MAP, 0x78);
1162         REG_FLD_MOD(av_base, HDMI_CORE_AV_SWAP_I2S, 1, 5, 5);
1163 }
1164
1165 static void ti_hdmi_4xxx_core_audio_infoframe_cfg(struct hdmi_ip_data *ip_data,
1166                 struct snd_cea_861_aud_if *info_aud)
1167 {
1168         u8 sum = 0, checksum = 0;
1169         void __iomem *av_base = hdmi_av_base(ip_data);
1170
1171         /*
1172          * Set audio info frame type, version and length as
1173          * described in HDMI 1.4a Section 8.2.2 specification.
1174          * Checksum calculation is defined in Section 5.3.5.
1175          */
1176         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1177         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1178         hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1179         sum += 0x84 + 0x001 + 0x00a;
1180
1181         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0),
1182                        info_aud->db1_ct_cc);
1183         sum += info_aud->db1_ct_cc;
1184
1185         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1),
1186                        info_aud->db2_sf_ss);
1187         sum += info_aud->db2_sf_ss;
1188
1189         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), info_aud->db3);
1190         sum += info_aud->db3;
1191
1192         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), info_aud->db4_ca);
1193         sum += info_aud->db4_ca;
1194
1195         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4),
1196                        info_aud->db5_dminh_lsv);
1197         sum += info_aud->db5_dminh_lsv;
1198
1199         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1200         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1201         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1202         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1203         hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1204
1205         checksum = 0x100 - sum;
1206         hdmi_write_reg(av_base,
1207                                         HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1208
1209         /*
1210          * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1211          * is available.
1212          */
1213 }
1214
1215 int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data,
1216                 struct omap_dss_audio *audio)
1217 {
1218         struct hdmi_audio_format audio_format;
1219         struct hdmi_audio_dma audio_dma;
1220         struct hdmi_core_audio_config core;
1221         int err, n, cts, channel_count;
1222         unsigned int fs_nr;
1223         bool word_length_16b = false;
1224
1225         if (!audio || !audio->iec || !audio->cea || !ip_data)
1226                 return -EINVAL;
1227
1228         core.iec60958_cfg = audio->iec;
1229         /*
1230          * In the IEC-60958 status word, check if the audio sample word length
1231          * is 16-bit as several optimizations can be performed in such case.
1232          */
1233         if (!(audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24))
1234                 if (audio->iec->status[4] & IEC958_AES4_CON_WORDLEN_20_16)
1235                         word_length_16b = true;
1236
1237         /* I2S configuration. See Phillips' specification */
1238         if (word_length_16b)
1239                 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1240         else
1241                 core.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1242         /*
1243          * The I2S input word length is twice the lenght given in the IEC-60958
1244          * status word. If the word size is greater than
1245          * 20 bits, increment by one.
1246          */
1247         core.i2s_cfg.in_length_bits = audio->iec->status[4]
1248                 & IEC958_AES4_CON_WORDLEN;
1249         if (audio->iec->status[4] & IEC958_AES4_CON_MAX_WORDLEN_24)
1250                 core.i2s_cfg.in_length_bits++;
1251         core.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
1252         core.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
1253         core.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
1254         core.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
1255
1256         /* convert sample frequency to a number */
1257         switch (audio->iec->status[3] & IEC958_AES3_CON_FS) {
1258         case IEC958_AES3_CON_FS_32000:
1259                 fs_nr = 32000;
1260                 break;
1261         case IEC958_AES3_CON_FS_44100:
1262                 fs_nr = 44100;
1263                 break;
1264         case IEC958_AES3_CON_FS_48000:
1265                 fs_nr = 48000;
1266                 break;
1267         case IEC958_AES3_CON_FS_88200:
1268                 fs_nr = 88200;
1269                 break;
1270         case IEC958_AES3_CON_FS_96000:
1271                 fs_nr = 96000;
1272                 break;
1273         case IEC958_AES3_CON_FS_176400:
1274                 fs_nr = 176400;
1275                 break;
1276         case IEC958_AES3_CON_FS_192000:
1277                 fs_nr = 192000;
1278                 break;
1279         default:
1280                 return -EINVAL;
1281         }
1282
1283         err = hdmi_compute_acr(fs_nr, &n, &cts);
1284
1285         /* Audio clock regeneration settings */
1286         core.n = n;
1287         core.cts = cts;
1288         if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
1289                 core.aud_par_busclk = 0;
1290                 core.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
1291                 core.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
1292         } else {
1293                 core.aud_par_busclk = (((128 * 31) - 1) << 8);
1294                 core.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
1295                 core.use_mclk = true;
1296         }
1297
1298         if (core.use_mclk)
1299                 core.mclk_mode = HDMI_AUDIO_MCLK_128FS;
1300
1301         /* Audio channels settings */
1302         channel_count = (audio->cea->db1_ct_cc &
1303                          CEA861_AUDIO_INFOFRAME_DB1CC) + 1;
1304
1305         switch (channel_count) {
1306         case 2:
1307                 audio_format.active_chnnls_msk = 0x03;
1308                 break;
1309         case 3:
1310                 audio_format.active_chnnls_msk = 0x07;
1311                 break;
1312         case 4:
1313                 audio_format.active_chnnls_msk = 0x0f;
1314                 break;
1315         case 5:
1316                 audio_format.active_chnnls_msk = 0x1f;
1317                 break;
1318         case 6:
1319                 audio_format.active_chnnls_msk = 0x3f;
1320                 break;
1321         case 7:
1322                 audio_format.active_chnnls_msk = 0x7f;
1323                 break;
1324         case 8:
1325                 audio_format.active_chnnls_msk = 0xff;
1326                 break;
1327         default:
1328                 return -EINVAL;
1329         }
1330
1331         /*
1332          * the HDMI IP needs to enable four stereo channels when transmitting
1333          * more than 2 audio channels
1334          */
1335         if (channel_count == 2) {
1336                 audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
1337                 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
1338                 core.layout = HDMI_AUDIO_LAYOUT_2CH;
1339         } else {
1340                 audio_format.stereo_channels = HDMI_AUDIO_STEREO_FOURCHANNELS;
1341                 core.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN |
1342                                 HDMI_AUDIO_I2S_SD1_EN | HDMI_AUDIO_I2S_SD2_EN |
1343                                 HDMI_AUDIO_I2S_SD3_EN;
1344                 core.layout = HDMI_AUDIO_LAYOUT_8CH;
1345         }
1346
1347         core.en_spdif = false;
1348         /* use sample frequency from channel status word */
1349         core.fs_override = true;
1350         /* enable ACR packets */
1351         core.en_acr_pkt = true;
1352         /* disable direct streaming digital audio */
1353         core.en_dsd_audio = false;
1354         /* use parallel audio interface */
1355         core.en_parallel_aud_input = true;
1356
1357         /* DMA settings */
1358         if (word_length_16b)
1359                 audio_dma.transfer_size = 0x10;
1360         else
1361                 audio_dma.transfer_size = 0x20;
1362         audio_dma.block_size = 0xC0;
1363         audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
1364         audio_dma.fifo_threshold = 0x20; /* in number of samples */
1365
1366         /* audio FIFO format settings */
1367         if (word_length_16b) {
1368                 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
1369                 audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
1370                 audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
1371         } else {
1372                 audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
1373                 audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
1374                 audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
1375         }
1376         audio_format.type = HDMI_AUDIO_TYPE_LPCM;
1377         audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
1378         /* disable start/stop signals of IEC 60958 blocks */
1379         audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_ON;
1380
1381         /* configure DMA and audio FIFO format*/
1382         ti_hdmi_4xxx_wp_audio_config_dma(ip_data, &audio_dma);
1383         ti_hdmi_4xxx_wp_audio_config_format(ip_data, &audio_format);
1384
1385         /* configure the core*/
1386         ti_hdmi_4xxx_core_audio_config(ip_data, &core);
1387
1388         /* configure CEA 861 audio infoframe*/
1389         ti_hdmi_4xxx_core_audio_infoframe_cfg(ip_data, audio->cea);
1390
1391         return 0;
1392 }
1393
1394 int ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data)
1395 {
1396         REG_FLD_MOD(hdmi_wp_base(ip_data),
1397                     HDMI_WP_AUDIO_CTRL, true, 31, 31);
1398         return 0;
1399 }
1400
1401 void ti_hdmi_4xxx_wp_audio_disable(struct hdmi_ip_data *ip_data)
1402 {
1403         REG_FLD_MOD(hdmi_wp_base(ip_data),
1404                     HDMI_WP_AUDIO_CTRL, false, 31, 31);
1405 }
1406
1407 int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data)
1408 {
1409         REG_FLD_MOD(hdmi_av_base(ip_data),
1410                     HDMI_CORE_AV_AUD_MODE, true, 0, 0);
1411         REG_FLD_MOD(hdmi_wp_base(ip_data),
1412                     HDMI_WP_AUDIO_CTRL, true, 30, 30);
1413         return 0;
1414 }
1415
1416 void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data)
1417 {
1418         REG_FLD_MOD(hdmi_av_base(ip_data),
1419                     HDMI_CORE_AV_AUD_MODE, false, 0, 0);
1420         REG_FLD_MOD(hdmi_wp_base(ip_data),
1421                     HDMI_WP_AUDIO_CTRL, false, 30, 30);
1422 }
1423 #endif