2 * include/asm-i386/processor.h
4 * Copyright (C) 1994 Linus Torvalds
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/threads.h>
21 #include <asm/percpu.h>
22 #include <linux/cpumask.h>
23 #include <linux/init.h>
24 #include <asm/processor-flags.h>
26 /* flag for disabling the tsc */
27 extern int tsc_disable;
33 #define desc_empty(desc) \
34 (!((desc)->a | (desc)->b))
36 #define desc_equal(desc1, desc2) \
37 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
39 * Default implementation of macro that returns current
40 * instruction pointer ("program counter").
42 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
45 * CPU type and hardware bug flags. Kept separately for each CPU.
46 * Members of this structure are referenced in head.S, so think twice
47 * before touching them. [mj]
51 __u8 x86; /* CPU family */
52 __u8 x86_vendor; /* CPU vendor */
55 char wp_works_ok; /* It doesn't on 386's */
56 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
59 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
60 unsigned long x86_capability[NCAPINTS];
61 char x86_vendor_id[16];
62 char x86_model_id[64];
63 int x86_cache_size; /* in KB - valid for CPUS which support this
65 int x86_cache_alignment; /* In bytes */
71 unsigned long loops_per_jiffy;
73 cpumask_t llc_shared_map; /* cpus sharing the last level cache */
75 unsigned char x86_max_cores; /* cpuid returned max cores value */
77 unsigned short x86_clflush_size;
79 unsigned char booted_cores; /* number of cores as seen by OS */
80 __u8 phys_proc_id; /* Physical processor id. */
81 __u8 cpu_core_id; /* Core id */
83 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
85 #define X86_VENDOR_INTEL 0
86 #define X86_VENDOR_CYRIX 1
87 #define X86_VENDOR_AMD 2
88 #define X86_VENDOR_UMC 3
89 #define X86_VENDOR_NEXGEN 4
90 #define X86_VENDOR_CENTAUR 5
91 #define X86_VENDOR_RISE 6
92 #define X86_VENDOR_TRANSMETA 7
93 #define X86_VENDOR_NSC 8
94 #define X86_VENDOR_NUM 9
95 #define X86_VENDOR_UNKNOWN 0xff
98 * capabilities of CPUs
101 extern struct cpuinfo_x86 boot_cpu_data;
102 extern struct cpuinfo_x86 new_cpu_data;
103 extern struct tss_struct doublefault_tss;
104 DECLARE_PER_CPU(struct tss_struct, init_tss);
107 extern struct cpuinfo_x86 cpu_data[];
108 #define current_cpu_data cpu_data[smp_processor_id()]
110 #define cpu_data (&boot_cpu_data)
111 #define current_cpu_data boot_cpu_data
114 extern int cpu_llc_id[NR_CPUS];
115 extern char ignore_fpu_irq;
117 void __init cpu_detect(struct cpuinfo_x86 *c);
119 extern void identify_boot_cpu(void);
120 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
121 extern void print_cpu_info(struct cpuinfo_x86 *);
122 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
123 extern unsigned short num_cache_leaves;
126 extern void detect_ht(struct cpuinfo_x86 *c);
128 static inline void detect_ht(struct cpuinfo_x86 *c) {}
131 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
132 unsigned int *ecx, unsigned int *edx)
134 /* ecx is often an input as well as an output. */
140 : "0" (*eax), "2" (*ecx));
143 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
146 * Intel CPU features in CR4
148 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
149 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
150 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
151 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
152 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
153 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
154 #define X86_CR4_MCE 0x0040 /* Machine check enable */
155 #define X86_CR4_PGE 0x0080 /* enable global pages */
156 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
157 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
158 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
161 * Save the cr4 feature set we're using (ie
162 * Pentium 4MB enable and PPro Global page
163 * enable), so that any CPU's that boot up
164 * after us can get the correct flags.
166 extern unsigned long mmu_cr4_features;
168 static inline void set_in_cr4 (unsigned long mask)
171 mmu_cr4_features |= mask;
177 static inline void clear_in_cr4 (unsigned long mask)
180 mmu_cr4_features &= ~mask;
187 * NSC/Cyrix CPU configuration register indexes
190 #define CX86_PCR0 0x20
191 #define CX86_GCR 0xb8
192 #define CX86_CCR0 0xc0
193 #define CX86_CCR1 0xc1
194 #define CX86_CCR2 0xc2
195 #define CX86_CCR3 0xc3
196 #define CX86_CCR4 0xe8
197 #define CX86_CCR5 0xe9
198 #define CX86_CCR6 0xea
199 #define CX86_CCR7 0xeb
200 #define CX86_PCR1 0xf0
201 #define CX86_DIR0 0xfe
202 #define CX86_DIR1 0xff
203 #define CX86_ARR_BASE 0xc4
204 #define CX86_RCR_BASE 0xdc
207 * NSC/Cyrix CPU indexed register access macros
210 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
212 #define setCx86(reg, data) do { \
214 outb((data), 0x23); \
217 /* Stop speculative execution */
218 static inline void sync_core(void)
221 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
224 static inline void __monitor(const void *eax, unsigned long ecx,
227 /* "monitor %eax,%ecx,%edx;" */
229 ".byte 0x0f,0x01,0xc8;"
230 : :"a" (eax), "c" (ecx), "d"(edx));
233 static inline void __mwait(unsigned long eax, unsigned long ecx)
235 /* "mwait %eax,%ecx;" */
237 ".byte 0x0f,0x01,0xc9;"
238 : :"a" (eax), "c" (ecx));
241 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
243 /* from system description table in BIOS. Mostly for MCA use, but
244 others may find it useful. */
245 extern unsigned int machine_id;
246 extern unsigned int machine_submodel_id;
247 extern unsigned int BIOS_revision;
248 extern unsigned int mca_pentium_flag;
250 /* Boot loader type from the setup header */
251 extern int bootloader_type;
254 * User space process size: 3GB (default).
256 #define TASK_SIZE (PAGE_OFFSET)
258 /* This decides where the kernel will search for a free chunk of vm
259 * space during mmap's.
261 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
263 #define HAVE_ARCH_PICK_MMAP_LAYOUT
268 #define IO_BITMAP_BITS 65536
269 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
270 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
271 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
272 #define INVALID_IO_BITMAP_OFFSET 0x8000
273 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
275 struct i387_fsave_struct {
283 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
284 long status; /* software status information */
287 struct i387_fxsave_struct {
298 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
299 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
301 } __attribute__ ((aligned (16)));
303 struct i387_soft_struct {
311 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
312 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
314 unsigned long entry_eip;
318 struct i387_fsave_struct fsave;
319 struct i387_fxsave_struct fxsave;
320 struct i387_soft_struct soft;
327 struct thread_struct;
330 unsigned short back_link,__blh;
332 unsigned short ss0,__ss0h;
334 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
336 unsigned short ss2,__ss2h;
339 unsigned long eflags;
340 unsigned long eax,ecx,edx,ebx;
345 unsigned short es, __esh;
346 unsigned short cs, __csh;
347 unsigned short ss, __ssh;
348 unsigned short ds, __dsh;
349 unsigned short fs, __fsh;
350 unsigned short gs, __gsh;
351 unsigned short ldt, __ldth;
352 unsigned short trace, io_bitmap_base;
354 * The extra 1 is there because the CPU will access an
355 * additional byte beyond the end of the IO permission
356 * bitmap. The extra byte must be all 1 bits, and must
357 * be within the limit.
359 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
361 * Cache the current maximum and the last task that used the bitmap:
363 unsigned long io_bitmap_max;
364 struct thread_struct *io_bitmap_owner;
366 * pads the TSS to be cacheline-aligned (size is 0x100)
368 unsigned long __cacheline_filler[35];
370 * .. and then another 0x100 bytes for emergency kernel stack
372 unsigned long stack[64];
373 } __attribute__((packed));
375 #define ARCH_MIN_TASKALIGN 16
377 struct thread_struct {
378 /* cached TLS descriptors. */
379 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
381 unsigned long sysenter_cs;
386 /* Hardware debugging registers */
387 unsigned long debugreg[8]; /* %%db0-7 debug registers */
389 unsigned long cr2, trap_no, error_code;
390 /* floating point info */
391 union i387_union i387;
392 /* virtual 86 mode info */
393 struct vm86_struct __user * vm86_info;
394 unsigned long screen_bitmap;
395 unsigned long v86flags, v86mask, saved_esp0;
396 unsigned int saved_fs, saved_gs;
398 unsigned long *io_bitmap_ptr;
400 /* max allowed port in the bitmap, in bytes: */
401 unsigned long io_bitmap_max;
404 #define INIT_THREAD { \
405 .esp0 = sizeof(init_stack) + (long)&init_stack, \
407 .sysenter_cs = __KERNEL_CS, \
408 .io_bitmap_ptr = NULL, \
409 .fs = __KERNEL_PDA, \
413 * Note that the .io_bitmap member must be extra-big. This is because
414 * the CPU will access an additional byte beyond the end of the IO
415 * permission bitmap. The extra byte must be all 1 bits, and must
416 * be within the limit.
419 .esp0 = sizeof(init_stack) + (long)&init_stack, \
420 .ss0 = __KERNEL_DS, \
421 .ss1 = __KERNEL_CS, \
422 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
423 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
426 #define start_thread(regs, new_eip, new_esp) do { \
427 __asm__("movl %0,%%gs": :"r" (0)); \
430 regs->xds = __USER_DS; \
431 regs->xes = __USER_DS; \
432 regs->xss = __USER_DS; \
433 regs->xcs = __USER_CS; \
434 regs->eip = new_eip; \
435 regs->esp = new_esp; \
438 /* Forward declaration, a strange C thing */
442 /* Free all resources held by a thread. */
443 extern void release_thread(struct task_struct *);
445 /* Prepare to copy thread state - unlazy all lazy status */
446 extern void prepare_to_copy(struct task_struct *tsk);
449 * create a kernel thread without removing it from tasklists
451 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
453 extern unsigned long thread_saved_pc(struct task_struct *tsk);
454 void show_trace(struct task_struct *task, struct pt_regs *regs, unsigned long *stack);
456 unsigned long get_wchan(struct task_struct *p);
458 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
459 #define KSTK_TOP(info) \
461 unsigned long *__ptr = (unsigned long *)(info); \
462 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
466 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
467 * This is necessary to guarantee that the entire "struct pt_regs"
468 * is accessable even if the CPU haven't stored the SS/ESP registers
469 * on the stack (interrupt gate does not save these registers
470 * when switching to the same priv ring).
471 * Therefore beware: accessing the xss/esp fields of the
472 * "struct pt_regs" is possible, but they may contain the
473 * completely wrong values.
475 #define task_pt_regs(task) \
477 struct pt_regs *__regs__; \
478 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
482 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
483 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
486 struct microcode_header {
494 unsigned int datasize;
495 unsigned int totalsize;
496 unsigned int reserved[3];
500 struct microcode_header hdr;
501 unsigned int bits[0];
504 typedef struct microcode microcode_t;
505 typedef struct microcode_header microcode_header_t;
507 /* microcode format is extended from prescott processors */
508 struct extended_signature {
514 struct extended_sigtable {
517 unsigned int reserved[3];
518 struct extended_signature sigs[0];
521 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
522 static inline void rep_nop(void)
524 __asm__ __volatile__("rep;nop": : :"memory");
527 #define cpu_relax() rep_nop()
529 static inline void native_load_esp0(struct tss_struct *tss, struct thread_struct *thread)
531 tss->esp0 = thread->esp0;
532 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
533 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
534 tss->ss1 = thread->sysenter_cs;
535 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
540 static inline unsigned long native_get_debugreg(int regno)
542 unsigned long val = 0; /* Damn you, gcc! */
546 asm("movl %%db0, %0" :"=r" (val)); break;
548 asm("movl %%db1, %0" :"=r" (val)); break;
550 asm("movl %%db2, %0" :"=r" (val)); break;
552 asm("movl %%db3, %0" :"=r" (val)); break;
554 asm("movl %%db6, %0" :"=r" (val)); break;
556 asm("movl %%db7, %0" :"=r" (val)); break;
563 static inline void native_set_debugreg(int regno, unsigned long value)
567 asm("movl %0,%%db0" : /* no output */ :"r" (value));
570 asm("movl %0,%%db1" : /* no output */ :"r" (value));
573 asm("movl %0,%%db2" : /* no output */ :"r" (value));
576 asm("movl %0,%%db3" : /* no output */ :"r" (value));
579 asm("movl %0,%%db6" : /* no output */ :"r" (value));
582 asm("movl %0,%%db7" : /* no output */ :"r" (value));
590 * Set IOPL bits in EFLAGS from given mask
592 static inline void native_set_iopl_mask(unsigned mask)
595 __asm__ __volatile__ ("pushfl;"
602 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
605 #ifdef CONFIG_PARAVIRT
606 #include <asm/paravirt.h>
608 #define paravirt_enabled() 0
609 #define __cpuid native_cpuid
611 static inline void load_esp0(struct tss_struct *tss, struct thread_struct *thread)
613 native_load_esp0(tss, thread);
617 * These special macros can be used to get or set a debugging register
619 #define get_debugreg(var, register) \
620 (var) = native_get_debugreg(register)
621 #define set_debugreg(value, register) \
622 native_set_debugreg(register, value)
624 #define set_iopl_mask native_set_iopl_mask
625 #endif /* CONFIG_PARAVIRT */
628 * Generic CPUID function
629 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
630 * resulting in stale register contents being returned.
632 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
636 __cpuid(eax, ebx, ecx, edx);
639 /* Some CPUID calls want 'count' to be placed in ecx */
640 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
645 __cpuid(eax, ebx, ecx, edx);
649 * CPUID functions returning a single datum
651 static inline unsigned int cpuid_eax(unsigned int op)
653 unsigned int eax, ebx, ecx, edx;
655 cpuid(op, &eax, &ebx, &ecx, &edx);
658 static inline unsigned int cpuid_ebx(unsigned int op)
660 unsigned int eax, ebx, ecx, edx;
662 cpuid(op, &eax, &ebx, &ecx, &edx);
665 static inline unsigned int cpuid_ecx(unsigned int op)
667 unsigned int eax, ebx, ecx, edx;
669 cpuid(op, &eax, &ebx, &ecx, &edx);
672 static inline unsigned int cpuid_edx(unsigned int op)
674 unsigned int eax, ebx, ecx, edx;
676 cpuid(op, &eax, &ebx, &ecx, &edx);
680 /* generic versions from gas */
681 #define GENERIC_NOP1 ".byte 0x90\n"
682 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
683 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
684 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
685 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
686 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
687 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
688 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
691 #define K8_NOP1 GENERIC_NOP1
692 #define K8_NOP2 ".byte 0x66,0x90\n"
693 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
694 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
695 #define K8_NOP5 K8_NOP3 K8_NOP2
696 #define K8_NOP6 K8_NOP3 K8_NOP3
697 #define K8_NOP7 K8_NOP4 K8_NOP3
698 #define K8_NOP8 K8_NOP4 K8_NOP4
701 /* uses eax dependencies (arbitary choice) */
702 #define K7_NOP1 GENERIC_NOP1
703 #define K7_NOP2 ".byte 0x8b,0xc0\n"
704 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
705 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
706 #define K7_NOP5 K7_NOP4 ASM_NOP1
707 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
708 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
709 #define K7_NOP8 K7_NOP7 ASM_NOP1
712 #define ASM_NOP1 K8_NOP1
713 #define ASM_NOP2 K8_NOP2
714 #define ASM_NOP3 K8_NOP3
715 #define ASM_NOP4 K8_NOP4
716 #define ASM_NOP5 K8_NOP5
717 #define ASM_NOP6 K8_NOP6
718 #define ASM_NOP7 K8_NOP7
719 #define ASM_NOP8 K8_NOP8
720 #elif defined(CONFIG_MK7)
721 #define ASM_NOP1 K7_NOP1
722 #define ASM_NOP2 K7_NOP2
723 #define ASM_NOP3 K7_NOP3
724 #define ASM_NOP4 K7_NOP4
725 #define ASM_NOP5 K7_NOP5
726 #define ASM_NOP6 K7_NOP6
727 #define ASM_NOP7 K7_NOP7
728 #define ASM_NOP8 K7_NOP8
730 #define ASM_NOP1 GENERIC_NOP1
731 #define ASM_NOP2 GENERIC_NOP2
732 #define ASM_NOP3 GENERIC_NOP3
733 #define ASM_NOP4 GENERIC_NOP4
734 #define ASM_NOP5 GENERIC_NOP5
735 #define ASM_NOP6 GENERIC_NOP6
736 #define ASM_NOP7 GENERIC_NOP7
737 #define ASM_NOP8 GENERIC_NOP8
740 #define ASM_NOP_MAX 8
742 /* Prefetch instructions for Pentium III and AMD Athlon */
743 /* It's not worth to care about 3dnow! prefetches for the K6
744 because they are microcoded there and very slow.
745 However we don't do prefetches for pre XP Athlons currently
746 That should be fixed. */
747 #define ARCH_HAS_PREFETCH
748 static inline void prefetch(const void *x)
750 alternative_input(ASM_NOP4,
756 #define ARCH_HAS_PREFETCH
757 #define ARCH_HAS_PREFETCHW
758 #define ARCH_HAS_SPINLOCK_PREFETCH
760 /* 3dnow! prefetch to get an exclusive cache line. Useful for
761 spinlocks to avoid one state transition in the cache coherency protocol. */
762 static inline void prefetchw(const void *x)
764 alternative_input(ASM_NOP4,
769 #define spin_lock_prefetch(x) prefetchw(x)
771 extern void select_idle_routine(const struct cpuinfo_x86 *c);
773 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
775 extern unsigned long boot_option_idle_override;
776 extern void enable_sep_cpu(void);
777 extern int sysenter_setup(void);
779 extern void cpu_set_gdt(int);
780 extern void cpu_init(void);
782 #endif /* __ASM_I386_PROCESSOR_H */