1 #ifndef _ASM_POWERPC_PCI_BRIDGE_H
2 #define _ASM_POWERPC_PCI_BRIDGE_H
6 #include <linux/list.h>
7 #include <linux/ioport.h>
12 struct pci_controller;
15 * Structure of a PCI controller (host bridge)
17 struct pci_controller {
21 struct list_head list_node;
22 struct device *parent;
28 void __iomem *io_base_virt;
29 resource_size_t io_base_phys;
31 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space
34 resource_size_t pci_mem_offset;
37 volatile unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data;
41 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
43 * EXT_REG - provides access to PCI-e extended registers
44 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0
48 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
49 * hanging if we don't have link and try to do config cycles to
50 * anything but the PHB. Only allow talking to the PHB if this is
52 * BIG_ENDIAN - cfg_addr is a big endian register
54 #define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
55 #define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
56 #define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
57 #define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
58 #define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
61 /* Currently, we limit ourselves to 1 IO range and 3 mem
62 * ranges since the common pci_bus structure can't handle more
64 struct resource io_resource;
65 struct resource mem_resources[3];
66 int global_number; /* PCI domain number */
69 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
74 /* These are used for config access before all the PCI probing
76 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
78 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
80 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
82 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
84 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
86 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
89 extern int early_find_capability(struct pci_controller *hose, int bus,
92 extern void setup_indirect_pci(struct pci_controller* hose,
93 u32 cfg_addr, u32 cfg_data, u32 flags);
94 extern void setup_grackle(struct pci_controller *hose);
95 extern void __init update_bridge_resource(struct pci_dev *dev,
96 struct resource *res);
102 * This program is free software; you can redistribute it and/or
103 * modify it under the terms of the GNU General Public License
104 * as published by the Free Software Foundation; either version
105 * 2 of the License, or (at your option) any later version.
109 * Structure of a PCI controller (host bridge)
111 struct pci_controller {
116 struct list_head list_node;
117 struct device *parent;
122 void __iomem *io_base_virt;
124 resource_size_t io_base_phys;
126 /* Some machines have a non 1:1 mapping of
127 * the PCI memory space in the CPU bus space
129 resource_size_t pci_mem_offset;
130 unsigned long pci_io_size;
133 volatile unsigned int __iomem *cfg_addr;
134 volatile void __iomem *cfg_data;
136 /* Currently, we limit ourselves to 1 IO range and 3 mem
137 * ranges since the common pci_bus structure can't handle more
139 struct resource io_resource;
140 struct resource mem_resources[3];
143 unsigned long dma_window_base_cur;
144 unsigned long dma_window_size;
150 * PCI stuff, for nodes representing PCI devices, pointed to
151 * by device_node->data.
153 struct pci_controller;
157 int busno; /* pci bus number */
158 int bussubno; /* pci subordinate bus number */
159 int devfn; /* pci device and function number */
160 int class_code; /* pci device class */
162 struct pci_controller *phb; /* for pci devices */
163 struct iommu_table *iommu_table; /* for phb's or bridges */
164 struct pci_dev *pcidev; /* back-pointer to the pci device */
165 struct device_node *node; /* back-pointer to the device_node */
167 int pci_ext_config_space; /* for pci devices */
170 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
172 int eeh_pe_config_addr; /* new-style partition endpoint address */
173 int eeh_check_count; /* # times driver ignored error */
174 int eeh_freeze_count; /* # times this device froze up. */
175 int eeh_false_positives; /* # times this device reported #ff's */
176 u32 config_space[16]; /* saved PCI config space */
180 /* Get the pointer to a device_node's pci_dn */
181 #define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
183 struct device_node *fetch_dev_dn(struct pci_dev *dev);
185 /* Get a device_node from a pci_dev. This code must be fast except
186 * in the case where the sysdata is incorrect and needs to be fixed
187 * up (this will only happen once).
188 * In this case the sysdata will have been inherited from a PCI host
189 * bridge or a PCI-PCI bridge further up the tree, so it will point
190 * to a valid struct pci_dn, just not the one we want.
192 static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
194 struct device_node *dn = dev->sysdata;
195 struct pci_dn *pdn = dn->data;
197 if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
198 return dn; /* fast path. sysdata is good */
199 return fetch_dev_dn(dev);
202 static inline int pci_device_from_OF_node(struct device_node *np,
207 *bus = PCI_DN(np)->busno;
208 *devfn = PCI_DN(np)->devfn;
212 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
215 return pci_device_to_OF_node(bus->self);
217 return bus->sysdata; /* Must be root bus (PHB) */
220 /** Find the bus corresponding to the indicated device node */
221 struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
223 /** Remove all of the PCI devices under this bus */
224 void pcibios_remove_pci_devices(struct pci_bus *bus);
226 /** Discover new pci devices under this bus, and add them */
227 void pcibios_add_pci_devices(struct pci_bus * bus);
228 void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
230 extern int pcibios_remove_root_bus(struct pci_controller *phb);
232 static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
234 struct device_node *busdn = bus->sysdata;
236 BUG_ON(busdn == NULL);
237 return PCI_DN(busdn)->phb;
240 extern void pcibios_free_controller(struct pci_controller *phb);
242 extern void isa_bridge_find_early(struct pci_controller *hose);
244 extern int pcibios_unmap_io_space(struct pci_bus *bus);
245 extern int pcibios_map_io_space(struct pci_bus *bus);
247 /* Return values for ppc_md.pci_probe_mode function */
248 #define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
249 #define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
250 #define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
253 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
255 #define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
258 #endif /* CONFIG_PPC64 */
260 /* Get the PCI host controller for an OF device */
261 extern struct pci_controller*
262 pci_find_hose_for_OF_device(struct device_node* node);
264 /* Fill up host controller resources from the OF node */
266 pci_process_bridge_OF_ranges(struct pci_controller *hose,
267 struct device_node *dev, int primary);
269 /* Allocate a new PCI host bridge structure */
270 extern struct pci_controller *
271 pcibios_alloc_controller(struct device_node *dev);
273 extern unsigned long pci_address_to_pio(phys_addr_t address);
275 static inline unsigned long pci_address_to_pio(phys_addr_t address)
277 return (unsigned long)-1;
283 #endif /* __KERNEL__ */