1 /* $Id: pgtable.h,v 1.156 2002/02/09 19:49:31 davem Exp $
2 * pgtable.h: SpitFire page table operations.
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
15 #include <asm-generic/pgtable-nopud.h>
17 #include <linux/config.h>
18 #include <linux/compiler.h>
19 #include <asm/types.h>
20 #include <asm/spitfire.h>
22 #include <asm/system.h>
24 #include <asm/processor.h>
25 #include <asm/const.h>
27 /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
28 * The page copy blockops can use 0x2000000 to 0x4000000.
29 * The TSB is mapped in the 0x4000000 to 0x6000000 range.
30 * The PROM resides in an area spanning 0xf0000000 to 0x100000000.
31 * The vmalloc area spans 0x100000000 to 0x200000000.
32 * Since modules need to be in the lowest 32-bits of the address space,
33 * we place them right before the OBP area from 0x10000000 to 0xf0000000.
34 * There is a single static kernel PMD which maps from 0x0 to address
37 #define TLBTEMP_BASE _AC(0x0000000002000000,UL)
38 #define TSBMAP_BASE _AC(0x0000000004000000,UL)
39 #define MODULES_VADDR _AC(0x0000000010000000,UL)
40 #define MODULES_LEN _AC(0x00000000e0000000,UL)
41 #define MODULES_END _AC(0x00000000f0000000,UL)
42 #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL)
43 #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL)
44 #define VMALLOC_START _AC(0x0000000100000000,UL)
45 #define VMALLOC_END _AC(0x0000000200000000,UL)
47 /* XXX All of this needs to be rethought so we can take advantage
48 * XXX cheetah's full 64-bit virtual address space, ie. no more hole
49 * XXX in the middle like on spitfire. -DaveM
52 * Given a virtual address, the lowest PAGE_SHIFT bits determine offset
53 * into the page; the next higher PAGE_SHIFT-3 bits determine the pte#
54 * in the proper pagetable (the -3 is from the 8 byte ptes, and each page
55 * table is a single page long). The next higher PMD_BITS determine pmd#
56 * in the proper pmdtable (where we must have PMD_BITS <= (PAGE_SHIFT-2)
57 * since the pmd entries are 4 bytes, and each pmd page is a single page
58 * long). Finally, the higher few bits determine pgde#.
61 /* PMD_SHIFT determines the size of the area a second-level page
64 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
65 #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT)
66 #define PMD_MASK (~(PMD_SIZE-1))
67 #define PMD_BITS (PAGE_SHIFT - 2)
69 /* PGDIR_SHIFT determines what a third-level page table entry can map */
70 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + PMD_BITS)
71 #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT)
72 #define PGDIR_MASK (~(PGDIR_SIZE-1))
73 #define PGDIR_BITS (PAGE_SHIFT - 2)
77 #include <linux/sched.h>
79 /* Entries per page directory level. */
80 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
81 #define PTRS_PER_PMD (1UL << PMD_BITS)
82 #define PTRS_PER_PGD (1UL << PGDIR_BITS)
84 /* Kernel has a separate 44bit address space. */
85 #define FIRST_USER_ADDRESS 0
87 #define pte_ERROR(e) __builtin_trap()
88 #define pmd_ERROR(e) __builtin_trap()
89 #define pgd_ERROR(e) __builtin_trap()
91 #endif /* !(__ASSEMBLY__) */
93 /* PTE bits which are the same in SUN4U and SUN4V format. */
94 #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */
95 #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/
97 /* SUN4U pte bits... */
98 #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */
99 #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */
100 #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */
101 #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */
102 #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */
103 #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */
104 #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */
105 #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */
106 #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */
107 #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */
108 #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */
109 #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */
110 #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */
111 #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */
112 #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */
113 #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */
114 #define _PAGE_FILE_4U _AC(0x0000000000000800,UL) /* Pagecache page */
115 #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */
116 #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */
117 #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */
118 #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */
119 #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */
120 #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */
121 #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */
122 #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */
123 #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */
124 #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */
126 /* SUN4V pte bits... */
127 #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */
128 #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */
129 #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */
130 #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */
131 #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */
132 #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */
133 #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */
134 #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */
135 #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */
136 #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */
137 #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */
138 #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */
139 #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */
140 #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */
141 #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */
142 #define _PAGE_FILE_4V _AC(0x0000000000000020,UL) /* Pagecache page */
143 #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */
144 #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */
145 #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */
146 #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */
147 #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */
148 #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */
149 #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */
150 #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */
151 #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */
152 #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */
155 #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U
156 #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V
157 #elif PAGE_SHIFT == 16
158 #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U
159 #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V
160 #elif PAGE_SHIFT == 19
161 #define _PAGE_SZBITS_4U _PAGE_SZ512K_4U
162 #define _PAGE_SZBITS_4V _PAGE_SZ512K_4V
163 #elif PAGE_SHIFT == 22
164 #define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U
165 #define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V
167 #error Wrong PAGE_SHIFT specified
170 #if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
171 #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U
172 #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V
173 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
174 #define _PAGE_SZHUGE_4U _PAGE_SZ512K_4U
175 #define _PAGE_SZHUGE_4V _PAGE_SZ512K_4V
176 #elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
177 #define _PAGE_SZHUGE_4U _PAGE_SZ64K_4U
178 #define _PAGE_SZHUGE_4V _PAGE_SZ64K_4V
181 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
182 #define __P000 __pgprot(0)
183 #define __P001 __pgprot(0)
184 #define __P010 __pgprot(0)
185 #define __P011 __pgprot(0)
186 #define __P100 __pgprot(0)
187 #define __P101 __pgprot(0)
188 #define __P110 __pgprot(0)
189 #define __P111 __pgprot(0)
191 #define __S000 __pgprot(0)
192 #define __S001 __pgprot(0)
193 #define __S010 __pgprot(0)
194 #define __S011 __pgprot(0)
195 #define __S100 __pgprot(0)
196 #define __S101 __pgprot(0)
197 #define __S110 __pgprot(0)
198 #define __S111 __pgprot(0)
202 extern pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long);
204 extern unsigned long pte_sz_bits(unsigned long size);
206 extern pgprot_t PAGE_KERNEL;
207 extern pgprot_t PAGE_KERNEL_LOCKED;
208 extern pgprot_t PAGE_COPY;
210 /* XXX This uglyness is for the atyfb driver's sparc mmap() support. XXX */
211 extern unsigned long _PAGE_IE;
212 extern unsigned long _PAGE_E;
213 extern unsigned long _PAGE_CACHE;
215 extern unsigned long pg_iobits;
216 extern unsigned long _PAGE_ALL_SZ_BITS;
217 extern unsigned long _PAGE_SZBITS;
219 extern unsigned long phys_base;
220 extern unsigned long pfn_base;
222 extern struct page *mem_map_zero;
223 #define ZERO_PAGE(vaddr) (mem_map_zero)
225 /* PFNs are real physical page numbers. However, mem_map only begins to record
226 * per-page information starting at pfn_base. This is to handle systems where
227 * the first physical page in the machine is at some huge physical address,
228 * such as 4GB. This is common on a partitioned E10000, for example.
230 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot)
232 unsigned long paddr = pfn << PAGE_SHIFT;
233 unsigned long sz_bits;
235 BUILD_BUG_ON(!__builtin_constant_p(_PAGE_SZBITS_4U) ||
236 !__builtin_constant_p(_PAGE_SZBITS_4V));
239 if (_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL) {
240 BUILD_BUG_ON((_PAGE_SZBITS_4U & ~(0xfffffc0000000000UL)) ||
241 (_PAGE_SZBITS_4V & ~(0x0000000000000fffUL)));
242 __asm__ __volatile__(
243 "\n661: sethi %uhi(%1), %0\n"
245 " .section .sun4v_2insn_patch, \"ax\"\n"
251 : "i" (_PAGE_SZBITS_4U), "i" (_PAGE_SZBITS_4V));
253 return __pte(paddr | sz_bits | pgprot_val(prot));
255 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
257 /* This one can be done with two shifts. */
258 static inline unsigned long pte_pfn(pte_t pte)
260 const unsigned long pte_paddr_shl_sun4u = 21;
261 const unsigned long pte_paddr_shr_sun4u = 21 + PAGE_SHIFT;
262 const unsigned long pte_paddr_shl_sun4v = 8;
263 const unsigned long pte_paddr_shr_sun4v = 8 + PAGE_SHIFT;
266 __asm__ __volatile__(
267 "\n661: sllx %1, %2, %0\n"
269 " .section .sun4v_2insn_patch, \"ax\"\n"
275 : "r" (pte_val(pte)),
276 "i" (pte_paddr_shl_sun4u), "i" (pte_paddr_shr_sun4u),
277 "i" (pte_paddr_shl_sun4v), "i" (pte_paddr_shr_sun4v));
281 #define pte_page(x) pfn_to_page(pte_pfn(x))
283 static inline pte_t pte_modify(pte_t pte, pgprot_t prot)
285 const unsigned long preserve_mask_sun4u = (_PAGE_PADDR_4U |
293 const unsigned long preserve_mask_sun4v = (_PAGE_PADDR_4V |
301 unsigned long mask, tmp;
303 /* SUN4U: 0x600307ffffffecb8 (negated == 0x9ffcf80000001347)
304 * SUN4V: 0x30ffffffffffee17 (negated == 0xcf000000000011e8)
306 * Even if we use negation tricks the result is still a 6
307 * instruction sequence, so don't try to play fancy and just
308 * do the most straightforward implementation.
310 * Note: We encode this into 3 sun4v 2-insn patch sequences.
313 __asm__ __volatile__(
314 "\n661: sethi %%uhi(%2), %1\n"
315 " sethi %%hi(%2), %0\n"
316 "\n662: or %1, %%ulo(%2), %1\n"
317 " or %0, %%lo(%2), %0\n"
318 "\n663: sllx %1, 32, %1\n"
320 " .section .sun4v_2insn_patch, \"ax\"\n"
322 " sethi %%uhi(%3), %1\n"
323 " sethi %%hi(%3), %0\n"
325 " or %1, %%ulo(%3), %1\n"
326 " or %0, %%lo(%3), %0\n"
331 : "=r" (mask), "=r" (tmp)
332 : "i" (preserve_mask_sun4u), "i" (preserve_mask_sun4v));
334 return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask));
337 static inline pte_t pgoff_to_pte(unsigned long off)
341 BUILD_BUG_ON((_PAGE_FILE_4U & ~0xfffUL) ||
342 (_PAGE_FILE_4V & ~0xfffUL));
344 __asm__ __volatile__(
345 "\n661: or %0, %2, %0\n"
346 " .section .sun4v_1insn_patch, \"ax\"\n"
351 : "0" (off), "i" (_PAGE_FILE_4U), "i" (_PAGE_FILE_4V));
356 static inline pgprot_t pgprot_noncached(pgprot_t prot)
358 unsigned long val = pgprot_val(prot);
360 BUILD_BUG_ON(((_PAGE_CP_4U | _PAGE_CP_4U | _PAGE_E_4U) & ~(0xfffUL)) ||
361 ((_PAGE_CP_4V | _PAGE_CP_4V | _PAGE_E_4V) & ~(0xfffUL)));
363 __asm__ __volatile__(
364 "\n661: andn %0, %2, %0\n"
366 " .section .sun4v_2insn_patch, \"ax\"\n"
372 : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U),
373 "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V));
375 return __pgprot(val);
377 /* Various pieces of code check for platform support by ifdef testing
378 * on "pgprot_noncached". That's broken and should be fixed, but for
381 #define pgprot_noncached pgprot_noncached
383 static inline pte_t pte_mkhuge(pte_t pte)
385 const unsigned long mask_4u = _PAGE_SZHUGE_4U;
386 const unsigned long mask_4v = _PAGE_SZHUGE_4V;
389 BUILD_BUG_ON((mask_4u & ~(0xfffffc0000000000UL)) ||
390 (mask_4v & ~(0xfffUL)));
392 __asm__ __volatile__(
393 "\n661: sethi %%uhi(%1), %0\n"
395 " .section .sun4v_2insn_patch, \"ax\"\n"
401 : "i" (mask_4u), "i" (mask_4v));
403 return __pte(pte_val(pte) | mask);
406 static inline pte_t pte_mkdirty(pte_t pte)
408 const unsigned long mask_4u = _PAGE_MODIFIED_4U | _PAGE_W_4U;
409 const unsigned long mask_4v = _PAGE_MODIFIED_4V | _PAGE_W_4V;
410 unsigned long val = pte_val(pte), tmp;
412 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
413 (mask_4v & ~(0xfffffc0000000fffUL)));
415 __asm__ __volatile__(
416 "\n661: or %0, %3, %0\n"
420 " .section .sun4v_2insn_patch, \"ax\"\n"
422 " sethi %%uhi(%4), %1\n"
425 " or %1, %%lo(%4), %1\n"
428 : "=r" (val), "=r" (tmp)
429 : "0" (val), "i" (mask_4u), "i" (mask_4v));
434 static inline pte_t pte_mkclean(pte_t pte)
436 const unsigned long mask_4u = _PAGE_MODIFIED_4U | _PAGE_W_4U;
437 const unsigned long mask_4v = _PAGE_MODIFIED_4V | _PAGE_W_4V;
438 unsigned long val = pte_val(pte), tmp;
440 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
441 (mask_4v & ~(0xfffffc0000000fffUL)));
443 __asm__ __volatile__(
444 "\n661: andn %0, %3, %0\n"
448 " .section .sun4v_2insn_patch, \"ax\"\n"
450 " sethi %%uhi(%4), %1\n"
453 " or %1, %%lo(%4), %1\n"
456 : "=r" (val), "=r" (tmp)
457 : "0" (val), "i" (mask_4u), "i" (mask_4v));
462 static inline pte_t pte_mkwrite(pte_t pte)
464 const unsigned long mask_4u = _PAGE_WRITE_4U;
465 const unsigned long mask_4v = _PAGE_WRITE_4V;
466 unsigned long val = pte_val(pte), mask;
468 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
469 (mask_4v & ~(0xfffffc0000000000UL)));
471 __asm__ __volatile__(
472 "\n661: mov %1, %0\n"
474 " .section .sun4v_2insn_patch, \"ax\"\n"
476 " sethi %%uhi(%2), %0\n"
480 : "i" (mask_4u), "i" (mask_4v));
482 return __pte(val | mask);
485 static inline pte_t pte_wrprotect(pte_t pte)
487 const unsigned long mask_4u = _PAGE_WRITE_4U | _PAGE_W_4U;
488 const unsigned long mask_4v = _PAGE_WRITE_4V | _PAGE_W_4V;
489 unsigned long val = pte_val(pte), tmp;
491 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
492 (mask_4v & ~(0xfffffc0000000fffUL)));
494 __asm__ __volatile__(
495 "\n661: andn %0, %3, %0\n"
499 " .section .sun4v_2insn_patch, \"ax\"\n"
501 " sethi %%uhi(%4), %1\n"
504 " or %1, %%lo(%4), %1\n"
507 : "=r" (val), "=r" (tmp)
508 : "0" (val), "i" (mask_4u), "i" (mask_4v));
513 static inline pte_t pte_mkold(pte_t pte)
515 const unsigned long mask_4u = _PAGE_ACCESSED_4U;
516 const unsigned long mask_4v = _PAGE_ACCESSED_4V;
519 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
520 (mask_4v & ~(0xfffffc0000000000UL)));
522 __asm__ __volatile__(
523 "\n661: mov %1, %0\n"
525 " .section .sun4v_2insn_patch, \"ax\"\n"
527 " sethi %%uhi(%2), %0\n"
531 : "i" (mask_4u), "i" (mask_4v));
535 return __pte(pte_val(pte) & ~mask);
538 static inline pte_t pte_mkyoung(pte_t pte)
540 const unsigned long mask_4u = _PAGE_ACCESSED_4U;
541 const unsigned long mask_4v = _PAGE_ACCESSED_4V;
544 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
545 (mask_4v & ~(0xfffffc0000000000UL)));
547 __asm__ __volatile__(
548 "\n661: mov %1, %0\n"
550 " .section .sun4v_2insn_patch, \"ax\"\n"
552 " sethi %%uhi(%2), %0\n"
556 : "i" (mask_4u), "i" (mask_4v));
560 return __pte(pte_val(pte) | mask);
563 static inline unsigned long pte_young(pte_t pte)
565 const unsigned long mask_4u = _PAGE_ACCESSED_4U;
566 const unsigned long mask_4v = _PAGE_ACCESSED_4V;
569 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
570 (mask_4v & ~(0xfffffc0000000000UL)));
572 __asm__ __volatile__(
573 "\n661: mov %1, %0\n"
575 " .section .sun4v_2insn_patch, \"ax\"\n"
577 " sethi %%uhi(%2), %0\n"
581 : "i" (mask_4u), "i" (mask_4v));
583 return (pte_val(pte) & mask);
586 static inline unsigned long pte_dirty(pte_t pte)
588 const unsigned long mask_4u = _PAGE_MODIFIED_4U;
589 const unsigned long mask_4v = _PAGE_MODIFIED_4V;
592 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
593 (mask_4v & ~(0xfffffc0000000000UL)));
595 __asm__ __volatile__(
596 "\n661: mov %1, %0\n"
598 " .section .sun4v_2insn_patch, \"ax\"\n"
600 " sethi %%uhi(%2), %0\n"
604 : "i" (mask_4u), "i" (mask_4v));
606 return (pte_val(pte) & mask);
609 static inline unsigned long pte_write(pte_t pte)
611 const unsigned long mask_4u = _PAGE_WRITE_4U;
612 const unsigned long mask_4v = _PAGE_WRITE_4V;
615 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
616 (mask_4v & ~(0xfffffc0000000000UL)));
618 __asm__ __volatile__(
619 "\n661: mov %1, %0\n"
621 " .section .sun4v_2insn_patch, \"ax\"\n"
623 " sethi %%uhi(%2), %0\n"
627 : "i" (mask_4u), "i" (mask_4v));
629 return (pte_val(pte) & mask);
632 static inline unsigned long pte_exec(pte_t pte)
634 const unsigned long mask_4u = _PAGE_EXEC_4U;
635 const unsigned long mask_4v = _PAGE_EXEC_4V;
638 BUILD_BUG_ON((mask_4u & ~(0x00000000fffffc00UL)) ||
639 (mask_4v & ~(0x0000000000000fffUL)));
641 __asm__ __volatile__(
642 "\n661: sethi %%hi(%1), %0\n"
643 " .section .sun4v_1insn_patch, \"ax\"\n"
648 : "i" (mask_4u), "i" (mask_4v));
650 return (pte_val(pte) & mask);
653 static inline unsigned long pte_read(pte_t pte)
655 const unsigned long mask_4u = _PAGE_READ_4U;
656 const unsigned long mask_4v = _PAGE_READ_4V;
659 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
660 (mask_4v & ~(0xfffffc0000000000UL)));
662 __asm__ __volatile__(
663 "\n661: mov %1, %0\n"
665 " .section .sun4v_2insn_patch, \"ax\"\n"
667 " sethi %%uhi(%2), %0\n"
671 : "i" (mask_4u), "i" (mask_4v));
673 return (pte_val(pte) & mask);
676 static inline unsigned long pte_file(pte_t pte)
678 const unsigned long mask_4u = _PAGE_FILE_4U;
679 const unsigned long mask_4v = _PAGE_FILE_4V;
680 unsigned long val = pte_val(pte);
682 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
683 (mask_4v & ~(0x0000000000000fffUL)));
685 __asm__ __volatile__(
686 "\n661: and %0, %2, %0\n"
687 " .section .sun4v_1insn_patch, \"ax\"\n"
692 : "0" (val), "i" (mask_4u), "i" (mask_4v));
697 static inline unsigned long pte_present(pte_t pte)
699 const unsigned long mask_4u = _PAGE_PRESENT_4U;
700 const unsigned long mask_4v = _PAGE_PRESENT_4V;
701 unsigned long val = pte_val(pte);
703 BUILD_BUG_ON((mask_4u & ~(0x0000000000000fffUL)) ||
704 (mask_4v & ~(0x0000000000000fffUL)));
706 __asm__ __volatile__(
707 "\n661: and %0, %2, %0\n"
708 " .section .sun4v_1insn_patch, \"ax\"\n"
713 : "0" (val), "i" (mask_4u), "i" (mask_4v));
718 #define pmd_set(pmdp, ptep) \
719 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
720 #define pud_set(pudp, pmdp) \
721 (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
722 #define __pmd_page(pmd) \
723 ((unsigned long) __va((((unsigned long)pmd_val(pmd))<<11UL)))
724 #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd))
725 #define pud_page(pud) \
726 ((unsigned long) __va((((unsigned long)pud_val(pud))<<11UL)))
727 #define pmd_none(pmd) (!pmd_val(pmd))
728 #define pmd_bad(pmd) (0)
729 #define pmd_present(pmd) (pmd_val(pmd) != 0U)
730 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0U)
731 #define pud_none(pud) (!pud_val(pud))
732 #define pud_bad(pud) (0)
733 #define pud_present(pud) (pud_val(pud) != 0U)
734 #define pud_clear(pudp) (pud_val(*(pudp)) = 0U)
736 /* Same in both SUN4V and SUN4U. */
737 #define pte_none(pte) (!pte_val(pte))
739 extern unsigned long pte_present(pte_t);
741 /* The following only work if pte_present() is true.
742 * Undefined behaviour if not..
744 extern unsigned long pte_read(pte_t);
745 extern unsigned long pte_exec(pte_t);
746 extern unsigned long pte_write(pte_t);
747 extern unsigned long pte_dirty(pte_t);
748 extern unsigned long pte_young(pte_t);
749 extern pte_t pte_wrprotect(pte_t);
750 extern pte_t pte_rdprotect(pte_t);
751 extern pte_t pte_mkclean(pte_t);
752 extern pte_t pte_mkold(pte_t);
754 /* Be very careful when you change these three, they are delicate. */
755 extern pte_t pte_mkyoung(pte_t);
756 extern pte_t pte_mkwrite(pte_t);
757 extern pte_t pte_mkdirty(pte_t);
758 extern pte_t pte_mkhuge(pte_t);
760 /* to find an entry in a page-table-directory. */
761 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
762 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
764 /* to find an entry in a kernel page-table-directory */
765 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
767 /* Find an entry in the second-level page table.. */
768 #define pmd_offset(pudp, address) \
769 ((pmd_t *) pud_page(*(pudp)) + \
770 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)))
772 /* Find an entry in the third-level page table.. */
773 #define pte_index(dir, address) \
774 ((pte_t *) __pmd_page(*(dir)) + \
775 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
776 #define pte_offset_kernel pte_index
777 #define pte_offset_map pte_index
778 #define pte_offset_map_nested pte_index
779 #define pte_unmap(pte) do { } while (0)
780 #define pte_unmap_nested(pte) do { } while (0)
782 /* Actual page table PTE updates. */
783 extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
785 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
791 /* It is more efficient to let flush_tlb_kernel_range()
792 * handle init_mm tlb flushes.
794 * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U
795 * and SUN4V pte layout, so this inline test is fine.
797 if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
798 tlb_batch_add(mm, addr, ptep, orig);
801 #define pte_clear(mm,addr,ptep) \
802 set_pte_at((mm), (addr), (ptep), __pte(0UL))
804 extern pgd_t swapper_pg_dir[2048];
805 extern pmd_t swapper_low_pmd_dir[2048];
807 extern void paging_init(void);
808 extern unsigned long find_ecache_flush_span(unsigned long size);
810 /* These do nothing with the way I have things setup. */
811 #define mmu_lockarea(vaddr, len) (vaddr)
812 #define mmu_unlockarea(vaddr, len) do { } while(0)
814 struct vm_area_struct;
815 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
817 /* Encode and de-code a swap entry */
818 #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL)
819 #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL))
820 #define __swp_entry(type, offset) \
823 (((long)(type) << PAGE_SHIFT) | \
824 ((long)(offset) << (PAGE_SHIFT + 8UL))) \
826 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
827 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
829 /* File offset in PTE support. */
830 extern unsigned long pte_file(pte_t);
831 #define pte_to_pgoff(pte) (pte_val(pte) >> PAGE_SHIFT)
832 extern pte_t pgoff_to_pte(unsigned long);
833 #define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
835 extern unsigned long prom_virt_to_phys(unsigned long, int *);
837 extern unsigned long sun4u_get_pte(unsigned long);
839 static inline unsigned long __get_phys(unsigned long addr)
841 return sun4u_get_pte(addr);
844 static inline int __get_iospace(unsigned long addr)
846 return ((sun4u_get_pte(addr) & 0xf0000000) >> 28);
849 extern unsigned long *sparc64_valid_addr_bitmap;
851 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
852 #define kern_addr_valid(addr) \
853 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
855 extern int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
857 unsigned long size, pgprot_t prot);
859 /* Clear virtual and physical cachability, set side-effect bit. */
860 extern pgprot_t pgprot_noncached(pgprot_t);
863 * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in
864 * its high 4 bits. These macros/functions put it there or get it from there.
866 #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4)))
867 #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4))
868 #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL)
870 #include <asm-generic/pgtable.h>
872 /* We provide our own get_unmapped_area to cope with VA holes for userland */
873 #define HAVE_ARCH_UNMAPPED_AREA
875 /* We provide a special get_unmapped_area for framebuffer mmaps to try and use
876 * the largest alignment possible such that larget PTEs can be used.
878 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long,
879 unsigned long, unsigned long,
881 #define HAVE_ARCH_FB_UNMAPPED_AREA
883 extern void pgtable_cache_init(void);
884 extern void sun4v_register_fault_status(void);
885 extern void sun4v_ktsb_register(void);
887 #endif /* !(__ASSEMBLY__) */
889 #endif /* !(_SPARC64_PGTABLE_H) */