include/asm-x86_64/spinlock.h

   1 #ifndef __ASM_SPINLOCK_H
   2 #define __ASM_SPINLOCK_H
   3
   4 #include <asm/atomic.h>
   5 #include <asm/rwlock.h>
   6 #include <asm/page.h>
   7
   8 /*
   9  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  10  *
  11  * Simple spin lock operations.  There are two variants, one clears IRQ's
  12  * on the local processor, one does not.
  13  *
  14  * We make no fairness assumptions. They have a cost.
  15  *
  16  * (the type definitions are in asm/spinlock_types.h)
  17  */
  18
  19 #define __raw_spin_is_locked(x) \
  20                 (*(volatile signed int *)(&(x)->slock) <= 0)
  21
  22 #define __raw_spin_lock_string \
  23         "\n1:\t" \
  24         LOCK_PREFIX " ; decl %0\n\t" \
  25         "jns 2f\n" \
  26         "3:\n" \
  27         "rep;nop\n\t" \
  28         "cmpl $0,%0\n\t" \
  29         "jle 3b\n\t" \
  30         "jmp 1b\n" \
  31         "2:\t" \
  32
  33 #define __raw_spin_lock_string_up \
  34         "\n\tdecl %0"
  35
  36 #define __raw_spin_unlock_string \
  37         "movl $1,%0" \
  38                 :"=m" (lock->slock) : : "memory"
  39
  40 static inline void __raw_spin_lock(raw_spinlock_t *lock)
  41 {
  42         asm volatile(__raw_spin_lock_string : "=m" (lock->slock) : : "memory");
  43 }
  44
  45 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  46
  47 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  48 {
  49         int oldval;
  50
  51         __asm__ __volatile__(
  52                 "xchgl %0,%1"
  53                 :"=q" (oldval), "=m" (lock->slock)
  54                 :"0" (0) : "memory");
  55
  56         return oldval > 0;
  57 }
  58
  59 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  60 {
  61         __asm__ __volatile__(
  62                 __raw_spin_unlock_string
  63         );
  64 }
  65
  66 #define __raw_spin_unlock_wait(lock) \
  67         do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
  68
  69 /*
  70  * Read-write spinlocks, allowing multiple readers
  71  * but only one writer.
  72  *
  73  * NOTE! it is quite common to have readers in interrupts
  74  * but no interrupt writers. For those circumstances we
  75  * can "mix" irq-safe locks - any writer needs to get a
  76  * irq-safe write-lock, but readers can get non-irqsafe
  77  * read-locks.
  78  *
  79  * On x86, we implement read-write locks as a 32-bit counter
  80  * with the high bit (sign) being the "contended" bit.
  81  */
  82
  83 #define __raw_read_can_lock(x)          ((int)(x)->lock > 0)
  84 #define __raw_write_can_lock(x)         ((x)->lock == RW_LOCK_BIAS)
  85
  86 static inline void __raw_read_lock(raw_rwlock_t *rw)
  87 {
  88         __build_read_lock(rw);
  89 }
  90
  91 static inline void __raw_write_lock(raw_rwlock_t *rw)
  92 {
  93         __build_write_lock(rw);
  94 }
  95
  96 static inline int __raw_read_trylock(raw_rwlock_t *lock)
  97 {
  98         atomic_t *count = (atomic_t *)lock;
  99         atomic_dec(count);
 100         if (atomic_read(count) >= 0)
 101                 return 1;
 102         atomic_inc(count);
 103         return 0;
 104 }
 105
 106 static inline int __raw_write_trylock(raw_rwlock_t *lock)
 107 {
 108         atomic_t *count = (atomic_t *)lock;
 109         if (atomic_sub_and_test(RW_LOCK_BIAS, count))
 110                 return 1;
 111         atomic_add(RW_LOCK_BIAS, count);
 112         return 0;
 113 }
 114
 115 static inline void __raw_read_unlock(raw_rwlock_t *rw)
 116 {
 117         asm volatile(LOCK_PREFIX " ; incl %0" :"=m" (rw->lock) : : "memory");
 118 }
 119
 120 static inline void __raw_write_unlock(raw_rwlock_t *rw)
 121 {
 122         asm volatile(LOCK_PREFIX " ; addl $" RW_LOCK_BIAS_STR ",%0"
 123                                 : "=m" (rw->lock) : : "memory");
 124 }
 125
 126 #endif /* __ASM_SPINLOCK_H */