include/dt-bindings/clock/r8a7790-clock.h

   1 /*
   2  * Copyright 2013 Ideas On Board SPRL
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  */
   9
  10 #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
  11 #define __DT_BINDINGS_CLOCK_R8A7790_H__
  12
  13 /* CPG */
  14 #define R8A7790_CLK_MAIN                0
  15 #define R8A7790_CLK_PLL0                1
  16 #define R8A7790_CLK_PLL1                2
  17 #define R8A7790_CLK_PLL3                3
  18 #define R8A7790_CLK_LB                  4
  19 #define R8A7790_CLK_QSPI                5
  20 #define R8A7790_CLK_SDH                 6
  21 #define R8A7790_CLK_SD0                 7
  22 #define R8A7790_CLK_SD1                 8
  23 #define R8A7790_CLK_Z                   9
  24
  25 /* MSTP0 */
  26 #define R8A7790_CLK_MSIOF0              0
  27
  28 /* MSTP1 */
  29 #define R8A7790_CLK_JPU         6
  30 #define R8A7790_CLK_TMU1                11
  31 #define R8A7790_CLK_TMU3                21
  32 #define R8A7790_CLK_TMU2                22
  33 #define R8A7790_CLK_CMT0                24
  34 #define R8A7790_CLK_TMU0                25
  35 #define R8A7790_CLK_VSP1_DU1            27
  36 #define R8A7790_CLK_VSP1_DU0            28
  37 #define R8A7790_CLK_VSP1_R              30
  38 #define R8A7790_CLK_VSP1_S              31
  39
  40 /* MSTP2 */
  41 #define R8A7790_CLK_SCIFA2              2
  42 #define R8A7790_CLK_SCIFA1              3
  43 #define R8A7790_CLK_SCIFA0              4
  44 #define R8A7790_CLK_MSIOF2              5
  45 #define R8A7790_CLK_SCIFB0              6
  46 #define R8A7790_CLK_SCIFB1              7
  47 #define R8A7790_CLK_MSIOF1              8
  48 #define R8A7790_CLK_MSIOF3              15
  49 #define R8A7790_CLK_SCIFB2              16
  50 #define R8A7790_CLK_SYS_DMAC1           18
  51 #define R8A7790_CLK_SYS_DMAC0           19
  52
  53 /* MSTP3 */
  54 #define R8A7790_CLK_IIC2                0
  55 #define R8A7790_CLK_TPU0                4
  56 #define R8A7790_CLK_MMCIF1              5
  57 #define R8A7790_CLK_SDHI3               11
  58 #define R8A7790_CLK_SDHI2               12
  59 #define R8A7790_CLK_SDHI1               13
  60 #define R8A7790_CLK_SDHI0               14
  61 #define R8A7790_CLK_MMCIF0              15
  62 #define R8A7790_CLK_IIC0                18
  63 #define R8A7790_CLK_PCIEC               19
  64 #define R8A7790_CLK_IIC1                23
  65 #define R8A7790_CLK_SSUSB               28
  66 #define R8A7790_CLK_CMT1                29
  67 #define R8A7790_CLK_USBDMAC0            30
  68 #define R8A7790_CLK_USBDMAC1            31
  69
  70 /* MSTP5 */
  71 #define R8A7790_CLK_THERMAL             22
  72 #define R8A7790_CLK_PWM                 23
  73
  74 /* MSTP7 */
  75 #define R8A7790_CLK_EHCI                3
  76 #define R8A7790_CLK_HSUSB               4
  77 #define R8A7790_CLK_HSCIF1              16
  78 #define R8A7790_CLK_HSCIF0              17
  79 #define R8A7790_CLK_SCIF1               20
  80 #define R8A7790_CLK_SCIF0               21
  81 #define R8A7790_CLK_DU2                 22
  82 #define R8A7790_CLK_DU1                 23
  83 #define R8A7790_CLK_DU0                 24
  84 #define R8A7790_CLK_LVDS1               25
  85 #define R8A7790_CLK_LVDS0               26
  86
  87 /* MSTP8 */
  88 #define R8A7790_CLK_VIN3                8
  89 #define R8A7790_CLK_VIN2                9
  90 #define R8A7790_CLK_VIN1                10
  91 #define R8A7790_CLK_VIN0                11
  92 #define R8A7790_CLK_ETHER               13
  93 #define R8A7790_CLK_SATA1               14
  94 #define R8A7790_CLK_SATA0               15
  95
  96 /* MSTP9 */
  97 #define R8A7790_CLK_GPIO5               7
  98 #define R8A7790_CLK_GPIO4               8
  99 #define R8A7790_CLK_GPIO3               9
 100 #define R8A7790_CLK_GPIO2               10
 101 #define R8A7790_CLK_GPIO1               11
 102 #define R8A7790_CLK_GPIO0               12
 103 #define R8A7790_CLK_RCAN1               15
 104 #define R8A7790_CLK_RCAN0               16
 105 #define R8A7790_CLK_QSPI_MOD            17
 106 #define R8A7790_CLK_IICDVFS             26
 107 #define R8A7790_CLK_I2C3                28
 108 #define R8A7790_CLK_I2C2                29
 109 #define R8A7790_CLK_I2C1                30
 110 #define R8A7790_CLK_I2C0                31
 111
 112 /* MSTP10 */
 113 #define R8A7790_CLK_SSI_ALL             5
 114 #define R8A7790_CLK_SSI9                6
 115 #define R8A7790_CLK_SSI8                7
 116 #define R8A7790_CLK_SSI7                8
 117 #define R8A7790_CLK_SSI6                9
 118 #define R8A7790_CLK_SSI5                10
 119 #define R8A7790_CLK_SSI4                11
 120 #define R8A7790_CLK_SSI3                12
 121 #define R8A7790_CLK_SSI2                13
 122 #define R8A7790_CLK_SSI1                14
 123 #define R8A7790_CLK_SSI0                15
 124 #define R8A7790_CLK_SCU_ALL             17
 125 #define R8A7790_CLK_SCU_DVC1            18
 126 #define R8A7790_CLK_SCU_DVC0            19
 127 #define R8A7790_CLK_SCU_SRC9            22
 128 #define R8A7790_CLK_SCU_SRC8            23
 129 #define R8A7790_CLK_SCU_SRC7            24
 130 #define R8A7790_CLK_SCU_SRC6            25
 131 #define R8A7790_CLK_SCU_SRC5            26
 132 #define R8A7790_CLK_SCU_SRC4            27
 133 #define R8A7790_CLK_SCU_SRC3            28
 134 #define R8A7790_CLK_SCU_SRC2            29
 135 #define R8A7790_CLK_SCU_SRC1            30
 136 #define R8A7790_CLK_SCU_SRC0            31
 137
 138 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */