2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #ifndef __ASM_ARM_KVM_VGIC_H
20 #define __ASM_ARM_KVM_VGIC_H
22 #include <linux/kernel.h>
23 #include <linux/kvm.h>
24 #include <linux/irqreturn.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
28 #define VGIC_NR_IRQS 256
29 #define VGIC_NR_SGIS 16
30 #define VGIC_NR_PPIS 16
31 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
32 #define VGIC_NR_SHARED_IRQS (VGIC_NR_IRQS - VGIC_NR_PRIVATE_IRQS)
33 #define VGIC_MAX_CPUS KVM_MAX_VCPUS
35 #define VGIC_V2_MAX_LRS (1 << 6)
36 #define VGIC_V3_MAX_LRS 16
38 /* Sanity checks... */
39 #if (VGIC_MAX_CPUS > 8)
40 #error Invalid number of CPU interfaces
43 #if (VGIC_NR_IRQS & 31)
44 #error "VGIC_NR_IRQS must be a multiple of 32"
47 #if (VGIC_NR_IRQS > 1024)
48 #error "VGIC_NR_IRQS must be <= 1024"
52 * The GIC distributor registers describing interrupts have two parts:
53 * - 32 per-CPU interrupts (SGI + PPI)
54 * - a bunch of shared interrupts (SPI)
58 u32 reg[VGIC_NR_PRIVATE_IRQS / 32];
59 DECLARE_BITMAP(reg_ul, VGIC_NR_PRIVATE_IRQS);
60 } percpu[VGIC_MAX_CPUS];
62 u32 reg[VGIC_NR_SHARED_IRQS / 32];
63 DECLARE_BITMAP(reg_ul, VGIC_NR_SHARED_IRQS);
68 u32 percpu[VGIC_MAX_CPUS][VGIC_NR_PRIVATE_IRQS / 4];
69 u32 shared[VGIC_NR_SHARED_IRQS / 4];
75 VGIC_V2, /* Good ol' GICv2 */
76 VGIC_V3, /* New fancy GICv3 */
79 #define LR_STATE_PENDING (1 << 0)
80 #define LR_STATE_ACTIVE (1 << 1)
81 #define LR_STATE_MASK (3 << 0)
82 #define LR_EOI_INT (1 << 2)
98 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
99 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
100 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
101 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
102 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
103 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
104 void (*enable_underflow)(struct kvm_vcpu *vcpu);
105 void (*disable_underflow)(struct kvm_vcpu *vcpu);
106 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
107 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
108 void (*enable)(struct kvm_vcpu *vcpu);
114 /* Physical address of vgic virtual cpu interface */
115 phys_addr_t vcpu_base;
116 /* Number of list registers */
118 /* Interrupt number */
119 unsigned int maint_irq;
120 /* Virtual control interface base address */
121 void __iomem *vctrl_base;
125 #ifdef CONFIG_KVM_ARM_VGIC
130 /* Virtual control interface mapping */
131 void __iomem *vctrl_base;
133 /* Distributor and vcpu interface mapping in the guest */
134 phys_addr_t vgic_dist_base;
135 phys_addr_t vgic_cpu_base;
137 /* Distributor enabled */
140 /* Interrupt enabled (one bit per IRQ) */
141 struct vgic_bitmap irq_enabled;
143 /* Interrupt 'pin' level */
144 struct vgic_bitmap irq_state;
146 /* Level-triggered interrupt in progress */
147 struct vgic_bitmap irq_active;
149 /* Interrupt priority. Not used yet. */
150 struct vgic_bytemap irq_priority;
152 /* Level/edge triggered */
153 struct vgic_bitmap irq_cfg;
155 /* Source CPU per SGI and target CPU */
156 u8 irq_sgi_sources[VGIC_MAX_CPUS][VGIC_NR_SGIS];
158 /* Target CPU for each IRQ */
159 u8 irq_spi_cpu[VGIC_NR_SHARED_IRQS];
160 struct vgic_bitmap irq_spi_target[VGIC_MAX_CPUS];
162 /* Bitmap indicating which CPU has something pending */
163 unsigned long irq_pending_on_cpu;
167 struct vgic_v2_cpu_if {
170 u32 vgic_misr; /* Saved only */
171 u32 vgic_eisr[2]; /* Saved only */
172 u32 vgic_elrsr[2]; /* Saved only */
174 u32 vgic_lr[VGIC_V2_MAX_LRS];
177 struct vgic_v3_cpu_if {
178 #ifdef CONFIG_ARM_GIC_V3
181 u32 vgic_misr; /* Saved only */
182 u32 vgic_eisr; /* Saved only */
183 u32 vgic_elrsr; /* Saved only */
186 u64 vgic_lr[VGIC_V3_MAX_LRS];
191 #ifdef CONFIG_KVM_ARM_VGIC
192 /* per IRQ to LR mapping */
193 u8 vgic_irq_lr_map[VGIC_NR_IRQS];
195 /* Pending interrupts on this VCPU */
196 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
197 DECLARE_BITMAP( pending_shared, VGIC_NR_SHARED_IRQS);
199 /* Bitmap of used/free list registers */
200 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
202 /* Number of list registers on this CPU */
205 /* CPU vif control registers for world switch */
207 struct vgic_v2_cpu_if vgic_v2;
208 struct vgic_v3_cpu_if vgic_v3;
213 #define LR_EMPTY 0xff
215 #define INT_STATUS_EOI (1 << 0)
216 #define INT_STATUS_UNDERFLOW (1 << 1)
221 struct kvm_exit_mmio;
223 #ifdef CONFIG_KVM_ARM_VGIC
224 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
225 int kvm_vgic_hyp_init(void);
226 int kvm_vgic_init(struct kvm *kvm);
227 int kvm_vgic_create(struct kvm *kvm);
228 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
229 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
230 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
231 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
233 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
234 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
235 struct kvm_exit_mmio *mmio);
237 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
238 #define vgic_initialized(k) ((k)->arch.vgic.ready)
240 int vgic_v2_probe(struct device_node *vgic_node,
241 const struct vgic_ops **ops,
242 const struct vgic_params **params);
243 #ifdef CONFIG_ARM_GIC_V3
244 int vgic_v3_probe(struct device_node *vgic_node,
245 const struct vgic_ops **ops,
246 const struct vgic_params **params);
248 static inline int vgic_v3_probe(struct device_node *vgic_node,
249 const struct vgic_ops **ops,
250 const struct vgic_params **params)
257 static inline int kvm_vgic_hyp_init(void)
262 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
267 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
272 static inline int kvm_vgic_init(struct kvm *kvm)
277 static inline int kvm_vgic_create(struct kvm *kvm)
282 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
287 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
288 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
290 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
291 unsigned int irq_num, bool level)
296 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
301 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
302 struct kvm_exit_mmio *mmio)
307 static inline int irqchip_in_kernel(struct kvm *kvm)
312 static inline bool vgic_initialized(struct kvm *kvm)