spi/topcliff-pch: Fix Kconfig dependencies
[cascardo/linux.git] / include / linux / mlx4 / qp.h
1 /*
2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32
33 #ifndef MLX4_QP_H
34 #define MLX4_QP_H
35
36 #include <linux/types.h>
37 #include <linux/if_ether.h>
38
39 #include <linux/mlx4/device.h>
40
41 #define MLX4_INVALID_LKEY       0x100
42
43 enum mlx4_qp_optpar {
44         MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
45         MLX4_QP_OPTPAR_RRE                      = 1 << 1,
46         MLX4_QP_OPTPAR_RAE                      = 1 << 2,
47         MLX4_QP_OPTPAR_RWE                      = 1 << 3,
48         MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
49         MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
50         MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
51         MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
52         MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
53         MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
54         MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
55         MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
56         MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
57         MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
58         MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
59         MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20
60 };
61
62 enum mlx4_qp_state {
63         MLX4_QP_STATE_RST                       = 0,
64         MLX4_QP_STATE_INIT                      = 1,
65         MLX4_QP_STATE_RTR                       = 2,
66         MLX4_QP_STATE_RTS                       = 3,
67         MLX4_QP_STATE_SQER                      = 4,
68         MLX4_QP_STATE_SQD                       = 5,
69         MLX4_QP_STATE_ERR                       = 6,
70         MLX4_QP_STATE_SQ_DRAINING               = 7,
71         MLX4_QP_NUM_STATE
72 };
73
74 enum {
75         MLX4_QP_ST_RC                           = 0x0,
76         MLX4_QP_ST_UC                           = 0x1,
77         MLX4_QP_ST_RD                           = 0x2,
78         MLX4_QP_ST_UD                           = 0x3,
79         MLX4_QP_ST_XRC                          = 0x6,
80         MLX4_QP_ST_MLX                          = 0x7
81 };
82
83 enum {
84         MLX4_QP_PM_MIGRATED                     = 0x3,
85         MLX4_QP_PM_ARMED                        = 0x0,
86         MLX4_QP_PM_REARM                        = 0x1
87 };
88
89 enum {
90         /* params1 */
91         MLX4_QP_BIT_SRE                         = 1 << 15,
92         MLX4_QP_BIT_SWE                         = 1 << 14,
93         MLX4_QP_BIT_SAE                         = 1 << 13,
94         /* params2 */
95         MLX4_QP_BIT_RRE                         = 1 << 15,
96         MLX4_QP_BIT_RWE                         = 1 << 14,
97         MLX4_QP_BIT_RAE                         = 1 << 13,
98         MLX4_QP_BIT_RIC                         = 1 <<  4,
99 };
100
101 enum {
102         MLX4_RSS_HASH_XOR                       = 0,
103         MLX4_RSS_HASH_TOP                       = 1,
104
105         MLX4_RSS_UDP_IPV6                       = 1 << 0,
106         MLX4_RSS_UDP_IPV4                       = 1 << 1,
107         MLX4_RSS_TCP_IPV6                       = 1 << 2,
108         MLX4_RSS_IPV6                           = 1 << 3,
109         MLX4_RSS_TCP_IPV4                       = 1 << 4,
110         MLX4_RSS_IPV4                           = 1 << 5,
111
112         MLX4_RSS_BY_OUTER_HEADERS               = 0 << 6,
113         MLX4_RSS_BY_INNER_HEADERS               = 2 << 6,
114         MLX4_RSS_BY_INNER_HEADERS_IPONLY        = 3 << 6,
115
116         /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
117         MLX4_RSS_OFFSET_IN_QPC_PRI_PATH         = 0x24,
118         /* offset of being RSS indirection QP within mlx4_qp_context.flags */
119         MLX4_RSS_QPC_FLAG_OFFSET                = 13,
120 };
121
122 struct mlx4_rss_context {
123         __be32                  base_qpn;
124         __be32                  default_qpn;
125         u16                     reserved;
126         u8                      hash_fn;
127         u8                      flags;
128         __be32                  rss_key[10];
129         __be32                  base_qpn_udp;
130 };
131
132 struct mlx4_qp_path {
133         u8                      fl;
134         u8                      vlan_control;
135         u8                      disable_pkey_check;
136         u8                      pkey_index;
137         u8                      counter_index;
138         u8                      grh_mylmc;
139         __be16                  rlid;
140         u8                      ackto;
141         u8                      mgid_index;
142         u8                      static_rate;
143         u8                      hop_limit;
144         __be32                  tclass_flowlabel;
145         u8                      rgid[16];
146         u8                      sched_queue;
147         u8                      vlan_index;
148         u8                      feup;
149         u8                      fvl_rx;
150         u8                      reserved4[2];
151         u8                      dmac[ETH_ALEN];
152 };
153
154 enum { /* fl */
155         MLX4_FL_CV      = 1 << 6,
156         MLX4_FL_ETH_HIDE_CQE_VLAN       = 1 << 2
157 };
158 enum { /* vlan_control */
159         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED      = 1 << 6,
160         MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
161         MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED    = 1 << 4,
162         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED      = 1 << 2,
163         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
164         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED    = 1 << 0
165 };
166
167 enum { /* feup */
168         MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
169         MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
170         MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
171 };
172
173 enum { /* fvl_rx */
174         MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
175 };
176
177 struct mlx4_qp_context {
178         __be32                  flags;
179         __be32                  pd;
180         u8                      mtu_msgmax;
181         u8                      rq_size_stride;
182         u8                      sq_size_stride;
183         u8                      rlkey;
184         __be32                  usr_page;
185         __be32                  local_qpn;
186         __be32                  remote_qpn;
187         struct                  mlx4_qp_path pri_path;
188         struct                  mlx4_qp_path alt_path;
189         __be32                  params1;
190         u32                     reserved1;
191         __be32                  next_send_psn;
192         __be32                  cqn_send;
193         u32                     reserved2[2];
194         __be32                  last_acked_psn;
195         __be32                  ssn;
196         __be32                  params2;
197         __be32                  rnr_nextrecvpsn;
198         __be32                  xrcd;
199         __be32                  cqn_recv;
200         __be64                  db_rec_addr;
201         __be32                  qkey;
202         __be32                  srqn;
203         __be32                  msn;
204         __be16                  rq_wqe_counter;
205         __be16                  sq_wqe_counter;
206         u32                     reserved3[2];
207         __be32                  param3;
208         __be32                  nummmcpeers_basemkey;
209         u8                      log_page_size;
210         u8                      reserved4[2];
211         u8                      mtt_base_addr_h;
212         __be32                  mtt_base_addr_l;
213         u32                     reserved5[10];
214 };
215
216 struct mlx4_update_qp_context {
217         __be64                  qp_mask;
218         __be64                  primary_addr_path_mask;
219         __be64                  secondary_addr_path_mask;
220         u64                     reserved1;
221         struct mlx4_qp_context  qp_context;
222         u64                     reserved2[58];
223 };
224
225 enum {
226         MLX4_UPD_QP_MASK_PM_STATE       = 32,
227         MLX4_UPD_QP_MASK_VSD            = 33,
228 };
229
230 enum {
231         MLX4_UPD_QP_PATH_MASK_PKEY_INDEX                = 0 + 32,
232         MLX4_UPD_QP_PATH_MASK_FSM                       = 1 + 32,
233         MLX4_UPD_QP_PATH_MASK_MAC_INDEX                 = 2 + 32,
234         MLX4_UPD_QP_PATH_MASK_FVL                       = 3 + 32,
235         MLX4_UPD_QP_PATH_MASK_CV                        = 4 + 32,
236         MLX4_UPD_QP_PATH_MASK_VLAN_INDEX                = 5 + 32,
237         MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN         = 6 + 32,
238         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED     = 7 + 32,
239         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P           = 8 + 32,
240         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED       = 9 + 32,
241         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED     = 10 + 32,
242         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P           = 11 + 32,
243         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED       = 12 + 32,
244         MLX4_UPD_QP_PATH_MASK_FEUP                      = 13 + 32,
245         MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE               = 14 + 32,
246         MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX          = 15 + 32,
247         MLX4_UPD_QP_PATH_MASK_FVL_RX                    = 16 + 32,
248 };
249
250 enum { /* param3 */
251         MLX4_STRIP_VLAN = 1 << 30
252 };
253
254 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
255 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
256
257 enum {
258         MLX4_WQE_CTRL_NEC               = 1 << 29,
259         MLX4_WQE_CTRL_IIP               = 1 << 28,
260         MLX4_WQE_CTRL_ILP               = 1 << 27,
261         MLX4_WQE_CTRL_FENCE             = 1 << 6,
262         MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
263         MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
264         MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
265         MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
266         MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
267         MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
268         MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
269 };
270
271 struct mlx4_wqe_ctrl_seg {
272         __be32                  owner_opcode;
273         union {
274                 struct {
275                         __be16                  vlan_tag;
276                         u8                      ins_vlan;
277                         u8                      fence_size;
278                 };
279                 __be32                  bf_qpn;
280         };
281         /*
282          * High 24 bits are SRC remote buffer; low 8 bits are flags:
283          * [7]   SO (strong ordering)
284          * [5]   TCP/UDP checksum
285          * [4]   IP checksum
286          * [3:2] C (generate completion queue entry)
287          * [1]   SE (solicited event)
288          * [0]   FL (force loopback)
289          */
290         union {
291                 __be32                  srcrb_flags;
292                 __be16                  srcrb_flags16[2];
293         };
294         /*
295          * imm is immediate data for send/RDMA write w/ immediate;
296          * also invalidation key for send with invalidate; input
297          * modifier for WQEs on CCQs.
298          */
299         __be32                  imm;
300 };
301
302 enum {
303         MLX4_WQE_MLX_VL15       = 1 << 17,
304         MLX4_WQE_MLX_SLR        = 1 << 16
305 };
306
307 struct mlx4_wqe_mlx_seg {
308         u8                      owner;
309         u8                      reserved1[2];
310         u8                      opcode;
311         __be16                  sched_prio;
312         u8                      reserved2;
313         u8                      size;
314         /*
315          * [17]    VL15
316          * [16]    SLR
317          * [15:12] static rate
318          * [11:8]  SL
319          * [4]     ICRC
320          * [3:2]   C
321          * [0]     FL (force loopback)
322          */
323         __be32                  flags;
324         __be16                  rlid;
325         u16                     reserved3;
326 };
327
328 struct mlx4_wqe_datagram_seg {
329         __be32                  av[8];
330         __be32                  dqpn;
331         __be32                  qkey;
332         __be16                  vlan;
333         u8                      mac[ETH_ALEN];
334 };
335
336 struct mlx4_wqe_lso_seg {
337         __be32                  mss_hdr_size;
338         __be32                  header[0];
339 };
340
341 enum mlx4_wqe_bind_seg_flags2 {
342         MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
343         MLX4_WQE_BIND_TYPE_2     = (1 << 31),
344 };
345
346 struct mlx4_wqe_bind_seg {
347         __be32                  flags1;
348         __be32                  flags2;
349         __be32                  new_rkey;
350         __be32                  lkey;
351         __be64                  addr;
352         __be64                  length;
353 };
354
355 enum {
356         MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
357         MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
358         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  = 1 << 29,
359         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
360         MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC       = 1 << 31
361 };
362
363 struct mlx4_wqe_fmr_seg {
364         __be32                  flags;
365         __be32                  mem_key;
366         __be64                  buf_list;
367         __be64                  start_addr;
368         __be64                  reg_len;
369         __be32                  offset;
370         __be32                  page_size;
371         u32                     reserved[2];
372 };
373
374 struct mlx4_wqe_fmr_ext_seg {
375         u8                      flags;
376         u8                      reserved;
377         __be16                  app_mask;
378         __be16                  wire_app_tag;
379         __be16                  mem_app_tag;
380         __be32                  wire_ref_tag_base;
381         __be32                  mem_ref_tag_base;
382 };
383
384 struct mlx4_wqe_local_inval_seg {
385         u64                     reserved1;
386         __be32                  mem_key;
387         u32                     reserved2;
388         u64                     reserved3[2];
389 };
390
391 struct mlx4_wqe_raddr_seg {
392         __be64                  raddr;
393         __be32                  rkey;
394         u32                     reserved;
395 };
396
397 struct mlx4_wqe_atomic_seg {
398         __be64                  swap_add;
399         __be64                  compare;
400 };
401
402 struct mlx4_wqe_masked_atomic_seg {
403         __be64                  swap_add;
404         __be64                  compare;
405         __be64                  swap_add_mask;
406         __be64                  compare_mask;
407 };
408
409 struct mlx4_wqe_data_seg {
410         __be32                  byte_count;
411         __be32                  lkey;
412         __be64                  addr;
413 };
414
415 enum {
416         MLX4_INLINE_ALIGN       = 64,
417         MLX4_INLINE_SEG         = 1 << 31,
418 };
419
420 struct mlx4_wqe_inline_seg {
421         __be32                  byte_count;
422 };
423
424 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
425                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
426                    struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
427                    int sqd_event, struct mlx4_qp *qp);
428
429 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
430                   struct mlx4_qp_context *context);
431
432 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
433                      struct mlx4_qp_context *context,
434                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
435
436 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
437 {
438         return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
439 }
440
441 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
442
443 #endif /* MLX4_QP_H */