include/linux/mlx4/qp.h

   1 /*
   2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX4_QP_H
  34 #define MLX4_QP_H
  35
  36 #include <linux/types.h>
  37 #include <linux/if_ether.h>
  38
  39 #include <linux/mlx4/device.h>
  40
  41 #define MLX4_INVALID_LKEY       0x100
  42
  43 enum mlx4_qp_optpar {
  44         MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
  45         MLX4_QP_OPTPAR_RRE                      = 1 << 1,
  46         MLX4_QP_OPTPAR_RAE                      = 1 << 2,
  47         MLX4_QP_OPTPAR_RWE                      = 1 << 3,
  48         MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
  49         MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
  50         MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
  51         MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
  52         MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
  53         MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
  54         MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
  55         MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
  56         MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
  57         MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
  58         MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
  59         MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20,
  60         MLX4_QP_OPTPAR_VLAN_STRIPPING           = 1 << 21,
  61 };
  62
  63 enum mlx4_qp_state {
  64         MLX4_QP_STATE_RST                       = 0,
  65         MLX4_QP_STATE_INIT                      = 1,
  66         MLX4_QP_STATE_RTR                       = 2,
  67         MLX4_QP_STATE_RTS                       = 3,
  68         MLX4_QP_STATE_SQER                      = 4,
  69         MLX4_QP_STATE_SQD                       = 5,
  70         MLX4_QP_STATE_ERR                       = 6,
  71         MLX4_QP_STATE_SQ_DRAINING               = 7,
  72         MLX4_QP_NUM_STATE
  73 };
  74
  75 enum {
  76         MLX4_QP_ST_RC                           = 0x0,
  77         MLX4_QP_ST_UC                           = 0x1,
  78         MLX4_QP_ST_RD                           = 0x2,
  79         MLX4_QP_ST_UD                           = 0x3,
  80         MLX4_QP_ST_XRC                          = 0x6,
  81         MLX4_QP_ST_MLX                          = 0x7
  82 };
  83
  84 enum {
  85         MLX4_QP_PM_MIGRATED                     = 0x3,
  86         MLX4_QP_PM_ARMED                        = 0x0,
  87         MLX4_QP_PM_REARM                        = 0x1
  88 };
  89
  90 enum {
  91         /* params1 */
  92         MLX4_QP_BIT_SRE                         = 1 << 15,
  93         MLX4_QP_BIT_SWE                         = 1 << 14,
  94         MLX4_QP_BIT_SAE                         = 1 << 13,
  95         /* params2 */
  96         MLX4_QP_BIT_RRE                         = 1 << 15,
  97         MLX4_QP_BIT_RWE                         = 1 << 14,
  98         MLX4_QP_BIT_RAE                         = 1 << 13,
  99         MLX4_QP_BIT_RIC                         = 1 <<  4,
 100 };
 101
 102 enum {
 103         MLX4_RSS_HASH_XOR                       = 0,
 104         MLX4_RSS_HASH_TOP                       = 1,
 105
 106         MLX4_RSS_UDP_IPV6                       = 1 << 0,
 107         MLX4_RSS_UDP_IPV4                       = 1 << 1,
 108         MLX4_RSS_TCP_IPV6                       = 1 << 2,
 109         MLX4_RSS_IPV6                           = 1 << 3,
 110         MLX4_RSS_TCP_IPV4                       = 1 << 4,
 111         MLX4_RSS_IPV4                           = 1 << 5,
 112
 113         MLX4_RSS_BY_OUTER_HEADERS               = 0 << 6,
 114         MLX4_RSS_BY_INNER_HEADERS               = 2 << 6,
 115         MLX4_RSS_BY_INNER_HEADERS_IPONLY        = 3 << 6,
 116
 117         /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
 118         MLX4_RSS_OFFSET_IN_QPC_PRI_PATH         = 0x24,
 119         /* offset of being RSS indirection QP within mlx4_qp_context.flags */
 120         MLX4_RSS_QPC_FLAG_OFFSET                = 13,
 121 };
 122
 123 #define MLX4_EN_RSS_KEY_SIZE 40
 124
 125 struct mlx4_rss_context {
 126         __be32                  base_qpn;
 127         __be32                  default_qpn;
 128         u16                     reserved;
 129         u8                      hash_fn;
 130         u8                      flags;
 131         __be32                  rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
 132         __be32                  base_qpn_udp;
 133 };
 134
 135 struct mlx4_qp_path {
 136         u8                      fl;
 137         u8                      vlan_control;
 138         u8                      disable_pkey_check;
 139         u8                      pkey_index;
 140         u8                      counter_index;
 141         u8                      grh_mylmc;
 142         __be16                  rlid;
 143         u8                      ackto;
 144         u8                      mgid_index;
 145         u8                      static_rate;
 146         u8                      hop_limit;
 147         __be32                  tclass_flowlabel;
 148         u8                      rgid[16];
 149         u8                      sched_queue;
 150         u8                      vlan_index;
 151         u8                      feup;
 152         u8                      fvl_rx;
 153         u8                      reserved4[2];
 154         u8                      dmac[ETH_ALEN];
 155 };
 156
 157 enum { /* fl */
 158         MLX4_FL_CV      = 1 << 6,
 159         MLX4_FL_ETH_HIDE_CQE_VLAN       = 1 << 2
 160 };
 161 enum { /* vlan_control */
 162         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED      = 1 << 6,
 163         MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
 164         MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED    = 1 << 4,
 165         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED      = 1 << 2,
 166         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
 167         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED    = 1 << 0
 168 };
 169
 170 enum { /* feup */
 171         MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
 172         MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
 173         MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
 174 };
 175
 176 enum { /* fvl_rx */
 177         MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
 178 };
 179
 180 struct mlx4_qp_context {
 181         __be32                  flags;
 182         __be32                  pd;
 183         u8                      mtu_msgmax;
 184         u8                      rq_size_stride;
 185         u8                      sq_size_stride;
 186         u8                      rlkey;
 187         __be32                  usr_page;
 188         __be32                  local_qpn;
 189         __be32                  remote_qpn;
 190         struct                  mlx4_qp_path pri_path;
 191         struct                  mlx4_qp_path alt_path;
 192         __be32                  params1;
 193         u32                     reserved1;
 194         __be32                  next_send_psn;
 195         __be32                  cqn_send;
 196         u32                     reserved2[2];
 197         __be32                  last_acked_psn;
 198         __be32                  ssn;
 199         __be32                  params2;
 200         __be32                  rnr_nextrecvpsn;
 201         __be32                  xrcd;
 202         __be32                  cqn_recv;
 203         __be64                  db_rec_addr;
 204         __be32                  qkey;
 205         __be32                  srqn;
 206         __be32                  msn;
 207         __be16                  rq_wqe_counter;
 208         __be16                  sq_wqe_counter;
 209         u32                     reserved3[2];
 210         __be32                  param3;
 211         __be32                  nummmcpeers_basemkey;
 212         u8                      log_page_size;
 213         u8                      reserved4[2];
 214         u8                      mtt_base_addr_h;
 215         __be32                  mtt_base_addr_l;
 216         u32                     reserved5[10];
 217 };
 218
 219 struct mlx4_update_qp_context {
 220         __be64                  qp_mask;
 221         __be64                  primary_addr_path_mask;
 222         __be64                  secondary_addr_path_mask;
 223         u64                     reserved1;
 224         struct mlx4_qp_context  qp_context;
 225         u64                     reserved2[58];
 226 };
 227
 228 enum {
 229         MLX4_UPD_QP_MASK_PM_STATE       = 32,
 230         MLX4_UPD_QP_MASK_VSD            = 33,
 231 };
 232
 233 enum {
 234         MLX4_UPD_QP_PATH_MASK_PKEY_INDEX                = 0 + 32,
 235         MLX4_UPD_QP_PATH_MASK_FSM                       = 1 + 32,
 236         MLX4_UPD_QP_PATH_MASK_MAC_INDEX                 = 2 + 32,
 237         MLX4_UPD_QP_PATH_MASK_FVL                       = 3 + 32,
 238         MLX4_UPD_QP_PATH_MASK_CV                        = 4 + 32,
 239         MLX4_UPD_QP_PATH_MASK_VLAN_INDEX                = 5 + 32,
 240         MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN         = 6 + 32,
 241         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED     = 7 + 32,
 242         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P           = 8 + 32,
 243         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED       = 9 + 32,
 244         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED     = 10 + 32,
 245         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P           = 11 + 32,
 246         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED       = 12 + 32,
 247         MLX4_UPD_QP_PATH_MASK_FEUP                      = 13 + 32,
 248         MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE               = 14 + 32,
 249         MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX          = 15 + 32,
 250         MLX4_UPD_QP_PATH_MASK_FVL_RX                    = 16 + 32,
 251 };
 252
 253 enum { /* param3 */
 254         MLX4_STRIP_VLAN = 1 << 30
 255 };
 256
 257 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
 258 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
 259
 260 enum {
 261         MLX4_WQE_CTRL_NEC               = 1 << 29,
 262         MLX4_WQE_CTRL_IIP               = 1 << 28,
 263         MLX4_WQE_CTRL_ILP               = 1 << 27,
 264         MLX4_WQE_CTRL_FENCE             = 1 << 6,
 265         MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
 266         MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
 267         MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
 268         MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
 269         MLX4_WQE_CTRL_INS_VLAN          = 1 << 6,
 270         MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
 271         MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
 272 };
 273
 274 struct mlx4_wqe_ctrl_seg {
 275         __be32                  owner_opcode;
 276         union {
 277                 struct {
 278                         __be16                  vlan_tag;
 279                         u8                      ins_vlan;
 280                         u8                      fence_size;
 281                 };
 282                 __be32                  bf_qpn;
 283         };
 284         /*
 285          * High 24 bits are SRC remote buffer; low 8 bits are flags:
 286          * [7]   SO (strong ordering)
 287          * [5]   TCP/UDP checksum
 288          * [4]   IP checksum
 289          * [3:2] C (generate completion queue entry)
 290          * [1]   SE (solicited event)
 291          * [0]   FL (force loopback)
 292          */
 293         union {
 294                 __be32                  srcrb_flags;
 295                 __be16                  srcrb_flags16[2];
 296         };
 297         /*
 298          * imm is immediate data for send/RDMA write w/ immediate;
 299          * also invalidation key for send with invalidate; input
 300          * modifier for WQEs on CCQs.
 301          */
 302         __be32                  imm;
 303 };
 304
 305 enum {
 306         MLX4_WQE_MLX_VL15       = 1 << 17,
 307         MLX4_WQE_MLX_SLR        = 1 << 16
 308 };
 309
 310 struct mlx4_wqe_mlx_seg {
 311         u8                      owner;
 312         u8                      reserved1[2];
 313         u8                      opcode;
 314         __be16                  sched_prio;
 315         u8                      reserved2;
 316         u8                      size;
 317         /*
 318          * [17]    VL15
 319          * [16]    SLR
 320          * [15:12] static rate
 321          * [11:8]  SL
 322          * [4]     ICRC
 323          * [3:2]   C
 324          * [0]     FL (force loopback)
 325          */
 326         __be32                  flags;
 327         __be16                  rlid;
 328         u16                     reserved3;
 329 };
 330
 331 struct mlx4_wqe_datagram_seg {
 332         __be32                  av[8];
 333         __be32                  dqpn;
 334         __be32                  qkey;
 335         __be16                  vlan;
 336         u8                      mac[ETH_ALEN];
 337 };
 338
 339 struct mlx4_wqe_lso_seg {
 340         __be32                  mss_hdr_size;
 341         __be32                  header[0];
 342 };
 343
 344 enum mlx4_wqe_bind_seg_flags2 {
 345         MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
 346         MLX4_WQE_BIND_TYPE_2     = (1 << 31),
 347 };
 348
 349 struct mlx4_wqe_bind_seg {
 350         __be32                  flags1;
 351         __be32                  flags2;
 352         __be32                  new_rkey;
 353         __be32                  lkey;
 354         __be64                  addr;
 355         __be64                  length;
 356 };
 357
 358 enum {
 359         MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
 360         MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
 361         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  = 1 << 29,
 362         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
 363         MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC       = 1 << 31
 364 };
 365
 366 struct mlx4_wqe_fmr_seg {
 367         __be32                  flags;
 368         __be32                  mem_key;
 369         __be64                  buf_list;
 370         __be64                  start_addr;
 371         __be64                  reg_len;
 372         __be32                  offset;
 373         __be32                  page_size;
 374         u32                     reserved[2];
 375 };
 376
 377 struct mlx4_wqe_fmr_ext_seg {
 378         u8                      flags;
 379         u8                      reserved;
 380         __be16                  app_mask;
 381         __be16                  wire_app_tag;
 382         __be16                  mem_app_tag;
 383         __be32                  wire_ref_tag_base;
 384         __be32                  mem_ref_tag_base;
 385 };
 386
 387 struct mlx4_wqe_local_inval_seg {
 388         u64                     reserved1;
 389         __be32                  mem_key;
 390         u32                     reserved2;
 391         u64                     reserved3[2];
 392 };
 393
 394 struct mlx4_wqe_raddr_seg {
 395         __be64                  raddr;
 396         __be32                  rkey;
 397         u32                     reserved;
 398 };
 399
 400 struct mlx4_wqe_atomic_seg {
 401         __be64                  swap_add;
 402         __be64                  compare;
 403 };
 404
 405 struct mlx4_wqe_masked_atomic_seg {
 406         __be64                  swap_add;
 407         __be64                  compare;
 408         __be64                  swap_add_mask;
 409         __be64                  compare_mask;
 410 };
 411
 412 struct mlx4_wqe_data_seg {
 413         __be32                  byte_count;
 414         __be32                  lkey;
 415         __be64                  addr;
 416 };
 417
 418 enum {
 419         MLX4_INLINE_ALIGN       = 64,
 420         MLX4_INLINE_SEG         = 1 << 31,
 421 };
 422
 423 struct mlx4_wqe_inline_seg {
 424         __be32                  byte_count;
 425 };
 426
 427 enum mlx4_update_qp_attr {
 428         MLX4_UPDATE_QP_SMAC             = 1 << 0,
 429         MLX4_UPDATE_QP_VSD              = 1 << 2,
 430         MLX4_UPDATE_QP_SUPPORTED_ATTRS  = (1 << 2) - 1
 431 };
 432
 433 enum mlx4_update_qp_params_flags {
 434         MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE          = 1 << 0,
 435 };
 436
 437 struct mlx4_update_qp_params {
 438         u8      smac_index;
 439         u32     flags;
 440 };
 441
 442 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
 443                    enum mlx4_update_qp_attr attr,
 444                    struct mlx4_update_qp_params *params);
 445 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 446                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
 447                    struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
 448                    int sqd_event, struct mlx4_qp *qp);
 449
 450 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
 451                   struct mlx4_qp_context *context);
 452
 453 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
 454                      struct mlx4_qp_context *context,
 455                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
 456
 457 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
 458 {
 459         return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
 460 }
 461
 462 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
 463
 464 #endif /* MLX4_QP_H */