include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38
  39 #if defined(__LITTLE_ENDIAN)
  40 #define MLX5_SET_HOST_ENDIANNESS        0
  41 #elif defined(__BIG_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0x80
  43 #else
  44 #error Host endianness not defined
  45 #endif
  46
  47 /* helper macros */
  48 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  49 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  50 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  53 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  54 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  55 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  56 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  57
  58 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  59 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  60 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  61 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  62 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  63
  64 /* insert a value to a struct */
  65 #define MLX5_SET(typ, p, fld, v) do { \
  66         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  67         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  68         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  69                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  70                      << __mlx5_dw_bit_off(typ, fld))); \
  71 } while (0)
  72
  73 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  74 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  75 __mlx5_mask(typ, fld))
  76
  77 #define MLX5_GET_PR(typ, p, fld) ({ \
  78         u32 ___t = MLX5_GET(typ, p, fld); \
  79         pr_debug(#fld " = 0x%x\n", ___t); \
  80         ___t; \
  81 })
  82
  83 #define MLX5_SET64(typ, p, fld, v) do { \
  84         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  85         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
  86         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  87 } while (0)
  88
  89 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
  90
  91 enum {
  92         MLX5_MAX_COMMANDS               = 32,
  93         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
  94         MLX5_PCI_CMD_XPORT              = 7,
  95         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
  96         MLX5_MAX_PSVS                   = 4,
  97 };
  98
  99 enum {
 100         MLX5_EXTENDED_UD_AV             = 0x80000000,
 101 };
 102
 103 enum {
 104         MLX5_CQ_STATE_ARMED             = 9,
 105         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 106         MLX5_CQ_STATE_FIRED             = 0xa,
 107 };
 108
 109 enum {
 110         MLX5_STAT_RATE_OFFSET   = 5,
 111 };
 112
 113 enum {
 114         MLX5_INLINE_SEG = 0x80000000,
 115 };
 116
 117 enum {
 118         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 119         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 120 };
 121
 122 enum {
 123         MLX5_PERM_LOCAL_READ    = 1 << 2,
 124         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 125         MLX5_PERM_REMOTE_READ   = 1 << 4,
 126         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 127         MLX5_PERM_ATOMIC        = 1 << 6,
 128         MLX5_PERM_UMR_EN        = 1 << 7,
 129 };
 130
 131 enum {
 132         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 133         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 134         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 135         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 136         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 137 };
 138
 139 enum {
 140         MLX5_ACCESS_MODE_PA     = 0,
 141         MLX5_ACCESS_MODE_MTT    = 1,
 142         MLX5_ACCESS_MODE_KLM    = 2
 143 };
 144
 145 enum {
 146         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 147         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 148         MLX5_MKEY_BSF_EN        = 1 << 30,
 149         MLX5_MKEY_LEN64         = 1 << 31,
 150 };
 151
 152 enum {
 153         MLX5_EN_RD      = (u64)1,
 154         MLX5_EN_WR      = (u64)2
 155 };
 156
 157 enum {
 158         MLX5_BF_REGS_PER_PAGE           = 4,
 159         MLX5_MAX_UAR_PAGES              = 1 << 8,
 160         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 161         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 162 };
 163
 164 enum {
 165         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 166         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 167         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 168         MLX5_MKEY_MASK_PD               = 1ull << 7,
 169         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 170         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 171         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 172         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 173         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 174         MLX5_MKEY_MASK_LR               = 1ull << 17,
 175         MLX5_MKEY_MASK_LW               = 1ull << 18,
 176         MLX5_MKEY_MASK_RR               = 1ull << 19,
 177         MLX5_MKEY_MASK_RW               = 1ull << 20,
 178         MLX5_MKEY_MASK_A                = 1ull << 21,
 179         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 180         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 181 };
 182
 183 enum {
 184         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 185
 186         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 187         MLX5_UMR_CHECK_FREE             = (2 << 5),
 188
 189         MLX5_UMR_INLINE                 = (1 << 7),
 190 };
 191
 192 enum mlx5_event {
 193         MLX5_EVENT_TYPE_COMP               = 0x0,
 194
 195         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 196         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 197         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 198         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 199         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 200
 201         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 202         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 203         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 204         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 205         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 206         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 207
 208         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 209         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 210         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 211         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 212
 213         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 214         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 215
 216         MLX5_EVENT_TYPE_CMD                = 0x0a,
 217         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 218 };
 219
 220 enum {
 221         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 222         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 223         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 224         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 225         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 226         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 227         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 228 };
 229
 230 enum {
 231         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 232         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 233         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 234         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 235         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 236         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 237         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 238         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 239         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 240         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 241         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 242         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 243 };
 244
 245 enum {
 246         MLX5_OPCODE_NOP                 = 0x00,
 247         MLX5_OPCODE_SEND_INVAL          = 0x01,
 248         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 249         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 250         MLX5_OPCODE_SEND                = 0x0a,
 251         MLX5_OPCODE_SEND_IMM            = 0x0b,
 252         MLX5_OPCODE_RDMA_READ           = 0x10,
 253         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 254         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 255         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 256         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 257         MLX5_OPCODE_BIND_MW             = 0x18,
 258         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 259
 260         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 261         MLX5_RECV_OPCODE_SEND           = 0x01,
 262         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 263         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 264
 265         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 266         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 267
 268         MLX5_OPCODE_SET_PSV             = 0x20,
 269         MLX5_OPCODE_GET_PSV             = 0x21,
 270         MLX5_OPCODE_CHECK_PSV           = 0x22,
 271         MLX5_OPCODE_RGET_PSV            = 0x26,
 272         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 273
 274         MLX5_OPCODE_UMR                 = 0x25,
 275
 276 };
 277
 278 enum {
 279         MLX5_SET_PORT_RESET_QKEY        = 0,
 280         MLX5_SET_PORT_GUID0             = 16,
 281         MLX5_SET_PORT_NODE_GUID         = 17,
 282         MLX5_SET_PORT_SYS_GUID          = 18,
 283         MLX5_SET_PORT_GID_TABLE         = 19,
 284         MLX5_SET_PORT_PKEY_TABLE        = 20,
 285 };
 286
 287 enum {
 288         MLX5_MAX_PAGE_SHIFT             = 31
 289 };
 290
 291 enum {
 292         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 293         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 294 };
 295
 296 enum {
 297         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 298 };
 299
 300 enum {
 301         HCA_CAP_OPMOD_GET_MAX   = 0,
 302         HCA_CAP_OPMOD_GET_CUR   = 1,
 303 };
 304
 305 struct mlx5_inbox_hdr {
 306         __be16          opcode;
 307         u8              rsvd[4];
 308         __be16          opmod;
 309 };
 310
 311 struct mlx5_outbox_hdr {
 312         u8              status;
 313         u8              rsvd[3];
 314         __be32          syndrome;
 315 };
 316
 317 struct mlx5_cmd_query_adapter_mbox_in {
 318         struct mlx5_inbox_hdr   hdr;
 319         u8                      rsvd[8];
 320 };
 321
 322 struct mlx5_cmd_query_adapter_mbox_out {
 323         struct mlx5_outbox_hdr  hdr;
 324         u8                      rsvd0[24];
 325         u8                      intapin;
 326         u8                      rsvd1[13];
 327         __be16                  vsd_vendor_id;
 328         u8                      vsd[208];
 329         u8                      vsd_psid[16];
 330 };
 331
 332 struct mlx5_cmd_init_hca_mbox_in {
 333         struct mlx5_inbox_hdr   hdr;
 334         u8                      rsvd0[2];
 335         __be16                  profile;
 336         u8                      rsvd1[4];
 337 };
 338
 339 struct mlx5_cmd_init_hca_mbox_out {
 340         struct mlx5_outbox_hdr  hdr;
 341         u8                      rsvd[8];
 342 };
 343
 344 struct mlx5_cmd_teardown_hca_mbox_in {
 345         struct mlx5_inbox_hdr   hdr;
 346         u8                      rsvd0[2];
 347         __be16                  profile;
 348         u8                      rsvd1[4];
 349 };
 350
 351 struct mlx5_cmd_teardown_hca_mbox_out {
 352         struct mlx5_outbox_hdr  hdr;
 353         u8                      rsvd[8];
 354 };
 355
 356 struct mlx5_cmd_layout {
 357         u8              type;
 358         u8              rsvd0[3];
 359         __be32          inlen;
 360         __be64          in_ptr;
 361         __be32          in[4];
 362         __be32          out[4];
 363         __be64          out_ptr;
 364         __be32          outlen;
 365         u8              token;
 366         u8              sig;
 367         u8              rsvd1;
 368         u8              status_own;
 369 };
 370
 371
 372 struct health_buffer {
 373         __be32          assert_var[5];
 374         __be32          rsvd0[3];
 375         __be32          assert_exit_ptr;
 376         __be32          assert_callra;
 377         __be32          rsvd1[2];
 378         __be32          fw_ver;
 379         __be32          hw_id;
 380         __be32          rsvd2;
 381         u8              irisc_index;
 382         u8              synd;
 383         __be16          ext_sync;
 384 };
 385
 386 struct mlx5_init_seg {
 387         __be32                  fw_rev;
 388         __be32                  cmdif_rev_fw_sub;
 389         __be32                  rsvd0[2];
 390         __be32                  cmdq_addr_h;
 391         __be32                  cmdq_addr_l_sz;
 392         __be32                  cmd_dbell;
 393         __be32                  rsvd1[121];
 394         struct health_buffer    health;
 395         __be32                  rsvd2[884];
 396         __be32                  health_counter;
 397         __be32                  rsvd3[1019];
 398         __be64                  ieee1588_clk;
 399         __be32                  ieee1588_clk_type;
 400         __be32                  clr_intx;
 401 };
 402
 403 struct mlx5_eqe_comp {
 404         __be32  reserved[6];
 405         __be32  cqn;
 406 };
 407
 408 struct mlx5_eqe_qp_srq {
 409         __be32  reserved[6];
 410         __be32  qp_srq_n;
 411 };
 412
 413 struct mlx5_eqe_cq_err {
 414         __be32  cqn;
 415         u8      reserved1[7];
 416         u8      syndrome;
 417 };
 418
 419 struct mlx5_eqe_port_state {
 420         u8      reserved0[8];
 421         u8      port;
 422 };
 423
 424 struct mlx5_eqe_gpio {
 425         __be32  reserved0[2];
 426         __be64  gpio_event;
 427 };
 428
 429 struct mlx5_eqe_congestion {
 430         u8      type;
 431         u8      rsvd0;
 432         u8      congestion_level;
 433 };
 434
 435 struct mlx5_eqe_stall_vl {
 436         u8      rsvd0[3];
 437         u8      port_vl;
 438 };
 439
 440 struct mlx5_eqe_cmd {
 441         __be32  vector;
 442         __be32  rsvd[6];
 443 };
 444
 445 struct mlx5_eqe_page_req {
 446         u8              rsvd0[2];
 447         __be16          func_id;
 448         __be32          num_pages;
 449         __be32          rsvd1[5];
 450 };
 451
 452 union ev_data {
 453         __be32                          raw[7];
 454         struct mlx5_eqe_cmd             cmd;
 455         struct mlx5_eqe_comp            comp;
 456         struct mlx5_eqe_qp_srq          qp_srq;
 457         struct mlx5_eqe_cq_err          cq_err;
 458         struct mlx5_eqe_port_state      port;
 459         struct mlx5_eqe_gpio            gpio;
 460         struct mlx5_eqe_congestion      cong;
 461         struct mlx5_eqe_stall_vl        stall_vl;
 462         struct mlx5_eqe_page_req        req_pages;
 463 } __packed;
 464
 465 struct mlx5_eqe {
 466         u8              rsvd0;
 467         u8              type;
 468         u8              rsvd1;
 469         u8              sub_type;
 470         __be32          rsvd2[7];
 471         union ev_data   data;
 472         __be16          rsvd3;
 473         u8              signature;
 474         u8              owner;
 475 } __packed;
 476
 477 struct mlx5_cmd_prot_block {
 478         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 479         u8              rsvd0[48];
 480         __be64          next;
 481         __be32          block_num;
 482         u8              rsvd1;
 483         u8              token;
 484         u8              ctrl_sig;
 485         u8              sig;
 486 };
 487
 488 struct mlx5_err_cqe {
 489         u8      rsvd0[32];
 490         __be32  srqn;
 491         u8      rsvd1[18];
 492         u8      vendor_err_synd;
 493         u8      syndrome;
 494         __be32  s_wqe_opcode_qpn;
 495         __be16  wqe_counter;
 496         u8      signature;
 497         u8      op_own;
 498 };
 499
 500 struct mlx5_cqe64 {
 501         u8              rsvd0[17];
 502         u8              ml_path;
 503         u8              rsvd20[4];
 504         __be16          slid;
 505         __be32          flags_rqpn;
 506         u8              rsvd28[4];
 507         __be32          srqn;
 508         __be32          imm_inval_pkey;
 509         u8              rsvd40[4];
 510         __be32          byte_cnt;
 511         __be64          timestamp;
 512         __be32          sop_drop_qpn;
 513         __be16          wqe_counter;
 514         u8              signature;
 515         u8              op_own;
 516 };
 517
 518 struct mlx5_sig_err_cqe {
 519         u8              rsvd0[16];
 520         __be32          expected_trans_sig;
 521         __be32          actual_trans_sig;
 522         __be32          expected_reftag;
 523         __be32          actual_reftag;
 524         __be16          syndrome;
 525         u8              rsvd22[2];
 526         __be32          mkey;
 527         __be64          err_offset;
 528         u8              rsvd30[8];
 529         __be32          qpn;
 530         u8              rsvd38[2];
 531         u8              signature;
 532         u8              op_own;
 533 };
 534
 535 struct mlx5_wqe_srq_next_seg {
 536         u8                      rsvd0[2];
 537         __be16                  next_wqe_index;
 538         u8                      signature;
 539         u8                      rsvd1[11];
 540 };
 541
 542 union mlx5_ext_cqe {
 543         struct ib_grh   grh;
 544         u8              inl[64];
 545 };
 546
 547 struct mlx5_cqe128 {
 548         union mlx5_ext_cqe      inl_grh;
 549         struct mlx5_cqe64       cqe64;
 550 };
 551
 552 struct mlx5_srq_ctx {
 553         u8                      state_log_sz;
 554         u8                      rsvd0[3];
 555         __be32                  flags_xrcd;
 556         __be32                  pgoff_cqn;
 557         u8                      rsvd1[4];
 558         u8                      log_pg_sz;
 559         u8                      rsvd2[7];
 560         __be32                  pd;
 561         __be16                  lwm;
 562         __be16                  wqe_cnt;
 563         u8                      rsvd3[8];
 564         __be64                  db_record;
 565 };
 566
 567 struct mlx5_create_srq_mbox_in {
 568         struct mlx5_inbox_hdr   hdr;
 569         __be32                  input_srqn;
 570         u8                      rsvd0[4];
 571         struct mlx5_srq_ctx     ctx;
 572         u8                      rsvd1[208];
 573         __be64                  pas[0];
 574 };
 575
 576 struct mlx5_create_srq_mbox_out {
 577         struct mlx5_outbox_hdr  hdr;
 578         __be32                  srqn;
 579         u8                      rsvd[4];
 580 };
 581
 582 struct mlx5_destroy_srq_mbox_in {
 583         struct mlx5_inbox_hdr   hdr;
 584         __be32                  srqn;
 585         u8                      rsvd[4];
 586 };
 587
 588 struct mlx5_destroy_srq_mbox_out {
 589         struct mlx5_outbox_hdr  hdr;
 590         u8                      rsvd[8];
 591 };
 592
 593 struct mlx5_query_srq_mbox_in {
 594         struct mlx5_inbox_hdr   hdr;
 595         __be32                  srqn;
 596         u8                      rsvd0[4];
 597 };
 598
 599 struct mlx5_query_srq_mbox_out {
 600         struct mlx5_outbox_hdr  hdr;
 601         u8                      rsvd0[8];
 602         struct mlx5_srq_ctx     ctx;
 603         u8                      rsvd1[32];
 604         __be64                  pas[0];
 605 };
 606
 607 struct mlx5_arm_srq_mbox_in {
 608         struct mlx5_inbox_hdr   hdr;
 609         __be32                  srqn;
 610         __be16                  rsvd;
 611         __be16                  lwm;
 612 };
 613
 614 struct mlx5_arm_srq_mbox_out {
 615         struct mlx5_outbox_hdr  hdr;
 616         u8                      rsvd[8];
 617 };
 618
 619 struct mlx5_cq_context {
 620         u8                      status;
 621         u8                      cqe_sz_flags;
 622         u8                      st;
 623         u8                      rsvd3;
 624         u8                      rsvd4[6];
 625         __be16                  page_offset;
 626         __be32                  log_sz_usr_page;
 627         __be16                  cq_period;
 628         __be16                  cq_max_count;
 629         __be16                  rsvd20;
 630         __be16                  c_eqn;
 631         u8                      log_pg_sz;
 632         u8                      rsvd25[7];
 633         __be32                  last_notified_index;
 634         __be32                  solicit_producer_index;
 635         __be32                  consumer_counter;
 636         __be32                  producer_counter;
 637         u8                      rsvd48[8];
 638         __be64                  db_record_addr;
 639 };
 640
 641 struct mlx5_create_cq_mbox_in {
 642         struct mlx5_inbox_hdr   hdr;
 643         __be32                  input_cqn;
 644         u8                      rsvdx[4];
 645         struct mlx5_cq_context  ctx;
 646         u8                      rsvd6[192];
 647         __be64                  pas[0];
 648 };
 649
 650 struct mlx5_create_cq_mbox_out {
 651         struct mlx5_outbox_hdr  hdr;
 652         __be32                  cqn;
 653         u8                      rsvd0[4];
 654 };
 655
 656 struct mlx5_destroy_cq_mbox_in {
 657         struct mlx5_inbox_hdr   hdr;
 658         __be32                  cqn;
 659         u8                      rsvd0[4];
 660 };
 661
 662 struct mlx5_destroy_cq_mbox_out {
 663         struct mlx5_outbox_hdr  hdr;
 664         u8                      rsvd0[8];
 665 };
 666
 667 struct mlx5_query_cq_mbox_in {
 668         struct mlx5_inbox_hdr   hdr;
 669         __be32                  cqn;
 670         u8                      rsvd0[4];
 671 };
 672
 673 struct mlx5_query_cq_mbox_out {
 674         struct mlx5_outbox_hdr  hdr;
 675         u8                      rsvd0[8];
 676         struct mlx5_cq_context  ctx;
 677         u8                      rsvd6[16];
 678         __be64                  pas[0];
 679 };
 680
 681 struct mlx5_modify_cq_mbox_in {
 682         struct mlx5_inbox_hdr   hdr;
 683         __be32                  cqn;
 684         __be32                  field_select;
 685         struct mlx5_cq_context  ctx;
 686         u8                      rsvd[192];
 687         __be64                  pas[0];
 688 };
 689
 690 struct mlx5_modify_cq_mbox_out {
 691         struct mlx5_outbox_hdr  hdr;
 692         u8                      rsvd[8];
 693 };
 694
 695 struct mlx5_enable_hca_mbox_in {
 696         struct mlx5_inbox_hdr   hdr;
 697         u8                      rsvd[8];
 698 };
 699
 700 struct mlx5_enable_hca_mbox_out {
 701         struct mlx5_outbox_hdr  hdr;
 702         u8                      rsvd[8];
 703 };
 704
 705 struct mlx5_disable_hca_mbox_in {
 706         struct mlx5_inbox_hdr   hdr;
 707         u8                      rsvd[8];
 708 };
 709
 710 struct mlx5_disable_hca_mbox_out {
 711         struct mlx5_outbox_hdr  hdr;
 712         u8                      rsvd[8];
 713 };
 714
 715 struct mlx5_eq_context {
 716         u8                      status;
 717         u8                      ec_oi;
 718         u8                      st;
 719         u8                      rsvd2[7];
 720         __be16                  page_pffset;
 721         __be32                  log_sz_usr_page;
 722         u8                      rsvd3[7];
 723         u8                      intr;
 724         u8                      log_page_size;
 725         u8                      rsvd4[15];
 726         __be32                  consumer_counter;
 727         __be32                  produser_counter;
 728         u8                      rsvd5[16];
 729 };
 730
 731 struct mlx5_create_eq_mbox_in {
 732         struct mlx5_inbox_hdr   hdr;
 733         u8                      rsvd0[3];
 734         u8                      input_eqn;
 735         u8                      rsvd1[4];
 736         struct mlx5_eq_context  ctx;
 737         u8                      rsvd2[8];
 738         __be64                  events_mask;
 739         u8                      rsvd3[176];
 740         __be64                  pas[0];
 741 };
 742
 743 struct mlx5_create_eq_mbox_out {
 744         struct mlx5_outbox_hdr  hdr;
 745         u8                      rsvd0[3];
 746         u8                      eq_number;
 747         u8                      rsvd1[4];
 748 };
 749
 750 struct mlx5_destroy_eq_mbox_in {
 751         struct mlx5_inbox_hdr   hdr;
 752         u8                      rsvd0[3];
 753         u8                      eqn;
 754         u8                      rsvd1[4];
 755 };
 756
 757 struct mlx5_destroy_eq_mbox_out {
 758         struct mlx5_outbox_hdr  hdr;
 759         u8                      rsvd[8];
 760 };
 761
 762 struct mlx5_map_eq_mbox_in {
 763         struct mlx5_inbox_hdr   hdr;
 764         __be64                  mask;
 765         u8                      mu;
 766         u8                      rsvd0[2];
 767         u8                      eqn;
 768         u8                      rsvd1[24];
 769 };
 770
 771 struct mlx5_map_eq_mbox_out {
 772         struct mlx5_outbox_hdr  hdr;
 773         u8                      rsvd[8];
 774 };
 775
 776 struct mlx5_query_eq_mbox_in {
 777         struct mlx5_inbox_hdr   hdr;
 778         u8                      rsvd0[3];
 779         u8                      eqn;
 780         u8                      rsvd1[4];
 781 };
 782
 783 struct mlx5_query_eq_mbox_out {
 784         struct mlx5_outbox_hdr  hdr;
 785         u8                      rsvd[8];
 786         struct mlx5_eq_context  ctx;
 787 };
 788
 789 enum {
 790         MLX5_MKEY_STATUS_FREE = 1 << 6,
 791 };
 792
 793 struct mlx5_mkey_seg {
 794         /* This is a two bit field occupying bits 31-30.
 795          * bit 31 is always 0,
 796          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 797          */
 798         u8              status;
 799         u8              pcie_control;
 800         u8              flags;
 801         u8              version;
 802         __be32          qpn_mkey7_0;
 803         u8              rsvd1[4];
 804         __be32          flags_pd;
 805         __be64          start_addr;
 806         __be64          len;
 807         __be32          bsfs_octo_size;
 808         u8              rsvd2[16];
 809         __be32          xlt_oct_size;
 810         u8              rsvd3[3];
 811         u8              log2_page_size;
 812         u8              rsvd4[4];
 813 };
 814
 815 struct mlx5_query_special_ctxs_mbox_in {
 816         struct mlx5_inbox_hdr   hdr;
 817         u8                      rsvd[8];
 818 };
 819
 820 struct mlx5_query_special_ctxs_mbox_out {
 821         struct mlx5_outbox_hdr  hdr;
 822         __be32                  dump_fill_mkey;
 823         __be32                  reserved_lkey;
 824 };
 825
 826 struct mlx5_create_mkey_mbox_in {
 827         struct mlx5_inbox_hdr   hdr;
 828         __be32                  input_mkey_index;
 829         u8                      rsvd0[4];
 830         struct mlx5_mkey_seg    seg;
 831         u8                      rsvd1[16];
 832         __be32                  xlat_oct_act_size;
 833         __be32                  rsvd2;
 834         u8                      rsvd3[168];
 835         __be64                  pas[0];
 836 };
 837
 838 struct mlx5_create_mkey_mbox_out {
 839         struct mlx5_outbox_hdr  hdr;
 840         __be32                  mkey;
 841         u8                      rsvd[4];
 842 };
 843
 844 struct mlx5_destroy_mkey_mbox_in {
 845         struct mlx5_inbox_hdr   hdr;
 846         __be32                  mkey;
 847         u8                      rsvd[4];
 848 };
 849
 850 struct mlx5_destroy_mkey_mbox_out {
 851         struct mlx5_outbox_hdr  hdr;
 852         u8                      rsvd[8];
 853 };
 854
 855 struct mlx5_query_mkey_mbox_in {
 856         struct mlx5_inbox_hdr   hdr;
 857         __be32                  mkey;
 858 };
 859
 860 struct mlx5_query_mkey_mbox_out {
 861         struct mlx5_outbox_hdr  hdr;
 862         __be64                  pas[0];
 863 };
 864
 865 struct mlx5_modify_mkey_mbox_in {
 866         struct mlx5_inbox_hdr   hdr;
 867         __be32                  mkey;
 868         __be64                  pas[0];
 869 };
 870
 871 struct mlx5_modify_mkey_mbox_out {
 872         struct mlx5_outbox_hdr  hdr;
 873         u8                      rsvd[8];
 874 };
 875
 876 struct mlx5_dump_mkey_mbox_in {
 877         struct mlx5_inbox_hdr   hdr;
 878 };
 879
 880 struct mlx5_dump_mkey_mbox_out {
 881         struct mlx5_outbox_hdr  hdr;
 882         __be32                  mkey;
 883 };
 884
 885 struct mlx5_mad_ifc_mbox_in {
 886         struct mlx5_inbox_hdr   hdr;
 887         __be16                  remote_lid;
 888         u8                      rsvd0;
 889         u8                      port;
 890         u8                      rsvd1[4];
 891         u8                      data[256];
 892 };
 893
 894 struct mlx5_mad_ifc_mbox_out {
 895         struct mlx5_outbox_hdr  hdr;
 896         u8                      rsvd[8];
 897         u8                      data[256];
 898 };
 899
 900 struct mlx5_access_reg_mbox_in {
 901         struct mlx5_inbox_hdr           hdr;
 902         u8                              rsvd0[2];
 903         __be16                          register_id;
 904         __be32                          arg;
 905         __be32                          data[0];
 906 };
 907
 908 struct mlx5_access_reg_mbox_out {
 909         struct mlx5_outbox_hdr          hdr;
 910         u8                              rsvd[8];
 911         __be32                          data[0];
 912 };
 913
 914 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 915
 916 enum {
 917         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 918 };
 919
 920 struct mlx5_allocate_psv_in {
 921         struct mlx5_inbox_hdr   hdr;
 922         __be32                  npsv_pd;
 923         __be32                  rsvd_psv0;
 924 };
 925
 926 struct mlx5_allocate_psv_out {
 927         struct mlx5_outbox_hdr  hdr;
 928         u8                      rsvd[8];
 929         __be32                  psv_idx[4];
 930 };
 931
 932 struct mlx5_destroy_psv_in {
 933         struct mlx5_inbox_hdr   hdr;
 934         __be32                  psv_number;
 935         u8                      rsvd[4];
 936 };
 937
 938 struct mlx5_destroy_psv_out {
 939         struct mlx5_outbox_hdr  hdr;
 940         u8                      rsvd[8];
 941 };
 942
 943 #endif /* MLX5_DEVICE_H */