include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38
  39 #if defined(__LITTLE_ENDIAN)
  40 #define MLX5_SET_HOST_ENDIANNESS        0
  41 #elif defined(__BIG_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0x80
  43 #else
  44 #error Host endianness not defined
  45 #endif
  46
  47 enum {
  48         MLX5_MAX_COMMANDS               = 32,
  49         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
  50         MLX5_PCI_CMD_XPORT              = 7,
  51 };
  52
  53 enum {
  54         MLX5_EXTENDED_UD_AV             = 0x80000000,
  55 };
  56
  57 enum {
  58         MLX5_CQ_STATE_ARMED             = 9,
  59         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
  60         MLX5_CQ_STATE_FIRED             = 0xa,
  61 };
  62
  63 enum {
  64         MLX5_STAT_RATE_OFFSET   = 5,
  65 };
  66
  67 enum {
  68         MLX5_INLINE_SEG = 0x80000000,
  69 };
  70
  71 enum {
  72         MLX5_PERM_LOCAL_READ    = 1 << 2,
  73         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
  74         MLX5_PERM_REMOTE_READ   = 1 << 4,
  75         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
  76         MLX5_PERM_ATOMIC        = 1 << 6,
  77         MLX5_PERM_UMR_EN        = 1 << 7,
  78 };
  79
  80 enum {
  81         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
  82         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
  83         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
  84         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
  85         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
  86 };
  87
  88 enum {
  89         MLX5_ACCESS_MODE_PA     = 0,
  90         MLX5_ACCESS_MODE_MTT    = 1,
  91         MLX5_ACCESS_MODE_KLM    = 2
  92 };
  93
  94 enum {
  95         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
  96         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
  97         MLX5_MKEY_BSF_EN        = 1 << 30,
  98         MLX5_MKEY_LEN64         = 1 << 31,
  99 };
 100
 101 enum {
 102         MLX5_EN_RD      = (u64)1,
 103         MLX5_EN_WR      = (u64)2
 104 };
 105
 106 enum {
 107         MLX5_BF_REGS_PER_PAGE           = 4,
 108         MLX5_MAX_UAR_PAGES              = 1 << 8,
 109         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 110         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 111 };
 112
 113 enum {
 114         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 115         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 116         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 117         MLX5_MKEY_MASK_PD               = 1ull << 7,
 118         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 119         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 120         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 121         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 122         MLX5_MKEY_MASK_LR               = 1ull << 17,
 123         MLX5_MKEY_MASK_LW               = 1ull << 18,
 124         MLX5_MKEY_MASK_RR               = 1ull << 19,
 125         MLX5_MKEY_MASK_RW               = 1ull << 20,
 126         MLX5_MKEY_MASK_A                = 1ull << 21,
 127         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 128         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 129 };
 130
 131 enum mlx5_event {
 132         MLX5_EVENT_TYPE_COMP               = 0x0,
 133
 134         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 135         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 136         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 137         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 138         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 139
 140         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 141         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 142         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 143         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 144         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 145         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 146
 147         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 148         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 149         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 150         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 151
 152         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 153         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 154
 155         MLX5_EVENT_TYPE_CMD                = 0x0a,
 156         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 157 };
 158
 159 enum {
 160         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 161         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 162         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 163         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 164         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 165         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 166         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 167 };
 168
 169 enum {
 170         MLX5_DEV_CAP_FLAG_RC            = 1LL <<  0,
 171         MLX5_DEV_CAP_FLAG_UC            = 1LL <<  1,
 172         MLX5_DEV_CAP_FLAG_UD            = 1LL <<  2,
 173         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 174         MLX5_DEV_CAP_FLAG_SRQ           = 1LL <<  6,
 175         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 176         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 177         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 178         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 179         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 180         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 181         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 182         MLX5_DEV_CAP_FLAG_RESIZE_SRQ    = 1LL << 32,
 183         MLX5_DEV_CAP_FLAG_REMOTE_FENCE  = 1LL << 38,
 184         MLX5_DEV_CAP_FLAG_TLP_HINTS     = 1LL << 39,
 185         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 186         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 41,
 187         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 188 };
 189
 190 enum {
 191         MLX5_OPCODE_NOP                 = 0x00,
 192         MLX5_OPCODE_SEND_INVAL          = 0x01,
 193         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 194         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 195         MLX5_OPCODE_SEND                = 0x0a,
 196         MLX5_OPCODE_SEND_IMM            = 0x0b,
 197         MLX5_OPCODE_RDMA_READ           = 0x10,
 198         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 199         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 200         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 201         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 202         MLX5_OPCODE_BIND_MW             = 0x18,
 203         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 204
 205         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 206         MLX5_RECV_OPCODE_SEND           = 0x01,
 207         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 208         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 209
 210         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 211         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 212
 213         MLX5_OPCODE_SET_PSV             = 0x20,
 214         MLX5_OPCODE_GET_PSV             = 0x21,
 215         MLX5_OPCODE_CHECK_PSV           = 0x22,
 216         MLX5_OPCODE_RGET_PSV            = 0x26,
 217         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 218
 219         MLX5_OPCODE_UMR                 = 0x25,
 220
 221 };
 222
 223 enum {
 224         MLX5_SET_PORT_RESET_QKEY        = 0,
 225         MLX5_SET_PORT_GUID0             = 16,
 226         MLX5_SET_PORT_NODE_GUID         = 17,
 227         MLX5_SET_PORT_SYS_GUID          = 18,
 228         MLX5_SET_PORT_GID_TABLE         = 19,
 229         MLX5_SET_PORT_PKEY_TABLE        = 20,
 230 };
 231
 232 enum {
 233         MLX5_MAX_PAGE_SHIFT             = 31
 234 };
 235
 236 enum {
 237         MLX5_ADAPTER_PAGE_SHIFT         = 12
 238 };
 239
 240 enum {
 241         MLX5_CAP_OFF_DCT                = 41,
 242         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 243 };
 244
 245 struct mlx5_inbox_hdr {
 246         __be16          opcode;
 247         u8              rsvd[4];
 248         __be16          opmod;
 249 };
 250
 251 struct mlx5_outbox_hdr {
 252         u8              status;
 253         u8              rsvd[3];
 254         __be32          syndrome;
 255 };
 256
 257 struct mlx5_cmd_query_adapter_mbox_in {
 258         struct mlx5_inbox_hdr   hdr;
 259         u8                      rsvd[8];
 260 };
 261
 262 struct mlx5_cmd_query_adapter_mbox_out {
 263         struct mlx5_outbox_hdr  hdr;
 264         u8                      rsvd0[24];
 265         u8                      intapin;
 266         u8                      rsvd1[13];
 267         __be16                  vsd_vendor_id;
 268         u8                      vsd[208];
 269         u8                      vsd_psid[16];
 270 };
 271
 272 struct mlx5_hca_cap {
 273         u8      rsvd1[16];
 274         u8      log_max_srq_sz;
 275         u8      log_max_qp_sz;
 276         u8      rsvd2;
 277         u8      log_max_qp;
 278         u8      log_max_strq_sz;
 279         u8      log_max_srqs;
 280         u8      rsvd4[2];
 281         u8      rsvd5;
 282         u8      log_max_cq_sz;
 283         u8      rsvd6;
 284         u8      log_max_cq;
 285         u8      log_max_eq_sz;
 286         u8      log_max_mkey;
 287         u8      rsvd7;
 288         u8      log_max_eq;
 289         u8      max_indirection;
 290         u8      log_max_mrw_sz;
 291         u8      log_max_bsf_list_sz;
 292         u8      log_max_klm_list_sz;
 293         u8      rsvd_8_0;
 294         u8      log_max_ra_req_dc;
 295         u8      rsvd_8_1;
 296         u8      log_max_ra_res_dc;
 297         u8      rsvd9;
 298         u8      log_max_ra_req_qp;
 299         u8      rsvd10;
 300         u8      log_max_ra_res_qp;
 301         u8      rsvd11[4];
 302         __be16  max_qp_count;
 303         __be16  rsvd12;
 304         u8      rsvd13;
 305         u8      local_ca_ack_delay;
 306         u8      rsvd14;
 307         u8      num_ports;
 308         u8      log_max_msg;
 309         u8      rsvd15[3];
 310         __be16  stat_rate_support;
 311         u8      rsvd16[2];
 312         __be64  flags;
 313         u8      rsvd17;
 314         u8      uar_sz;
 315         u8      rsvd18;
 316         u8      log_pg_sz;
 317         __be16  bf_log_bf_reg_size;
 318         u8      rsvd19[4];
 319         __be16  max_desc_sz_sq;
 320         u8      rsvd20[2];
 321         __be16  max_desc_sz_rq;
 322         u8      rsvd21[2];
 323         __be16  max_desc_sz_sq_dc;
 324         __be32  max_qp_mcg;
 325         u8      rsvd22[3];
 326         u8      log_max_mcg;
 327         u8      rsvd23;
 328         u8      log_max_pd;
 329         u8      rsvd24;
 330         u8      log_max_xrcd;
 331         u8      rsvd25[42];
 332         __be16  log_uar_page_sz;
 333         u8      rsvd26[28];
 334         u8      log_max_atomic_size_qp;
 335         u8      rsvd27[2];
 336         u8      log_max_atomic_size_dc;
 337         u8      rsvd28[76];
 338 };
 339
 340
 341 struct mlx5_cmd_query_hca_cap_mbox_in {
 342         struct mlx5_inbox_hdr   hdr;
 343         u8                      rsvd[8];
 344 };
 345
 346
 347 struct mlx5_cmd_query_hca_cap_mbox_out {
 348         struct mlx5_outbox_hdr  hdr;
 349         u8                      rsvd0[8];
 350         struct mlx5_hca_cap     hca_cap;
 351 };
 352
 353
 354 struct mlx5_cmd_set_hca_cap_mbox_in {
 355         struct mlx5_inbox_hdr   hdr;
 356         u8                      rsvd[8];
 357         struct mlx5_hca_cap     hca_cap;
 358 };
 359
 360
 361 struct mlx5_cmd_set_hca_cap_mbox_out {
 362         struct mlx5_outbox_hdr  hdr;
 363         u8                      rsvd0[8];
 364 };
 365
 366
 367 struct mlx5_cmd_init_hca_mbox_in {
 368         struct mlx5_inbox_hdr   hdr;
 369         u8                      rsvd0[2];
 370         __be16                  profile;
 371         u8                      rsvd1[4];
 372 };
 373
 374 struct mlx5_cmd_init_hca_mbox_out {
 375         struct mlx5_outbox_hdr  hdr;
 376         u8                      rsvd[8];
 377 };
 378
 379 struct mlx5_cmd_teardown_hca_mbox_in {
 380         struct mlx5_inbox_hdr   hdr;
 381         u8                      rsvd0[2];
 382         __be16                  profile;
 383         u8                      rsvd1[4];
 384 };
 385
 386 struct mlx5_cmd_teardown_hca_mbox_out {
 387         struct mlx5_outbox_hdr  hdr;
 388         u8                      rsvd[8];
 389 };
 390
 391 struct mlx5_cmd_layout {
 392         u8              type;
 393         u8              rsvd0[3];
 394         __be32          inlen;
 395         __be64          in_ptr;
 396         __be32          in[4];
 397         __be32          out[4];
 398         __be64          out_ptr;
 399         __be32          outlen;
 400         u8              token;
 401         u8              sig;
 402         u8              rsvd1;
 403         u8              status_own;
 404 };
 405
 406
 407 struct health_buffer {
 408         __be32          assert_var[5];
 409         __be32          rsvd0[3];
 410         __be32          assert_exit_ptr;
 411         __be32          assert_callra;
 412         __be32          rsvd1[2];
 413         __be32          fw_ver;
 414         __be32          hw_id;
 415         __be32          rsvd2;
 416         u8              irisc_index;
 417         u8              synd;
 418         __be16          ext_sync;
 419 };
 420
 421 struct mlx5_init_seg {
 422         __be32                  fw_rev;
 423         __be32                  cmdif_rev_fw_sub;
 424         __be32                  rsvd0[2];
 425         __be32                  cmdq_addr_h;
 426         __be32                  cmdq_addr_l_sz;
 427         __be32                  cmd_dbell;
 428         __be32                  rsvd1[121];
 429         struct health_buffer    health;
 430         __be32                  rsvd2[884];
 431         __be32                  health_counter;
 432         __be32                  rsvd3[1019];
 433         __be64                  ieee1588_clk;
 434         __be32                  ieee1588_clk_type;
 435         __be32                  clr_intx;
 436 };
 437
 438 struct mlx5_eqe_comp {
 439         __be32  reserved[6];
 440         __be32  cqn;
 441 };
 442
 443 struct mlx5_eqe_qp_srq {
 444         __be32  reserved[6];
 445         __be32  qp_srq_n;
 446 };
 447
 448 struct mlx5_eqe_cq_err {
 449         __be32  cqn;
 450         u8      reserved1[7];
 451         u8      syndrome;
 452 };
 453
 454 struct mlx5_eqe_dropped_packet {
 455 };
 456
 457 struct mlx5_eqe_port_state {
 458         u8      reserved0[8];
 459         u8      port;
 460 };
 461
 462 struct mlx5_eqe_gpio {
 463         __be32  reserved0[2];
 464         __be64  gpio_event;
 465 };
 466
 467 struct mlx5_eqe_congestion {
 468         u8      type;
 469         u8      rsvd0;
 470         u8      congestion_level;
 471 };
 472
 473 struct mlx5_eqe_stall_vl {
 474         u8      rsvd0[3];
 475         u8      port_vl;
 476 };
 477
 478 struct mlx5_eqe_cmd {
 479         __be32  vector;
 480         __be32  rsvd[6];
 481 };
 482
 483 struct mlx5_eqe_page_req {
 484         u8              rsvd0[2];
 485         __be16          func_id;
 486         __be32          num_pages;
 487         __be32          rsvd1[5];
 488 };
 489
 490 union ev_data {
 491         __be32                          raw[7];
 492         struct mlx5_eqe_cmd             cmd;
 493         struct mlx5_eqe_comp            comp;
 494         struct mlx5_eqe_qp_srq          qp_srq;
 495         struct mlx5_eqe_cq_err          cq_err;
 496         struct mlx5_eqe_dropped_packet  dp;
 497         struct mlx5_eqe_port_state      port;
 498         struct mlx5_eqe_gpio            gpio;
 499         struct mlx5_eqe_congestion      cong;
 500         struct mlx5_eqe_stall_vl        stall_vl;
 501         struct mlx5_eqe_page_req        req_pages;
 502 } __packed;
 503
 504 struct mlx5_eqe {
 505         u8              rsvd0;
 506         u8              type;
 507         u8              rsvd1;
 508         u8              sub_type;
 509         __be32          rsvd2[7];
 510         union ev_data   data;
 511         __be16          rsvd3;
 512         u8              signature;
 513         u8              owner;
 514 } __packed;
 515
 516 struct mlx5_cmd_prot_block {
 517         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 518         u8              rsvd0[48];
 519         __be64          next;
 520         __be32          block_num;
 521         u8              rsvd1;
 522         u8              token;
 523         u8              ctrl_sig;
 524         u8              sig;
 525 };
 526
 527 struct mlx5_err_cqe {
 528         u8      rsvd0[32];
 529         __be32  srqn;
 530         u8      rsvd1[18];
 531         u8      vendor_err_synd;
 532         u8      syndrome;
 533         __be32  s_wqe_opcode_qpn;
 534         __be16  wqe_counter;
 535         u8      signature;
 536         u8      op_own;
 537 };
 538
 539 struct mlx5_cqe64 {
 540         u8              rsvd0[17];
 541         u8              ml_path;
 542         u8              rsvd20[4];
 543         __be16          slid;
 544         __be32          flags_rqpn;
 545         u8              rsvd28[4];
 546         __be32          srqn;
 547         __be32          imm_inval_pkey;
 548         u8              rsvd40[4];
 549         __be32          byte_cnt;
 550         __be64          timestamp;
 551         __be32          sop_drop_qpn;
 552         __be16          wqe_counter;
 553         u8              signature;
 554         u8              op_own;
 555 };
 556
 557 struct mlx5_wqe_srq_next_seg {
 558         u8                      rsvd0[2];
 559         __be16                  next_wqe_index;
 560         u8                      signature;
 561         u8                      rsvd1[11];
 562 };
 563
 564 union mlx5_ext_cqe {
 565         struct ib_grh   grh;
 566         u8              inl[64];
 567 };
 568
 569 struct mlx5_cqe128 {
 570         union mlx5_ext_cqe      inl_grh;
 571         struct mlx5_cqe64       cqe64;
 572 };
 573
 574 struct mlx5_srq_ctx {
 575         u8                      state_log_sz;
 576         u8                      rsvd0[3];
 577         __be32                  flags_xrcd;
 578         __be32                  pgoff_cqn;
 579         u8                      rsvd1[4];
 580         u8                      log_pg_sz;
 581         u8                      rsvd2[7];
 582         __be32                  pd;
 583         __be16                  lwm;
 584         __be16                  wqe_cnt;
 585         u8                      rsvd3[8];
 586         __be64                  db_record;
 587 };
 588
 589 struct mlx5_create_srq_mbox_in {
 590         struct mlx5_inbox_hdr   hdr;
 591         __be32                  input_srqn;
 592         u8                      rsvd0[4];
 593         struct mlx5_srq_ctx     ctx;
 594         u8                      rsvd1[208];
 595         __be64                  pas[0];
 596 };
 597
 598 struct mlx5_create_srq_mbox_out {
 599         struct mlx5_outbox_hdr  hdr;
 600         __be32                  srqn;
 601         u8                      rsvd[4];
 602 };
 603
 604 struct mlx5_destroy_srq_mbox_in {
 605         struct mlx5_inbox_hdr   hdr;
 606         __be32                  srqn;
 607         u8                      rsvd[4];
 608 };
 609
 610 struct mlx5_destroy_srq_mbox_out {
 611         struct mlx5_outbox_hdr  hdr;
 612         u8                      rsvd[8];
 613 };
 614
 615 struct mlx5_query_srq_mbox_in {
 616         struct mlx5_inbox_hdr   hdr;
 617         __be32                  srqn;
 618         u8                      rsvd0[4];
 619 };
 620
 621 struct mlx5_query_srq_mbox_out {
 622         struct mlx5_outbox_hdr  hdr;
 623         u8                      rsvd0[8];
 624         struct mlx5_srq_ctx     ctx;
 625         u8                      rsvd1[32];
 626         __be64                  pas[0];
 627 };
 628
 629 struct mlx5_arm_srq_mbox_in {
 630         struct mlx5_inbox_hdr   hdr;
 631         __be32                  srqn;
 632         __be16                  rsvd;
 633         __be16                  lwm;
 634 };
 635
 636 struct mlx5_arm_srq_mbox_out {
 637         struct mlx5_outbox_hdr  hdr;
 638         u8                      rsvd[8];
 639 };
 640
 641 struct mlx5_cq_context {
 642         u8                      status;
 643         u8                      cqe_sz_flags;
 644         u8                      st;
 645         u8                      rsvd3;
 646         u8                      rsvd4[6];
 647         __be16                  page_offset;
 648         __be32                  log_sz_usr_page;
 649         __be16                  cq_period;
 650         __be16                  cq_max_count;
 651         __be16                  rsvd20;
 652         __be16                  c_eqn;
 653         u8                      log_pg_sz;
 654         u8                      rsvd25[7];
 655         __be32                  last_notified_index;
 656         __be32                  solicit_producer_index;
 657         __be32                  consumer_counter;
 658         __be32                  producer_counter;
 659         u8                      rsvd48[8];
 660         __be64                  db_record_addr;
 661 };
 662
 663 struct mlx5_create_cq_mbox_in {
 664         struct mlx5_inbox_hdr   hdr;
 665         __be32                  input_cqn;
 666         u8                      rsvdx[4];
 667         struct mlx5_cq_context  ctx;
 668         u8                      rsvd6[192];
 669         __be64                  pas[0];
 670 };
 671
 672 struct mlx5_create_cq_mbox_out {
 673         struct mlx5_outbox_hdr  hdr;
 674         __be32                  cqn;
 675         u8                      rsvd0[4];
 676 };
 677
 678 struct mlx5_destroy_cq_mbox_in {
 679         struct mlx5_inbox_hdr   hdr;
 680         __be32                  cqn;
 681         u8                      rsvd0[4];
 682 };
 683
 684 struct mlx5_destroy_cq_mbox_out {
 685         struct mlx5_outbox_hdr  hdr;
 686         u8                      rsvd0[8];
 687 };
 688
 689 struct mlx5_query_cq_mbox_in {
 690         struct mlx5_inbox_hdr   hdr;
 691         __be32                  cqn;
 692         u8                      rsvd0[4];
 693 };
 694
 695 struct mlx5_query_cq_mbox_out {
 696         struct mlx5_outbox_hdr  hdr;
 697         u8                      rsvd0[8];
 698         struct mlx5_cq_context  ctx;
 699         u8                      rsvd6[16];
 700         __be64                  pas[0];
 701 };
 702
 703 struct mlx5_modify_cq_mbox_in {
 704         struct mlx5_inbox_hdr   hdr;
 705         __be32                  cqn;
 706         __be32                  field_select;
 707         struct mlx5_cq_context  ctx;
 708         u8                      rsvd[192];
 709         __be64                  pas[0];
 710 };
 711
 712 struct mlx5_modify_cq_mbox_out {
 713         struct mlx5_outbox_hdr  hdr;
 714         u8                      rsvd[8];
 715 };
 716
 717 struct mlx5_enable_hca_mbox_in {
 718         struct mlx5_inbox_hdr   hdr;
 719         u8                      rsvd[8];
 720 };
 721
 722 struct mlx5_enable_hca_mbox_out {
 723         struct mlx5_outbox_hdr  hdr;
 724         u8                      rsvd[8];
 725 };
 726
 727 struct mlx5_disable_hca_mbox_in {
 728         struct mlx5_inbox_hdr   hdr;
 729         u8                      rsvd[8];
 730 };
 731
 732 struct mlx5_disable_hca_mbox_out {
 733         struct mlx5_outbox_hdr  hdr;
 734         u8                      rsvd[8];
 735 };
 736
 737 struct mlx5_eq_context {
 738         u8                      status;
 739         u8                      ec_oi;
 740         u8                      st;
 741         u8                      rsvd2[7];
 742         __be16                  page_pffset;
 743         __be32                  log_sz_usr_page;
 744         u8                      rsvd3[7];
 745         u8                      intr;
 746         u8                      log_page_size;
 747         u8                      rsvd4[15];
 748         __be32                  consumer_counter;
 749         __be32                  produser_counter;
 750         u8                      rsvd5[16];
 751 };
 752
 753 struct mlx5_create_eq_mbox_in {
 754         struct mlx5_inbox_hdr   hdr;
 755         u8                      rsvd0[3];
 756         u8                      input_eqn;
 757         u8                      rsvd1[4];
 758         struct mlx5_eq_context  ctx;
 759         u8                      rsvd2[8];
 760         __be64                  events_mask;
 761         u8                      rsvd3[176];
 762         __be64                  pas[0];
 763 };
 764
 765 struct mlx5_create_eq_mbox_out {
 766         struct mlx5_outbox_hdr  hdr;
 767         u8                      rsvd0[3];
 768         u8                      eq_number;
 769         u8                      rsvd1[4];
 770 };
 771
 772 struct mlx5_destroy_eq_mbox_in {
 773         struct mlx5_inbox_hdr   hdr;
 774         u8                      rsvd0[3];
 775         u8                      eqn;
 776         u8                      rsvd1[4];
 777 };
 778
 779 struct mlx5_destroy_eq_mbox_out {
 780         struct mlx5_outbox_hdr  hdr;
 781         u8                      rsvd[8];
 782 };
 783
 784 struct mlx5_map_eq_mbox_in {
 785         struct mlx5_inbox_hdr   hdr;
 786         __be64                  mask;
 787         u8                      mu;
 788         u8                      rsvd0[2];
 789         u8                      eqn;
 790         u8                      rsvd1[24];
 791 };
 792
 793 struct mlx5_map_eq_mbox_out {
 794         struct mlx5_outbox_hdr  hdr;
 795         u8                      rsvd[8];
 796 };
 797
 798 struct mlx5_query_eq_mbox_in {
 799         struct mlx5_inbox_hdr   hdr;
 800         u8                      rsvd0[3];
 801         u8                      eqn;
 802         u8                      rsvd1[4];
 803 };
 804
 805 struct mlx5_query_eq_mbox_out {
 806         struct mlx5_outbox_hdr  hdr;
 807         u8                      rsvd[8];
 808         struct mlx5_eq_context  ctx;
 809 };
 810
 811 struct mlx5_mkey_seg {
 812         /* This is a two bit field occupying bits 31-30.
 813          * bit 31 is always 0,
 814          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 815          */
 816         u8              status;
 817         u8              pcie_control;
 818         u8              flags;
 819         u8              version;
 820         __be32          qpn_mkey7_0;
 821         u8              rsvd1[4];
 822         __be32          flags_pd;
 823         __be64          start_addr;
 824         __be64          len;
 825         __be32          bsfs_octo_size;
 826         u8              rsvd2[16];
 827         __be32          xlt_oct_size;
 828         u8              rsvd3[3];
 829         u8              log2_page_size;
 830         u8              rsvd4[4];
 831 };
 832
 833 struct mlx5_query_special_ctxs_mbox_in {
 834         struct mlx5_inbox_hdr   hdr;
 835         u8                      rsvd[8];
 836 };
 837
 838 struct mlx5_query_special_ctxs_mbox_out {
 839         struct mlx5_outbox_hdr  hdr;
 840         __be32                  dump_fill_mkey;
 841         __be32                  reserved_lkey;
 842 };
 843
 844 struct mlx5_create_mkey_mbox_in {
 845         struct mlx5_inbox_hdr   hdr;
 846         __be32                  input_mkey_index;
 847         u8                      rsvd0[4];
 848         struct mlx5_mkey_seg    seg;
 849         u8                      rsvd1[16];
 850         __be32                  xlat_oct_act_size;
 851         __be32                  bsf_coto_act_size;
 852         u8                      rsvd2[168];
 853         __be64                  pas[0];
 854 };
 855
 856 struct mlx5_create_mkey_mbox_out {
 857         struct mlx5_outbox_hdr  hdr;
 858         __be32                  mkey;
 859         u8                      rsvd[4];
 860 };
 861
 862 struct mlx5_destroy_mkey_mbox_in {
 863         struct mlx5_inbox_hdr   hdr;
 864         __be32                  mkey;
 865         u8                      rsvd[4];
 866 };
 867
 868 struct mlx5_destroy_mkey_mbox_out {
 869         struct mlx5_outbox_hdr  hdr;
 870         u8                      rsvd[8];
 871 };
 872
 873 struct mlx5_query_mkey_mbox_in {
 874         struct mlx5_inbox_hdr   hdr;
 875         __be32                  mkey;
 876 };
 877
 878 struct mlx5_query_mkey_mbox_out {
 879         struct mlx5_outbox_hdr  hdr;
 880         __be64                  pas[0];
 881 };
 882
 883 struct mlx5_modify_mkey_mbox_in {
 884         struct mlx5_inbox_hdr   hdr;
 885         __be32                  mkey;
 886         __be64                  pas[0];
 887 };
 888
 889 struct mlx5_modify_mkey_mbox_out {
 890         struct mlx5_outbox_hdr  hdr;
 891         u8                      rsvd[8];
 892 };
 893
 894 struct mlx5_dump_mkey_mbox_in {
 895         struct mlx5_inbox_hdr   hdr;
 896 };
 897
 898 struct mlx5_dump_mkey_mbox_out {
 899         struct mlx5_outbox_hdr  hdr;
 900         __be32                  mkey;
 901 };
 902
 903 struct mlx5_mad_ifc_mbox_in {
 904         struct mlx5_inbox_hdr   hdr;
 905         __be16                  remote_lid;
 906         u8                      rsvd0;
 907         u8                      port;
 908         u8                      rsvd1[4];
 909         u8                      data[256];
 910 };
 911
 912 struct mlx5_mad_ifc_mbox_out {
 913         struct mlx5_outbox_hdr  hdr;
 914         u8                      rsvd[8];
 915         u8                      data[256];
 916 };
 917
 918 struct mlx5_access_reg_mbox_in {
 919         struct mlx5_inbox_hdr           hdr;
 920         u8                              rsvd0[2];
 921         __be16                          register_id;
 922         __be32                          arg;
 923         __be32                          data[0];
 924 };
 925
 926 struct mlx5_access_reg_mbox_out {
 927         struct mlx5_outbox_hdr          hdr;
 928         u8                              rsvd[8];
 929         __be32                          data[0];
 930 };
 931
 932 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 933
 934 enum {
 935         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 936 };
 937
 938 #endif /* MLX5_DEVICE_H */