include/linux/mlx5/device.h

   1 /*
   2  * Copyright (c) 2013, Mellanox Technologies inc.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef MLX5_DEVICE_H
  34 #define MLX5_DEVICE_H
  35
  36 #include <linux/types.h>
  37 #include <rdma/ib_verbs.h>
  38
  39 #if defined(__LITTLE_ENDIAN)
  40 #define MLX5_SET_HOST_ENDIANNESS        0
  41 #elif defined(__BIG_ENDIAN)
  42 #define MLX5_SET_HOST_ENDIANNESS        0x80
  43 #else
  44 #error Host endianness not defined
  45 #endif
  46
  47 /* helper macros */
  48 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  49 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  50 #define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
  51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  53 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  54 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  55 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  56 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  57
  58 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  59 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  60 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  61 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  62 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  63
  64 /* insert a value to a struct */
  65 #define MLX5_SET(typ, p, fld, v) do { \
  66         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  67         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  68         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  69                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  70                      << __mlx5_dw_bit_off(typ, fld))); \
  71 } while (0)
  72
  73 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  74 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  75 __mlx5_mask(typ, fld))
  76
  77 #define MLX5_GET_PR(typ, p, fld) ({ \
  78         u32 ___t = MLX5_GET(typ, p, fld); \
  79         pr_debug(#fld " = 0x%x\n", ___t); \
  80         ___t; \
  81 })
  82
  83 #define MLX5_SET64(typ, p, fld, v) do { \
  84         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
  85         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
  86         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
  87 } while (0)
  88
  89 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
  90
  91 enum {
  92         MLX5_MAX_COMMANDS               = 32,
  93         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
  94         MLX5_PCI_CMD_XPORT              = 7,
  95         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
  96         MLX5_MAX_PSVS                   = 4,
  97 };
  98
  99 enum {
 100         MLX5_EXTENDED_UD_AV             = 0x80000000,
 101 };
 102
 103 enum {
 104         MLX5_CQ_STATE_ARMED             = 9,
 105         MLX5_CQ_STATE_ALWAYS_ARMED      = 0xb,
 106         MLX5_CQ_STATE_FIRED             = 0xa,
 107 };
 108
 109 enum {
 110         MLX5_STAT_RATE_OFFSET   = 5,
 111 };
 112
 113 enum {
 114         MLX5_INLINE_SEG = 0x80000000,
 115 };
 116
 117 enum {
 118         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 119         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 120 };
 121
 122 enum {
 123         MLX5_PERM_LOCAL_READ    = 1 << 2,
 124         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 125         MLX5_PERM_REMOTE_READ   = 1 << 4,
 126         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 127         MLX5_PERM_ATOMIC        = 1 << 6,
 128         MLX5_PERM_UMR_EN        = 1 << 7,
 129 };
 130
 131 enum {
 132         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 133         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 134         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 135         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 136         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 137 };
 138
 139 enum {
 140         MLX5_ACCESS_MODE_PA     = 0,
 141         MLX5_ACCESS_MODE_MTT    = 1,
 142         MLX5_ACCESS_MODE_KLM    = 2
 143 };
 144
 145 enum {
 146         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 147         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 148         MLX5_MKEY_BSF_EN        = 1 << 30,
 149         MLX5_MKEY_LEN64         = 1 << 31,
 150 };
 151
 152 enum {
 153         MLX5_EN_RD      = (u64)1,
 154         MLX5_EN_WR      = (u64)2
 155 };
 156
 157 enum {
 158         MLX5_BF_REGS_PER_PAGE           = 4,
 159         MLX5_MAX_UAR_PAGES              = 1 << 8,
 160         MLX5_NON_FP_BF_REGS_PER_PAGE    = 2,
 161         MLX5_MAX_UUARS  = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
 162 };
 163
 164 enum {
 165         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 166         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 167         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 168         MLX5_MKEY_MASK_PD               = 1ull << 7,
 169         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 170         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 171         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 172         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 173         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 174         MLX5_MKEY_MASK_LR               = 1ull << 17,
 175         MLX5_MKEY_MASK_LW               = 1ull << 18,
 176         MLX5_MKEY_MASK_RR               = 1ull << 19,
 177         MLX5_MKEY_MASK_RW               = 1ull << 20,
 178         MLX5_MKEY_MASK_A                = 1ull << 21,
 179         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 180         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 181 };
 182
 183 enum mlx5_event {
 184         MLX5_EVENT_TYPE_COMP               = 0x0,
 185
 186         MLX5_EVENT_TYPE_PATH_MIG           = 0x01,
 187         MLX5_EVENT_TYPE_COMM_EST           = 0x02,
 188         MLX5_EVENT_TYPE_SQ_DRAINED         = 0x03,
 189         MLX5_EVENT_TYPE_SRQ_LAST_WQE       = 0x13,
 190         MLX5_EVENT_TYPE_SRQ_RQ_LIMIT       = 0x14,
 191
 192         MLX5_EVENT_TYPE_CQ_ERROR           = 0x04,
 193         MLX5_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
 194         MLX5_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
 195         MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
 196         MLX5_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
 197         MLX5_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
 198
 199         MLX5_EVENT_TYPE_INTERNAL_ERROR     = 0x08,
 200         MLX5_EVENT_TYPE_PORT_CHANGE        = 0x09,
 201         MLX5_EVENT_TYPE_GPIO_EVENT         = 0x15,
 202         MLX5_EVENT_TYPE_REMOTE_CONFIG      = 0x19,
 203
 204         MLX5_EVENT_TYPE_DB_BF_CONGESTION   = 0x1a,
 205         MLX5_EVENT_TYPE_STALL_EVENT        = 0x1b,
 206
 207         MLX5_EVENT_TYPE_CMD                = 0x0a,
 208         MLX5_EVENT_TYPE_PAGE_REQUEST       = 0xb,
 209 };
 210
 211 enum {
 212         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 213         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 214         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 215         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 216         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 217         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 218         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 219 };
 220
 221 enum {
 222         MLX5_DEV_CAP_FLAG_RC            = 1LL <<  0,
 223         MLX5_DEV_CAP_FLAG_UC            = 1LL <<  1,
 224         MLX5_DEV_CAP_FLAG_UD            = 1LL <<  2,
 225         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 226         MLX5_DEV_CAP_FLAG_SRQ           = 1LL <<  6,
 227         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 228         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 229         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 230         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 18,
 231         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 232         MLX5_DEV_CAP_FLAG_ON_DMND_PG    = 1LL << 24,
 233         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 234         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 235         MLX5_DEV_CAP_FLAG_RESIZE_SRQ    = 1LL << 32,
 236         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 237         MLX5_DEV_CAP_FLAG_REMOTE_FENCE  = 1LL << 38,
 238         MLX5_DEV_CAP_FLAG_TLP_HINTS     = 1LL << 39,
 239         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 240         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 241 };
 242
 243 enum {
 244         MLX5_OPCODE_NOP                 = 0x00,
 245         MLX5_OPCODE_SEND_INVAL          = 0x01,
 246         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 247         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 248         MLX5_OPCODE_SEND                = 0x0a,
 249         MLX5_OPCODE_SEND_IMM            = 0x0b,
 250         MLX5_OPCODE_RDMA_READ           = 0x10,
 251         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 252         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 253         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 254         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 255         MLX5_OPCODE_BIND_MW             = 0x18,
 256         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 257
 258         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 259         MLX5_RECV_OPCODE_SEND           = 0x01,
 260         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 261         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 262
 263         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 264         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 265
 266         MLX5_OPCODE_SET_PSV             = 0x20,
 267         MLX5_OPCODE_GET_PSV             = 0x21,
 268         MLX5_OPCODE_CHECK_PSV           = 0x22,
 269         MLX5_OPCODE_RGET_PSV            = 0x26,
 270         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 271
 272         MLX5_OPCODE_UMR                 = 0x25,
 273
 274 };
 275
 276 enum {
 277         MLX5_SET_PORT_RESET_QKEY        = 0,
 278         MLX5_SET_PORT_GUID0             = 16,
 279         MLX5_SET_PORT_NODE_GUID         = 17,
 280         MLX5_SET_PORT_SYS_GUID          = 18,
 281         MLX5_SET_PORT_GID_TABLE         = 19,
 282         MLX5_SET_PORT_PKEY_TABLE        = 20,
 283 };
 284
 285 enum {
 286         MLX5_MAX_PAGE_SHIFT             = 31
 287 };
 288
 289 enum {
 290         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 291         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 292 };
 293
 294 enum {
 295         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 296 };
 297
 298 enum {
 299         HCA_CAP_OPMOD_GET_MAX   = 0,
 300         HCA_CAP_OPMOD_GET_CUR   = 1,
 301 };
 302
 303 struct mlx5_inbox_hdr {
 304         __be16          opcode;
 305         u8              rsvd[4];
 306         __be16          opmod;
 307 };
 308
 309 struct mlx5_outbox_hdr {
 310         u8              status;
 311         u8              rsvd[3];
 312         __be32          syndrome;
 313 };
 314
 315 struct mlx5_cmd_query_adapter_mbox_in {
 316         struct mlx5_inbox_hdr   hdr;
 317         u8                      rsvd[8];
 318 };
 319
 320 struct mlx5_cmd_query_adapter_mbox_out {
 321         struct mlx5_outbox_hdr  hdr;
 322         u8                      rsvd0[24];
 323         u8                      intapin;
 324         u8                      rsvd1[13];
 325         __be16                  vsd_vendor_id;
 326         u8                      vsd[208];
 327         u8                      vsd_psid[16];
 328 };
 329
 330 struct mlx5_cmd_init_hca_mbox_in {
 331         struct mlx5_inbox_hdr   hdr;
 332         u8                      rsvd0[2];
 333         __be16                  profile;
 334         u8                      rsvd1[4];
 335 };
 336
 337 struct mlx5_cmd_init_hca_mbox_out {
 338         struct mlx5_outbox_hdr  hdr;
 339         u8                      rsvd[8];
 340 };
 341
 342 struct mlx5_cmd_teardown_hca_mbox_in {
 343         struct mlx5_inbox_hdr   hdr;
 344         u8                      rsvd0[2];
 345         __be16                  profile;
 346         u8                      rsvd1[4];
 347 };
 348
 349 struct mlx5_cmd_teardown_hca_mbox_out {
 350         struct mlx5_outbox_hdr  hdr;
 351         u8                      rsvd[8];
 352 };
 353
 354 struct mlx5_cmd_layout {
 355         u8              type;
 356         u8              rsvd0[3];
 357         __be32          inlen;
 358         __be64          in_ptr;
 359         __be32          in[4];
 360         __be32          out[4];
 361         __be64          out_ptr;
 362         __be32          outlen;
 363         u8              token;
 364         u8              sig;
 365         u8              rsvd1;
 366         u8              status_own;
 367 };
 368
 369
 370 struct health_buffer {
 371         __be32          assert_var[5];
 372         __be32          rsvd0[3];
 373         __be32          assert_exit_ptr;
 374         __be32          assert_callra;
 375         __be32          rsvd1[2];
 376         __be32          fw_ver;
 377         __be32          hw_id;
 378         __be32          rsvd2;
 379         u8              irisc_index;
 380         u8              synd;
 381         __be16          ext_sync;
 382 };
 383
 384 struct mlx5_init_seg {
 385         __be32                  fw_rev;
 386         __be32                  cmdif_rev_fw_sub;
 387         __be32                  rsvd0[2];
 388         __be32                  cmdq_addr_h;
 389         __be32                  cmdq_addr_l_sz;
 390         __be32                  cmd_dbell;
 391         __be32                  rsvd1[121];
 392         struct health_buffer    health;
 393         __be32                  rsvd2[884];
 394         __be32                  health_counter;
 395         __be32                  rsvd3[1019];
 396         __be64                  ieee1588_clk;
 397         __be32                  ieee1588_clk_type;
 398         __be32                  clr_intx;
 399 };
 400
 401 struct mlx5_eqe_comp {
 402         __be32  reserved[6];
 403         __be32  cqn;
 404 };
 405
 406 struct mlx5_eqe_qp_srq {
 407         __be32  reserved[6];
 408         __be32  qp_srq_n;
 409 };
 410
 411 struct mlx5_eqe_cq_err {
 412         __be32  cqn;
 413         u8      reserved1[7];
 414         u8      syndrome;
 415 };
 416
 417 struct mlx5_eqe_port_state {
 418         u8      reserved0[8];
 419         u8      port;
 420 };
 421
 422 struct mlx5_eqe_gpio {
 423         __be32  reserved0[2];
 424         __be64  gpio_event;
 425 };
 426
 427 struct mlx5_eqe_congestion {
 428         u8      type;
 429         u8      rsvd0;
 430         u8      congestion_level;
 431 };
 432
 433 struct mlx5_eqe_stall_vl {
 434         u8      rsvd0[3];
 435         u8      port_vl;
 436 };
 437
 438 struct mlx5_eqe_cmd {
 439         __be32  vector;
 440         __be32  rsvd[6];
 441 };
 442
 443 struct mlx5_eqe_page_req {
 444         u8              rsvd0[2];
 445         __be16          func_id;
 446         __be32          num_pages;
 447         __be32          rsvd1[5];
 448 };
 449
 450 union ev_data {
 451         __be32                          raw[7];
 452         struct mlx5_eqe_cmd             cmd;
 453         struct mlx5_eqe_comp            comp;
 454         struct mlx5_eqe_qp_srq          qp_srq;
 455         struct mlx5_eqe_cq_err          cq_err;
 456         struct mlx5_eqe_port_state      port;
 457         struct mlx5_eqe_gpio            gpio;
 458         struct mlx5_eqe_congestion      cong;
 459         struct mlx5_eqe_stall_vl        stall_vl;
 460         struct mlx5_eqe_page_req        req_pages;
 461 } __packed;
 462
 463 struct mlx5_eqe {
 464         u8              rsvd0;
 465         u8              type;
 466         u8              rsvd1;
 467         u8              sub_type;
 468         __be32          rsvd2[7];
 469         union ev_data   data;
 470         __be16          rsvd3;
 471         u8              signature;
 472         u8              owner;
 473 } __packed;
 474
 475 struct mlx5_cmd_prot_block {
 476         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 477         u8              rsvd0[48];
 478         __be64          next;
 479         __be32          block_num;
 480         u8              rsvd1;
 481         u8              token;
 482         u8              ctrl_sig;
 483         u8              sig;
 484 };
 485
 486 struct mlx5_err_cqe {
 487         u8      rsvd0[32];
 488         __be32  srqn;
 489         u8      rsvd1[18];
 490         u8      vendor_err_synd;
 491         u8      syndrome;
 492         __be32  s_wqe_opcode_qpn;
 493         __be16  wqe_counter;
 494         u8      signature;
 495         u8      op_own;
 496 };
 497
 498 struct mlx5_cqe64 {
 499         u8              rsvd0[17];
 500         u8              ml_path;
 501         u8              rsvd20[4];
 502         __be16          slid;
 503         __be32          flags_rqpn;
 504         u8              rsvd28[4];
 505         __be32          srqn;
 506         __be32          imm_inval_pkey;
 507         u8              rsvd40[4];
 508         __be32          byte_cnt;
 509         __be64          timestamp;
 510         __be32          sop_drop_qpn;
 511         __be16          wqe_counter;
 512         u8              signature;
 513         u8              op_own;
 514 };
 515
 516 struct mlx5_sig_err_cqe {
 517         u8              rsvd0[16];
 518         __be32          expected_trans_sig;
 519         __be32          actual_trans_sig;
 520         __be32          expected_reftag;
 521         __be32          actual_reftag;
 522         __be16          syndrome;
 523         u8              rsvd22[2];
 524         __be32          mkey;
 525         __be64          err_offset;
 526         u8              rsvd30[8];
 527         __be32          qpn;
 528         u8              rsvd38[2];
 529         u8              signature;
 530         u8              op_own;
 531 };
 532
 533 struct mlx5_wqe_srq_next_seg {
 534         u8                      rsvd0[2];
 535         __be16                  next_wqe_index;
 536         u8                      signature;
 537         u8                      rsvd1[11];
 538 };
 539
 540 union mlx5_ext_cqe {
 541         struct ib_grh   grh;
 542         u8              inl[64];
 543 };
 544
 545 struct mlx5_cqe128 {
 546         union mlx5_ext_cqe      inl_grh;
 547         struct mlx5_cqe64       cqe64;
 548 };
 549
 550 struct mlx5_srq_ctx {
 551         u8                      state_log_sz;
 552         u8                      rsvd0[3];
 553         __be32                  flags_xrcd;
 554         __be32                  pgoff_cqn;
 555         u8                      rsvd1[4];
 556         u8                      log_pg_sz;
 557         u8                      rsvd2[7];
 558         __be32                  pd;
 559         __be16                  lwm;
 560         __be16                  wqe_cnt;
 561         u8                      rsvd3[8];
 562         __be64                  db_record;
 563 };
 564
 565 struct mlx5_create_srq_mbox_in {
 566         struct mlx5_inbox_hdr   hdr;
 567         __be32                  input_srqn;
 568         u8                      rsvd0[4];
 569         struct mlx5_srq_ctx     ctx;
 570         u8                      rsvd1[208];
 571         __be64                  pas[0];
 572 };
 573
 574 struct mlx5_create_srq_mbox_out {
 575         struct mlx5_outbox_hdr  hdr;
 576         __be32                  srqn;
 577         u8                      rsvd[4];
 578 };
 579
 580 struct mlx5_destroy_srq_mbox_in {
 581         struct mlx5_inbox_hdr   hdr;
 582         __be32                  srqn;
 583         u8                      rsvd[4];
 584 };
 585
 586 struct mlx5_destroy_srq_mbox_out {
 587         struct mlx5_outbox_hdr  hdr;
 588         u8                      rsvd[8];
 589 };
 590
 591 struct mlx5_query_srq_mbox_in {
 592         struct mlx5_inbox_hdr   hdr;
 593         __be32                  srqn;
 594         u8                      rsvd0[4];
 595 };
 596
 597 struct mlx5_query_srq_mbox_out {
 598         struct mlx5_outbox_hdr  hdr;
 599         u8                      rsvd0[8];
 600         struct mlx5_srq_ctx     ctx;
 601         u8                      rsvd1[32];
 602         __be64                  pas[0];
 603 };
 604
 605 struct mlx5_arm_srq_mbox_in {
 606         struct mlx5_inbox_hdr   hdr;
 607         __be32                  srqn;
 608         __be16                  rsvd;
 609         __be16                  lwm;
 610 };
 611
 612 struct mlx5_arm_srq_mbox_out {
 613         struct mlx5_outbox_hdr  hdr;
 614         u8                      rsvd[8];
 615 };
 616
 617 struct mlx5_cq_context {
 618         u8                      status;
 619         u8                      cqe_sz_flags;
 620         u8                      st;
 621         u8                      rsvd3;
 622         u8                      rsvd4[6];
 623         __be16                  page_offset;
 624         __be32                  log_sz_usr_page;
 625         __be16                  cq_period;
 626         __be16                  cq_max_count;
 627         __be16                  rsvd20;
 628         __be16                  c_eqn;
 629         u8                      log_pg_sz;
 630         u8                      rsvd25[7];
 631         __be32                  last_notified_index;
 632         __be32                  solicit_producer_index;
 633         __be32                  consumer_counter;
 634         __be32                  producer_counter;
 635         u8                      rsvd48[8];
 636         __be64                  db_record_addr;
 637 };
 638
 639 struct mlx5_create_cq_mbox_in {
 640         struct mlx5_inbox_hdr   hdr;
 641         __be32                  input_cqn;
 642         u8                      rsvdx[4];
 643         struct mlx5_cq_context  ctx;
 644         u8                      rsvd6[192];
 645         __be64                  pas[0];
 646 };
 647
 648 struct mlx5_create_cq_mbox_out {
 649         struct mlx5_outbox_hdr  hdr;
 650         __be32                  cqn;
 651         u8                      rsvd0[4];
 652 };
 653
 654 struct mlx5_destroy_cq_mbox_in {
 655         struct mlx5_inbox_hdr   hdr;
 656         __be32                  cqn;
 657         u8                      rsvd0[4];
 658 };
 659
 660 struct mlx5_destroy_cq_mbox_out {
 661         struct mlx5_outbox_hdr  hdr;
 662         u8                      rsvd0[8];
 663 };
 664
 665 struct mlx5_query_cq_mbox_in {
 666         struct mlx5_inbox_hdr   hdr;
 667         __be32                  cqn;
 668         u8                      rsvd0[4];
 669 };
 670
 671 struct mlx5_query_cq_mbox_out {
 672         struct mlx5_outbox_hdr  hdr;
 673         u8                      rsvd0[8];
 674         struct mlx5_cq_context  ctx;
 675         u8                      rsvd6[16];
 676         __be64                  pas[0];
 677 };
 678
 679 struct mlx5_modify_cq_mbox_in {
 680         struct mlx5_inbox_hdr   hdr;
 681         __be32                  cqn;
 682         __be32                  field_select;
 683         struct mlx5_cq_context  ctx;
 684         u8                      rsvd[192];
 685         __be64                  pas[0];
 686 };
 687
 688 struct mlx5_modify_cq_mbox_out {
 689         struct mlx5_outbox_hdr  hdr;
 690         u8                      rsvd[8];
 691 };
 692
 693 struct mlx5_enable_hca_mbox_in {
 694         struct mlx5_inbox_hdr   hdr;
 695         u8                      rsvd[8];
 696 };
 697
 698 struct mlx5_enable_hca_mbox_out {
 699         struct mlx5_outbox_hdr  hdr;
 700         u8                      rsvd[8];
 701 };
 702
 703 struct mlx5_disable_hca_mbox_in {
 704         struct mlx5_inbox_hdr   hdr;
 705         u8                      rsvd[8];
 706 };
 707
 708 struct mlx5_disable_hca_mbox_out {
 709         struct mlx5_outbox_hdr  hdr;
 710         u8                      rsvd[8];
 711 };
 712
 713 struct mlx5_eq_context {
 714         u8                      status;
 715         u8                      ec_oi;
 716         u8                      st;
 717         u8                      rsvd2[7];
 718         __be16                  page_pffset;
 719         __be32                  log_sz_usr_page;
 720         u8                      rsvd3[7];
 721         u8                      intr;
 722         u8                      log_page_size;
 723         u8                      rsvd4[15];
 724         __be32                  consumer_counter;
 725         __be32                  produser_counter;
 726         u8                      rsvd5[16];
 727 };
 728
 729 struct mlx5_create_eq_mbox_in {
 730         struct mlx5_inbox_hdr   hdr;
 731         u8                      rsvd0[3];
 732         u8                      input_eqn;
 733         u8                      rsvd1[4];
 734         struct mlx5_eq_context  ctx;
 735         u8                      rsvd2[8];
 736         __be64                  events_mask;
 737         u8                      rsvd3[176];
 738         __be64                  pas[0];
 739 };
 740
 741 struct mlx5_create_eq_mbox_out {
 742         struct mlx5_outbox_hdr  hdr;
 743         u8                      rsvd0[3];
 744         u8                      eq_number;
 745         u8                      rsvd1[4];
 746 };
 747
 748 struct mlx5_destroy_eq_mbox_in {
 749         struct mlx5_inbox_hdr   hdr;
 750         u8                      rsvd0[3];
 751         u8                      eqn;
 752         u8                      rsvd1[4];
 753 };
 754
 755 struct mlx5_destroy_eq_mbox_out {
 756         struct mlx5_outbox_hdr  hdr;
 757         u8                      rsvd[8];
 758 };
 759
 760 struct mlx5_map_eq_mbox_in {
 761         struct mlx5_inbox_hdr   hdr;
 762         __be64                  mask;
 763         u8                      mu;
 764         u8                      rsvd0[2];
 765         u8                      eqn;
 766         u8                      rsvd1[24];
 767 };
 768
 769 struct mlx5_map_eq_mbox_out {
 770         struct mlx5_outbox_hdr  hdr;
 771         u8                      rsvd[8];
 772 };
 773
 774 struct mlx5_query_eq_mbox_in {
 775         struct mlx5_inbox_hdr   hdr;
 776         u8                      rsvd0[3];
 777         u8                      eqn;
 778         u8                      rsvd1[4];
 779 };
 780
 781 struct mlx5_query_eq_mbox_out {
 782         struct mlx5_outbox_hdr  hdr;
 783         u8                      rsvd[8];
 784         struct mlx5_eq_context  ctx;
 785 };
 786
 787 struct mlx5_mkey_seg {
 788         /* This is a two bit field occupying bits 31-30.
 789          * bit 31 is always 0,
 790          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 791          */
 792         u8              status;
 793         u8              pcie_control;
 794         u8              flags;
 795         u8              version;
 796         __be32          qpn_mkey7_0;
 797         u8              rsvd1[4];
 798         __be32          flags_pd;
 799         __be64          start_addr;
 800         __be64          len;
 801         __be32          bsfs_octo_size;
 802         u8              rsvd2[16];
 803         __be32          xlt_oct_size;
 804         u8              rsvd3[3];
 805         u8              log2_page_size;
 806         u8              rsvd4[4];
 807 };
 808
 809 struct mlx5_query_special_ctxs_mbox_in {
 810         struct mlx5_inbox_hdr   hdr;
 811         u8                      rsvd[8];
 812 };
 813
 814 struct mlx5_query_special_ctxs_mbox_out {
 815         struct mlx5_outbox_hdr  hdr;
 816         __be32                  dump_fill_mkey;
 817         __be32                  reserved_lkey;
 818 };
 819
 820 struct mlx5_create_mkey_mbox_in {
 821         struct mlx5_inbox_hdr   hdr;
 822         __be32                  input_mkey_index;
 823         u8                      rsvd0[4];
 824         struct mlx5_mkey_seg    seg;
 825         u8                      rsvd1[16];
 826         __be32                  xlat_oct_act_size;
 827         __be32                  rsvd2;
 828         u8                      rsvd3[168];
 829         __be64                  pas[0];
 830 };
 831
 832 struct mlx5_create_mkey_mbox_out {
 833         struct mlx5_outbox_hdr  hdr;
 834         __be32                  mkey;
 835         u8                      rsvd[4];
 836 };
 837
 838 struct mlx5_destroy_mkey_mbox_in {
 839         struct mlx5_inbox_hdr   hdr;
 840         __be32                  mkey;
 841         u8                      rsvd[4];
 842 };
 843
 844 struct mlx5_destroy_mkey_mbox_out {
 845         struct mlx5_outbox_hdr  hdr;
 846         u8                      rsvd[8];
 847 };
 848
 849 struct mlx5_query_mkey_mbox_in {
 850         struct mlx5_inbox_hdr   hdr;
 851         __be32                  mkey;
 852 };
 853
 854 struct mlx5_query_mkey_mbox_out {
 855         struct mlx5_outbox_hdr  hdr;
 856         __be64                  pas[0];
 857 };
 858
 859 struct mlx5_modify_mkey_mbox_in {
 860         struct mlx5_inbox_hdr   hdr;
 861         __be32                  mkey;
 862         __be64                  pas[0];
 863 };
 864
 865 struct mlx5_modify_mkey_mbox_out {
 866         struct mlx5_outbox_hdr  hdr;
 867         u8                      rsvd[8];
 868 };
 869
 870 struct mlx5_dump_mkey_mbox_in {
 871         struct mlx5_inbox_hdr   hdr;
 872 };
 873
 874 struct mlx5_dump_mkey_mbox_out {
 875         struct mlx5_outbox_hdr  hdr;
 876         __be32                  mkey;
 877 };
 878
 879 struct mlx5_mad_ifc_mbox_in {
 880         struct mlx5_inbox_hdr   hdr;
 881         __be16                  remote_lid;
 882         u8                      rsvd0;
 883         u8                      port;
 884         u8                      rsvd1[4];
 885         u8                      data[256];
 886 };
 887
 888 struct mlx5_mad_ifc_mbox_out {
 889         struct mlx5_outbox_hdr  hdr;
 890         u8                      rsvd[8];
 891         u8                      data[256];
 892 };
 893
 894 struct mlx5_access_reg_mbox_in {
 895         struct mlx5_inbox_hdr           hdr;
 896         u8                              rsvd0[2];
 897         __be16                          register_id;
 898         __be32                          arg;
 899         __be32                          data[0];
 900 };
 901
 902 struct mlx5_access_reg_mbox_out {
 903         struct mlx5_outbox_hdr          hdr;
 904         u8                              rsvd[8];
 905         __be32                          data[0];
 906 };
 907
 908 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 909
 910 enum {
 911         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 912 };
 913
 914 struct mlx5_allocate_psv_in {
 915         struct mlx5_inbox_hdr   hdr;
 916         __be32                  npsv_pd;
 917         __be32                  rsvd_psv0;
 918 };
 919
 920 struct mlx5_allocate_psv_out {
 921         struct mlx5_outbox_hdr  hdr;
 922         u8                      rsvd[8];
 923         __be32                  psv_idx[4];
 924 };
 925
 926 struct mlx5_destroy_psv_in {
 927         struct mlx5_inbox_hdr   hdr;
 928         __be32                  psv_number;
 929         u8                      rsvd[4];
 930 };
 931
 932 struct mlx5_destroy_psv_out {
 933         struct mlx5_outbox_hdr  hdr;
 934         u8                      rsvd[8];
 935 };
 936
 937 #endif /* MLX5_DEVICE_H */