2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_CREATE_XRQ = 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
128 MLX5_CMD_OP_QUERY_XRQ = 0x719,
129 MLX5_CMD_OP_ARM_XRQ = 0x71a,
130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
148 MLX5_CMD_OP_ALLOC_PD = 0x800,
149 MLX5_CMD_OP_DEALLOC_PD = 0x801,
150 MLX5_CMD_OP_ALLOC_UAR = 0x802,
151 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
153 MLX5_CMD_OP_ACCESS_REG = 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
155 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
157 MLX5_CMD_OP_MAD_IFC = 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
160 MLX5_CMD_OP_NOP = 0x80d,
161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
175 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
177 MLX5_CMD_OP_CREATE_TIR = 0x900,
178 MLX5_CMD_OP_MODIFY_TIR = 0x901,
179 MLX5_CMD_OP_DESTROY_TIR = 0x902,
180 MLX5_CMD_OP_QUERY_TIR = 0x903,
181 MLX5_CMD_OP_CREATE_SQ = 0x904,
182 MLX5_CMD_OP_MODIFY_SQ = 0x905,
183 MLX5_CMD_OP_DESTROY_SQ = 0x906,
184 MLX5_CMD_OP_QUERY_SQ = 0x907,
185 MLX5_CMD_OP_CREATE_RQ = 0x908,
186 MLX5_CMD_OP_MODIFY_RQ = 0x909,
187 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
188 MLX5_CMD_OP_QUERY_RQ = 0x90b,
189 MLX5_CMD_OP_CREATE_RMP = 0x90c,
190 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
191 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
192 MLX5_CMD_OP_QUERY_RMP = 0x90f,
193 MLX5_CMD_OP_CREATE_TIS = 0x912,
194 MLX5_CMD_OP_MODIFY_TIS = 0x913,
195 MLX5_CMD_OP_DESTROY_TIS = 0x914,
196 MLX5_CMD_OP_QUERY_TIS = 0x915,
197 MLX5_CMD_OP_CREATE_RQT = 0x916,
198 MLX5_CMD_OP_MODIFY_RQT = 0x917,
199 MLX5_CMD_OP_DESTROY_RQT = 0x918,
200 MLX5_CMD_OP_QUERY_RQT = 0x919,
201 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
202 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
203 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
204 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
205 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
206 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
207 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
208 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
209 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
210 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
211 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
218 struct mlx5_ifc_flow_table_fields_supported_bits {
221 u8 outer_ether_type[0x1];
222 u8 reserved_at_3[0x1];
223 u8 outer_first_prio[0x1];
224 u8 outer_first_cfi[0x1];
225 u8 outer_first_vid[0x1];
226 u8 reserved_at_7[0x1];
227 u8 outer_second_prio[0x1];
228 u8 outer_second_cfi[0x1];
229 u8 outer_second_vid[0x1];
230 u8 reserved_at_b[0x1];
234 u8 outer_ip_protocol[0x1];
235 u8 outer_ip_ecn[0x1];
236 u8 outer_ip_dscp[0x1];
237 u8 outer_udp_sport[0x1];
238 u8 outer_udp_dport[0x1];
239 u8 outer_tcp_sport[0x1];
240 u8 outer_tcp_dport[0x1];
241 u8 outer_tcp_flags[0x1];
242 u8 outer_gre_protocol[0x1];
243 u8 outer_gre_key[0x1];
244 u8 outer_vxlan_vni[0x1];
245 u8 reserved_at_1a[0x5];
246 u8 source_eswitch_port[0x1];
250 u8 inner_ether_type[0x1];
251 u8 reserved_at_23[0x1];
252 u8 inner_first_prio[0x1];
253 u8 inner_first_cfi[0x1];
254 u8 inner_first_vid[0x1];
255 u8 reserved_at_27[0x1];
256 u8 inner_second_prio[0x1];
257 u8 inner_second_cfi[0x1];
258 u8 inner_second_vid[0x1];
259 u8 reserved_at_2b[0x1];
263 u8 inner_ip_protocol[0x1];
264 u8 inner_ip_ecn[0x1];
265 u8 inner_ip_dscp[0x1];
266 u8 inner_udp_sport[0x1];
267 u8 inner_udp_dport[0x1];
268 u8 inner_tcp_sport[0x1];
269 u8 inner_tcp_dport[0x1];
270 u8 inner_tcp_flags[0x1];
271 u8 reserved_at_37[0x9];
273 u8 reserved_at_40[0x40];
276 struct mlx5_ifc_flow_table_prop_layout_bits {
278 u8 reserved_at_1[0x1];
279 u8 flow_counter[0x1];
280 u8 flow_modify_en[0x1];
282 u8 identified_miss_table_mode[0x1];
283 u8 flow_table_modify[0x1];
284 u8 reserved_at_7[0x19];
286 u8 reserved_at_20[0x2];
287 u8 log_max_ft_size[0x6];
288 u8 reserved_at_28[0x10];
289 u8 max_ft_level[0x8];
291 u8 reserved_at_40[0x20];
293 u8 reserved_at_60[0x18];
294 u8 log_max_ft_num[0x8];
296 u8 reserved_at_80[0x18];
297 u8 log_max_destination[0x8];
299 u8 reserved_at_a0[0x18];
300 u8 log_max_flow[0x8];
302 u8 reserved_at_c0[0x40];
304 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
306 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
309 struct mlx5_ifc_odp_per_transport_service_cap_bits {
314 u8 reserved_at_4[0x1];
316 u8 reserved_at_6[0x1a];
319 struct mlx5_ifc_ipv4_layout_bits {
320 u8 reserved_at_0[0x60];
325 struct mlx5_ifc_ipv6_layout_bits {
329 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
330 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
331 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
332 u8 reserved_at_0[0x80];
335 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
352 u8 reserved_at_91[0x1];
354 u8 reserved_at_93[0x4];
360 u8 reserved_at_c0[0x20];
365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
370 struct mlx5_ifc_fte_match_set_misc_bits {
371 u8 reserved_at_0[0x8];
374 u8 reserved_at_20[0x10];
375 u8 source_port[0x10];
377 u8 outer_second_prio[0x3];
378 u8 outer_second_cfi[0x1];
379 u8 outer_second_vid[0xc];
380 u8 inner_second_prio[0x3];
381 u8 inner_second_cfi[0x1];
382 u8 inner_second_vid[0xc];
384 u8 outer_second_vlan_tag[0x1];
385 u8 inner_second_vlan_tag[0x1];
386 u8 reserved_at_62[0xe];
387 u8 gre_protocol[0x10];
393 u8 reserved_at_b8[0x8];
395 u8 reserved_at_c0[0x20];
397 u8 reserved_at_e0[0xc];
398 u8 outer_ipv6_flow_label[0x14];
400 u8 reserved_at_100[0xc];
401 u8 inner_ipv6_flow_label[0x14];
403 u8 reserved_at_120[0xe0];
406 struct mlx5_ifc_cmd_pas_bits {
410 u8 reserved_at_34[0xc];
413 struct mlx5_ifc_uint64_bits {
420 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
421 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
422 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
423 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
424 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
425 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
426 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
427 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
428 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
429 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
432 struct mlx5_ifc_ads_bits {
435 u8 reserved_at_2[0xe];
438 u8 reserved_at_20[0x8];
444 u8 reserved_at_45[0x3];
445 u8 src_addr_index[0x8];
446 u8 reserved_at_50[0x4];
450 u8 reserved_at_60[0x4];
454 u8 rgid_rip[16][0x8];
456 u8 reserved_at_100[0x4];
459 u8 reserved_at_106[0x1];
474 struct mlx5_ifc_flow_table_nic_cap_bits {
475 u8 nic_rx_multi_path_tirs[0x1];
476 u8 reserved_at_1[0x1ff];
478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
480 u8 reserved_at_400[0x200];
482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
486 u8 reserved_at_a00[0x200];
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
490 u8 reserved_at_e00[0x7200];
493 struct mlx5_ifc_flow_table_eswitch_cap_bits {
494 u8 reserved_at_0[0x200];
496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
498 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
502 u8 reserved_at_800[0x7800];
505 struct mlx5_ifc_e_switch_cap_bits {
506 u8 vport_svlan_strip[0x1];
507 u8 vport_cvlan_strip[0x1];
508 u8 vport_svlan_insert[0x1];
509 u8 vport_cvlan_insert_if_not_exist[0x1];
510 u8 vport_cvlan_insert_overwrite[0x1];
511 u8 reserved_at_5[0x19];
512 u8 nic_vport_node_guid_modify[0x1];
513 u8 nic_vport_port_guid_modify[0x1];
515 u8 reserved_at_20[0x7e0];
518 struct mlx5_ifc_qos_cap_bits {
519 u8 packet_pacing[0x1];
522 u8 packet_pacing_max_rate[0x20];
523 u8 packet_pacing_min_rate[0x20];
525 u8 packet_pacing_rate_table_size[0x10];
526 u8 reserved_3[0x760];
529 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
533 u8 lro_psh_flag[0x1];
534 u8 lro_time_stamp[0x1];
535 u8 reserved_at_5[0x3];
536 u8 self_lb_en_modifiable[0x1];
537 u8 reserved_at_9[0x2];
539 u8 reserved_at_10[0x4];
540 u8 rss_ind_tbl_cap[0x4];
543 u8 reserved_at_1a[0x1];
544 u8 tunnel_lso_const_out_ip_id[0x1];
545 u8 reserved_at_1c[0x2];
546 u8 tunnel_statless_gre[0x1];
547 u8 tunnel_stateless_vxlan[0x1];
549 u8 reserved_at_20[0x20];
551 u8 reserved_at_40[0x10];
552 u8 lro_min_mss_size[0x10];
554 u8 reserved_at_60[0x120];
556 u8 lro_timer_supported_periods[4][0x20];
558 u8 reserved_at_200[0x600];
561 struct mlx5_ifc_roce_cap_bits {
563 u8 reserved_at_1[0x1f];
565 u8 reserved_at_20[0x60];
567 u8 reserved_at_80[0xc];
569 u8 reserved_at_90[0x8];
570 u8 roce_version[0x8];
572 u8 reserved_at_a0[0x10];
573 u8 r_roce_dest_udp_port[0x10];
575 u8 r_roce_max_src_udp_port[0x10];
576 u8 r_roce_min_src_udp_port[0x10];
578 u8 reserved_at_e0[0x10];
579 u8 roce_address_table_size[0x10];
581 u8 reserved_at_100[0x700];
585 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
588 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
589 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
590 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
591 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
592 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
593 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
597 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
598 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
599 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
600 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
601 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
602 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
603 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
604 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
605 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
608 struct mlx5_ifc_atomic_caps_bits {
609 u8 reserved_at_0[0x40];
611 u8 atomic_req_8B_endianess_mode[0x2];
612 u8 reserved_at_42[0x4];
613 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
615 u8 reserved_at_47[0x19];
617 u8 reserved_at_60[0x20];
619 u8 reserved_at_80[0x10];
620 u8 atomic_operations[0x10];
622 u8 reserved_at_a0[0x10];
623 u8 atomic_size_qp[0x10];
625 u8 reserved_at_c0[0x10];
626 u8 atomic_size_dc[0x10];
628 u8 reserved_at_e0[0x720];
631 struct mlx5_ifc_odp_cap_bits {
632 u8 reserved_at_0[0x40];
635 u8 reserved_at_41[0x1f];
637 u8 reserved_at_60[0x20];
639 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
641 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
643 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
645 u8 reserved_at_e0[0x720];
648 struct mlx5_ifc_calc_op {
649 u8 reserved_at_0[0x10];
650 u8 reserved_at_10[0x9];
651 u8 op_swap_endianness[0x1];
660 struct mlx5_ifc_vector_calc_cap_bits {
662 u8 reserved_at_1[0x1f];
663 u8 reserved_at_20[0x8];
664 u8 max_vec_count[0x8];
665 u8 reserved_at_30[0xd];
666 u8 max_chunk_size[0x3];
667 struct mlx5_ifc_calc_op calc0;
668 struct mlx5_ifc_calc_op calc1;
669 struct mlx5_ifc_calc_op calc2;
670 struct mlx5_ifc_calc_op calc3;
672 u8 reserved_at_e0[0x720];
676 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
677 MLX5_WQ_TYPE_CYCLIC = 0x1,
678 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
682 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
683 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
687 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
688 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
689 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
690 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
691 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
695 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
696 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
697 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
698 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
699 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
700 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
704 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
705 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
709 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
710 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
711 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
715 MLX5_CAP_PORT_TYPE_IB = 0x0,
716 MLX5_CAP_PORT_TYPE_ETH = 0x1,
719 struct mlx5_ifc_cmd_hca_cap_bits {
720 u8 reserved_at_0[0x80];
722 u8 log_max_srq_sz[0x8];
723 u8 log_max_qp_sz[0x8];
724 u8 reserved_at_90[0xb];
727 u8 reserved_at_a0[0xb];
729 u8 reserved_at_b0[0x10];
731 u8 reserved_at_c0[0x8];
732 u8 log_max_cq_sz[0x8];
733 u8 reserved_at_d0[0xb];
736 u8 log_max_eq_sz[0x8];
737 u8 reserved_at_e8[0x2];
738 u8 log_max_mkey[0x6];
739 u8 reserved_at_f0[0xc];
742 u8 max_indirection[0x8];
743 u8 reserved_at_108[0x1];
744 u8 log_max_mrw_sz[0x7];
745 u8 reserved_at_110[0x2];
746 u8 log_max_bsf_list_size[0x6];
747 u8 reserved_at_118[0x2];
748 u8 log_max_klm_list_size[0x6];
750 u8 reserved_at_120[0xa];
751 u8 log_max_ra_req_dc[0x6];
752 u8 reserved_at_130[0xa];
753 u8 log_max_ra_res_dc[0x6];
755 u8 reserved_at_140[0xa];
756 u8 log_max_ra_req_qp[0x6];
757 u8 reserved_at_150[0xa];
758 u8 log_max_ra_res_qp[0x6];
761 u8 cc_query_allowed[0x1];
762 u8 cc_modify_allowed[0x1];
763 u8 reserved_at_163[0xd];
764 u8 gid_table_size[0x10];
766 u8 out_of_seq_cnt[0x1];
767 u8 vport_counters[0x1];
768 u8 retransmission_q_counters[0x1];
769 u8 reserved_at_183[0x3];
771 u8 pkey_table_size[0x10];
773 u8 vport_group_manager[0x1];
774 u8 vhca_group_manager[0x1];
777 u8 reserved_at_1a4[0x1];
779 u8 nic_flow_table[0x1];
780 u8 eswitch_flow_table[0x1];
781 u8 early_vf_enable[0x1];
782 u8 reserved_at_1a9[0x2];
783 u8 local_ca_ack_delay[0x5];
784 u8 reserved_at_1af[0x2];
786 u8 reserved_at_1b2[0x1];
787 u8 disable_link_up[0x1];
792 u8 reserved_at_1c0[0x3];
794 u8 reserved_at_1c8[0x4];
796 u8 reserved_at_1d0[0x1];
798 u8 reserved_at_1d2[0x4];
801 u8 reserved_at_1d8[0x1];
810 u8 stat_rate_support[0x10];
811 u8 reserved_at_1f0[0xc];
814 u8 compact_address_vector[0x1];
816 u8 reserved_at_201[0x2];
817 u8 ipoib_basic_offloads[0x1];
818 u8 reserved_at_205[0xa];
819 u8 drain_sigerr[0x1];
820 u8 cmdif_checksum[0x2];
822 u8 reserved_at_213[0x1];
823 u8 wq_signature[0x1];
824 u8 sctr_data_cqe[0x1];
825 u8 reserved_at_216[0x1];
831 u8 eth_net_offloads[0x1];
834 u8 reserved_at_21f[0x1];
838 u8 cq_moderation[0x1];
839 u8 reserved_at_223[0x3];
843 u8 reserved_at_229[0x1];
844 u8 scqe_break_moderation[0x1];
845 u8 cq_period_start_from_cqe[0x1];
847 u8 reserved_at_22d[0x1];
850 u8 umr_ptr_rlky[0x1];
852 u8 reserved_at_232[0x4];
855 u8 set_deth_sqpn[0x1];
856 u8 reserved_at_239[0x3];
862 u8 reserved_at_240[0xa];
864 u8 reserved_at_250[0x8];
868 u8 reserved_at_261[0x1];
869 u8 pad_tx_eth_packet[0x1];
870 u8 reserved_at_263[0x8];
871 u8 log_bf_reg_size[0x5];
872 u8 reserved_at_270[0x10];
874 u8 reserved_at_280[0x10];
875 u8 max_wqe_sz_sq[0x10];
877 u8 reserved_at_2a0[0x10];
878 u8 max_wqe_sz_rq[0x10];
880 u8 reserved_at_2c0[0x10];
881 u8 max_wqe_sz_sq_dc[0x10];
883 u8 reserved_at_2e0[0x7];
886 u8 reserved_at_300[0x18];
889 u8 reserved_at_320[0x3];
890 u8 log_max_transport_domain[0x5];
891 u8 reserved_at_328[0x3];
893 u8 reserved_at_330[0xb];
894 u8 log_max_xrcd[0x5];
896 u8 reserved_at_340[0x8];
897 u8 log_max_flow_counter_bulk[0x8];
898 u8 max_flow_counter[0x10];
901 u8 reserved_at_360[0x3];
903 u8 reserved_at_368[0x3];
905 u8 reserved_at_370[0x3];
907 u8 reserved_at_378[0x3];
910 u8 basic_cyclic_rcv_wqe[0x1];
911 u8 reserved_at_381[0x2];
913 u8 reserved_at_388[0x3];
915 u8 reserved_at_390[0x3];
916 u8 log_max_rqt_size[0x5];
917 u8 reserved_at_398[0x3];
918 u8 log_max_tis_per_sq[0x5];
920 u8 reserved_at_3a0[0x3];
921 u8 log_max_stride_sz_rq[0x5];
922 u8 reserved_at_3a8[0x3];
923 u8 log_min_stride_sz_rq[0x5];
924 u8 reserved_at_3b0[0x3];
925 u8 log_max_stride_sz_sq[0x5];
926 u8 reserved_at_3b8[0x3];
927 u8 log_min_stride_sz_sq[0x5];
929 u8 reserved_at_3c0[0x1b];
930 u8 log_max_wq_sz[0x5];
932 u8 nic_vport_change_event[0x1];
933 u8 reserved_at_3e1[0xa];
934 u8 log_max_vlan_list[0x5];
935 u8 reserved_at_3f0[0x3];
936 u8 log_max_current_mc_list[0x5];
937 u8 reserved_at_3f8[0x3];
938 u8 log_max_current_uc_list[0x5];
940 u8 reserved_at_400[0x80];
942 u8 reserved_at_480[0x3];
943 u8 log_max_l2_table[0x5];
944 u8 reserved_at_488[0x8];
945 u8 log_uar_page_sz[0x10];
947 u8 reserved_at_4a0[0x20];
948 u8 device_frequency_mhz[0x20];
949 u8 device_frequency_khz[0x20];
951 u8 reserved_at_500[0x80];
953 u8 reserved_at_580[0x3f];
954 u8 cqe_compression[0x1];
956 u8 cqe_compression_timeout[0x10];
957 u8 cqe_compression_max_num[0x10];
959 u8 reserved_at_5e0[0x10];
960 u8 tag_matching[0x1];
961 u8 rndv_offload_rc[0x1];
962 u8 rndv_offload_dc[0x1];
963 u8 log_tag_matching_list_sz[0x5];
964 u8 reserved_at_5e8[0x3];
967 u8 reserved_at_5f0[0x200];
970 enum mlx5_flow_destination_type {
971 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
972 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
973 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
975 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
978 struct mlx5_ifc_dest_format_struct_bits {
979 u8 destination_type[0x8];
980 u8 destination_id[0x18];
982 u8 reserved_at_20[0x20];
985 struct mlx5_ifc_flow_counter_list_bits {
987 u8 num_of_counters[0xf];
988 u8 flow_counter_id[0x10];
990 u8 reserved_at_20[0x20];
993 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
994 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
995 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
996 u8 reserved_at_0[0x40];
999 struct mlx5_ifc_fte_match_param_bits {
1000 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1002 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1004 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1006 u8 reserved_at_600[0xa00];
1010 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1011 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1012 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1013 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1014 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1017 struct mlx5_ifc_rx_hash_field_select_bits {
1018 u8 l3_prot_type[0x1];
1019 u8 l4_prot_type[0x1];
1020 u8 selected_fields[0x1e];
1024 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1025 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1029 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1030 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1033 struct mlx5_ifc_wq_bits {
1035 u8 wq_signature[0x1];
1036 u8 end_padding_mode[0x2];
1038 u8 reserved_at_8[0x18];
1040 u8 hds_skip_first_sge[0x1];
1041 u8 log2_hds_buf_size[0x3];
1042 u8 reserved_at_24[0x7];
1043 u8 page_offset[0x5];
1046 u8 reserved_at_40[0x8];
1049 u8 reserved_at_60[0x8];
1054 u8 hw_counter[0x20];
1056 u8 sw_counter[0x20];
1058 u8 reserved_at_100[0xc];
1059 u8 log_wq_stride[0x4];
1060 u8 reserved_at_110[0x3];
1061 u8 log_wq_pg_sz[0x5];
1062 u8 reserved_at_118[0x3];
1065 u8 reserved_at_120[0x15];
1066 u8 log_wqe_num_of_strides[0x3];
1067 u8 two_byte_shift_en[0x1];
1068 u8 reserved_at_139[0x4];
1069 u8 log_wqe_stride_size[0x3];
1071 u8 reserved_at_140[0x4c0];
1073 struct mlx5_ifc_cmd_pas_bits pas[0];
1076 struct mlx5_ifc_rq_num_bits {
1077 u8 reserved_at_0[0x8];
1081 struct mlx5_ifc_mac_address_layout_bits {
1082 u8 reserved_at_0[0x10];
1083 u8 mac_addr_47_32[0x10];
1085 u8 mac_addr_31_0[0x20];
1088 struct mlx5_ifc_vlan_layout_bits {
1089 u8 reserved_at_0[0x14];
1092 u8 reserved_at_20[0x20];
1095 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1096 u8 reserved_at_0[0xa0];
1098 u8 min_time_between_cnps[0x20];
1100 u8 reserved_at_c0[0x12];
1102 u8 reserved_at_d8[0x5];
1103 u8 cnp_802p_prio[0x3];
1105 u8 reserved_at_e0[0x720];
1108 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1109 u8 reserved_at_0[0x60];
1111 u8 reserved_at_60[0x4];
1112 u8 clamp_tgt_rate[0x1];
1113 u8 reserved_at_65[0x3];
1114 u8 clamp_tgt_rate_after_time_inc[0x1];
1115 u8 reserved_at_69[0x17];
1117 u8 reserved_at_80[0x20];
1119 u8 rpg_time_reset[0x20];
1121 u8 rpg_byte_reset[0x20];
1123 u8 rpg_threshold[0x20];
1125 u8 rpg_max_rate[0x20];
1127 u8 rpg_ai_rate[0x20];
1129 u8 rpg_hai_rate[0x20];
1133 u8 rpg_min_dec_fac[0x20];
1135 u8 rpg_min_rate[0x20];
1137 u8 reserved_at_1c0[0xe0];
1139 u8 rate_to_set_on_first_cnp[0x20];
1143 u8 dce_tcp_rtt[0x20];
1145 u8 rate_reduce_monitor_period[0x20];
1147 u8 reserved_at_320[0x20];
1149 u8 initial_alpha_value[0x20];
1151 u8 reserved_at_360[0x4a0];
1154 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1155 u8 reserved_at_0[0x80];
1157 u8 rppp_max_rps[0x20];
1159 u8 rpg_time_reset[0x20];
1161 u8 rpg_byte_reset[0x20];
1163 u8 rpg_threshold[0x20];
1165 u8 rpg_max_rate[0x20];
1167 u8 rpg_ai_rate[0x20];
1169 u8 rpg_hai_rate[0x20];
1173 u8 rpg_min_dec_fac[0x20];
1175 u8 rpg_min_rate[0x20];
1177 u8 reserved_at_1c0[0x640];
1181 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1182 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1183 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1186 struct mlx5_ifc_resize_field_select_bits {
1187 u8 resize_field_select[0x20];
1191 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1192 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1193 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1194 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1197 struct mlx5_ifc_modify_field_select_bits {
1198 u8 modify_field_select[0x20];
1201 struct mlx5_ifc_field_select_r_roce_np_bits {
1202 u8 field_select_r_roce_np[0x20];
1205 struct mlx5_ifc_field_select_r_roce_rp_bits {
1206 u8 field_select_r_roce_rp[0x20];
1210 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1211 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1212 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1213 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1214 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1215 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1216 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1217 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1218 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1222 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1223 u8 field_select_8021qaurp[0x20];
1226 struct mlx5_ifc_phys_layer_cntrs_bits {
1227 u8 time_since_last_clear_high[0x20];
1229 u8 time_since_last_clear_low[0x20];
1231 u8 symbol_errors_high[0x20];
1233 u8 symbol_errors_low[0x20];
1235 u8 sync_headers_errors_high[0x20];
1237 u8 sync_headers_errors_low[0x20];
1239 u8 edpl_bip_errors_lane0_high[0x20];
1241 u8 edpl_bip_errors_lane0_low[0x20];
1243 u8 edpl_bip_errors_lane1_high[0x20];
1245 u8 edpl_bip_errors_lane1_low[0x20];
1247 u8 edpl_bip_errors_lane2_high[0x20];
1249 u8 edpl_bip_errors_lane2_low[0x20];
1251 u8 edpl_bip_errors_lane3_high[0x20];
1253 u8 edpl_bip_errors_lane3_low[0x20];
1255 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1257 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1259 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1261 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1263 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1265 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1267 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1269 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1271 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1273 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1275 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1277 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1279 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1281 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1283 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1285 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1287 u8 rs_fec_corrected_blocks_high[0x20];
1289 u8 rs_fec_corrected_blocks_low[0x20];
1291 u8 rs_fec_uncorrectable_blocks_high[0x20];
1293 u8 rs_fec_uncorrectable_blocks_low[0x20];
1295 u8 rs_fec_no_errors_blocks_high[0x20];
1297 u8 rs_fec_no_errors_blocks_low[0x20];
1299 u8 rs_fec_single_error_blocks_high[0x20];
1301 u8 rs_fec_single_error_blocks_low[0x20];
1303 u8 rs_fec_corrected_symbols_total_high[0x20];
1305 u8 rs_fec_corrected_symbols_total_low[0x20];
1307 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1309 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1311 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1313 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1315 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1317 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1319 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1321 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1323 u8 link_down_events[0x20];
1325 u8 successful_recovery_events[0x20];
1327 u8 reserved_at_640[0x180];
1330 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1331 u8 symbol_error_counter[0x10];
1333 u8 link_error_recovery_counter[0x8];
1335 u8 link_downed_counter[0x8];
1337 u8 port_rcv_errors[0x10];
1339 u8 port_rcv_remote_physical_errors[0x10];
1341 u8 port_rcv_switch_relay_errors[0x10];
1343 u8 port_xmit_discards[0x10];
1345 u8 port_xmit_constraint_errors[0x8];
1347 u8 port_rcv_constraint_errors[0x8];
1349 u8 reserved_at_70[0x8];
1351 u8 link_overrun_errors[0x8];
1353 u8 reserved_at_80[0x10];
1355 u8 vl_15_dropped[0x10];
1357 u8 reserved_at_a0[0xa0];
1360 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1361 u8 transmit_queue_high[0x20];
1363 u8 transmit_queue_low[0x20];
1365 u8 reserved_at_40[0x780];
1368 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1369 u8 rx_octets_high[0x20];
1371 u8 rx_octets_low[0x20];
1373 u8 reserved_at_40[0xc0];
1375 u8 rx_frames_high[0x20];
1377 u8 rx_frames_low[0x20];
1379 u8 tx_octets_high[0x20];
1381 u8 tx_octets_low[0x20];
1383 u8 reserved_at_180[0xc0];
1385 u8 tx_frames_high[0x20];
1387 u8 tx_frames_low[0x20];
1389 u8 rx_pause_high[0x20];
1391 u8 rx_pause_low[0x20];
1393 u8 rx_pause_duration_high[0x20];
1395 u8 rx_pause_duration_low[0x20];
1397 u8 tx_pause_high[0x20];
1399 u8 tx_pause_low[0x20];
1401 u8 tx_pause_duration_high[0x20];
1403 u8 tx_pause_duration_low[0x20];
1405 u8 rx_pause_transition_high[0x20];
1407 u8 rx_pause_transition_low[0x20];
1409 u8 reserved_at_3c0[0x400];
1412 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1413 u8 port_transmit_wait_high[0x20];
1415 u8 port_transmit_wait_low[0x20];
1417 u8 reserved_at_40[0x780];
1420 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1421 u8 dot3stats_alignment_errors_high[0x20];
1423 u8 dot3stats_alignment_errors_low[0x20];
1425 u8 dot3stats_fcs_errors_high[0x20];
1427 u8 dot3stats_fcs_errors_low[0x20];
1429 u8 dot3stats_single_collision_frames_high[0x20];
1431 u8 dot3stats_single_collision_frames_low[0x20];
1433 u8 dot3stats_multiple_collision_frames_high[0x20];
1435 u8 dot3stats_multiple_collision_frames_low[0x20];
1437 u8 dot3stats_sqe_test_errors_high[0x20];
1439 u8 dot3stats_sqe_test_errors_low[0x20];
1441 u8 dot3stats_deferred_transmissions_high[0x20];
1443 u8 dot3stats_deferred_transmissions_low[0x20];
1445 u8 dot3stats_late_collisions_high[0x20];
1447 u8 dot3stats_late_collisions_low[0x20];
1449 u8 dot3stats_excessive_collisions_high[0x20];
1451 u8 dot3stats_excessive_collisions_low[0x20];
1453 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1455 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1457 u8 dot3stats_carrier_sense_errors_high[0x20];
1459 u8 dot3stats_carrier_sense_errors_low[0x20];
1461 u8 dot3stats_frame_too_longs_high[0x20];
1463 u8 dot3stats_frame_too_longs_low[0x20];
1465 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1467 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1469 u8 dot3stats_symbol_errors_high[0x20];
1471 u8 dot3stats_symbol_errors_low[0x20];
1473 u8 dot3control_in_unknown_opcodes_high[0x20];
1475 u8 dot3control_in_unknown_opcodes_low[0x20];
1477 u8 dot3in_pause_frames_high[0x20];
1479 u8 dot3in_pause_frames_low[0x20];
1481 u8 dot3out_pause_frames_high[0x20];
1483 u8 dot3out_pause_frames_low[0x20];
1485 u8 reserved_at_400[0x3c0];
1488 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1489 u8 ether_stats_drop_events_high[0x20];
1491 u8 ether_stats_drop_events_low[0x20];
1493 u8 ether_stats_octets_high[0x20];
1495 u8 ether_stats_octets_low[0x20];
1497 u8 ether_stats_pkts_high[0x20];
1499 u8 ether_stats_pkts_low[0x20];
1501 u8 ether_stats_broadcast_pkts_high[0x20];
1503 u8 ether_stats_broadcast_pkts_low[0x20];
1505 u8 ether_stats_multicast_pkts_high[0x20];
1507 u8 ether_stats_multicast_pkts_low[0x20];
1509 u8 ether_stats_crc_align_errors_high[0x20];
1511 u8 ether_stats_crc_align_errors_low[0x20];
1513 u8 ether_stats_undersize_pkts_high[0x20];
1515 u8 ether_stats_undersize_pkts_low[0x20];
1517 u8 ether_stats_oversize_pkts_high[0x20];
1519 u8 ether_stats_oversize_pkts_low[0x20];
1521 u8 ether_stats_fragments_high[0x20];
1523 u8 ether_stats_fragments_low[0x20];
1525 u8 ether_stats_jabbers_high[0x20];
1527 u8 ether_stats_jabbers_low[0x20];
1529 u8 ether_stats_collisions_high[0x20];
1531 u8 ether_stats_collisions_low[0x20];
1533 u8 ether_stats_pkts64octets_high[0x20];
1535 u8 ether_stats_pkts64octets_low[0x20];
1537 u8 ether_stats_pkts65to127octets_high[0x20];
1539 u8 ether_stats_pkts65to127octets_low[0x20];
1541 u8 ether_stats_pkts128to255octets_high[0x20];
1543 u8 ether_stats_pkts128to255octets_low[0x20];
1545 u8 ether_stats_pkts256to511octets_high[0x20];
1547 u8 ether_stats_pkts256to511octets_low[0x20];
1549 u8 ether_stats_pkts512to1023octets_high[0x20];
1551 u8 ether_stats_pkts512to1023octets_low[0x20];
1553 u8 ether_stats_pkts1024to1518octets_high[0x20];
1555 u8 ether_stats_pkts1024to1518octets_low[0x20];
1557 u8 ether_stats_pkts1519to2047octets_high[0x20];
1559 u8 ether_stats_pkts1519to2047octets_low[0x20];
1561 u8 ether_stats_pkts2048to4095octets_high[0x20];
1563 u8 ether_stats_pkts2048to4095octets_low[0x20];
1565 u8 ether_stats_pkts4096to8191octets_high[0x20];
1567 u8 ether_stats_pkts4096to8191octets_low[0x20];
1569 u8 ether_stats_pkts8192to10239octets_high[0x20];
1571 u8 ether_stats_pkts8192to10239octets_low[0x20];
1573 u8 reserved_at_540[0x280];
1576 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1577 u8 if_in_octets_high[0x20];
1579 u8 if_in_octets_low[0x20];
1581 u8 if_in_ucast_pkts_high[0x20];
1583 u8 if_in_ucast_pkts_low[0x20];
1585 u8 if_in_discards_high[0x20];
1587 u8 if_in_discards_low[0x20];
1589 u8 if_in_errors_high[0x20];
1591 u8 if_in_errors_low[0x20];
1593 u8 if_in_unknown_protos_high[0x20];
1595 u8 if_in_unknown_protos_low[0x20];
1597 u8 if_out_octets_high[0x20];
1599 u8 if_out_octets_low[0x20];
1601 u8 if_out_ucast_pkts_high[0x20];
1603 u8 if_out_ucast_pkts_low[0x20];
1605 u8 if_out_discards_high[0x20];
1607 u8 if_out_discards_low[0x20];
1609 u8 if_out_errors_high[0x20];
1611 u8 if_out_errors_low[0x20];
1613 u8 if_in_multicast_pkts_high[0x20];
1615 u8 if_in_multicast_pkts_low[0x20];
1617 u8 if_in_broadcast_pkts_high[0x20];
1619 u8 if_in_broadcast_pkts_low[0x20];
1621 u8 if_out_multicast_pkts_high[0x20];
1623 u8 if_out_multicast_pkts_low[0x20];
1625 u8 if_out_broadcast_pkts_high[0x20];
1627 u8 if_out_broadcast_pkts_low[0x20];
1629 u8 reserved_at_340[0x480];
1632 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1633 u8 a_frames_transmitted_ok_high[0x20];
1635 u8 a_frames_transmitted_ok_low[0x20];
1637 u8 a_frames_received_ok_high[0x20];
1639 u8 a_frames_received_ok_low[0x20];
1641 u8 a_frame_check_sequence_errors_high[0x20];
1643 u8 a_frame_check_sequence_errors_low[0x20];
1645 u8 a_alignment_errors_high[0x20];
1647 u8 a_alignment_errors_low[0x20];
1649 u8 a_octets_transmitted_ok_high[0x20];
1651 u8 a_octets_transmitted_ok_low[0x20];
1653 u8 a_octets_received_ok_high[0x20];
1655 u8 a_octets_received_ok_low[0x20];
1657 u8 a_multicast_frames_xmitted_ok_high[0x20];
1659 u8 a_multicast_frames_xmitted_ok_low[0x20];
1661 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1663 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1665 u8 a_multicast_frames_received_ok_high[0x20];
1667 u8 a_multicast_frames_received_ok_low[0x20];
1669 u8 a_broadcast_frames_received_ok_high[0x20];
1671 u8 a_broadcast_frames_received_ok_low[0x20];
1673 u8 a_in_range_length_errors_high[0x20];
1675 u8 a_in_range_length_errors_low[0x20];
1677 u8 a_out_of_range_length_field_high[0x20];
1679 u8 a_out_of_range_length_field_low[0x20];
1681 u8 a_frame_too_long_errors_high[0x20];
1683 u8 a_frame_too_long_errors_low[0x20];
1685 u8 a_symbol_error_during_carrier_high[0x20];
1687 u8 a_symbol_error_during_carrier_low[0x20];
1689 u8 a_mac_control_frames_transmitted_high[0x20];
1691 u8 a_mac_control_frames_transmitted_low[0x20];
1693 u8 a_mac_control_frames_received_high[0x20];
1695 u8 a_mac_control_frames_received_low[0x20];
1697 u8 a_unsupported_opcodes_received_high[0x20];
1699 u8 a_unsupported_opcodes_received_low[0x20];
1701 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1703 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1705 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1707 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1709 u8 reserved_at_4c0[0x300];
1712 struct mlx5_ifc_cmd_inter_comp_event_bits {
1713 u8 command_completion_vector[0x20];
1715 u8 reserved_at_20[0xc0];
1718 struct mlx5_ifc_stall_vl_event_bits {
1719 u8 reserved_at_0[0x18];
1721 u8 reserved_at_19[0x3];
1724 u8 reserved_at_20[0xa0];
1727 struct mlx5_ifc_db_bf_congestion_event_bits {
1728 u8 event_subtype[0x8];
1729 u8 reserved_at_8[0x8];
1730 u8 congestion_level[0x8];
1731 u8 reserved_at_18[0x8];
1733 u8 reserved_at_20[0xa0];
1736 struct mlx5_ifc_gpio_event_bits {
1737 u8 reserved_at_0[0x60];
1739 u8 gpio_event_hi[0x20];
1741 u8 gpio_event_lo[0x20];
1743 u8 reserved_at_a0[0x40];
1746 struct mlx5_ifc_port_state_change_event_bits {
1747 u8 reserved_at_0[0x40];
1750 u8 reserved_at_44[0x1c];
1752 u8 reserved_at_60[0x80];
1755 struct mlx5_ifc_dropped_packet_logged_bits {
1756 u8 reserved_at_0[0xe0];
1760 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1761 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1764 struct mlx5_ifc_cq_error_bits {
1765 u8 reserved_at_0[0x8];
1768 u8 reserved_at_20[0x20];
1770 u8 reserved_at_40[0x18];
1773 u8 reserved_at_60[0x80];
1776 struct mlx5_ifc_rdma_page_fault_event_bits {
1777 u8 bytes_committed[0x20];
1781 u8 reserved_at_40[0x10];
1782 u8 packet_len[0x10];
1784 u8 rdma_op_len[0x20];
1788 u8 reserved_at_c0[0x5];
1795 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1796 u8 bytes_committed[0x20];
1798 u8 reserved_at_20[0x10];
1801 u8 reserved_at_40[0x10];
1804 u8 reserved_at_60[0x60];
1806 u8 reserved_at_c0[0x5];
1813 struct mlx5_ifc_qp_events_bits {
1814 u8 reserved_at_0[0xa0];
1817 u8 reserved_at_a8[0x18];
1819 u8 reserved_at_c0[0x8];
1820 u8 qpn_rqn_sqn[0x18];
1823 struct mlx5_ifc_dct_events_bits {
1824 u8 reserved_at_0[0xc0];
1826 u8 reserved_at_c0[0x8];
1827 u8 dct_number[0x18];
1830 struct mlx5_ifc_comp_event_bits {
1831 u8 reserved_at_0[0xc0];
1833 u8 reserved_at_c0[0x8];
1838 MLX5_QPC_STATE_RST = 0x0,
1839 MLX5_QPC_STATE_INIT = 0x1,
1840 MLX5_QPC_STATE_RTR = 0x2,
1841 MLX5_QPC_STATE_RTS = 0x3,
1842 MLX5_QPC_STATE_SQER = 0x4,
1843 MLX5_QPC_STATE_ERR = 0x6,
1844 MLX5_QPC_STATE_SQD = 0x7,
1845 MLX5_QPC_STATE_SUSPENDED = 0x9,
1849 MLX5_QPC_ST_RC = 0x0,
1850 MLX5_QPC_ST_UC = 0x1,
1851 MLX5_QPC_ST_UD = 0x2,
1852 MLX5_QPC_ST_XRC = 0x3,
1853 MLX5_QPC_ST_DCI = 0x5,
1854 MLX5_QPC_ST_QP0 = 0x7,
1855 MLX5_QPC_ST_QP1 = 0x8,
1856 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1857 MLX5_QPC_ST_REG_UMR = 0xc,
1861 MLX5_QPC_PM_STATE_ARMED = 0x0,
1862 MLX5_QPC_PM_STATE_REARM = 0x1,
1863 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1864 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1868 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1869 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1873 MLX5_QPC_MTU_256_BYTES = 0x1,
1874 MLX5_QPC_MTU_512_BYTES = 0x2,
1875 MLX5_QPC_MTU_1K_BYTES = 0x3,
1876 MLX5_QPC_MTU_2K_BYTES = 0x4,
1877 MLX5_QPC_MTU_4K_BYTES = 0x5,
1878 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1882 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1883 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1884 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1885 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1886 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1887 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1888 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1889 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1893 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1894 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1895 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1899 MLX5_QPC_CS_RES_DISABLE = 0x0,
1900 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1901 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1904 struct mlx5_ifc_qpc_bits {
1906 u8 reserved_at_4[0x4];
1908 u8 reserved_at_10[0x3];
1910 u8 reserved_at_15[0x7];
1911 u8 end_padding_mode[0x2];
1912 u8 reserved_at_1e[0x2];
1914 u8 wq_signature[0x1];
1915 u8 block_lb_mc[0x1];
1916 u8 atomic_like_write_en[0x1];
1917 u8 latency_sensitive[0x1];
1918 u8 reserved_at_24[0x1];
1919 u8 drain_sigerr[0x1];
1920 u8 reserved_at_26[0x2];
1924 u8 log_msg_max[0x5];
1925 u8 reserved_at_48[0x1];
1926 u8 log_rq_size[0x4];
1927 u8 log_rq_stride[0x3];
1929 u8 log_sq_size[0x4];
1930 u8 reserved_at_55[0x6];
1932 u8 ulp_stateless_offload_mode[0x4];
1934 u8 counter_set_id[0x8];
1937 u8 reserved_at_80[0x8];
1938 u8 user_index[0x18];
1940 u8 reserved_at_a0[0x3];
1941 u8 log_page_size[0x5];
1942 u8 remote_qpn[0x18];
1944 struct mlx5_ifc_ads_bits primary_address_path;
1946 struct mlx5_ifc_ads_bits secondary_address_path;
1948 u8 log_ack_req_freq[0x4];
1949 u8 reserved_at_384[0x4];
1950 u8 log_sra_max[0x3];
1951 u8 reserved_at_38b[0x2];
1952 u8 retry_count[0x3];
1954 u8 reserved_at_393[0x1];
1956 u8 cur_rnr_retry[0x3];
1957 u8 cur_retry_count[0x3];
1958 u8 reserved_at_39b[0x5];
1960 u8 reserved_at_3a0[0x20];
1962 u8 reserved_at_3c0[0x8];
1963 u8 next_send_psn[0x18];
1965 u8 reserved_at_3e0[0x8];
1968 u8 reserved_at_400[0x40];
1970 u8 reserved_at_440[0x8];
1971 u8 last_acked_psn[0x18];
1973 u8 reserved_at_460[0x8];
1976 u8 reserved_at_480[0x8];
1977 u8 log_rra_max[0x3];
1978 u8 reserved_at_48b[0x1];
1979 u8 atomic_mode[0x4];
1983 u8 reserved_at_493[0x1];
1984 u8 page_offset[0x6];
1985 u8 reserved_at_49a[0x3];
1986 u8 cd_slave_receive[0x1];
1987 u8 cd_slave_send[0x1];
1990 u8 reserved_at_4a0[0x3];
1991 u8 min_rnr_nak[0x5];
1992 u8 next_rcv_psn[0x18];
1994 u8 reserved_at_4c0[0x8];
1997 u8 reserved_at_4e0[0x8];
2004 u8 reserved_at_560[0x5];
2006 u8 srqn_rmpn_xrqn[0x18];
2008 u8 reserved_at_580[0x8];
2011 u8 hw_sq_wqebb_counter[0x10];
2012 u8 sw_sq_wqebb_counter[0x10];
2014 u8 hw_rq_counter[0x20];
2016 u8 sw_rq_counter[0x20];
2018 u8 reserved_at_600[0x20];
2020 u8 reserved_at_620[0xf];
2025 u8 dc_access_key[0x40];
2027 u8 reserved_at_680[0xc0];
2030 struct mlx5_ifc_roce_addr_layout_bits {
2031 u8 source_l3_address[16][0x8];
2033 u8 reserved_at_80[0x3];
2036 u8 source_mac_47_32[0x10];
2038 u8 source_mac_31_0[0x20];
2040 u8 reserved_at_c0[0x14];
2041 u8 roce_l3_type[0x4];
2042 u8 roce_version[0x8];
2044 u8 reserved_at_e0[0x20];
2047 union mlx5_ifc_hca_cap_union_bits {
2048 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2049 struct mlx5_ifc_odp_cap_bits odp_cap;
2050 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2051 struct mlx5_ifc_roce_cap_bits roce_cap;
2052 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2053 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2054 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2055 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2056 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2057 struct mlx5_ifc_qos_cap_bits qos_cap;
2058 u8 reserved_at_0[0x8000];
2062 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2063 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2064 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2065 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2068 struct mlx5_ifc_flow_context_bits {
2069 u8 reserved_at_0[0x20];
2073 u8 reserved_at_40[0x8];
2076 u8 reserved_at_60[0x10];
2079 u8 reserved_at_80[0x8];
2080 u8 destination_list_size[0x18];
2082 u8 reserved_at_a0[0x8];
2083 u8 flow_counter_list_size[0x18];
2085 u8 reserved_at_c0[0x140];
2087 struct mlx5_ifc_fte_match_param_bits match_value;
2089 u8 reserved_at_1200[0x600];
2091 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2095 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2096 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2099 struct mlx5_ifc_xrc_srqc_bits {
2101 u8 log_xrc_srq_size[0x4];
2102 u8 reserved_at_8[0x18];
2104 u8 wq_signature[0x1];
2106 u8 reserved_at_22[0x1];
2108 u8 basic_cyclic_rcv_wqe[0x1];
2109 u8 log_rq_stride[0x3];
2112 u8 page_offset[0x6];
2113 u8 reserved_at_46[0x2];
2116 u8 reserved_at_60[0x20];
2118 u8 user_index_equal_xrc_srqn[0x1];
2119 u8 reserved_at_81[0x1];
2120 u8 log_page_size[0x6];
2121 u8 user_index[0x18];
2123 u8 reserved_at_a0[0x20];
2125 u8 reserved_at_c0[0x8];
2131 u8 reserved_at_100[0x40];
2133 u8 db_record_addr_h[0x20];
2135 u8 db_record_addr_l[0x1e];
2136 u8 reserved_at_17e[0x2];
2138 u8 reserved_at_180[0x80];
2141 struct mlx5_ifc_traffic_counter_bits {
2147 struct mlx5_ifc_tisc_bits {
2148 u8 reserved_at_0[0xc];
2150 u8 reserved_at_10[0x10];
2152 u8 reserved_at_20[0x100];
2154 u8 reserved_at_120[0x8];
2155 u8 transport_domain[0x18];
2157 u8 reserved_at_140[0x3c0];
2161 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2162 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2166 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2167 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2171 MLX5_RX_HASH_FN_NONE = 0x0,
2172 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2173 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2177 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2178 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2181 struct mlx5_ifc_tirc_bits {
2182 u8 reserved_at_0[0x20];
2185 u8 reserved_at_24[0x1c];
2187 u8 reserved_at_40[0x40];
2189 u8 reserved_at_80[0x4];
2190 u8 lro_timeout_period_usecs[0x10];
2191 u8 lro_enable_mask[0x4];
2192 u8 lro_max_ip_payload_size[0x8];
2194 u8 reserved_at_a0[0x40];
2196 u8 reserved_at_e0[0x8];
2197 u8 inline_rqn[0x18];
2199 u8 rx_hash_symmetric[0x1];
2200 u8 reserved_at_101[0x1];
2201 u8 tunneled_offload_en[0x1];
2202 u8 reserved_at_103[0x5];
2203 u8 indirect_table[0x18];
2206 u8 reserved_at_124[0x2];
2207 u8 self_lb_block[0x2];
2208 u8 transport_domain[0x18];
2210 u8 rx_hash_toeplitz_key[10][0x20];
2212 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2214 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2216 u8 reserved_at_2c0[0x4c0];
2220 MLX5_SRQC_STATE_GOOD = 0x0,
2221 MLX5_SRQC_STATE_ERROR = 0x1,
2224 struct mlx5_ifc_srqc_bits {
2226 u8 log_srq_size[0x4];
2227 u8 reserved_at_8[0x18];
2229 u8 wq_signature[0x1];
2231 u8 reserved_at_22[0x1];
2233 u8 reserved_at_24[0x1];
2234 u8 log_rq_stride[0x3];
2237 u8 page_offset[0x6];
2238 u8 reserved_at_46[0x2];
2241 u8 reserved_at_60[0x20];
2243 u8 reserved_at_80[0x2];
2244 u8 log_page_size[0x6];
2245 u8 reserved_at_88[0x18];
2247 u8 reserved_at_a0[0x20];
2249 u8 reserved_at_c0[0x8];
2255 u8 reserved_at_100[0x40];
2259 u8 reserved_at_180[0x80];
2263 MLX5_SQC_STATE_RST = 0x0,
2264 MLX5_SQC_STATE_RDY = 0x1,
2265 MLX5_SQC_STATE_ERR = 0x3,
2268 struct mlx5_ifc_sqc_bits {
2272 u8 flush_in_error_en[0x1];
2273 u8 reserved_at_4[0x4];
2276 u8 reserved_at_d[0x13];
2278 u8 reserved_at_20[0x8];
2279 u8 user_index[0x18];
2281 u8 reserved_at_40[0x8];
2284 u8 reserved_at_60[0x90];
2286 u8 packet_pacing_rate_limit_index[0x10];
2287 u8 tis_lst_sz[0x10];
2288 u8 reserved_at_110[0x10];
2290 u8 reserved_at_120[0x40];
2292 u8 reserved_at_160[0x8];
2295 struct mlx5_ifc_wq_bits wq;
2298 struct mlx5_ifc_rqtc_bits {
2299 u8 reserved_at_0[0xa0];
2301 u8 reserved_at_a0[0x10];
2302 u8 rqt_max_size[0x10];
2304 u8 reserved_at_c0[0x10];
2305 u8 rqt_actual_size[0x10];
2307 u8 reserved_at_e0[0x6a0];
2309 struct mlx5_ifc_rq_num_bits rq_num[0];
2313 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2314 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2318 MLX5_RQC_STATE_RST = 0x0,
2319 MLX5_RQC_STATE_RDY = 0x1,
2320 MLX5_RQC_STATE_ERR = 0x3,
2323 struct mlx5_ifc_rqc_bits {
2325 u8 reserved_at_1[0x1];
2326 u8 scatter_fcs[0x1];
2328 u8 mem_rq_type[0x4];
2330 u8 reserved_at_c[0x1];
2331 u8 flush_in_error_en[0x1];
2332 u8 reserved_at_e[0x12];
2334 u8 reserved_at_20[0x8];
2335 u8 user_index[0x18];
2337 u8 reserved_at_40[0x8];
2340 u8 counter_set_id[0x8];
2341 u8 reserved_at_68[0x18];
2343 u8 reserved_at_80[0x8];
2346 u8 reserved_at_a0[0xe0];
2348 struct mlx5_ifc_wq_bits wq;
2352 MLX5_RMPC_STATE_RDY = 0x1,
2353 MLX5_RMPC_STATE_ERR = 0x3,
2356 struct mlx5_ifc_rmpc_bits {
2357 u8 reserved_at_0[0x8];
2359 u8 reserved_at_c[0x14];
2361 u8 basic_cyclic_rcv_wqe[0x1];
2362 u8 reserved_at_21[0x1f];
2364 u8 reserved_at_40[0x140];
2366 struct mlx5_ifc_wq_bits wq;
2369 struct mlx5_ifc_nic_vport_context_bits {
2370 u8 reserved_at_0[0x1f];
2373 u8 arm_change_event[0x1];
2374 u8 reserved_at_21[0x1a];
2375 u8 event_on_mtu[0x1];
2376 u8 event_on_promisc_change[0x1];
2377 u8 event_on_vlan_change[0x1];
2378 u8 event_on_mc_address_change[0x1];
2379 u8 event_on_uc_address_change[0x1];
2381 u8 reserved_at_40[0xf0];
2385 u8 system_image_guid[0x40];
2389 u8 reserved_at_200[0x140];
2390 u8 qkey_violation_counter[0x10];
2391 u8 reserved_at_350[0x430];
2395 u8 promisc_all[0x1];
2396 u8 reserved_at_783[0x2];
2397 u8 allowed_list_type[0x3];
2398 u8 reserved_at_788[0xc];
2399 u8 allowed_list_size[0xc];
2401 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2403 u8 reserved_at_7e0[0x20];
2405 u8 current_uc_mac_address[0][0x40];
2409 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2410 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2411 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2414 struct mlx5_ifc_mkc_bits {
2415 u8 reserved_at_0[0x1];
2417 u8 reserved_at_2[0xd];
2418 u8 small_fence_on_rdma_read_response[0x1];
2425 u8 access_mode[0x2];
2426 u8 reserved_at_18[0x8];
2431 u8 reserved_at_40[0x20];
2436 u8 reserved_at_63[0x2];
2437 u8 expected_sigerr_count[0x1];
2438 u8 reserved_at_66[0x1];
2442 u8 start_addr[0x40];
2446 u8 bsf_octword_size[0x20];
2448 u8 reserved_at_120[0x80];
2450 u8 translations_octword_size[0x20];
2452 u8 reserved_at_1c0[0x1b];
2453 u8 log_page_size[0x5];
2455 u8 reserved_at_1e0[0x20];
2458 struct mlx5_ifc_pkey_bits {
2459 u8 reserved_at_0[0x10];
2463 struct mlx5_ifc_array128_auto_bits {
2464 u8 array128_auto[16][0x8];
2467 struct mlx5_ifc_hca_vport_context_bits {
2468 u8 field_select[0x20];
2470 u8 reserved_at_20[0xe0];
2472 u8 sm_virt_aware[0x1];
2475 u8 grh_required[0x1];
2476 u8 reserved_at_104[0xc];
2477 u8 port_physical_state[0x4];
2478 u8 vport_state_policy[0x4];
2480 u8 vport_state[0x4];
2482 u8 reserved_at_120[0x20];
2484 u8 system_image_guid[0x40];
2492 u8 cap_mask1_field_select[0x20];
2496 u8 cap_mask2_field_select[0x20];
2498 u8 reserved_at_280[0x80];
2501 u8 reserved_at_310[0x4];
2502 u8 init_type_reply[0x4];
2504 u8 subnet_timeout[0x5];
2508 u8 reserved_at_334[0xc];
2510 u8 qkey_violation_counter[0x10];
2511 u8 pkey_violation_counter[0x10];
2513 u8 reserved_at_360[0xca0];
2516 struct mlx5_ifc_esw_vport_context_bits {
2517 u8 reserved_at_0[0x3];
2518 u8 vport_svlan_strip[0x1];
2519 u8 vport_cvlan_strip[0x1];
2520 u8 vport_svlan_insert[0x1];
2521 u8 vport_cvlan_insert[0x2];
2522 u8 reserved_at_8[0x18];
2524 u8 reserved_at_20[0x20];
2533 u8 reserved_at_60[0x7a0];
2537 MLX5_EQC_STATUS_OK = 0x0,
2538 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2542 MLX5_EQC_ST_ARMED = 0x9,
2543 MLX5_EQC_ST_FIRED = 0xa,
2546 struct mlx5_ifc_eqc_bits {
2548 u8 reserved_at_4[0x9];
2551 u8 reserved_at_f[0x5];
2553 u8 reserved_at_18[0x8];
2555 u8 reserved_at_20[0x20];
2557 u8 reserved_at_40[0x14];
2558 u8 page_offset[0x6];
2559 u8 reserved_at_5a[0x6];
2561 u8 reserved_at_60[0x3];
2562 u8 log_eq_size[0x5];
2565 u8 reserved_at_80[0x20];
2567 u8 reserved_at_a0[0x18];
2570 u8 reserved_at_c0[0x3];
2571 u8 log_page_size[0x5];
2572 u8 reserved_at_c8[0x18];
2574 u8 reserved_at_e0[0x60];
2576 u8 reserved_at_140[0x8];
2577 u8 consumer_counter[0x18];
2579 u8 reserved_at_160[0x8];
2580 u8 producer_counter[0x18];
2582 u8 reserved_at_180[0x80];
2586 MLX5_DCTC_STATE_ACTIVE = 0x0,
2587 MLX5_DCTC_STATE_DRAINING = 0x1,
2588 MLX5_DCTC_STATE_DRAINED = 0x2,
2592 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2593 MLX5_DCTC_CS_RES_NA = 0x1,
2594 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2598 MLX5_DCTC_MTU_256_BYTES = 0x1,
2599 MLX5_DCTC_MTU_512_BYTES = 0x2,
2600 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2601 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2602 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2605 struct mlx5_ifc_dctc_bits {
2606 u8 reserved_at_0[0x4];
2608 u8 reserved_at_8[0x18];
2610 u8 reserved_at_20[0x8];
2611 u8 user_index[0x18];
2613 u8 reserved_at_40[0x8];
2616 u8 counter_set_id[0x8];
2617 u8 atomic_mode[0x4];
2621 u8 atomic_like_write_en[0x1];
2622 u8 latency_sensitive[0x1];
2625 u8 reserved_at_73[0xd];
2627 u8 reserved_at_80[0x8];
2629 u8 reserved_at_90[0x3];
2630 u8 min_rnr_nak[0x5];
2631 u8 reserved_at_98[0x8];
2633 u8 reserved_at_a0[0x8];
2636 u8 reserved_at_c0[0x8];
2640 u8 reserved_at_e8[0x4];
2641 u8 flow_label[0x14];
2643 u8 dc_access_key[0x40];
2645 u8 reserved_at_140[0x5];
2648 u8 pkey_index[0x10];
2650 u8 reserved_at_160[0x8];
2651 u8 my_addr_index[0x8];
2652 u8 reserved_at_170[0x8];
2655 u8 dc_access_key_violation_count[0x20];
2657 u8 reserved_at_1a0[0x14];
2663 u8 reserved_at_1c0[0x40];
2667 MLX5_CQC_STATUS_OK = 0x0,
2668 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2669 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2673 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2674 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2678 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2679 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2680 MLX5_CQC_ST_FIRED = 0xa,
2684 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2685 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2686 MLX5_CQ_PERIOD_NUM_MODES
2689 struct mlx5_ifc_cqc_bits {
2691 u8 reserved_at_4[0x4];
2694 u8 reserved_at_c[0x1];
2695 u8 scqe_break_moderation_en[0x1];
2697 u8 cq_period_mode[0x2];
2698 u8 cqe_comp_en[0x1];
2699 u8 mini_cqe_res_format[0x2];
2701 u8 reserved_at_18[0x8];
2703 u8 reserved_at_20[0x20];
2705 u8 reserved_at_40[0x14];
2706 u8 page_offset[0x6];
2707 u8 reserved_at_5a[0x6];
2709 u8 reserved_at_60[0x3];
2710 u8 log_cq_size[0x5];
2713 u8 reserved_at_80[0x4];
2715 u8 cq_max_count[0x10];
2717 u8 reserved_at_a0[0x18];
2720 u8 reserved_at_c0[0x3];
2721 u8 log_page_size[0x5];
2722 u8 reserved_at_c8[0x18];
2724 u8 reserved_at_e0[0x20];
2726 u8 reserved_at_100[0x8];
2727 u8 last_notified_index[0x18];
2729 u8 reserved_at_120[0x8];
2730 u8 last_solicit_index[0x18];
2732 u8 reserved_at_140[0x8];
2733 u8 consumer_counter[0x18];
2735 u8 reserved_at_160[0x8];
2736 u8 producer_counter[0x18];
2738 u8 reserved_at_180[0x40];
2743 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2744 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2745 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2746 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2747 u8 reserved_at_0[0x800];
2750 struct mlx5_ifc_query_adapter_param_block_bits {
2751 u8 reserved_at_0[0xc0];
2753 u8 reserved_at_c0[0x8];
2754 u8 ieee_vendor_id[0x18];
2756 u8 reserved_at_e0[0x10];
2757 u8 vsd_vendor_id[0x10];
2761 u8 vsd_contd_psid[16][0x8];
2765 MLX5_XRQC_STATE_GOOD = 0x0,
2766 MLX5_XRQC_STATE_ERROR = 0x1,
2770 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2771 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2775 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2778 struct mlx5_ifc_tag_matching_topology_context_bits {
2779 u8 log_matching_list_sz[0x4];
2780 u8 reserved_at_4[0xc];
2781 u8 append_next_index[0x10];
2783 u8 sw_phase_cnt[0x10];
2784 u8 hw_phase_cnt[0x10];
2786 u8 reserved_at_40[0x40];
2789 struct mlx5_ifc_xrqc_bits {
2792 u8 reserved_at_5[0xf];
2794 u8 reserved_at_18[0x4];
2797 u8 reserved_at_20[0x8];
2798 u8 user_index[0x18];
2800 u8 reserved_at_40[0x8];
2803 u8 reserved_at_60[0xa0];
2805 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2807 u8 reserved_at_180[0x180];
2809 struct mlx5_ifc_wq_bits wq;
2812 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2813 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2814 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2815 u8 reserved_at_0[0x20];
2818 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2819 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2820 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2821 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2822 u8 reserved_at_0[0x20];
2825 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2826 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2827 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2828 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2829 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2830 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2831 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2832 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2833 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2834 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2835 u8 reserved_at_0[0x7c0];
2838 union mlx5_ifc_event_auto_bits {
2839 struct mlx5_ifc_comp_event_bits comp_event;
2840 struct mlx5_ifc_dct_events_bits dct_events;
2841 struct mlx5_ifc_qp_events_bits qp_events;
2842 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2843 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2844 struct mlx5_ifc_cq_error_bits cq_error;
2845 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2846 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2847 struct mlx5_ifc_gpio_event_bits gpio_event;
2848 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2849 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2850 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2851 u8 reserved_at_0[0xe0];
2854 struct mlx5_ifc_health_buffer_bits {
2855 u8 reserved_at_0[0x100];
2857 u8 assert_existptr[0x20];
2859 u8 assert_callra[0x20];
2861 u8 reserved_at_140[0x40];
2863 u8 fw_version[0x20];
2867 u8 reserved_at_1c0[0x20];
2869 u8 irisc_index[0x8];
2874 struct mlx5_ifc_register_loopback_control_bits {
2876 u8 reserved_at_1[0x7];
2878 u8 reserved_at_10[0x10];
2880 u8 reserved_at_20[0x60];
2883 struct mlx5_ifc_teardown_hca_out_bits {
2885 u8 reserved_at_8[0x18];
2889 u8 reserved_at_40[0x40];
2893 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2894 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2897 struct mlx5_ifc_teardown_hca_in_bits {
2899 u8 reserved_at_10[0x10];
2901 u8 reserved_at_20[0x10];
2904 u8 reserved_at_40[0x10];
2907 u8 reserved_at_60[0x20];
2910 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2912 u8 reserved_at_8[0x18];
2916 u8 reserved_at_40[0x40];
2919 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2921 u8 reserved_at_10[0x10];
2923 u8 reserved_at_20[0x10];
2926 u8 reserved_at_40[0x8];
2929 u8 reserved_at_60[0x20];
2931 u8 opt_param_mask[0x20];
2933 u8 reserved_at_a0[0x20];
2935 struct mlx5_ifc_qpc_bits qpc;
2937 u8 reserved_at_800[0x80];
2940 struct mlx5_ifc_sqd2rts_qp_out_bits {
2942 u8 reserved_at_8[0x18];
2946 u8 reserved_at_40[0x40];
2949 struct mlx5_ifc_sqd2rts_qp_in_bits {
2951 u8 reserved_at_10[0x10];
2953 u8 reserved_at_20[0x10];
2956 u8 reserved_at_40[0x8];
2959 u8 reserved_at_60[0x20];
2961 u8 opt_param_mask[0x20];
2963 u8 reserved_at_a0[0x20];
2965 struct mlx5_ifc_qpc_bits qpc;
2967 u8 reserved_at_800[0x80];
2970 struct mlx5_ifc_set_roce_address_out_bits {
2972 u8 reserved_at_8[0x18];
2976 u8 reserved_at_40[0x40];
2979 struct mlx5_ifc_set_roce_address_in_bits {
2981 u8 reserved_at_10[0x10];
2983 u8 reserved_at_20[0x10];
2986 u8 roce_address_index[0x10];
2987 u8 reserved_at_50[0x10];
2989 u8 reserved_at_60[0x20];
2991 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2994 struct mlx5_ifc_set_mad_demux_out_bits {
2996 u8 reserved_at_8[0x18];
3000 u8 reserved_at_40[0x40];
3004 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3005 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3008 struct mlx5_ifc_set_mad_demux_in_bits {
3010 u8 reserved_at_10[0x10];
3012 u8 reserved_at_20[0x10];
3015 u8 reserved_at_40[0x20];
3017 u8 reserved_at_60[0x6];
3019 u8 reserved_at_68[0x18];
3022 struct mlx5_ifc_set_l2_table_entry_out_bits {
3024 u8 reserved_at_8[0x18];
3028 u8 reserved_at_40[0x40];
3031 struct mlx5_ifc_set_l2_table_entry_in_bits {
3033 u8 reserved_at_10[0x10];
3035 u8 reserved_at_20[0x10];
3038 u8 reserved_at_40[0x60];
3040 u8 reserved_at_a0[0x8];
3041 u8 table_index[0x18];
3043 u8 reserved_at_c0[0x20];
3045 u8 reserved_at_e0[0x13];
3049 struct mlx5_ifc_mac_address_layout_bits mac_address;
3051 u8 reserved_at_140[0xc0];
3054 struct mlx5_ifc_set_issi_out_bits {
3056 u8 reserved_at_8[0x18];
3060 u8 reserved_at_40[0x40];
3063 struct mlx5_ifc_set_issi_in_bits {
3065 u8 reserved_at_10[0x10];
3067 u8 reserved_at_20[0x10];
3070 u8 reserved_at_40[0x10];
3071 u8 current_issi[0x10];
3073 u8 reserved_at_60[0x20];
3076 struct mlx5_ifc_set_hca_cap_out_bits {
3078 u8 reserved_at_8[0x18];
3082 u8 reserved_at_40[0x40];
3085 struct mlx5_ifc_set_hca_cap_in_bits {
3087 u8 reserved_at_10[0x10];
3089 u8 reserved_at_20[0x10];
3092 u8 reserved_at_40[0x40];
3094 union mlx5_ifc_hca_cap_union_bits capability;
3098 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3099 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3100 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3101 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3104 struct mlx5_ifc_set_fte_out_bits {
3106 u8 reserved_at_8[0x18];
3110 u8 reserved_at_40[0x40];
3113 struct mlx5_ifc_set_fte_in_bits {
3115 u8 reserved_at_10[0x10];
3117 u8 reserved_at_20[0x10];
3120 u8 other_vport[0x1];
3121 u8 reserved_at_41[0xf];
3122 u8 vport_number[0x10];
3124 u8 reserved_at_60[0x20];
3127 u8 reserved_at_88[0x18];
3129 u8 reserved_at_a0[0x8];
3132 u8 reserved_at_c0[0x18];
3133 u8 modify_enable_mask[0x8];
3135 u8 reserved_at_e0[0x20];
3137 u8 flow_index[0x20];
3139 u8 reserved_at_120[0xe0];
3141 struct mlx5_ifc_flow_context_bits flow_context;
3144 struct mlx5_ifc_rts2rts_qp_out_bits {
3146 u8 reserved_at_8[0x18];
3150 u8 reserved_at_40[0x40];
3153 struct mlx5_ifc_rts2rts_qp_in_bits {
3155 u8 reserved_at_10[0x10];
3157 u8 reserved_at_20[0x10];
3160 u8 reserved_at_40[0x8];
3163 u8 reserved_at_60[0x20];
3165 u8 opt_param_mask[0x20];
3167 u8 reserved_at_a0[0x20];
3169 struct mlx5_ifc_qpc_bits qpc;
3171 u8 reserved_at_800[0x80];
3174 struct mlx5_ifc_rtr2rts_qp_out_bits {
3176 u8 reserved_at_8[0x18];
3180 u8 reserved_at_40[0x40];
3183 struct mlx5_ifc_rtr2rts_qp_in_bits {
3185 u8 reserved_at_10[0x10];
3187 u8 reserved_at_20[0x10];
3190 u8 reserved_at_40[0x8];
3193 u8 reserved_at_60[0x20];
3195 u8 opt_param_mask[0x20];
3197 u8 reserved_at_a0[0x20];
3199 struct mlx5_ifc_qpc_bits qpc;
3201 u8 reserved_at_800[0x80];
3204 struct mlx5_ifc_rst2init_qp_out_bits {
3206 u8 reserved_at_8[0x18];
3210 u8 reserved_at_40[0x40];
3213 struct mlx5_ifc_rst2init_qp_in_bits {
3215 u8 reserved_at_10[0x10];
3217 u8 reserved_at_20[0x10];
3220 u8 reserved_at_40[0x8];
3223 u8 reserved_at_60[0x20];
3225 u8 opt_param_mask[0x20];
3227 u8 reserved_at_a0[0x20];
3229 struct mlx5_ifc_qpc_bits qpc;
3231 u8 reserved_at_800[0x80];
3234 struct mlx5_ifc_query_xrq_out_bits {
3236 u8 reserved_at_8[0x18];
3240 u8 reserved_at_40[0x40];
3242 struct mlx5_ifc_xrqc_bits xrq_context;
3245 struct mlx5_ifc_query_xrq_in_bits {
3247 u8 reserved_at_10[0x10];
3249 u8 reserved_at_20[0x10];
3252 u8 reserved_at_40[0x8];
3255 u8 reserved_at_60[0x20];
3258 struct mlx5_ifc_query_xrc_srq_out_bits {
3260 u8 reserved_at_8[0x18];
3264 u8 reserved_at_40[0x40];
3266 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3268 u8 reserved_at_280[0x600];
3273 struct mlx5_ifc_query_xrc_srq_in_bits {
3275 u8 reserved_at_10[0x10];
3277 u8 reserved_at_20[0x10];
3280 u8 reserved_at_40[0x8];
3283 u8 reserved_at_60[0x20];
3287 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3288 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3291 struct mlx5_ifc_query_vport_state_out_bits {
3293 u8 reserved_at_8[0x18];
3297 u8 reserved_at_40[0x20];
3299 u8 reserved_at_60[0x18];
3300 u8 admin_state[0x4];
3305 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3306 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3309 struct mlx5_ifc_query_vport_state_in_bits {
3311 u8 reserved_at_10[0x10];
3313 u8 reserved_at_20[0x10];
3316 u8 other_vport[0x1];
3317 u8 reserved_at_41[0xf];
3318 u8 vport_number[0x10];
3320 u8 reserved_at_60[0x20];
3323 struct mlx5_ifc_query_vport_counter_out_bits {
3325 u8 reserved_at_8[0x18];
3329 u8 reserved_at_40[0x40];
3331 struct mlx5_ifc_traffic_counter_bits received_errors;
3333 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3335 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3337 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3339 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3341 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3343 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3345 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3347 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3349 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3351 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3353 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3355 u8 reserved_at_680[0xa00];
3359 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3362 struct mlx5_ifc_query_vport_counter_in_bits {
3364 u8 reserved_at_10[0x10];
3366 u8 reserved_at_20[0x10];
3369 u8 other_vport[0x1];
3370 u8 reserved_at_41[0xb];
3372 u8 vport_number[0x10];
3374 u8 reserved_at_60[0x60];
3377 u8 reserved_at_c1[0x1f];
3379 u8 reserved_at_e0[0x20];
3382 struct mlx5_ifc_query_tis_out_bits {
3384 u8 reserved_at_8[0x18];
3388 u8 reserved_at_40[0x40];
3390 struct mlx5_ifc_tisc_bits tis_context;
3393 struct mlx5_ifc_query_tis_in_bits {
3395 u8 reserved_at_10[0x10];
3397 u8 reserved_at_20[0x10];
3400 u8 reserved_at_40[0x8];
3403 u8 reserved_at_60[0x20];
3406 struct mlx5_ifc_query_tir_out_bits {
3408 u8 reserved_at_8[0x18];
3412 u8 reserved_at_40[0xc0];
3414 struct mlx5_ifc_tirc_bits tir_context;
3417 struct mlx5_ifc_query_tir_in_bits {
3419 u8 reserved_at_10[0x10];
3421 u8 reserved_at_20[0x10];
3424 u8 reserved_at_40[0x8];
3427 u8 reserved_at_60[0x20];
3430 struct mlx5_ifc_query_srq_out_bits {
3432 u8 reserved_at_8[0x18];
3436 u8 reserved_at_40[0x40];
3438 struct mlx5_ifc_srqc_bits srq_context_entry;
3440 u8 reserved_at_280[0x600];
3445 struct mlx5_ifc_query_srq_in_bits {
3447 u8 reserved_at_10[0x10];
3449 u8 reserved_at_20[0x10];
3452 u8 reserved_at_40[0x8];
3455 u8 reserved_at_60[0x20];
3458 struct mlx5_ifc_query_sq_out_bits {
3460 u8 reserved_at_8[0x18];
3464 u8 reserved_at_40[0xc0];
3466 struct mlx5_ifc_sqc_bits sq_context;
3469 struct mlx5_ifc_query_sq_in_bits {
3471 u8 reserved_at_10[0x10];
3473 u8 reserved_at_20[0x10];
3476 u8 reserved_at_40[0x8];
3479 u8 reserved_at_60[0x20];
3482 struct mlx5_ifc_query_special_contexts_out_bits {
3484 u8 reserved_at_8[0x18];
3488 u8 reserved_at_40[0x20];
3493 struct mlx5_ifc_query_special_contexts_in_bits {
3495 u8 reserved_at_10[0x10];
3497 u8 reserved_at_20[0x10];
3500 u8 reserved_at_40[0x40];
3503 struct mlx5_ifc_query_rqt_out_bits {
3505 u8 reserved_at_8[0x18];
3509 u8 reserved_at_40[0xc0];
3511 struct mlx5_ifc_rqtc_bits rqt_context;
3514 struct mlx5_ifc_query_rqt_in_bits {
3516 u8 reserved_at_10[0x10];
3518 u8 reserved_at_20[0x10];
3521 u8 reserved_at_40[0x8];
3524 u8 reserved_at_60[0x20];
3527 struct mlx5_ifc_query_rq_out_bits {
3529 u8 reserved_at_8[0x18];
3533 u8 reserved_at_40[0xc0];
3535 struct mlx5_ifc_rqc_bits rq_context;
3538 struct mlx5_ifc_query_rq_in_bits {
3540 u8 reserved_at_10[0x10];
3542 u8 reserved_at_20[0x10];
3545 u8 reserved_at_40[0x8];
3548 u8 reserved_at_60[0x20];
3551 struct mlx5_ifc_query_roce_address_out_bits {
3553 u8 reserved_at_8[0x18];
3557 u8 reserved_at_40[0x40];
3559 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3562 struct mlx5_ifc_query_roce_address_in_bits {
3564 u8 reserved_at_10[0x10];
3566 u8 reserved_at_20[0x10];
3569 u8 roce_address_index[0x10];
3570 u8 reserved_at_50[0x10];
3572 u8 reserved_at_60[0x20];
3575 struct mlx5_ifc_query_rmp_out_bits {
3577 u8 reserved_at_8[0x18];
3581 u8 reserved_at_40[0xc0];
3583 struct mlx5_ifc_rmpc_bits rmp_context;
3586 struct mlx5_ifc_query_rmp_in_bits {
3588 u8 reserved_at_10[0x10];
3590 u8 reserved_at_20[0x10];
3593 u8 reserved_at_40[0x8];
3596 u8 reserved_at_60[0x20];
3599 struct mlx5_ifc_query_qp_out_bits {
3601 u8 reserved_at_8[0x18];
3605 u8 reserved_at_40[0x40];
3607 u8 opt_param_mask[0x20];
3609 u8 reserved_at_a0[0x20];
3611 struct mlx5_ifc_qpc_bits qpc;
3613 u8 reserved_at_800[0x80];
3618 struct mlx5_ifc_query_qp_in_bits {
3620 u8 reserved_at_10[0x10];
3622 u8 reserved_at_20[0x10];
3625 u8 reserved_at_40[0x8];
3628 u8 reserved_at_60[0x20];
3631 struct mlx5_ifc_query_q_counter_out_bits {
3633 u8 reserved_at_8[0x18];
3637 u8 reserved_at_40[0x40];
3639 u8 rx_write_requests[0x20];
3641 u8 reserved_at_a0[0x20];
3643 u8 rx_read_requests[0x20];
3645 u8 reserved_at_e0[0x20];
3647 u8 rx_atomic_requests[0x20];
3649 u8 reserved_at_120[0x20];
3651 u8 rx_dct_connect[0x20];
3653 u8 reserved_at_160[0x20];
3655 u8 out_of_buffer[0x20];
3657 u8 reserved_at_1a0[0x20];
3659 u8 out_of_sequence[0x20];
3661 u8 reserved_at_1e0[0x20];
3663 u8 duplicate_request[0x20];
3665 u8 reserved_at_220[0x20];
3667 u8 rnr_nak_retry_err[0x20];
3669 u8 reserved_at_260[0x20];
3671 u8 packet_seq_err[0x20];
3673 u8 reserved_at_2a0[0x20];
3675 u8 implied_nak_seq_err[0x20];
3677 u8 reserved_at_2e0[0x20];
3679 u8 local_ack_timeout_err[0x20];
3681 u8 reserved_at_320[0x4e0];
3684 struct mlx5_ifc_query_q_counter_in_bits {
3686 u8 reserved_at_10[0x10];
3688 u8 reserved_at_20[0x10];
3691 u8 reserved_at_40[0x80];
3694 u8 reserved_at_c1[0x1f];
3696 u8 reserved_at_e0[0x18];
3697 u8 counter_set_id[0x8];
3700 struct mlx5_ifc_query_pages_out_bits {
3702 u8 reserved_at_8[0x18];
3706 u8 reserved_at_40[0x10];
3707 u8 function_id[0x10];
3713 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3714 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3715 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3718 struct mlx5_ifc_query_pages_in_bits {
3720 u8 reserved_at_10[0x10];
3722 u8 reserved_at_20[0x10];
3725 u8 reserved_at_40[0x10];
3726 u8 function_id[0x10];
3728 u8 reserved_at_60[0x20];
3731 struct mlx5_ifc_query_nic_vport_context_out_bits {
3733 u8 reserved_at_8[0x18];
3737 u8 reserved_at_40[0x40];
3739 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3742 struct mlx5_ifc_query_nic_vport_context_in_bits {
3744 u8 reserved_at_10[0x10];
3746 u8 reserved_at_20[0x10];
3749 u8 other_vport[0x1];
3750 u8 reserved_at_41[0xf];
3751 u8 vport_number[0x10];
3753 u8 reserved_at_60[0x5];
3754 u8 allowed_list_type[0x3];
3755 u8 reserved_at_68[0x18];
3758 struct mlx5_ifc_query_mkey_out_bits {
3760 u8 reserved_at_8[0x18];
3764 u8 reserved_at_40[0x40];
3766 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3768 u8 reserved_at_280[0x600];
3770 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3772 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3775 struct mlx5_ifc_query_mkey_in_bits {
3777 u8 reserved_at_10[0x10];
3779 u8 reserved_at_20[0x10];
3782 u8 reserved_at_40[0x8];
3783 u8 mkey_index[0x18];
3786 u8 reserved_at_61[0x1f];
3789 struct mlx5_ifc_query_mad_demux_out_bits {
3791 u8 reserved_at_8[0x18];
3795 u8 reserved_at_40[0x40];
3797 u8 mad_dumux_parameters_block[0x20];
3800 struct mlx5_ifc_query_mad_demux_in_bits {
3802 u8 reserved_at_10[0x10];
3804 u8 reserved_at_20[0x10];
3807 u8 reserved_at_40[0x40];
3810 struct mlx5_ifc_query_l2_table_entry_out_bits {
3812 u8 reserved_at_8[0x18];
3816 u8 reserved_at_40[0xa0];
3818 u8 reserved_at_e0[0x13];
3822 struct mlx5_ifc_mac_address_layout_bits mac_address;
3824 u8 reserved_at_140[0xc0];
3827 struct mlx5_ifc_query_l2_table_entry_in_bits {
3829 u8 reserved_at_10[0x10];
3831 u8 reserved_at_20[0x10];
3834 u8 reserved_at_40[0x60];
3836 u8 reserved_at_a0[0x8];
3837 u8 table_index[0x18];
3839 u8 reserved_at_c0[0x140];
3842 struct mlx5_ifc_query_issi_out_bits {
3844 u8 reserved_at_8[0x18];
3848 u8 reserved_at_40[0x10];
3849 u8 current_issi[0x10];
3851 u8 reserved_at_60[0xa0];
3853 u8 reserved_at_100[76][0x8];
3854 u8 supported_issi_dw0[0x20];
3857 struct mlx5_ifc_query_issi_in_bits {
3859 u8 reserved_at_10[0x10];
3861 u8 reserved_at_20[0x10];
3864 u8 reserved_at_40[0x40];
3867 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3869 u8 reserved_at_8[0x18];
3873 u8 reserved_at_40[0x40];
3875 struct mlx5_ifc_pkey_bits pkey[0];
3878 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3880 u8 reserved_at_10[0x10];
3882 u8 reserved_at_20[0x10];
3885 u8 other_vport[0x1];
3886 u8 reserved_at_41[0xb];
3888 u8 vport_number[0x10];
3890 u8 reserved_at_60[0x10];
3891 u8 pkey_index[0x10];
3895 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3896 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3897 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3900 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3902 u8 reserved_at_8[0x18];
3906 u8 reserved_at_40[0x20];
3909 u8 reserved_at_70[0x10];
3911 struct mlx5_ifc_array128_auto_bits gid[0];
3914 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3916 u8 reserved_at_10[0x10];
3918 u8 reserved_at_20[0x10];
3921 u8 other_vport[0x1];
3922 u8 reserved_at_41[0xb];
3924 u8 vport_number[0x10];
3926 u8 reserved_at_60[0x10];
3930 struct mlx5_ifc_query_hca_vport_context_out_bits {
3932 u8 reserved_at_8[0x18];
3936 u8 reserved_at_40[0x40];
3938 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3941 struct mlx5_ifc_query_hca_vport_context_in_bits {
3943 u8 reserved_at_10[0x10];
3945 u8 reserved_at_20[0x10];
3948 u8 other_vport[0x1];
3949 u8 reserved_at_41[0xb];
3951 u8 vport_number[0x10];
3953 u8 reserved_at_60[0x20];
3956 struct mlx5_ifc_query_hca_cap_out_bits {
3958 u8 reserved_at_8[0x18];
3962 u8 reserved_at_40[0x40];
3964 union mlx5_ifc_hca_cap_union_bits capability;
3967 struct mlx5_ifc_query_hca_cap_in_bits {
3969 u8 reserved_at_10[0x10];
3971 u8 reserved_at_20[0x10];
3974 u8 reserved_at_40[0x40];
3977 struct mlx5_ifc_query_flow_table_out_bits {
3979 u8 reserved_at_8[0x18];
3983 u8 reserved_at_40[0x80];
3985 u8 reserved_at_c0[0x8];
3987 u8 reserved_at_d0[0x8];
3990 u8 reserved_at_e0[0x120];
3993 struct mlx5_ifc_query_flow_table_in_bits {
3995 u8 reserved_at_10[0x10];
3997 u8 reserved_at_20[0x10];
4000 u8 reserved_at_40[0x40];
4003 u8 reserved_at_88[0x18];
4005 u8 reserved_at_a0[0x8];
4008 u8 reserved_at_c0[0x140];
4011 struct mlx5_ifc_query_fte_out_bits {
4013 u8 reserved_at_8[0x18];
4017 u8 reserved_at_40[0x1c0];
4019 struct mlx5_ifc_flow_context_bits flow_context;
4022 struct mlx5_ifc_query_fte_in_bits {
4024 u8 reserved_at_10[0x10];
4026 u8 reserved_at_20[0x10];
4029 u8 reserved_at_40[0x40];
4032 u8 reserved_at_88[0x18];
4034 u8 reserved_at_a0[0x8];
4037 u8 reserved_at_c0[0x40];
4039 u8 flow_index[0x20];
4041 u8 reserved_at_120[0xe0];
4045 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4046 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4047 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4050 struct mlx5_ifc_query_flow_group_out_bits {
4052 u8 reserved_at_8[0x18];
4056 u8 reserved_at_40[0xa0];
4058 u8 start_flow_index[0x20];
4060 u8 reserved_at_100[0x20];
4062 u8 end_flow_index[0x20];
4064 u8 reserved_at_140[0xa0];
4066 u8 reserved_at_1e0[0x18];
4067 u8 match_criteria_enable[0x8];
4069 struct mlx5_ifc_fte_match_param_bits match_criteria;
4071 u8 reserved_at_1200[0xe00];
4074 struct mlx5_ifc_query_flow_group_in_bits {
4076 u8 reserved_at_10[0x10];
4078 u8 reserved_at_20[0x10];
4081 u8 reserved_at_40[0x40];
4084 u8 reserved_at_88[0x18];
4086 u8 reserved_at_a0[0x8];
4091 u8 reserved_at_e0[0x120];
4094 struct mlx5_ifc_query_flow_counter_out_bits {
4096 u8 reserved_at_8[0x18];
4100 u8 reserved_at_40[0x40];
4102 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4105 struct mlx5_ifc_query_flow_counter_in_bits {
4107 u8 reserved_at_10[0x10];
4109 u8 reserved_at_20[0x10];
4112 u8 reserved_at_40[0x80];
4115 u8 reserved_at_c1[0xf];
4116 u8 num_of_counters[0x10];
4118 u8 reserved_at_e0[0x10];
4119 u8 flow_counter_id[0x10];
4122 struct mlx5_ifc_query_esw_vport_context_out_bits {
4124 u8 reserved_at_8[0x18];
4128 u8 reserved_at_40[0x40];
4130 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4133 struct mlx5_ifc_query_esw_vport_context_in_bits {
4135 u8 reserved_at_10[0x10];
4137 u8 reserved_at_20[0x10];
4140 u8 other_vport[0x1];
4141 u8 reserved_at_41[0xf];
4142 u8 vport_number[0x10];
4144 u8 reserved_at_60[0x20];
4147 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4149 u8 reserved_at_8[0x18];
4153 u8 reserved_at_40[0x40];
4156 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4157 u8 reserved_at_0[0x1c];
4158 u8 vport_cvlan_insert[0x1];
4159 u8 vport_svlan_insert[0x1];
4160 u8 vport_cvlan_strip[0x1];
4161 u8 vport_svlan_strip[0x1];
4164 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4166 u8 reserved_at_10[0x10];
4168 u8 reserved_at_20[0x10];
4171 u8 other_vport[0x1];
4172 u8 reserved_at_41[0xf];
4173 u8 vport_number[0x10];
4175 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4177 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4180 struct mlx5_ifc_query_eq_out_bits {
4182 u8 reserved_at_8[0x18];
4186 u8 reserved_at_40[0x40];
4188 struct mlx5_ifc_eqc_bits eq_context_entry;
4190 u8 reserved_at_280[0x40];
4192 u8 event_bitmask[0x40];
4194 u8 reserved_at_300[0x580];
4199 struct mlx5_ifc_query_eq_in_bits {
4201 u8 reserved_at_10[0x10];
4203 u8 reserved_at_20[0x10];
4206 u8 reserved_at_40[0x18];
4209 u8 reserved_at_60[0x20];
4212 struct mlx5_ifc_query_dct_out_bits {
4214 u8 reserved_at_8[0x18];
4218 u8 reserved_at_40[0x40];
4220 struct mlx5_ifc_dctc_bits dct_context_entry;
4222 u8 reserved_at_280[0x180];
4225 struct mlx5_ifc_query_dct_in_bits {
4227 u8 reserved_at_10[0x10];
4229 u8 reserved_at_20[0x10];
4232 u8 reserved_at_40[0x8];
4235 u8 reserved_at_60[0x20];
4238 struct mlx5_ifc_query_cq_out_bits {
4240 u8 reserved_at_8[0x18];
4244 u8 reserved_at_40[0x40];
4246 struct mlx5_ifc_cqc_bits cq_context;
4248 u8 reserved_at_280[0x600];
4253 struct mlx5_ifc_query_cq_in_bits {
4255 u8 reserved_at_10[0x10];
4257 u8 reserved_at_20[0x10];
4260 u8 reserved_at_40[0x8];
4263 u8 reserved_at_60[0x20];
4266 struct mlx5_ifc_query_cong_status_out_bits {
4268 u8 reserved_at_8[0x18];
4272 u8 reserved_at_40[0x20];
4276 u8 reserved_at_62[0x1e];
4279 struct mlx5_ifc_query_cong_status_in_bits {
4281 u8 reserved_at_10[0x10];
4283 u8 reserved_at_20[0x10];
4286 u8 reserved_at_40[0x18];
4288 u8 cong_protocol[0x4];
4290 u8 reserved_at_60[0x20];
4293 struct mlx5_ifc_query_cong_statistics_out_bits {
4295 u8 reserved_at_8[0x18];
4299 u8 reserved_at_40[0x40];
4305 u8 cnp_ignored_high[0x20];
4307 u8 cnp_ignored_low[0x20];
4309 u8 cnp_handled_high[0x20];
4311 u8 cnp_handled_low[0x20];
4313 u8 reserved_at_140[0x100];
4315 u8 time_stamp_high[0x20];
4317 u8 time_stamp_low[0x20];
4319 u8 accumulators_period[0x20];
4321 u8 ecn_marked_roce_packets_high[0x20];
4323 u8 ecn_marked_roce_packets_low[0x20];
4325 u8 cnps_sent_high[0x20];
4327 u8 cnps_sent_low[0x20];
4329 u8 reserved_at_320[0x560];
4332 struct mlx5_ifc_query_cong_statistics_in_bits {
4334 u8 reserved_at_10[0x10];
4336 u8 reserved_at_20[0x10];
4340 u8 reserved_at_41[0x1f];
4342 u8 reserved_at_60[0x20];
4345 struct mlx5_ifc_query_cong_params_out_bits {
4347 u8 reserved_at_8[0x18];
4351 u8 reserved_at_40[0x40];
4353 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4356 struct mlx5_ifc_query_cong_params_in_bits {
4358 u8 reserved_at_10[0x10];
4360 u8 reserved_at_20[0x10];
4363 u8 reserved_at_40[0x1c];
4364 u8 cong_protocol[0x4];
4366 u8 reserved_at_60[0x20];
4369 struct mlx5_ifc_query_adapter_out_bits {
4371 u8 reserved_at_8[0x18];
4375 u8 reserved_at_40[0x40];
4377 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4380 struct mlx5_ifc_query_adapter_in_bits {
4382 u8 reserved_at_10[0x10];
4384 u8 reserved_at_20[0x10];
4387 u8 reserved_at_40[0x40];
4390 struct mlx5_ifc_qp_2rst_out_bits {
4392 u8 reserved_at_8[0x18];
4396 u8 reserved_at_40[0x40];
4399 struct mlx5_ifc_qp_2rst_in_bits {
4401 u8 reserved_at_10[0x10];
4403 u8 reserved_at_20[0x10];
4406 u8 reserved_at_40[0x8];
4409 u8 reserved_at_60[0x20];
4412 struct mlx5_ifc_qp_2err_out_bits {
4414 u8 reserved_at_8[0x18];
4418 u8 reserved_at_40[0x40];
4421 struct mlx5_ifc_qp_2err_in_bits {
4423 u8 reserved_at_10[0x10];
4425 u8 reserved_at_20[0x10];
4428 u8 reserved_at_40[0x8];
4431 u8 reserved_at_60[0x20];
4434 struct mlx5_ifc_page_fault_resume_out_bits {
4436 u8 reserved_at_8[0x18];
4440 u8 reserved_at_40[0x40];
4443 struct mlx5_ifc_page_fault_resume_in_bits {
4445 u8 reserved_at_10[0x10];
4447 u8 reserved_at_20[0x10];
4451 u8 reserved_at_41[0x4];
4457 u8 reserved_at_60[0x20];
4460 struct mlx5_ifc_nop_out_bits {
4462 u8 reserved_at_8[0x18];
4466 u8 reserved_at_40[0x40];
4469 struct mlx5_ifc_nop_in_bits {
4471 u8 reserved_at_10[0x10];
4473 u8 reserved_at_20[0x10];
4476 u8 reserved_at_40[0x40];
4479 struct mlx5_ifc_modify_vport_state_out_bits {
4481 u8 reserved_at_8[0x18];
4485 u8 reserved_at_40[0x40];
4488 struct mlx5_ifc_modify_vport_state_in_bits {
4490 u8 reserved_at_10[0x10];
4492 u8 reserved_at_20[0x10];
4495 u8 other_vport[0x1];
4496 u8 reserved_at_41[0xf];
4497 u8 vport_number[0x10];
4499 u8 reserved_at_60[0x18];
4500 u8 admin_state[0x4];
4501 u8 reserved_at_7c[0x4];
4504 struct mlx5_ifc_modify_tis_out_bits {
4506 u8 reserved_at_8[0x18];
4510 u8 reserved_at_40[0x40];
4513 struct mlx5_ifc_modify_tis_bitmask_bits {
4514 u8 reserved_at_0[0x20];
4516 u8 reserved_at_20[0x1f];
4520 struct mlx5_ifc_modify_tis_in_bits {
4522 u8 reserved_at_10[0x10];
4524 u8 reserved_at_20[0x10];
4527 u8 reserved_at_40[0x8];
4530 u8 reserved_at_60[0x20];
4532 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4534 u8 reserved_at_c0[0x40];
4536 struct mlx5_ifc_tisc_bits ctx;
4539 struct mlx5_ifc_modify_tir_bitmask_bits {
4540 u8 reserved_at_0[0x20];
4542 u8 reserved_at_20[0x1b];
4544 u8 reserved_at_3c[0x1];
4546 u8 reserved_at_3e[0x1];
4550 struct mlx5_ifc_modify_tir_out_bits {
4552 u8 reserved_at_8[0x18];
4556 u8 reserved_at_40[0x40];
4559 struct mlx5_ifc_modify_tir_in_bits {
4561 u8 reserved_at_10[0x10];
4563 u8 reserved_at_20[0x10];
4566 u8 reserved_at_40[0x8];
4569 u8 reserved_at_60[0x20];
4571 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4573 u8 reserved_at_c0[0x40];
4575 struct mlx5_ifc_tirc_bits ctx;
4578 struct mlx5_ifc_modify_sq_out_bits {
4580 u8 reserved_at_8[0x18];
4584 u8 reserved_at_40[0x40];
4587 struct mlx5_ifc_modify_sq_in_bits {
4589 u8 reserved_at_10[0x10];
4591 u8 reserved_at_20[0x10];
4595 u8 reserved_at_44[0x4];
4598 u8 reserved_at_60[0x20];
4600 u8 modify_bitmask[0x40];
4602 u8 reserved_at_c0[0x40];
4604 struct mlx5_ifc_sqc_bits ctx;
4607 struct mlx5_ifc_modify_rqt_out_bits {
4609 u8 reserved_at_8[0x18];
4613 u8 reserved_at_40[0x40];
4616 struct mlx5_ifc_rqt_bitmask_bits {
4617 u8 reserved_at_0[0x20];
4619 u8 reserved_at_20[0x1f];
4623 struct mlx5_ifc_modify_rqt_in_bits {
4625 u8 reserved_at_10[0x10];
4627 u8 reserved_at_20[0x10];
4630 u8 reserved_at_40[0x8];
4633 u8 reserved_at_60[0x20];
4635 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4637 u8 reserved_at_c0[0x40];
4639 struct mlx5_ifc_rqtc_bits ctx;
4642 struct mlx5_ifc_modify_rq_out_bits {
4644 u8 reserved_at_8[0x18];
4648 u8 reserved_at_40[0x40];
4651 struct mlx5_ifc_modify_rq_in_bits {
4653 u8 reserved_at_10[0x10];
4655 u8 reserved_at_20[0x10];
4659 u8 reserved_at_44[0x4];
4662 u8 reserved_at_60[0x20];
4664 u8 modify_bitmask[0x40];
4666 u8 reserved_at_c0[0x40];
4668 struct mlx5_ifc_rqc_bits ctx;
4671 struct mlx5_ifc_modify_rmp_out_bits {
4673 u8 reserved_at_8[0x18];
4677 u8 reserved_at_40[0x40];
4680 struct mlx5_ifc_rmp_bitmask_bits {
4681 u8 reserved_at_0[0x20];
4683 u8 reserved_at_20[0x1f];
4687 struct mlx5_ifc_modify_rmp_in_bits {
4689 u8 reserved_at_10[0x10];
4691 u8 reserved_at_20[0x10];
4695 u8 reserved_at_44[0x4];
4698 u8 reserved_at_60[0x20];
4700 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4702 u8 reserved_at_c0[0x40];
4704 struct mlx5_ifc_rmpc_bits ctx;
4707 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4709 u8 reserved_at_8[0x18];
4713 u8 reserved_at_40[0x40];
4716 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4717 u8 reserved_at_0[0x16];
4720 u8 reserved_at_18[0x1];
4722 u8 change_event[0x1];
4724 u8 permanent_address[0x1];
4725 u8 addresses_list[0x1];
4727 u8 reserved_at_1f[0x1];
4730 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4732 u8 reserved_at_10[0x10];
4734 u8 reserved_at_20[0x10];
4737 u8 other_vport[0x1];
4738 u8 reserved_at_41[0xf];
4739 u8 vport_number[0x10];
4741 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4743 u8 reserved_at_80[0x780];
4745 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4748 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4750 u8 reserved_at_8[0x18];
4754 u8 reserved_at_40[0x40];
4757 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4759 u8 reserved_at_10[0x10];
4761 u8 reserved_at_20[0x10];
4764 u8 other_vport[0x1];
4765 u8 reserved_at_41[0xb];
4767 u8 vport_number[0x10];
4769 u8 reserved_at_60[0x20];
4771 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4774 struct mlx5_ifc_modify_cq_out_bits {
4776 u8 reserved_at_8[0x18];
4780 u8 reserved_at_40[0x40];
4784 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4785 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4788 struct mlx5_ifc_modify_cq_in_bits {
4790 u8 reserved_at_10[0x10];
4792 u8 reserved_at_20[0x10];
4795 u8 reserved_at_40[0x8];
4798 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4800 struct mlx5_ifc_cqc_bits cq_context;
4802 u8 reserved_at_280[0x600];
4807 struct mlx5_ifc_modify_cong_status_out_bits {
4809 u8 reserved_at_8[0x18];
4813 u8 reserved_at_40[0x40];
4816 struct mlx5_ifc_modify_cong_status_in_bits {
4818 u8 reserved_at_10[0x10];
4820 u8 reserved_at_20[0x10];
4823 u8 reserved_at_40[0x18];
4825 u8 cong_protocol[0x4];
4829 u8 reserved_at_62[0x1e];
4832 struct mlx5_ifc_modify_cong_params_out_bits {
4834 u8 reserved_at_8[0x18];
4838 u8 reserved_at_40[0x40];
4841 struct mlx5_ifc_modify_cong_params_in_bits {
4843 u8 reserved_at_10[0x10];
4845 u8 reserved_at_20[0x10];
4848 u8 reserved_at_40[0x1c];
4849 u8 cong_protocol[0x4];
4851 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4853 u8 reserved_at_80[0x80];
4855 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4858 struct mlx5_ifc_manage_pages_out_bits {
4860 u8 reserved_at_8[0x18];
4864 u8 output_num_entries[0x20];
4866 u8 reserved_at_60[0x20];
4872 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4873 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4874 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4877 struct mlx5_ifc_manage_pages_in_bits {
4879 u8 reserved_at_10[0x10];
4881 u8 reserved_at_20[0x10];
4884 u8 reserved_at_40[0x10];
4885 u8 function_id[0x10];
4887 u8 input_num_entries[0x20];
4892 struct mlx5_ifc_mad_ifc_out_bits {
4894 u8 reserved_at_8[0x18];
4898 u8 reserved_at_40[0x40];
4900 u8 response_mad_packet[256][0x8];
4903 struct mlx5_ifc_mad_ifc_in_bits {
4905 u8 reserved_at_10[0x10];
4907 u8 reserved_at_20[0x10];
4910 u8 remote_lid[0x10];
4911 u8 reserved_at_50[0x8];
4914 u8 reserved_at_60[0x20];
4919 struct mlx5_ifc_init_hca_out_bits {
4921 u8 reserved_at_8[0x18];
4925 u8 reserved_at_40[0x40];
4928 struct mlx5_ifc_init_hca_in_bits {
4930 u8 reserved_at_10[0x10];
4932 u8 reserved_at_20[0x10];
4935 u8 reserved_at_40[0x40];
4938 struct mlx5_ifc_init2rtr_qp_out_bits {
4940 u8 reserved_at_8[0x18];
4944 u8 reserved_at_40[0x40];
4947 struct mlx5_ifc_init2rtr_qp_in_bits {
4949 u8 reserved_at_10[0x10];
4951 u8 reserved_at_20[0x10];
4954 u8 reserved_at_40[0x8];
4957 u8 reserved_at_60[0x20];
4959 u8 opt_param_mask[0x20];
4961 u8 reserved_at_a0[0x20];
4963 struct mlx5_ifc_qpc_bits qpc;
4965 u8 reserved_at_800[0x80];
4968 struct mlx5_ifc_init2init_qp_out_bits {
4970 u8 reserved_at_8[0x18];
4974 u8 reserved_at_40[0x40];
4977 struct mlx5_ifc_init2init_qp_in_bits {
4979 u8 reserved_at_10[0x10];
4981 u8 reserved_at_20[0x10];
4984 u8 reserved_at_40[0x8];
4987 u8 reserved_at_60[0x20];
4989 u8 opt_param_mask[0x20];
4991 u8 reserved_at_a0[0x20];
4993 struct mlx5_ifc_qpc_bits qpc;
4995 u8 reserved_at_800[0x80];
4998 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5000 u8 reserved_at_8[0x18];
5004 u8 reserved_at_40[0x40];
5006 u8 packet_headers_log[128][0x8];
5008 u8 packet_syndrome[64][0x8];
5011 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5013 u8 reserved_at_10[0x10];
5015 u8 reserved_at_20[0x10];
5018 u8 reserved_at_40[0x40];
5021 struct mlx5_ifc_gen_eqe_in_bits {
5023 u8 reserved_at_10[0x10];
5025 u8 reserved_at_20[0x10];
5028 u8 reserved_at_40[0x18];
5031 u8 reserved_at_60[0x20];
5036 struct mlx5_ifc_gen_eq_out_bits {
5038 u8 reserved_at_8[0x18];
5042 u8 reserved_at_40[0x40];
5045 struct mlx5_ifc_enable_hca_out_bits {
5047 u8 reserved_at_8[0x18];
5051 u8 reserved_at_40[0x20];
5054 struct mlx5_ifc_enable_hca_in_bits {
5056 u8 reserved_at_10[0x10];
5058 u8 reserved_at_20[0x10];
5061 u8 reserved_at_40[0x10];
5062 u8 function_id[0x10];
5064 u8 reserved_at_60[0x20];
5067 struct mlx5_ifc_drain_dct_out_bits {
5069 u8 reserved_at_8[0x18];
5073 u8 reserved_at_40[0x40];
5076 struct mlx5_ifc_drain_dct_in_bits {
5078 u8 reserved_at_10[0x10];
5080 u8 reserved_at_20[0x10];
5083 u8 reserved_at_40[0x8];
5086 u8 reserved_at_60[0x20];
5089 struct mlx5_ifc_disable_hca_out_bits {
5091 u8 reserved_at_8[0x18];
5095 u8 reserved_at_40[0x20];
5098 struct mlx5_ifc_disable_hca_in_bits {
5100 u8 reserved_at_10[0x10];
5102 u8 reserved_at_20[0x10];
5105 u8 reserved_at_40[0x10];
5106 u8 function_id[0x10];
5108 u8 reserved_at_60[0x20];
5111 struct mlx5_ifc_detach_from_mcg_out_bits {
5113 u8 reserved_at_8[0x18];
5117 u8 reserved_at_40[0x40];
5120 struct mlx5_ifc_detach_from_mcg_in_bits {
5122 u8 reserved_at_10[0x10];
5124 u8 reserved_at_20[0x10];
5127 u8 reserved_at_40[0x8];
5130 u8 reserved_at_60[0x20];
5132 u8 multicast_gid[16][0x8];
5135 struct mlx5_ifc_destroy_xrq_out_bits {
5137 u8 reserved_at_8[0x18];
5141 u8 reserved_at_40[0x40];
5144 struct mlx5_ifc_destroy_xrq_in_bits {
5146 u8 reserved_at_10[0x10];
5148 u8 reserved_at_20[0x10];
5151 u8 reserved_at_40[0x8];
5154 u8 reserved_at_60[0x20];
5157 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5159 u8 reserved_at_8[0x18];
5163 u8 reserved_at_40[0x40];
5166 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5168 u8 reserved_at_10[0x10];
5170 u8 reserved_at_20[0x10];
5173 u8 reserved_at_40[0x8];
5176 u8 reserved_at_60[0x20];
5179 struct mlx5_ifc_destroy_tis_out_bits {
5181 u8 reserved_at_8[0x18];
5185 u8 reserved_at_40[0x40];
5188 struct mlx5_ifc_destroy_tis_in_bits {
5190 u8 reserved_at_10[0x10];
5192 u8 reserved_at_20[0x10];
5195 u8 reserved_at_40[0x8];
5198 u8 reserved_at_60[0x20];
5201 struct mlx5_ifc_destroy_tir_out_bits {
5203 u8 reserved_at_8[0x18];
5207 u8 reserved_at_40[0x40];
5210 struct mlx5_ifc_destroy_tir_in_bits {
5212 u8 reserved_at_10[0x10];
5214 u8 reserved_at_20[0x10];
5217 u8 reserved_at_40[0x8];
5220 u8 reserved_at_60[0x20];
5223 struct mlx5_ifc_destroy_srq_out_bits {
5225 u8 reserved_at_8[0x18];
5229 u8 reserved_at_40[0x40];
5232 struct mlx5_ifc_destroy_srq_in_bits {
5234 u8 reserved_at_10[0x10];
5236 u8 reserved_at_20[0x10];
5239 u8 reserved_at_40[0x8];
5242 u8 reserved_at_60[0x20];
5245 struct mlx5_ifc_destroy_sq_out_bits {
5247 u8 reserved_at_8[0x18];
5251 u8 reserved_at_40[0x40];
5254 struct mlx5_ifc_destroy_sq_in_bits {
5256 u8 reserved_at_10[0x10];
5258 u8 reserved_at_20[0x10];
5261 u8 reserved_at_40[0x8];
5264 u8 reserved_at_60[0x20];
5267 struct mlx5_ifc_destroy_rqt_out_bits {
5269 u8 reserved_at_8[0x18];
5273 u8 reserved_at_40[0x40];
5276 struct mlx5_ifc_destroy_rqt_in_bits {
5278 u8 reserved_at_10[0x10];
5280 u8 reserved_at_20[0x10];
5283 u8 reserved_at_40[0x8];
5286 u8 reserved_at_60[0x20];
5289 struct mlx5_ifc_destroy_rq_out_bits {
5291 u8 reserved_at_8[0x18];
5295 u8 reserved_at_40[0x40];
5298 struct mlx5_ifc_destroy_rq_in_bits {
5300 u8 reserved_at_10[0x10];
5302 u8 reserved_at_20[0x10];
5305 u8 reserved_at_40[0x8];
5308 u8 reserved_at_60[0x20];
5311 struct mlx5_ifc_destroy_rmp_out_bits {
5313 u8 reserved_at_8[0x18];
5317 u8 reserved_at_40[0x40];
5320 struct mlx5_ifc_destroy_rmp_in_bits {
5322 u8 reserved_at_10[0x10];
5324 u8 reserved_at_20[0x10];
5327 u8 reserved_at_40[0x8];
5330 u8 reserved_at_60[0x20];
5333 struct mlx5_ifc_destroy_qp_out_bits {
5335 u8 reserved_at_8[0x18];
5339 u8 reserved_at_40[0x40];
5342 struct mlx5_ifc_destroy_qp_in_bits {
5344 u8 reserved_at_10[0x10];
5346 u8 reserved_at_20[0x10];
5349 u8 reserved_at_40[0x8];
5352 u8 reserved_at_60[0x20];
5355 struct mlx5_ifc_destroy_psv_out_bits {
5357 u8 reserved_at_8[0x18];
5361 u8 reserved_at_40[0x40];
5364 struct mlx5_ifc_destroy_psv_in_bits {
5366 u8 reserved_at_10[0x10];
5368 u8 reserved_at_20[0x10];
5371 u8 reserved_at_40[0x8];
5374 u8 reserved_at_60[0x20];
5377 struct mlx5_ifc_destroy_mkey_out_bits {
5379 u8 reserved_at_8[0x18];
5383 u8 reserved_at_40[0x40];
5386 struct mlx5_ifc_destroy_mkey_in_bits {
5388 u8 reserved_at_10[0x10];
5390 u8 reserved_at_20[0x10];
5393 u8 reserved_at_40[0x8];
5394 u8 mkey_index[0x18];
5396 u8 reserved_at_60[0x20];
5399 struct mlx5_ifc_destroy_flow_table_out_bits {
5401 u8 reserved_at_8[0x18];
5405 u8 reserved_at_40[0x40];
5408 struct mlx5_ifc_destroy_flow_table_in_bits {
5410 u8 reserved_at_10[0x10];
5412 u8 reserved_at_20[0x10];
5415 u8 other_vport[0x1];
5416 u8 reserved_at_41[0xf];
5417 u8 vport_number[0x10];
5419 u8 reserved_at_60[0x20];
5422 u8 reserved_at_88[0x18];
5424 u8 reserved_at_a0[0x8];
5427 u8 reserved_at_c0[0x140];
5430 struct mlx5_ifc_destroy_flow_group_out_bits {
5432 u8 reserved_at_8[0x18];
5436 u8 reserved_at_40[0x40];
5439 struct mlx5_ifc_destroy_flow_group_in_bits {
5441 u8 reserved_at_10[0x10];
5443 u8 reserved_at_20[0x10];
5446 u8 other_vport[0x1];
5447 u8 reserved_at_41[0xf];
5448 u8 vport_number[0x10];
5450 u8 reserved_at_60[0x20];
5453 u8 reserved_at_88[0x18];
5455 u8 reserved_at_a0[0x8];
5460 u8 reserved_at_e0[0x120];
5463 struct mlx5_ifc_destroy_eq_out_bits {
5465 u8 reserved_at_8[0x18];
5469 u8 reserved_at_40[0x40];
5472 struct mlx5_ifc_destroy_eq_in_bits {
5474 u8 reserved_at_10[0x10];
5476 u8 reserved_at_20[0x10];
5479 u8 reserved_at_40[0x18];
5482 u8 reserved_at_60[0x20];
5485 struct mlx5_ifc_destroy_dct_out_bits {
5487 u8 reserved_at_8[0x18];
5491 u8 reserved_at_40[0x40];
5494 struct mlx5_ifc_destroy_dct_in_bits {
5496 u8 reserved_at_10[0x10];
5498 u8 reserved_at_20[0x10];
5501 u8 reserved_at_40[0x8];
5504 u8 reserved_at_60[0x20];
5507 struct mlx5_ifc_destroy_cq_out_bits {
5509 u8 reserved_at_8[0x18];
5513 u8 reserved_at_40[0x40];
5516 struct mlx5_ifc_destroy_cq_in_bits {
5518 u8 reserved_at_10[0x10];
5520 u8 reserved_at_20[0x10];
5523 u8 reserved_at_40[0x8];
5526 u8 reserved_at_60[0x20];
5529 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5531 u8 reserved_at_8[0x18];
5535 u8 reserved_at_40[0x40];
5538 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5540 u8 reserved_at_10[0x10];
5542 u8 reserved_at_20[0x10];
5545 u8 reserved_at_40[0x20];
5547 u8 reserved_at_60[0x10];
5548 u8 vxlan_udp_port[0x10];
5551 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5553 u8 reserved_at_8[0x18];
5557 u8 reserved_at_40[0x40];
5560 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5562 u8 reserved_at_10[0x10];
5564 u8 reserved_at_20[0x10];
5567 u8 reserved_at_40[0x60];
5569 u8 reserved_at_a0[0x8];
5570 u8 table_index[0x18];
5572 u8 reserved_at_c0[0x140];
5575 struct mlx5_ifc_delete_fte_out_bits {
5577 u8 reserved_at_8[0x18];
5581 u8 reserved_at_40[0x40];
5584 struct mlx5_ifc_delete_fte_in_bits {
5586 u8 reserved_at_10[0x10];
5588 u8 reserved_at_20[0x10];
5591 u8 other_vport[0x1];
5592 u8 reserved_at_41[0xf];
5593 u8 vport_number[0x10];
5595 u8 reserved_at_60[0x20];
5598 u8 reserved_at_88[0x18];
5600 u8 reserved_at_a0[0x8];
5603 u8 reserved_at_c0[0x40];
5605 u8 flow_index[0x20];
5607 u8 reserved_at_120[0xe0];
5610 struct mlx5_ifc_dealloc_xrcd_out_bits {
5612 u8 reserved_at_8[0x18];
5616 u8 reserved_at_40[0x40];
5619 struct mlx5_ifc_dealloc_xrcd_in_bits {
5621 u8 reserved_at_10[0x10];
5623 u8 reserved_at_20[0x10];
5626 u8 reserved_at_40[0x8];
5629 u8 reserved_at_60[0x20];
5632 struct mlx5_ifc_dealloc_uar_out_bits {
5634 u8 reserved_at_8[0x18];
5638 u8 reserved_at_40[0x40];
5641 struct mlx5_ifc_dealloc_uar_in_bits {
5643 u8 reserved_at_10[0x10];
5645 u8 reserved_at_20[0x10];
5648 u8 reserved_at_40[0x8];
5651 u8 reserved_at_60[0x20];
5654 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5656 u8 reserved_at_8[0x18];
5660 u8 reserved_at_40[0x40];
5663 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5665 u8 reserved_at_10[0x10];
5667 u8 reserved_at_20[0x10];
5670 u8 reserved_at_40[0x8];
5671 u8 transport_domain[0x18];
5673 u8 reserved_at_60[0x20];
5676 struct mlx5_ifc_dealloc_q_counter_out_bits {
5678 u8 reserved_at_8[0x18];
5682 u8 reserved_at_40[0x40];
5685 struct mlx5_ifc_dealloc_q_counter_in_bits {
5687 u8 reserved_at_10[0x10];
5689 u8 reserved_at_20[0x10];
5692 u8 reserved_at_40[0x18];
5693 u8 counter_set_id[0x8];
5695 u8 reserved_at_60[0x20];
5698 struct mlx5_ifc_dealloc_pd_out_bits {
5700 u8 reserved_at_8[0x18];
5704 u8 reserved_at_40[0x40];
5707 struct mlx5_ifc_dealloc_pd_in_bits {
5709 u8 reserved_at_10[0x10];
5711 u8 reserved_at_20[0x10];
5714 u8 reserved_at_40[0x8];
5717 u8 reserved_at_60[0x20];
5720 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5722 u8 reserved_at_8[0x18];
5726 u8 reserved_at_40[0x40];
5729 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5731 u8 reserved_at_10[0x10];
5733 u8 reserved_at_20[0x10];
5736 u8 reserved_at_40[0x10];
5737 u8 flow_counter_id[0x10];
5739 u8 reserved_at_60[0x20];
5742 struct mlx5_ifc_create_xrq_out_bits {
5744 u8 reserved_at_8[0x18];
5748 u8 reserved_at_40[0x8];
5751 u8 reserved_at_60[0x20];
5754 struct mlx5_ifc_create_xrq_in_bits {
5756 u8 reserved_at_10[0x10];
5758 u8 reserved_at_20[0x10];
5761 u8 reserved_at_40[0x40];
5763 struct mlx5_ifc_xrqc_bits xrq_context;
5766 struct mlx5_ifc_create_xrc_srq_out_bits {
5768 u8 reserved_at_8[0x18];
5772 u8 reserved_at_40[0x8];
5775 u8 reserved_at_60[0x20];
5778 struct mlx5_ifc_create_xrc_srq_in_bits {
5780 u8 reserved_at_10[0x10];
5782 u8 reserved_at_20[0x10];
5785 u8 reserved_at_40[0x40];
5787 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5789 u8 reserved_at_280[0x600];
5794 struct mlx5_ifc_create_tis_out_bits {
5796 u8 reserved_at_8[0x18];
5800 u8 reserved_at_40[0x8];
5803 u8 reserved_at_60[0x20];
5806 struct mlx5_ifc_create_tis_in_bits {
5808 u8 reserved_at_10[0x10];
5810 u8 reserved_at_20[0x10];
5813 u8 reserved_at_40[0xc0];
5815 struct mlx5_ifc_tisc_bits ctx;
5818 struct mlx5_ifc_create_tir_out_bits {
5820 u8 reserved_at_8[0x18];
5824 u8 reserved_at_40[0x8];
5827 u8 reserved_at_60[0x20];
5830 struct mlx5_ifc_create_tir_in_bits {
5832 u8 reserved_at_10[0x10];
5834 u8 reserved_at_20[0x10];
5837 u8 reserved_at_40[0xc0];
5839 struct mlx5_ifc_tirc_bits ctx;
5842 struct mlx5_ifc_create_srq_out_bits {
5844 u8 reserved_at_8[0x18];
5848 u8 reserved_at_40[0x8];
5851 u8 reserved_at_60[0x20];
5854 struct mlx5_ifc_create_srq_in_bits {
5856 u8 reserved_at_10[0x10];
5858 u8 reserved_at_20[0x10];
5861 u8 reserved_at_40[0x40];
5863 struct mlx5_ifc_srqc_bits srq_context_entry;
5865 u8 reserved_at_280[0x600];
5870 struct mlx5_ifc_create_sq_out_bits {
5872 u8 reserved_at_8[0x18];
5876 u8 reserved_at_40[0x8];
5879 u8 reserved_at_60[0x20];
5882 struct mlx5_ifc_create_sq_in_bits {
5884 u8 reserved_at_10[0x10];
5886 u8 reserved_at_20[0x10];
5889 u8 reserved_at_40[0xc0];
5891 struct mlx5_ifc_sqc_bits ctx;
5894 struct mlx5_ifc_create_rqt_out_bits {
5896 u8 reserved_at_8[0x18];
5900 u8 reserved_at_40[0x8];
5903 u8 reserved_at_60[0x20];
5906 struct mlx5_ifc_create_rqt_in_bits {
5908 u8 reserved_at_10[0x10];
5910 u8 reserved_at_20[0x10];
5913 u8 reserved_at_40[0xc0];
5915 struct mlx5_ifc_rqtc_bits rqt_context;
5918 struct mlx5_ifc_create_rq_out_bits {
5920 u8 reserved_at_8[0x18];
5924 u8 reserved_at_40[0x8];
5927 u8 reserved_at_60[0x20];
5930 struct mlx5_ifc_create_rq_in_bits {
5932 u8 reserved_at_10[0x10];
5934 u8 reserved_at_20[0x10];
5937 u8 reserved_at_40[0xc0];
5939 struct mlx5_ifc_rqc_bits ctx;
5942 struct mlx5_ifc_create_rmp_out_bits {
5944 u8 reserved_at_8[0x18];
5948 u8 reserved_at_40[0x8];
5951 u8 reserved_at_60[0x20];
5954 struct mlx5_ifc_create_rmp_in_bits {
5956 u8 reserved_at_10[0x10];
5958 u8 reserved_at_20[0x10];
5961 u8 reserved_at_40[0xc0];
5963 struct mlx5_ifc_rmpc_bits ctx;
5966 struct mlx5_ifc_create_qp_out_bits {
5968 u8 reserved_at_8[0x18];
5972 u8 reserved_at_40[0x8];
5975 u8 reserved_at_60[0x20];
5978 struct mlx5_ifc_create_qp_in_bits {
5980 u8 reserved_at_10[0x10];
5982 u8 reserved_at_20[0x10];
5985 u8 reserved_at_40[0x40];
5987 u8 opt_param_mask[0x20];
5989 u8 reserved_at_a0[0x20];
5991 struct mlx5_ifc_qpc_bits qpc;
5993 u8 reserved_at_800[0x80];
5998 struct mlx5_ifc_create_psv_out_bits {
6000 u8 reserved_at_8[0x18];
6004 u8 reserved_at_40[0x40];
6006 u8 reserved_at_80[0x8];
6007 u8 psv0_index[0x18];
6009 u8 reserved_at_a0[0x8];
6010 u8 psv1_index[0x18];
6012 u8 reserved_at_c0[0x8];
6013 u8 psv2_index[0x18];
6015 u8 reserved_at_e0[0x8];
6016 u8 psv3_index[0x18];
6019 struct mlx5_ifc_create_psv_in_bits {
6021 u8 reserved_at_10[0x10];
6023 u8 reserved_at_20[0x10];
6027 u8 reserved_at_44[0x4];
6030 u8 reserved_at_60[0x20];
6033 struct mlx5_ifc_create_mkey_out_bits {
6035 u8 reserved_at_8[0x18];
6039 u8 reserved_at_40[0x8];
6040 u8 mkey_index[0x18];
6042 u8 reserved_at_60[0x20];
6045 struct mlx5_ifc_create_mkey_in_bits {
6047 u8 reserved_at_10[0x10];
6049 u8 reserved_at_20[0x10];
6052 u8 reserved_at_40[0x20];
6055 u8 reserved_at_61[0x1f];
6057 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6059 u8 reserved_at_280[0x80];
6061 u8 translations_octword_actual_size[0x20];
6063 u8 reserved_at_320[0x560];
6065 u8 klm_pas_mtt[0][0x20];
6068 struct mlx5_ifc_create_flow_table_out_bits {
6070 u8 reserved_at_8[0x18];
6074 u8 reserved_at_40[0x8];
6077 u8 reserved_at_60[0x20];
6080 struct mlx5_ifc_create_flow_table_in_bits {
6082 u8 reserved_at_10[0x10];
6084 u8 reserved_at_20[0x10];
6087 u8 other_vport[0x1];
6088 u8 reserved_at_41[0xf];
6089 u8 vport_number[0x10];
6091 u8 reserved_at_60[0x20];
6094 u8 reserved_at_88[0x18];
6096 u8 reserved_at_a0[0x20];
6098 u8 reserved_at_c0[0x4];
6099 u8 table_miss_mode[0x4];
6101 u8 reserved_at_d0[0x8];
6104 u8 reserved_at_e0[0x8];
6105 u8 table_miss_id[0x18];
6107 u8 reserved_at_100[0x100];
6110 struct mlx5_ifc_create_flow_group_out_bits {
6112 u8 reserved_at_8[0x18];
6116 u8 reserved_at_40[0x8];
6119 u8 reserved_at_60[0x20];
6123 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6124 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6125 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6128 struct mlx5_ifc_create_flow_group_in_bits {
6130 u8 reserved_at_10[0x10];
6132 u8 reserved_at_20[0x10];
6135 u8 other_vport[0x1];
6136 u8 reserved_at_41[0xf];
6137 u8 vport_number[0x10];
6139 u8 reserved_at_60[0x20];
6142 u8 reserved_at_88[0x18];
6144 u8 reserved_at_a0[0x8];
6147 u8 reserved_at_c0[0x20];
6149 u8 start_flow_index[0x20];
6151 u8 reserved_at_100[0x20];
6153 u8 end_flow_index[0x20];
6155 u8 reserved_at_140[0xa0];
6157 u8 reserved_at_1e0[0x18];
6158 u8 match_criteria_enable[0x8];
6160 struct mlx5_ifc_fte_match_param_bits match_criteria;
6162 u8 reserved_at_1200[0xe00];
6165 struct mlx5_ifc_create_eq_out_bits {
6167 u8 reserved_at_8[0x18];
6171 u8 reserved_at_40[0x18];
6174 u8 reserved_at_60[0x20];
6177 struct mlx5_ifc_create_eq_in_bits {
6179 u8 reserved_at_10[0x10];
6181 u8 reserved_at_20[0x10];
6184 u8 reserved_at_40[0x40];
6186 struct mlx5_ifc_eqc_bits eq_context_entry;
6188 u8 reserved_at_280[0x40];
6190 u8 event_bitmask[0x40];
6192 u8 reserved_at_300[0x580];
6197 struct mlx5_ifc_create_dct_out_bits {
6199 u8 reserved_at_8[0x18];
6203 u8 reserved_at_40[0x8];
6206 u8 reserved_at_60[0x20];
6209 struct mlx5_ifc_create_dct_in_bits {
6211 u8 reserved_at_10[0x10];
6213 u8 reserved_at_20[0x10];
6216 u8 reserved_at_40[0x40];
6218 struct mlx5_ifc_dctc_bits dct_context_entry;
6220 u8 reserved_at_280[0x180];
6223 struct mlx5_ifc_create_cq_out_bits {
6225 u8 reserved_at_8[0x18];
6229 u8 reserved_at_40[0x8];
6232 u8 reserved_at_60[0x20];
6235 struct mlx5_ifc_create_cq_in_bits {
6237 u8 reserved_at_10[0x10];
6239 u8 reserved_at_20[0x10];
6242 u8 reserved_at_40[0x40];
6244 struct mlx5_ifc_cqc_bits cq_context;
6246 u8 reserved_at_280[0x600];
6251 struct mlx5_ifc_config_int_moderation_out_bits {
6253 u8 reserved_at_8[0x18];
6257 u8 reserved_at_40[0x4];
6259 u8 int_vector[0x10];
6261 u8 reserved_at_60[0x20];
6265 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6266 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6269 struct mlx5_ifc_config_int_moderation_in_bits {
6271 u8 reserved_at_10[0x10];
6273 u8 reserved_at_20[0x10];
6276 u8 reserved_at_40[0x4];
6278 u8 int_vector[0x10];
6280 u8 reserved_at_60[0x20];
6283 struct mlx5_ifc_attach_to_mcg_out_bits {
6285 u8 reserved_at_8[0x18];
6289 u8 reserved_at_40[0x40];
6292 struct mlx5_ifc_attach_to_mcg_in_bits {
6294 u8 reserved_at_10[0x10];
6296 u8 reserved_at_20[0x10];
6299 u8 reserved_at_40[0x8];
6302 u8 reserved_at_60[0x20];
6304 u8 multicast_gid[16][0x8];
6307 struct mlx5_ifc_arm_xrq_out_bits {
6309 u8 reserved_at_8[0x18];
6313 u8 reserved_at_40[0x40];
6316 struct mlx5_ifc_arm_xrq_in_bits {
6318 u8 reserved_at_10[0x10];
6320 u8 reserved_at_20[0x10];
6323 u8 reserved_at_40[0x8];
6326 u8 reserved_at_60[0x10];
6330 struct mlx5_ifc_arm_xrc_srq_out_bits {
6332 u8 reserved_at_8[0x18];
6336 u8 reserved_at_40[0x40];
6340 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6343 struct mlx5_ifc_arm_xrc_srq_in_bits {
6345 u8 reserved_at_10[0x10];
6347 u8 reserved_at_20[0x10];
6350 u8 reserved_at_40[0x8];
6353 u8 reserved_at_60[0x10];
6357 struct mlx5_ifc_arm_rq_out_bits {
6359 u8 reserved_at_8[0x18];
6363 u8 reserved_at_40[0x40];
6367 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6368 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6371 struct mlx5_ifc_arm_rq_in_bits {
6373 u8 reserved_at_10[0x10];
6375 u8 reserved_at_20[0x10];
6378 u8 reserved_at_40[0x8];
6379 u8 srq_number[0x18];
6381 u8 reserved_at_60[0x10];
6385 struct mlx5_ifc_arm_dct_out_bits {
6387 u8 reserved_at_8[0x18];
6391 u8 reserved_at_40[0x40];
6394 struct mlx5_ifc_arm_dct_in_bits {
6396 u8 reserved_at_10[0x10];
6398 u8 reserved_at_20[0x10];
6401 u8 reserved_at_40[0x8];
6402 u8 dct_number[0x18];
6404 u8 reserved_at_60[0x20];
6407 struct mlx5_ifc_alloc_xrcd_out_bits {
6409 u8 reserved_at_8[0x18];
6413 u8 reserved_at_40[0x8];
6416 u8 reserved_at_60[0x20];
6419 struct mlx5_ifc_alloc_xrcd_in_bits {
6421 u8 reserved_at_10[0x10];
6423 u8 reserved_at_20[0x10];
6426 u8 reserved_at_40[0x40];
6429 struct mlx5_ifc_alloc_uar_out_bits {
6431 u8 reserved_at_8[0x18];
6435 u8 reserved_at_40[0x8];
6438 u8 reserved_at_60[0x20];
6441 struct mlx5_ifc_alloc_uar_in_bits {
6443 u8 reserved_at_10[0x10];
6445 u8 reserved_at_20[0x10];
6448 u8 reserved_at_40[0x40];
6451 struct mlx5_ifc_alloc_transport_domain_out_bits {
6453 u8 reserved_at_8[0x18];
6457 u8 reserved_at_40[0x8];
6458 u8 transport_domain[0x18];
6460 u8 reserved_at_60[0x20];
6463 struct mlx5_ifc_alloc_transport_domain_in_bits {
6465 u8 reserved_at_10[0x10];
6467 u8 reserved_at_20[0x10];
6470 u8 reserved_at_40[0x40];
6473 struct mlx5_ifc_alloc_q_counter_out_bits {
6475 u8 reserved_at_8[0x18];
6479 u8 reserved_at_40[0x18];
6480 u8 counter_set_id[0x8];
6482 u8 reserved_at_60[0x20];
6485 struct mlx5_ifc_alloc_q_counter_in_bits {
6487 u8 reserved_at_10[0x10];
6489 u8 reserved_at_20[0x10];
6492 u8 reserved_at_40[0x40];
6495 struct mlx5_ifc_alloc_pd_out_bits {
6497 u8 reserved_at_8[0x18];
6501 u8 reserved_at_40[0x8];
6504 u8 reserved_at_60[0x20];
6507 struct mlx5_ifc_alloc_pd_in_bits {
6509 u8 reserved_at_10[0x10];
6511 u8 reserved_at_20[0x10];
6514 u8 reserved_at_40[0x40];
6517 struct mlx5_ifc_alloc_flow_counter_out_bits {
6519 u8 reserved_at_8[0x18];
6523 u8 reserved_at_40[0x10];
6524 u8 flow_counter_id[0x10];
6526 u8 reserved_at_60[0x20];
6529 struct mlx5_ifc_alloc_flow_counter_in_bits {
6531 u8 reserved_at_10[0x10];
6533 u8 reserved_at_20[0x10];
6536 u8 reserved_at_40[0x40];
6539 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6541 u8 reserved_at_8[0x18];
6545 u8 reserved_at_40[0x40];
6548 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6550 u8 reserved_at_10[0x10];
6552 u8 reserved_at_20[0x10];
6555 u8 reserved_at_40[0x20];
6557 u8 reserved_at_60[0x10];
6558 u8 vxlan_udp_port[0x10];
6561 struct mlx5_ifc_set_rate_limit_out_bits {
6563 u8 reserved_at_8[0x18];
6567 u8 reserved_at_40[0x40];
6570 struct mlx5_ifc_set_rate_limit_in_bits {
6572 u8 reserved_at_10[0x10];
6574 u8 reserved_at_20[0x10];
6577 u8 reserved_at_40[0x10];
6578 u8 rate_limit_index[0x10];
6580 u8 reserved_at_60[0x20];
6582 u8 rate_limit[0x20];
6585 struct mlx5_ifc_access_register_out_bits {
6587 u8 reserved_at_8[0x18];
6591 u8 reserved_at_40[0x40];
6593 u8 register_data[0][0x20];
6597 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6598 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6601 struct mlx5_ifc_access_register_in_bits {
6603 u8 reserved_at_10[0x10];
6605 u8 reserved_at_20[0x10];
6608 u8 reserved_at_40[0x10];
6609 u8 register_id[0x10];
6613 u8 register_data[0][0x20];
6616 struct mlx5_ifc_sltp_reg_bits {
6621 u8 reserved_at_12[0x2];
6623 u8 reserved_at_18[0x8];
6625 u8 reserved_at_20[0x20];
6627 u8 reserved_at_40[0x7];
6633 u8 reserved_at_60[0xc];
6634 u8 ob_preemp_mode[0x4];
6638 u8 reserved_at_80[0x20];
6641 struct mlx5_ifc_slrg_reg_bits {
6646 u8 reserved_at_12[0x2];
6648 u8 reserved_at_18[0x8];
6650 u8 time_to_link_up[0x10];
6651 u8 reserved_at_30[0xc];
6652 u8 grade_lane_speed[0x4];
6654 u8 grade_version[0x8];
6657 u8 reserved_at_60[0x4];
6658 u8 height_grade_type[0x4];
6659 u8 height_grade[0x18];
6664 u8 reserved_at_a0[0x10];
6665 u8 height_sigma[0x10];
6667 u8 reserved_at_c0[0x20];
6669 u8 reserved_at_e0[0x4];
6670 u8 phase_grade_type[0x4];
6671 u8 phase_grade[0x18];
6673 u8 reserved_at_100[0x8];
6674 u8 phase_eo_pos[0x8];
6675 u8 reserved_at_110[0x8];
6676 u8 phase_eo_neg[0x8];
6678 u8 ffe_set_tested[0x10];
6679 u8 test_errors_per_lane[0x10];
6682 struct mlx5_ifc_pvlc_reg_bits {
6683 u8 reserved_at_0[0x8];
6685 u8 reserved_at_10[0x10];
6687 u8 reserved_at_20[0x1c];
6690 u8 reserved_at_40[0x1c];
6693 u8 reserved_at_60[0x1c];
6694 u8 vl_operational[0x4];
6697 struct mlx5_ifc_pude_reg_bits {
6700 u8 reserved_at_10[0x4];
6701 u8 admin_status[0x4];
6702 u8 reserved_at_18[0x4];
6703 u8 oper_status[0x4];
6705 u8 reserved_at_20[0x60];
6708 struct mlx5_ifc_ptys_reg_bits {
6709 u8 an_disable_cap[0x1];
6710 u8 an_disable_admin[0x1];
6711 u8 reserved_at_2[0x6];
6713 u8 reserved_at_10[0xd];
6717 u8 reserved_at_24[0x3c];
6719 u8 eth_proto_capability[0x20];
6721 u8 ib_link_width_capability[0x10];
6722 u8 ib_proto_capability[0x10];
6724 u8 reserved_at_a0[0x20];
6726 u8 eth_proto_admin[0x20];
6728 u8 ib_link_width_admin[0x10];
6729 u8 ib_proto_admin[0x10];
6731 u8 reserved_at_100[0x20];
6733 u8 eth_proto_oper[0x20];
6735 u8 ib_link_width_oper[0x10];
6736 u8 ib_proto_oper[0x10];
6738 u8 reserved_at_160[0x20];
6740 u8 eth_proto_lp_advertise[0x20];
6742 u8 reserved_at_1a0[0x60];
6745 struct mlx5_ifc_mlcr_reg_bits {
6746 u8 reserved_at_0[0x8];
6748 u8 reserved_at_10[0x20];
6750 u8 beacon_duration[0x10];
6751 u8 reserved_at_40[0x10];
6753 u8 beacon_remain[0x10];
6756 struct mlx5_ifc_ptas_reg_bits {
6757 u8 reserved_at_0[0x20];
6759 u8 algorithm_options[0x10];
6760 u8 reserved_at_30[0x4];
6761 u8 repetitions_mode[0x4];
6762 u8 num_of_repetitions[0x8];
6764 u8 grade_version[0x8];
6765 u8 height_grade_type[0x4];
6766 u8 phase_grade_type[0x4];
6767 u8 height_grade_weight[0x8];
6768 u8 phase_grade_weight[0x8];
6770 u8 gisim_measure_bits[0x10];
6771 u8 adaptive_tap_measure_bits[0x10];
6773 u8 ber_bath_high_error_threshold[0x10];
6774 u8 ber_bath_mid_error_threshold[0x10];
6776 u8 ber_bath_low_error_threshold[0x10];
6777 u8 one_ratio_high_threshold[0x10];
6779 u8 one_ratio_high_mid_threshold[0x10];
6780 u8 one_ratio_low_mid_threshold[0x10];
6782 u8 one_ratio_low_threshold[0x10];
6783 u8 ndeo_error_threshold[0x10];
6785 u8 mixer_offset_step_size[0x10];
6786 u8 reserved_at_110[0x8];
6787 u8 mix90_phase_for_voltage_bath[0x8];
6789 u8 mixer_offset_start[0x10];
6790 u8 mixer_offset_end[0x10];
6792 u8 reserved_at_140[0x15];
6793 u8 ber_test_time[0xb];
6796 struct mlx5_ifc_pspa_reg_bits {
6800 u8 reserved_at_18[0x8];
6802 u8 reserved_at_20[0x20];
6805 struct mlx5_ifc_pqdr_reg_bits {
6806 u8 reserved_at_0[0x8];
6808 u8 reserved_at_10[0x5];
6810 u8 reserved_at_18[0x6];
6813 u8 reserved_at_20[0x20];
6815 u8 reserved_at_40[0x10];
6816 u8 min_threshold[0x10];
6818 u8 reserved_at_60[0x10];
6819 u8 max_threshold[0x10];
6821 u8 reserved_at_80[0x10];
6822 u8 mark_probability_denominator[0x10];
6824 u8 reserved_at_a0[0x60];
6827 struct mlx5_ifc_ppsc_reg_bits {
6828 u8 reserved_at_0[0x8];
6830 u8 reserved_at_10[0x10];
6832 u8 reserved_at_20[0x60];
6834 u8 reserved_at_80[0x1c];
6837 u8 reserved_at_a0[0x1c];
6838 u8 wrps_status[0x4];
6840 u8 reserved_at_c0[0x8];
6841 u8 up_threshold[0x8];
6842 u8 reserved_at_d0[0x8];
6843 u8 down_threshold[0x8];
6845 u8 reserved_at_e0[0x20];
6847 u8 reserved_at_100[0x1c];
6850 u8 reserved_at_120[0x1c];
6851 u8 srps_status[0x4];
6853 u8 reserved_at_140[0x40];
6856 struct mlx5_ifc_pplr_reg_bits {
6857 u8 reserved_at_0[0x8];
6859 u8 reserved_at_10[0x10];
6861 u8 reserved_at_20[0x8];
6863 u8 reserved_at_30[0x8];
6867 struct mlx5_ifc_pplm_reg_bits {
6868 u8 reserved_at_0[0x8];
6870 u8 reserved_at_10[0x10];
6872 u8 reserved_at_20[0x20];
6874 u8 port_profile_mode[0x8];
6875 u8 static_port_profile[0x8];
6876 u8 active_port_profile[0x8];
6877 u8 reserved_at_58[0x8];
6879 u8 retransmission_active[0x8];
6880 u8 fec_mode_active[0x18];
6882 u8 reserved_at_80[0x20];
6885 struct mlx5_ifc_ppcnt_reg_bits {
6889 u8 reserved_at_12[0x8];
6893 u8 reserved_at_21[0x1c];
6896 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6899 struct mlx5_ifc_ppad_reg_bits {
6900 u8 reserved_at_0[0x3];
6902 u8 reserved_at_4[0x4];
6908 u8 reserved_at_40[0x40];
6911 struct mlx5_ifc_pmtu_reg_bits {
6912 u8 reserved_at_0[0x8];
6914 u8 reserved_at_10[0x10];
6917 u8 reserved_at_30[0x10];
6920 u8 reserved_at_50[0x10];
6923 u8 reserved_at_70[0x10];
6926 struct mlx5_ifc_pmpr_reg_bits {
6927 u8 reserved_at_0[0x8];
6929 u8 reserved_at_10[0x10];
6931 u8 reserved_at_20[0x18];
6932 u8 attenuation_5g[0x8];
6934 u8 reserved_at_40[0x18];
6935 u8 attenuation_7g[0x8];
6937 u8 reserved_at_60[0x18];
6938 u8 attenuation_12g[0x8];
6941 struct mlx5_ifc_pmpe_reg_bits {
6942 u8 reserved_at_0[0x8];
6944 u8 reserved_at_10[0xc];
6945 u8 module_status[0x4];
6947 u8 reserved_at_20[0x60];
6950 struct mlx5_ifc_pmpc_reg_bits {
6951 u8 module_state_updated[32][0x8];
6954 struct mlx5_ifc_pmlpn_reg_bits {
6955 u8 reserved_at_0[0x4];
6956 u8 mlpn_status[0x4];
6958 u8 reserved_at_10[0x10];
6961 u8 reserved_at_21[0x1f];
6964 struct mlx5_ifc_pmlp_reg_bits {
6966 u8 reserved_at_1[0x7];
6968 u8 reserved_at_10[0x8];
6971 u8 lane0_module_mapping[0x20];
6973 u8 lane1_module_mapping[0x20];
6975 u8 lane2_module_mapping[0x20];
6977 u8 lane3_module_mapping[0x20];
6979 u8 reserved_at_a0[0x160];
6982 struct mlx5_ifc_pmaos_reg_bits {
6983 u8 reserved_at_0[0x8];
6985 u8 reserved_at_10[0x4];
6986 u8 admin_status[0x4];
6987 u8 reserved_at_18[0x4];
6988 u8 oper_status[0x4];
6992 u8 reserved_at_22[0x1c];
6995 u8 reserved_at_40[0x40];
6998 struct mlx5_ifc_plpc_reg_bits {
6999 u8 reserved_at_0[0x4];
7001 u8 reserved_at_10[0x4];
7003 u8 reserved_at_18[0x8];
7005 u8 reserved_at_20[0x10];
7006 u8 lane_speed[0x10];
7008 u8 reserved_at_40[0x17];
7010 u8 fec_mode_policy[0x8];
7012 u8 retransmission_capability[0x8];
7013 u8 fec_mode_capability[0x18];
7015 u8 retransmission_support_admin[0x8];
7016 u8 fec_mode_support_admin[0x18];
7018 u8 retransmission_request_admin[0x8];
7019 u8 fec_mode_request_admin[0x18];
7021 u8 reserved_at_c0[0x80];
7024 struct mlx5_ifc_plib_reg_bits {
7025 u8 reserved_at_0[0x8];
7027 u8 reserved_at_10[0x8];
7030 u8 reserved_at_20[0x60];
7033 struct mlx5_ifc_plbf_reg_bits {
7034 u8 reserved_at_0[0x8];
7036 u8 reserved_at_10[0xd];
7039 u8 reserved_at_20[0x20];
7042 struct mlx5_ifc_pipg_reg_bits {
7043 u8 reserved_at_0[0x8];
7045 u8 reserved_at_10[0x10];
7048 u8 reserved_at_21[0x19];
7050 u8 reserved_at_3e[0x2];
7053 struct mlx5_ifc_pifr_reg_bits {
7054 u8 reserved_at_0[0x8];
7056 u8 reserved_at_10[0x10];
7058 u8 reserved_at_20[0xe0];
7060 u8 port_filter[8][0x20];
7062 u8 port_filter_update_en[8][0x20];
7065 struct mlx5_ifc_pfcc_reg_bits {
7066 u8 reserved_at_0[0x8];
7068 u8 reserved_at_10[0x10];
7071 u8 reserved_at_24[0x4];
7072 u8 prio_mask_tx[0x8];
7073 u8 reserved_at_30[0x8];
7074 u8 prio_mask_rx[0x8];
7078 u8 reserved_at_42[0x6];
7080 u8 reserved_at_50[0x10];
7084 u8 reserved_at_62[0x6];
7086 u8 reserved_at_70[0x10];
7088 u8 reserved_at_80[0x80];
7091 struct mlx5_ifc_pelc_reg_bits {
7093 u8 reserved_at_4[0x4];
7095 u8 reserved_at_10[0x10];
7098 u8 op_capability[0x8];
7104 u8 capability[0x40];
7110 u8 reserved_at_140[0x80];
7113 struct mlx5_ifc_peir_reg_bits {
7114 u8 reserved_at_0[0x8];
7116 u8 reserved_at_10[0x10];
7118 u8 reserved_at_20[0xc];
7119 u8 error_count[0x4];
7120 u8 reserved_at_30[0x10];
7122 u8 reserved_at_40[0xc];
7124 u8 reserved_at_50[0x8];
7128 struct mlx5_ifc_pcap_reg_bits {
7129 u8 reserved_at_0[0x8];
7131 u8 reserved_at_10[0x10];
7133 u8 port_capability_mask[4][0x20];
7136 struct mlx5_ifc_paos_reg_bits {
7139 u8 reserved_at_10[0x4];
7140 u8 admin_status[0x4];
7141 u8 reserved_at_18[0x4];
7142 u8 oper_status[0x4];
7146 u8 reserved_at_22[0x1c];
7149 u8 reserved_at_40[0x40];
7152 struct mlx5_ifc_pamp_reg_bits {
7153 u8 reserved_at_0[0x8];
7154 u8 opamp_group[0x8];
7155 u8 reserved_at_10[0xc];
7156 u8 opamp_group_type[0x4];
7158 u8 start_index[0x10];
7159 u8 reserved_at_30[0x4];
7160 u8 num_of_indices[0xc];
7162 u8 index_data[18][0x10];
7165 struct mlx5_ifc_pcmr_reg_bits {
7166 u8 reserved_at_0[0x8];
7168 u8 reserved_at_10[0x2e];
7170 u8 reserved_at_3f[0x1f];
7172 u8 reserved_at_5f[0x1];
7175 struct mlx5_ifc_lane_2_module_mapping_bits {
7176 u8 reserved_at_0[0x6];
7178 u8 reserved_at_8[0x6];
7180 u8 reserved_at_10[0x8];
7184 struct mlx5_ifc_bufferx_reg_bits {
7185 u8 reserved_at_0[0x6];
7188 u8 reserved_at_8[0xc];
7191 u8 xoff_threshold[0x10];
7192 u8 xon_threshold[0x10];
7195 struct mlx5_ifc_set_node_in_bits {
7196 u8 node_description[64][0x8];
7199 struct mlx5_ifc_register_power_settings_bits {
7200 u8 reserved_at_0[0x18];
7201 u8 power_settings_level[0x8];
7203 u8 reserved_at_20[0x60];
7206 struct mlx5_ifc_register_host_endianness_bits {
7208 u8 reserved_at_1[0x1f];
7210 u8 reserved_at_20[0x60];
7213 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7214 u8 reserved_at_0[0x20];
7218 u8 addressh_63_32[0x20];
7220 u8 addressl_31_0[0x20];
7223 struct mlx5_ifc_ud_adrs_vector_bits {
7227 u8 reserved_at_41[0x7];
7228 u8 destination_qp_dct[0x18];
7230 u8 static_rate[0x4];
7231 u8 sl_eth_prio[0x4];
7234 u8 rlid_udp_sport[0x10];
7236 u8 reserved_at_80[0x20];
7238 u8 rmac_47_16[0x20];
7244 u8 reserved_at_e0[0x1];
7246 u8 reserved_at_e2[0x2];
7247 u8 src_addr_index[0x8];
7248 u8 flow_label[0x14];
7250 u8 rgid_rip[16][0x8];
7253 struct mlx5_ifc_pages_req_event_bits {
7254 u8 reserved_at_0[0x10];
7255 u8 function_id[0x10];
7259 u8 reserved_at_40[0xa0];
7262 struct mlx5_ifc_eqe_bits {
7263 u8 reserved_at_0[0x8];
7265 u8 reserved_at_10[0x8];
7266 u8 event_sub_type[0x8];
7268 u8 reserved_at_20[0xe0];
7270 union mlx5_ifc_event_auto_bits event_data;
7272 u8 reserved_at_1e0[0x10];
7274 u8 reserved_at_1f8[0x7];
7279 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7282 struct mlx5_ifc_cmd_queue_entry_bits {
7284 u8 reserved_at_8[0x18];
7286 u8 input_length[0x20];
7288 u8 input_mailbox_pointer_63_32[0x20];
7290 u8 input_mailbox_pointer_31_9[0x17];
7291 u8 reserved_at_77[0x9];
7293 u8 command_input_inline_data[16][0x8];
7295 u8 command_output_inline_data[16][0x8];
7297 u8 output_mailbox_pointer_63_32[0x20];
7299 u8 output_mailbox_pointer_31_9[0x17];
7300 u8 reserved_at_1b7[0x9];
7302 u8 output_length[0x20];
7306 u8 reserved_at_1f0[0x8];
7311 struct mlx5_ifc_cmd_out_bits {
7313 u8 reserved_at_8[0x18];
7317 u8 command_output[0x20];
7320 struct mlx5_ifc_cmd_in_bits {
7322 u8 reserved_at_10[0x10];
7324 u8 reserved_at_20[0x10];
7327 u8 command[0][0x20];
7330 struct mlx5_ifc_cmd_if_box_bits {
7331 u8 mailbox_data[512][0x8];
7333 u8 reserved_at_1000[0x180];
7335 u8 next_pointer_63_32[0x20];
7337 u8 next_pointer_31_10[0x16];
7338 u8 reserved_at_11b6[0xa];
7340 u8 block_number[0x20];
7342 u8 reserved_at_11e0[0x8];
7344 u8 ctrl_signature[0x8];
7348 struct mlx5_ifc_mtt_bits {
7349 u8 ptag_63_32[0x20];
7352 u8 reserved_at_38[0x6];
7357 struct mlx5_ifc_query_wol_rol_out_bits {
7359 u8 reserved_at_8[0x18];
7363 u8 reserved_at_40[0x10];
7367 u8 reserved_at_60[0x20];
7370 struct mlx5_ifc_query_wol_rol_in_bits {
7372 u8 reserved_at_10[0x10];
7374 u8 reserved_at_20[0x10];
7377 u8 reserved_at_40[0x40];
7380 struct mlx5_ifc_set_wol_rol_out_bits {
7382 u8 reserved_at_8[0x18];
7386 u8 reserved_at_40[0x40];
7389 struct mlx5_ifc_set_wol_rol_in_bits {
7391 u8 reserved_at_10[0x10];
7393 u8 reserved_at_20[0x10];
7396 u8 rol_mode_valid[0x1];
7397 u8 wol_mode_valid[0x1];
7398 u8 reserved_at_42[0xe];
7402 u8 reserved_at_60[0x20];
7406 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7407 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7408 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7412 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7413 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7414 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7427 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7428 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7431 struct mlx5_ifc_initial_seg_bits {
7432 u8 fw_rev_minor[0x10];
7433 u8 fw_rev_major[0x10];
7435 u8 cmd_interface_rev[0x10];
7436 u8 fw_rev_subminor[0x10];
7438 u8 reserved_at_40[0x40];
7440 u8 cmdq_phy_addr_63_32[0x20];
7442 u8 cmdq_phy_addr_31_12[0x14];
7443 u8 reserved_at_b4[0x2];
7444 u8 nic_interface[0x2];
7445 u8 log_cmdq_size[0x4];
7446 u8 log_cmdq_stride[0x4];
7448 u8 command_doorbell_vector[0x20];
7450 u8 reserved_at_e0[0xf00];
7452 u8 initializing[0x1];
7453 u8 reserved_at_fe1[0x4];
7454 u8 nic_interface_supported[0x3];
7455 u8 reserved_at_fe8[0x18];
7457 struct mlx5_ifc_health_buffer_bits health_buffer;
7459 u8 no_dram_nic_offset[0x20];
7461 u8 reserved_at_1220[0x6e40];
7463 u8 reserved_at_8060[0x1f];
7466 u8 health_syndrome[0x8];
7467 u8 health_counter[0x18];
7469 u8 reserved_at_80a0[0x17fc0];
7472 union mlx5_ifc_ports_control_registers_document_bits {
7473 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7474 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7475 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7476 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7477 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7478 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7479 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7480 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7481 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7482 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7483 struct mlx5_ifc_paos_reg_bits paos_reg;
7484 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7485 struct mlx5_ifc_peir_reg_bits peir_reg;
7486 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7487 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7488 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7489 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7490 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7491 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7492 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7493 struct mlx5_ifc_plib_reg_bits plib_reg;
7494 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7495 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7496 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7497 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7498 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7499 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7500 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7501 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7502 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7503 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7504 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7505 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7506 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7507 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7508 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7509 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7510 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7511 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7512 struct mlx5_ifc_pude_reg_bits pude_reg;
7513 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7514 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7515 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7516 u8 reserved_at_0[0x60e0];
7519 union mlx5_ifc_debug_enhancements_document_bits {
7520 struct mlx5_ifc_health_buffer_bits health_buffer;
7521 u8 reserved_at_0[0x200];
7524 union mlx5_ifc_uplink_pci_interface_document_bits {
7525 struct mlx5_ifc_initial_seg_bits initial_seg;
7526 u8 reserved_at_0[0x20060];
7529 struct mlx5_ifc_set_flow_table_root_out_bits {
7531 u8 reserved_at_8[0x18];
7535 u8 reserved_at_40[0x40];
7538 struct mlx5_ifc_set_flow_table_root_in_bits {
7540 u8 reserved_at_10[0x10];
7542 u8 reserved_at_20[0x10];
7545 u8 other_vport[0x1];
7546 u8 reserved_at_41[0xf];
7547 u8 vport_number[0x10];
7549 u8 reserved_at_60[0x20];
7552 u8 reserved_at_88[0x18];
7554 u8 reserved_at_a0[0x8];
7557 u8 reserved_at_c0[0x140];
7561 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7564 struct mlx5_ifc_modify_flow_table_out_bits {
7566 u8 reserved_at_8[0x18];
7570 u8 reserved_at_40[0x40];
7573 struct mlx5_ifc_modify_flow_table_in_bits {
7575 u8 reserved_at_10[0x10];
7577 u8 reserved_at_20[0x10];
7580 u8 other_vport[0x1];
7581 u8 reserved_at_41[0xf];
7582 u8 vport_number[0x10];
7584 u8 reserved_at_60[0x10];
7585 u8 modify_field_select[0x10];
7588 u8 reserved_at_88[0x18];
7590 u8 reserved_at_a0[0x8];
7593 u8 reserved_at_c0[0x4];
7594 u8 table_miss_mode[0x4];
7595 u8 reserved_at_c8[0x18];
7597 u8 reserved_at_e0[0x8];
7598 u8 table_miss_id[0x18];
7600 u8 reserved_at_100[0x100];
7603 struct mlx5_ifc_ets_tcn_config_reg_bits {
7607 u8 reserved_at_3[0x9];
7609 u8 reserved_at_10[0x9];
7610 u8 bw_allocation[0x7];
7612 u8 reserved_at_20[0xc];
7613 u8 max_bw_units[0x4];
7614 u8 reserved_at_30[0x8];
7615 u8 max_bw_value[0x8];
7618 struct mlx5_ifc_ets_global_config_reg_bits {
7619 u8 reserved_at_0[0x2];
7621 u8 reserved_at_3[0x1d];
7623 u8 reserved_at_20[0xc];
7624 u8 max_bw_units[0x4];
7625 u8 reserved_at_30[0x8];
7626 u8 max_bw_value[0x8];
7629 struct mlx5_ifc_qetc_reg_bits {
7630 u8 reserved_at_0[0x8];
7631 u8 port_number[0x8];
7632 u8 reserved_at_10[0x30];
7634 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7635 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7638 struct mlx5_ifc_qtct_reg_bits {
7639 u8 reserved_at_0[0x8];
7640 u8 port_number[0x8];
7641 u8 reserved_at_10[0xd];
7644 u8 reserved_at_20[0x1d];
7648 struct mlx5_ifc_mcia_reg_bits {
7650 u8 reserved_at_1[0x7];
7652 u8 reserved_at_10[0x8];
7655 u8 i2c_device_address[0x8];
7656 u8 page_number[0x8];
7657 u8 device_address[0x10];
7659 u8 reserved_at_40[0x10];
7662 u8 reserved_at_60[0x20];
7678 struct mlx5_ifc_dcbx_param_bits {
7679 u8 dcbx_cee_cap[0x1];
7680 u8 dcbx_ieee_cap[0x1];
7681 u8 dcbx_standby_cap[0x1];
7682 u8 reserved_at_0[0x5];
7683 u8 port_number[0x8];
7684 u8 reserved_at_10[0xa];
7685 u8 max_application_table_size[6];
7686 u8 reserved_at_20[0x15];
7687 u8 version_oper[0x3];
7688 u8 reserved_at_38[5];
7689 u8 version_admin[0x3];
7690 u8 willing_admin[0x1];
7691 u8 reserved_at_41[0x3];
7692 u8 pfc_cap_oper[0x4];
7693 u8 reserved_at_48[0x4];
7694 u8 pfc_cap_admin[0x4];
7695 u8 reserved_at_50[0x4];
7696 u8 num_of_tc_oper[0x4];
7697 u8 reserved_at_58[0x4];
7698 u8 num_of_tc_admin[0x4];
7699 u8 remote_willing[0x1];
7700 u8 reserved_at_61[3];
7701 u8 remote_pfc_cap[4];
7702 u8 reserved_at_68[0x14];
7703 u8 remote_num_of_tc[0x4];
7704 u8 reserved_at_80[0x18];
7706 u8 reserved_at_a0[0x160];
7708 #endif /* MLX5_IFC_H */