include/uapi/linux/v4l2-dv-timings.h

   1 /*
   2  * V4L2 DV timings header.
   3  *
   4  * Copyright (C) 2012  Hans Verkuil <hans.verkuil@cisco.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  */
  20
  21 #ifndef _V4L2_DV_TIMINGS_H
  22 #define _V4L2_DV_TIMINGS_H
  23
  24 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  25         { .bt = { _width , ## args } }
  26
  27 /* CEA-861-E timings (i.e. standard HDTV timings) */
  28
  29 #define V4L2_DV_BT_CEA_640X480P59_94 { \
  30         .type = V4L2_DV_BT_656_1120, \
  31         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  32                 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
  33                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, 0) \
  34 }
  35
  36 /* Note: these are the nominal timings, for HDMI links this format is typically
  37  * double-clocked to meet the minimum pixelclock requirements.  */
  38 #define V4L2_DV_BT_CEA_720X480I59_94 { \
  39         .type = V4L2_DV_BT_656_1120, \
  40         V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
  41                 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
  42                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
  43 }
  44
  45 #define V4L2_DV_BT_CEA_720X480P59_94 { \
  46         .type = V4L2_DV_BT_656_1120, \
  47         V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
  48                 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
  49                 V4L2_DV_BT_STD_CEA861, 0) \
  50 }
  51
  52 /* Note: these are the nominal timings, for HDMI links this format is typically
  53  * double-clocked to meet the minimum pixelclock requirements.  */
  54 #define V4L2_DV_BT_CEA_720X576I50 { \
  55         .type = V4L2_DV_BT_656_1120, \
  56         V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
  57                 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
  58                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
  59 }
  60
  61 #define V4L2_DV_BT_CEA_720X576P50 { \
  62         .type = V4L2_DV_BT_656_1120, \
  63         V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
  64                 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
  65                 V4L2_DV_BT_STD_CEA861, 0) \
  66 }
  67
  68 #define V4L2_DV_BT_CEA_1280X720P24 { \
  69         .type = V4L2_DV_BT_656_1120, \
  70         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  71                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  72                 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  73                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  74                 V4L2_DV_FL_CAN_REDUCE_FPS) \
  75 }
  76
  77 #define V4L2_DV_BT_CEA_1280X720P25 { \
  78         .type = V4L2_DV_BT_656_1120, \
  79         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  80                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  81                 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
  82                 V4L2_DV_BT_STD_CEA861, 0) \
  83 }
  84
  85 #define V4L2_DV_BT_CEA_1280X720P30 { \
  86         .type = V4L2_DV_BT_656_1120, \
  87         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  88                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  89                 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  90                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
  91 }
  92
  93 #define V4L2_DV_BT_CEA_1280X720P50 { \
  94         .type = V4L2_DV_BT_656_1120, \
  95         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  96                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  97                 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
  98                 V4L2_DV_BT_STD_CEA861, 0) \
  99 }
 100
 101 #define V4L2_DV_BT_CEA_1280X720P60 { \
 102         .type = V4L2_DV_BT_656_1120, \
 103         V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
 104                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 105                 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
 106                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 107 }
 108
 109 #define V4L2_DV_BT_CEA_1920X1080P24 { \
 110         .type = V4L2_DV_BT_656_1120, \
 111         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 112                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 113                 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
 114                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 115 }
 116
 117 #define V4L2_DV_BT_CEA_1920X1080P25 { \
 118         .type = V4L2_DV_BT_656_1120, \
 119         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 120                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 121                 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
 122                 V4L2_DV_BT_STD_CEA861, 0) \
 123 }
 124
 125 #define V4L2_DV_BT_CEA_1920X1080P30 { \
 126         .type = V4L2_DV_BT_656_1120, \
 127         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 128                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 129                 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
 130                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 131 }
 132
 133 #define V4L2_DV_BT_CEA_1920X1080I50 { \
 134         .type = V4L2_DV_BT_656_1120, \
 135         V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
 136                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 137                 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
 138                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_HALF_LINE) \
 139 }
 140
 141 #define V4L2_DV_BT_CEA_1920X1080P50 { \
 142         .type = V4L2_DV_BT_656_1120, \
 143         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 144                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 145                 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
 146                 V4L2_DV_BT_STD_CEA861, 0) \
 147 }
 148
 149 #define V4L2_DV_BT_CEA_1920X1080I60 { \
 150         .type = V4L2_DV_BT_656_1120, \
 151         V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
 152                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 153                 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
 154                 V4L2_DV_BT_STD_CEA861, \
 155                 V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HALF_LINE) \
 156 }
 157
 158 #define V4L2_DV_BT_CEA_1920X1080P60 { \
 159         .type = V4L2_DV_BT_656_1120, \
 160         V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
 161                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 162                 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
 163                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
 164                 V4L2_DV_FL_CAN_REDUCE_FPS) \
 165 }
 166
 167 #define V4L2_DV_BT_CEA_3840X2160P24 { \
 168         .type = V4L2_DV_BT_656_1120, \
 169         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 170                 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
 171                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 172 }
 173
 174 #define V4L2_DV_BT_CEA_3840X2160P25 { \
 175         .type = V4L2_DV_BT_656_1120, \
 176         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 177                 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
 178                 V4L2_DV_BT_STD_CEA861, 0) \
 179 }
 180
 181 #define V4L2_DV_BT_CEA_3840X2160P30 { \
 182         .type = V4L2_DV_BT_656_1120, \
 183         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 184                 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
 185                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 186 }
 187
 188 #define V4L2_DV_BT_CEA_3840X2160P50 { \
 189         .type = V4L2_DV_BT_656_1120, \
 190         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 191                 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
 192                 V4L2_DV_BT_STD_CEA861, 0) \
 193 }
 194
 195 #define V4L2_DV_BT_CEA_3840X2160P60 { \
 196         .type = V4L2_DV_BT_656_1120, \
 197         V4L2_INIT_BT_TIMINGS(3840, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 198                 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
 199                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 200 }
 201
 202 #define V4L2_DV_BT_CEA_4096X2160P24 { \
 203         .type = V4L2_DV_BT_656_1120, \
 204         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 205                 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
 206                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 207 }
 208
 209 #define V4L2_DV_BT_CEA_4096X2160P25 { \
 210         .type = V4L2_DV_BT_656_1120, \
 211         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 212                 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
 213                 V4L2_DV_BT_STD_CEA861, 0) \
 214 }
 215
 216 #define V4L2_DV_BT_CEA_4096X2160P30 { \
 217         .type = V4L2_DV_BT_656_1120, \
 218         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 219                 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
 220                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 221 }
 222
 223 #define V4L2_DV_BT_CEA_4096X2160P50 { \
 224         .type = V4L2_DV_BT_656_1120, \
 225         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 226                 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
 227                 V4L2_DV_BT_STD_CEA861, 0) \
 228 }
 229
 230 #define V4L2_DV_BT_CEA_4096X2160P60 { \
 231         .type = V4L2_DV_BT_656_1120, \
 232         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 233                 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
 234                 V4L2_DV_BT_STD_CEA861, V4L2_DV_FL_CAN_REDUCE_FPS) \
 235 }
 236
 237
 238 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
 239
 240 #define V4L2_DV_BT_DMT_640X350P85 { \
 241         .type = V4L2_DV_BT_656_1120, \
 242         V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
 243                 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
 244                 V4L2_DV_BT_STD_DMT, 0) \
 245 }
 246
 247 #define V4L2_DV_BT_DMT_640X400P85 { \
 248         .type = V4L2_DV_BT_656_1120, \
 249         V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
 250                 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
 251                 V4L2_DV_BT_STD_DMT, 0) \
 252 }
 253
 254 #define V4L2_DV_BT_DMT_720X400P85 { \
 255         .type = V4L2_DV_BT_656_1120, \
 256         V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
 257                 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
 258                 V4L2_DV_BT_STD_DMT, 0) \
 259 }
 260
 261 /* VGA resolutions */
 262 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
 263
 264 #define V4L2_DV_BT_DMT_640X480P72 { \
 265         .type = V4L2_DV_BT_656_1120, \
 266         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 267                 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
 268                 V4L2_DV_BT_STD_DMT, 0) \
 269 }
 270
 271 #define V4L2_DV_BT_DMT_640X480P75 { \
 272         .type = V4L2_DV_BT_656_1120, \
 273         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 274                 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
 275                 V4L2_DV_BT_STD_DMT, 0) \
 276 }
 277
 278 #define V4L2_DV_BT_DMT_640X480P85 { \
 279         .type = V4L2_DV_BT_656_1120, \
 280         V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
 281                 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
 282                 V4L2_DV_BT_STD_DMT, 0) \
 283 }
 284
 285 /* SVGA resolutions */
 286 #define V4L2_DV_BT_DMT_800X600P56 { \
 287         .type = V4L2_DV_BT_656_1120, \
 288         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 289                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 290                 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
 291                 V4L2_DV_BT_STD_DMT, 0) \
 292 }
 293
 294 #define V4L2_DV_BT_DMT_800X600P60 { \
 295         .type = V4L2_DV_BT_656_1120, \
 296         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 297                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 298                 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
 299                 V4L2_DV_BT_STD_DMT, 0) \
 300 }
 301
 302 #define V4L2_DV_BT_DMT_800X600P72 { \
 303         .type = V4L2_DV_BT_656_1120, \
 304         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 305                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 306                 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
 307                 V4L2_DV_BT_STD_DMT, 0) \
 308 }
 309
 310 #define V4L2_DV_BT_DMT_800X600P75 { \
 311         .type = V4L2_DV_BT_656_1120, \
 312         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 313                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 314                 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
 315                 V4L2_DV_BT_STD_DMT, 0) \
 316 }
 317
 318 #define V4L2_DV_BT_DMT_800X600P85 { \
 319         .type = V4L2_DV_BT_656_1120, \
 320         V4L2_INIT_BT_TIMINGS(800, 600, 0, \
 321                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 322                 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
 323                 V4L2_DV_BT_STD_DMT, 0) \
 324 }
 325
 326 #define V4L2_DV_BT_DMT_800X600P120_RB { \
 327         .type = V4L2_DV_BT_656_1120, \
 328         V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
 329                 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
 330                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 331                 V4L2_DV_FL_REDUCED_BLANKING) \
 332 }
 333
 334 #define V4L2_DV_BT_DMT_848X480P60 { \
 335         .type = V4L2_DV_BT_656_1120, \
 336         V4L2_INIT_BT_TIMINGS(848, 480, 0, \
 337                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 338                 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
 339                 V4L2_DV_BT_STD_DMT, 0) \
 340 }
 341
 342 #define V4L2_DV_BT_DMT_1024X768I43 { \
 343         .type = V4L2_DV_BT_656_1120, \
 344         V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
 345                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 346                 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
 347                 V4L2_DV_BT_STD_DMT, 0) \
 348 }
 349
 350 /* XGA resolutions */
 351 #define V4L2_DV_BT_DMT_1024X768P60 { \
 352         .type = V4L2_DV_BT_656_1120, \
 353         V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
 354                 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
 355                 V4L2_DV_BT_STD_DMT, 0) \
 356 }
 357
 358 #define V4L2_DV_BT_DMT_1024X768P70 { \
 359         .type = V4L2_DV_BT_656_1120, \
 360         V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
 361                 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
 362                 V4L2_DV_BT_STD_DMT, 0) \
 363 }
 364
 365 #define V4L2_DV_BT_DMT_1024X768P75 { \
 366         .type = V4L2_DV_BT_656_1120, \
 367         V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
 368                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 369                 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
 370                 V4L2_DV_BT_STD_DMT, 0) \
 371 }
 372
 373 #define V4L2_DV_BT_DMT_1024X768P85 { \
 374         .type = V4L2_DV_BT_656_1120, \
 375         V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
 376                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 377                 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
 378                 V4L2_DV_BT_STD_DMT, 0) \
 379 }
 380
 381 #define V4L2_DV_BT_DMT_1024X768P120_RB { \
 382         .type = V4L2_DV_BT_656_1120, \
 383         V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 384                 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
 385                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 386                 V4L2_DV_FL_REDUCED_BLANKING) \
 387 }
 388
 389 /* XGA+ resolution */
 390 #define V4L2_DV_BT_DMT_1152X864P75 { \
 391         .type = V4L2_DV_BT_656_1120, \
 392         V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
 393                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 394                 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
 395                 V4L2_DV_BT_STD_DMT, 0) \
 396 }
 397
 398 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
 399
 400 /* WXGA resolutions */
 401 #define V4L2_DV_BT_DMT_1280X768P60_RB { \
 402         .type = V4L2_DV_BT_656_1120, \
 403         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 404                 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
 405                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 406                 V4L2_DV_FL_REDUCED_BLANKING) \
 407 }
 408
 409 #define V4L2_DV_BT_DMT_1280X768P60 { \
 410         .type = V4L2_DV_BT_656_1120, \
 411         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 412                 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
 413                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 414 }
 415
 416 #define V4L2_DV_BT_DMT_1280X768P75 { \
 417         .type = V4L2_DV_BT_656_1120, \
 418         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 419                 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
 420                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 421 }
 422
 423 #define V4L2_DV_BT_DMT_1280X768P85 { \
 424         .type = V4L2_DV_BT_656_1120, \
 425         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
 426                 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
 427                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 428 }
 429
 430 #define V4L2_DV_BT_DMT_1280X768P120_RB { \
 431         .type = V4L2_DV_BT_656_1120, \
 432         V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 433                 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
 434                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 435                 V4L2_DV_FL_REDUCED_BLANKING) \
 436 }
 437
 438 #define V4L2_DV_BT_DMT_1280X800P60_RB { \
 439         .type = V4L2_DV_BT_656_1120, \
 440         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
 441                 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
 442                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 443                 V4L2_DV_FL_REDUCED_BLANKING) \
 444 }
 445
 446 #define V4L2_DV_BT_DMT_1280X800P60 { \
 447         .type = V4L2_DV_BT_656_1120, \
 448         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 449                 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
 450                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 451 }
 452
 453 #define V4L2_DV_BT_DMT_1280X800P75 { \
 454         .type = V4L2_DV_BT_656_1120, \
 455         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 456                 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
 457                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 458 }
 459
 460 #define V4L2_DV_BT_DMT_1280X800P85 { \
 461         .type = V4L2_DV_BT_656_1120, \
 462         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
 463                 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
 464                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 465 }
 466
 467 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
 468         .type = V4L2_DV_BT_656_1120, \
 469         V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
 470                 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
 471                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 472                 V4L2_DV_FL_REDUCED_BLANKING) \
 473 }
 474
 475 #define V4L2_DV_BT_DMT_1280X960P60 { \
 476         .type = V4L2_DV_BT_656_1120, \
 477         V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
 478                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 479                 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
 480                 V4L2_DV_BT_STD_DMT, 0) \
 481 }
 482
 483 #define V4L2_DV_BT_DMT_1280X960P85 { \
 484         .type = V4L2_DV_BT_656_1120, \
 485         V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
 486                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 487                 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
 488                 V4L2_DV_BT_STD_DMT, 0) \
 489 }
 490
 491 #define V4L2_DV_BT_DMT_1280X960P120_RB { \
 492         .type = V4L2_DV_BT_656_1120, \
 493         V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
 494                 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
 495                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 496                 V4L2_DV_FL_REDUCED_BLANKING) \
 497 }
 498
 499 /* SXGA resolutions */
 500 #define V4L2_DV_BT_DMT_1280X1024P60 { \
 501         .type = V4L2_DV_BT_656_1120, \
 502         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 503                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 504                 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
 505                 V4L2_DV_BT_STD_DMT, 0) \
 506 }
 507
 508 #define V4L2_DV_BT_DMT_1280X1024P75 { \
 509         .type = V4L2_DV_BT_656_1120, \
 510         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 511                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 512                 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
 513                 V4L2_DV_BT_STD_DMT, 0) \
 514 }
 515
 516 #define V4L2_DV_BT_DMT_1280X1024P85 { \
 517         .type = V4L2_DV_BT_656_1120, \
 518         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
 519                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 520                 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
 521                 V4L2_DV_BT_STD_DMT, 0) \
 522 }
 523
 524 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
 525         .type = V4L2_DV_BT_656_1120, \
 526         V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
 527                 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
 528                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 529                 V4L2_DV_FL_REDUCED_BLANKING) \
 530 }
 531
 532 #define V4L2_DV_BT_DMT_1360X768P60 { \
 533         .type = V4L2_DV_BT_656_1120, \
 534         V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
 535                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 536                 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
 537                 V4L2_DV_BT_STD_DMT, 0) \
 538 }
 539
 540 #define V4L2_DV_BT_DMT_1360X768P120_RB { \
 541         .type = V4L2_DV_BT_656_1120, \
 542         V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
 543                 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
 544                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 545                 V4L2_DV_FL_REDUCED_BLANKING) \
 546 }
 547
 548 #define V4L2_DV_BT_DMT_1366X768P60 { \
 549         .type = V4L2_DV_BT_656_1120, \
 550         V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
 551                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 552                 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
 553                 V4L2_DV_BT_STD_DMT, 0) \
 554 }
 555
 556 #define V4L2_DV_BT_DMT_1366X768P60_RB { \
 557         .type = V4L2_DV_BT_656_1120, \
 558         V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
 559                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 560                 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
 561                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 562 }
 563
 564 /* SXGA+ resolutions */
 565 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
 566         .type = V4L2_DV_BT_656_1120, \
 567         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 568                 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
 569                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 570                 V4L2_DV_FL_REDUCED_BLANKING) \
 571 }
 572
 573 #define V4L2_DV_BT_DMT_1400X1050P60 { \
 574         .type = V4L2_DV_BT_656_1120, \
 575         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 576                 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
 577                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 578 }
 579
 580 #define V4L2_DV_BT_DMT_1400X1050P75 { \
 581         .type = V4L2_DV_BT_656_1120, \
 582         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 583                 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
 584                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 585 }
 586
 587 #define V4L2_DV_BT_DMT_1400X1050P85 { \
 588         .type = V4L2_DV_BT_656_1120, \
 589         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 590                 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
 591                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 592 }
 593
 594 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
 595         .type = V4L2_DV_BT_656_1120, \
 596         V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 597                 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
 598                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 599                 V4L2_DV_FL_REDUCED_BLANKING) \
 600 }
 601
 602 /* WXGA+ resolutions */
 603 #define V4L2_DV_BT_DMT_1440X900P60_RB { \
 604         .type = V4L2_DV_BT_656_1120, \
 605         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
 606                 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
 607                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 608                 V4L2_DV_FL_REDUCED_BLANKING) \
 609 }
 610
 611 #define V4L2_DV_BT_DMT_1440X900P60 { \
 612         .type = V4L2_DV_BT_656_1120, \
 613         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 614                 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
 615                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 616 }
 617
 618 #define V4L2_DV_BT_DMT_1440X900P75 { \
 619         .type = V4L2_DV_BT_656_1120, \
 620         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 621                 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
 622                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 623 }
 624
 625 #define V4L2_DV_BT_DMT_1440X900P85 { \
 626         .type = V4L2_DV_BT_656_1120, \
 627         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
 628                 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
 629                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 630 }
 631
 632 #define V4L2_DV_BT_DMT_1440X900P120_RB { \
 633         .type = V4L2_DV_BT_656_1120, \
 634         V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
 635                 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
 636                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 637                 V4L2_DV_FL_REDUCED_BLANKING) \
 638 }
 639
 640 #define V4L2_DV_BT_DMT_1600X900P60_RB { \
 641         .type = V4L2_DV_BT_656_1120, \
 642         V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
 643                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 644                 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
 645                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 646 }
 647
 648 /* UXGA resolutions */
 649 #define V4L2_DV_BT_DMT_1600X1200P60 { \
 650         .type = V4L2_DV_BT_656_1120, \
 651         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 652                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 653                 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 654                 V4L2_DV_BT_STD_DMT, 0) \
 655 }
 656
 657 #define V4L2_DV_BT_DMT_1600X1200P65 { \
 658         .type = V4L2_DV_BT_656_1120, \
 659         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 660                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 661                 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 662                 V4L2_DV_BT_STD_DMT, 0) \
 663 }
 664
 665 #define V4L2_DV_BT_DMT_1600X1200P70 { \
 666         .type = V4L2_DV_BT_656_1120, \
 667         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 668                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 669                 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 670                 V4L2_DV_BT_STD_DMT, 0) \
 671 }
 672
 673 #define V4L2_DV_BT_DMT_1600X1200P75 { \
 674         .type = V4L2_DV_BT_656_1120, \
 675         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 676                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 677                 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 678                 V4L2_DV_BT_STD_DMT, 0) \
 679 }
 680
 681 #define V4L2_DV_BT_DMT_1600X1200P85 { \
 682         .type = V4L2_DV_BT_656_1120, \
 683         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
 684                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 685                 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
 686                 V4L2_DV_BT_STD_DMT, 0) \
 687 }
 688
 689 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
 690         .type = V4L2_DV_BT_656_1120, \
 691         V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 692                 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
 693                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 694                 V4L2_DV_FL_REDUCED_BLANKING) \
 695 }
 696
 697 /* WSXGA+ resolutions */
 698 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
 699         .type = V4L2_DV_BT_656_1120, \
 700         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 701                 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
 702                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 703                 V4L2_DV_FL_REDUCED_BLANKING) \
 704 }
 705
 706 #define V4L2_DV_BT_DMT_1680X1050P60 { \
 707         .type = V4L2_DV_BT_656_1120, \
 708         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 709                 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
 710                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 711 }
 712
 713 #define V4L2_DV_BT_DMT_1680X1050P75 { \
 714         .type = V4L2_DV_BT_656_1120, \
 715         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 716                 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
 717                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 718 }
 719
 720 #define V4L2_DV_BT_DMT_1680X1050P85 { \
 721         .type = V4L2_DV_BT_656_1120, \
 722         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
 723                 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
 724                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 725 }
 726
 727 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
 728         .type = V4L2_DV_BT_656_1120, \
 729         V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
 730                 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
 731                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 732                 V4L2_DV_FL_REDUCED_BLANKING) \
 733 }
 734
 735 #define V4L2_DV_BT_DMT_1792X1344P60 { \
 736         .type = V4L2_DV_BT_656_1120, \
 737         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
 738                 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
 739                 V4L2_DV_BT_STD_DMT, 0) \
 740 }
 741
 742 #define V4L2_DV_BT_DMT_1792X1344P75 { \
 743         .type = V4L2_DV_BT_656_1120, \
 744         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
 745                 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
 746                 V4L2_DV_BT_STD_DMT, 0) \
 747 }
 748
 749 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
 750         .type = V4L2_DV_BT_656_1120, \
 751         V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
 752                 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
 753                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 754                 V4L2_DV_FL_REDUCED_BLANKING) \
 755 }
 756
 757 #define V4L2_DV_BT_DMT_1856X1392P60 { \
 758         .type = V4L2_DV_BT_656_1120, \
 759         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
 760                 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
 761                 V4L2_DV_BT_STD_DMT, 0) \
 762 }
 763
 764 #define V4L2_DV_BT_DMT_1856X1392P75 { \
 765         .type = V4L2_DV_BT_656_1120, \
 766         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
 767                 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
 768                 V4L2_DV_BT_STD_DMT, 0) \
 769 }
 770
 771 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
 772         .type = V4L2_DV_BT_656_1120, \
 773         V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
 774                 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
 775                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 776                 V4L2_DV_FL_REDUCED_BLANKING) \
 777 }
 778
 779 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
 780
 781 /* WUXGA resolutions */
 782 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
 783         .type = V4L2_DV_BT_656_1120, \
 784         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 785                 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
 786                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 787                 V4L2_DV_FL_REDUCED_BLANKING) \
 788 }
 789
 790 #define V4L2_DV_BT_DMT_1920X1200P60 { \
 791         .type = V4L2_DV_BT_656_1120, \
 792         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 793                 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
 794                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 795 }
 796
 797 #define V4L2_DV_BT_DMT_1920X1200P75 { \
 798         .type = V4L2_DV_BT_656_1120, \
 799         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 800                 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
 801                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 802 }
 803
 804 #define V4L2_DV_BT_DMT_1920X1200P85 { \
 805         .type = V4L2_DV_BT_656_1120, \
 806         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
 807                 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
 808                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 809 }
 810
 811 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
 812         .type = V4L2_DV_BT_656_1120, \
 813         V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
 814                 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
 815                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 816                 V4L2_DV_FL_REDUCED_BLANKING) \
 817 }
 818
 819 #define V4L2_DV_BT_DMT_1920X1440P60 { \
 820         .type = V4L2_DV_BT_656_1120, \
 821         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
 822                 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
 823                 V4L2_DV_BT_STD_DMT, 0) \
 824 }
 825
 826 #define V4L2_DV_BT_DMT_1920X1440P75 { \
 827         .type = V4L2_DV_BT_656_1120, \
 828         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
 829                 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
 830                 V4L2_DV_BT_STD_DMT, 0) \
 831 }
 832
 833 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
 834         .type = V4L2_DV_BT_656_1120, \
 835         V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
 836                 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
 837                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 838                 V4L2_DV_FL_REDUCED_BLANKING) \
 839 }
 840
 841 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
 842         .type = V4L2_DV_BT_656_1120, \
 843         V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
 844                 V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
 845                 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
 846                 V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
 847 }
 848
 849 /* WQXGA resolutions */
 850 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
 851         .type = V4L2_DV_BT_656_1120, \
 852         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
 853                 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
 854                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 855                 V4L2_DV_FL_REDUCED_BLANKING) \
 856 }
 857
 858 #define V4L2_DV_BT_DMT_2560X1600P60 { \
 859         .type = V4L2_DV_BT_656_1120, \
 860         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 861                 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
 862                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 863 }
 864
 865 #define V4L2_DV_BT_DMT_2560X1600P75 { \
 866         .type = V4L2_DV_BT_656_1120, \
 867         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 868                 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
 869                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 870 }
 871
 872 #define V4L2_DV_BT_DMT_2560X1600P85 { \
 873         .type = V4L2_DV_BT_656_1120, \
 874         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
 875                 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
 876                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
 877 }
 878
 879 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
 880         .type = V4L2_DV_BT_656_1120, \
 881         V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
 882                 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
 883                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 884                 V4L2_DV_FL_REDUCED_BLANKING) \
 885 }
 886
 887 /* 4K resolutions */
 888 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \
 889         .type = V4L2_DV_BT_656_1120, \
 890         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 891                 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
 892                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 893                 V4L2_DV_FL_REDUCED_BLANKING) \
 894 }
 895
 896 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
 897         .type = V4L2_DV_BT_656_1120, \
 898         V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
 899                 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
 900                 V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
 901                 V4L2_DV_FL_REDUCED_BLANKING) \
 902 }
 903
 904 #endif