2 * Common functionality for the alsa driver code base for HD Audio.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef __SOUND_HDA_CONTROLLER_H
16 #define __SOUND_HDA_CONTROLLER_H
18 #include <linux/timecounter.h>
19 #include <linux/interrupt.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/initval.h>
23 #include "hda_codec.h"
24 #include <sound/hda_register.h>
26 #define AZX_MAX_CODECS HDA_MAX_CODECS
27 #define AZX_DEFAULT_CODECS 4
29 /* driver quirks (capabilities) */
30 /* bits 0-7 are used for indicating driver type */
31 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
32 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
33 #define AZX_DCAPS_SNOOP_MASK (3 << 10) /* snoop type mask */
34 #define AZX_DCAPS_SNOOP_OFF (1 << 12) /* snoop default off */
35 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
36 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
37 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
38 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
39 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
40 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
41 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
42 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
43 #define AZX_DCAPS_NO_ALIGN_BUFSIZE (1 << 21) /* no buffer size alignment */
45 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23) /* BDLE in 4k boundary */
46 #define AZX_DCAPS_REVERSE_ASSIGN (1 << 24) /* Assign devices in reverse order */
47 #define AZX_DCAPS_COUNT_LPIB_DELAY (1 << 25) /* Take LPIB as delay */
48 #define AZX_DCAPS_PM_RUNTIME (1 << 26) /* runtime PM support */
49 #define AZX_DCAPS_I915_POWERWELL (1 << 27) /* HSW i915 powerwell support */
50 #define AZX_DCAPS_CORBRP_SELF_CLEAR (1 << 28) /* CORBRP clears itself after reset */
51 #define AZX_DCAPS_NO_MSI64 (1 << 29) /* Stick to 32-bit MSIs */
52 #define AZX_DCAPS_SEPARATE_STREAM_TAG (1 << 30) /* capture and playback use separate stream tag */
58 AZX_SNOOP_TYPE_NVIDIA,
62 struct snd_dma_buffer bdl; /* BDL buffer */
63 u32 *posbuf; /* position buffer pointer */
65 unsigned int bufsize; /* size of the play buffer in bytes */
66 unsigned int period_bytes; /* size of the period in bytes */
67 unsigned int frags; /* number for period in the play buffer */
68 unsigned int fifo_size; /* FIFO size */
69 unsigned long start_wallclk; /* start + minimum wallclk */
70 unsigned long period_wallclk; /* wallclk for period */
72 void __iomem *sd_addr; /* stream descriptor pointer */
74 u32 sd_int_sta_mask; /* stream int status mask */
77 struct snd_pcm_substream *substream; /* assigned substream,
80 unsigned int format_val; /* format value to be set in the
81 * controller and the codec
83 unsigned char stream_tag; /* assigned stream */
84 unsigned char index; /* stream index */
85 int assigned_key; /* last device# key assigned to */
87 unsigned int opened:1;
88 unsigned int running:1;
89 unsigned int irq_pending:1;
90 unsigned int prepared:1;
91 unsigned int locked:1;
94 * A flag to ensure DMA position is 0
95 * when link position is not greater than FIFO size
97 unsigned int insufficient:1;
98 unsigned int wc_marked:1;
99 unsigned int no_period_wakeup:1;
101 struct timecounter azx_tc;
102 struct cyclecounter azx_cc;
104 int delay_negative_threshold;
106 #ifdef CONFIG_SND_HDA_DSP_LOADER
107 /* Allows dsp load to have sole access to the playback stream. */
108 struct mutex dsp_mutex;
114 u32 *buf; /* CORB/RIRB buffer
115 * Each CORB entry is 4byte, RIRB is 8byte
117 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
119 unsigned short rp, wp; /* read/write pointers */
120 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
121 u32 res[AZX_MAX_CODECS]; /* last read value */
126 /* Functions to read/write to hda registers. */
127 struct hda_controller_ops {
128 /* Register Access */
129 void (*reg_writel)(u32 value, u32 __iomem *addr);
130 u32 (*reg_readl)(u32 __iomem *addr);
131 void (*reg_writew)(u16 value, u16 __iomem *addr);
132 u16 (*reg_readw)(u16 __iomem *addr);
133 void (*reg_writeb)(u8 value, u8 __iomem *addr);
134 u8 (*reg_readb)(u8 __iomem *addr);
135 /* Disable msi if supported, PCI only */
136 int (*disable_msi_reset_irq)(struct azx *);
138 int (*dma_alloc_pages)(struct azx *chip,
141 struct snd_dma_buffer *buf);
142 void (*dma_free_pages)(struct azx *chip, struct snd_dma_buffer *buf);
143 int (*substream_alloc_pages)(struct azx *chip,
144 struct snd_pcm_substream *substream,
146 int (*substream_free_pages)(struct azx *chip,
147 struct snd_pcm_substream *substream);
148 void (*pcm_mmap_prepare)(struct snd_pcm_substream *substream,
149 struct vm_area_struct *area);
150 /* Check if current position is acceptable */
151 int (*position_check)(struct azx *chip, struct azx_dev *azx_dev);
157 struct hda_codec *codec;
158 struct hda_pcm *info;
159 struct list_head list;
162 typedef unsigned int (*azx_get_pos_callback_t)(struct azx *, struct azx_dev *);
163 typedef int (*azx_get_delay_callback_t)(struct azx *, struct azx_dev *, unsigned int pos);
166 struct snd_card *card;
170 /* chip type specific */
172 unsigned int driver_caps;
173 int playback_streams;
174 int playback_index_offset;
176 int capture_index_offset;
178 const int *jackpoll_ms; /* per-card jack poll interval */
180 /* Register interaction. */
181 const struct hda_controller_ops *ops;
183 /* position adjustment callbacks */
184 azx_get_pos_callback_t get_position[2];
185 azx_get_delay_callback_t get_delay[2];
189 void __iomem *remap_addr;
194 struct mutex open_mutex; /* Prevents concurrent open/close operations */
196 /* streams (x num_streams) */
197 struct azx_dev *azx_dev;
200 struct list_head pcm_list; /* azx_pcm list */
203 unsigned short codec_mask;
204 int codec_probe_mask; /* copied from probe_mask option */
206 unsigned int beep_mode;
212 /* CORB/RIRB and position buffers */
213 struct snd_dma_buffer rb;
214 struct snd_dma_buffer posbuf;
216 #ifdef CONFIG_SND_HDA_PATCH_LOADER
217 const struct firmware *fw;
221 const int *bdl_pos_adj;
223 unsigned int running:1;
224 unsigned int initialized:1;
225 unsigned int single_cmd:1;
226 unsigned int polling_mode:1;
228 unsigned int probing:1; /* codec probing phase */
229 unsigned int snoop:1;
230 unsigned int align_buffer_size:1;
231 unsigned int region_requested:1;
232 unsigned int disabled:1; /* disabled by VGA-switcher */
235 unsigned int last_cmd[AZX_MAX_CODECS];
237 #ifdef CONFIG_SND_HDA_DSP_LOADER
238 struct azx_dev saved_azx_dev;
243 #define azx_snoop(chip) ((chip)->snoop)
245 #define azx_snoop(chip) true
249 * macros for easy use
252 #define azx_writel(chip, reg, value) \
253 ((chip)->ops->reg_writel(value, (chip)->remap_addr + AZX_REG_##reg))
254 #define azx_readl(chip, reg) \
255 ((chip)->ops->reg_readl((chip)->remap_addr + AZX_REG_##reg))
256 #define azx_writew(chip, reg, value) \
257 ((chip)->ops->reg_writew(value, (chip)->remap_addr + AZX_REG_##reg))
258 #define azx_readw(chip, reg) \
259 ((chip)->ops->reg_readw((chip)->remap_addr + AZX_REG_##reg))
260 #define azx_writeb(chip, reg, value) \
261 ((chip)->ops->reg_writeb(value, (chip)->remap_addr + AZX_REG_##reg))
262 #define azx_readb(chip, reg) \
263 ((chip)->ops->reg_readb((chip)->remap_addr + AZX_REG_##reg))
265 #define azx_sd_writel(chip, dev, reg, value) \
266 ((chip)->ops->reg_writel(value, (dev)->sd_addr + AZX_REG_##reg))
267 #define azx_sd_readl(chip, dev, reg) \
268 ((chip)->ops->reg_readl((dev)->sd_addr + AZX_REG_##reg))
269 #define azx_sd_writew(chip, dev, reg, value) \
270 ((chip)->ops->reg_writew(value, (dev)->sd_addr + AZX_REG_##reg))
271 #define azx_sd_readw(chip, dev, reg) \
272 ((chip)->ops->reg_readw((dev)->sd_addr + AZX_REG_##reg))
273 #define azx_sd_writeb(chip, dev, reg, value) \
274 ((chip)->ops->reg_writeb(value, (dev)->sd_addr + AZX_REG_##reg))
275 #define azx_sd_readb(chip, dev, reg) \
276 ((chip)->ops->reg_readb((dev)->sd_addr + AZX_REG_##reg))
278 #define azx_has_pm_runtime(chip) \
279 (!AZX_DCAPS_PM_RUNTIME || ((chip)->driver_caps & AZX_DCAPS_PM_RUNTIME))
282 static inline struct azx_dev *get_azx_dev(struct snd_pcm_substream *substream)
284 return substream->runtime->private_data;
286 unsigned int azx_get_position(struct azx *chip, struct azx_dev *azx_dev);
287 unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev);
288 unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev);
290 /* Stream control. */
291 void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev);
293 /* Allocation functions. */
294 int azx_alloc_stream_pages(struct azx *chip);
295 void azx_free_stream_pages(struct azx *chip);
297 /* Low level azx interface */
298 void azx_init_chip(struct azx *chip, bool full_reset);
299 void azx_stop_chip(struct azx *chip);
300 void azx_enter_link_reset(struct azx *chip);
301 irqreturn_t azx_interrupt(int irq, void *dev_id);
303 /* Codec interface */
304 int azx_bus_create(struct azx *chip, const char *model);
305 int azx_probe_codecs(struct azx *chip, unsigned int max_slots);
306 int azx_codec_configure(struct azx *chip);
307 int azx_init_stream(struct azx *chip);
309 #endif /* __SOUND_HDA_CONTROLLER_H */