sound/pci/hda/patch_hdmi.c

   1 /*
   2  *
   3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
   4  *
   5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
   6  *  Copyright (c) 2006 ATI Technologies Inc.
   7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
   8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
   9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10  *
  11  *  Authors:
  12  *                      Wu Fengguang <wfg@linux.intel.com>
  13  *
  14  *  Maintained by:
  15  *                      Wu Fengguang <wfg@linux.intel.com>
  16  *
  17  *  This program is free software; you can redistribute it and/or modify it
  18  *  under the terms of the GNU General Public License as published by the Free
  19  *  Software Foundation; either version 2 of the License, or (at your option)
  20  *  any later version.
  21  *
  22  *  This program is distributed in the hope that it will be useful, but
  23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  25  *  for more details.
  26  *
  27  *  You should have received a copy of the GNU General Public License
  28  *  along with this program; if not, write to the Free Software Foundation,
  29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  30  */
  31
  32 #include <linux/init.h>
  33 #include <linux/delay.h>
  34 #include <linux/slab.h>
  35 #include <linux/module.h>
  36 #include <sound/core.h>
  37 #include <sound/jack.h>
  38 #include <sound/asoundef.h>
  39 #include <sound/tlv.h>
  40 #include <sound/hdaudio.h>
  41 #include <sound/hda_i915.h>
  42 #include "hda_codec.h"
  43 #include "hda_local.h"
  44 #include "hda_jack.h"
  45
  46 static bool static_hdmi_pcm;
  47 module_param(static_hdmi_pcm, bool, 0644);
  48 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  49
  50 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
  51 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
  52 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  53 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  54 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  55                                 || is_skylake(codec) || is_broxton(codec))
  56
  57 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  58 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  59 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  60
  61 struct hdmi_spec_per_cvt {
  62         hda_nid_t cvt_nid;
  63         int assigned;
  64         unsigned int channels_min;
  65         unsigned int channels_max;
  66         u32 rates;
  67         u64 formats;
  68         unsigned int maxbps;
  69 };
  70
  71 /* max. connections to a widget */
  72 #define HDA_MAX_CONNECTIONS     32
  73
  74 struct hdmi_spec_per_pin {
  75         hda_nid_t pin_nid;
  76         int num_mux_nids;
  77         hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  78         int mux_idx;
  79         hda_nid_t cvt_nid;
  80
  81         struct hda_codec *codec;
  82         struct hdmi_eld sink_eld;
  83         struct mutex lock;
  84         struct delayed_work work;
  85         struct snd_kcontrol *eld_ctl;
  86         int repoll_count;
  87         bool setup; /* the stream has been set up by prepare callback */
  88         int channels; /* current number of channels */
  89         bool non_pcm;
  90         bool chmap_set;         /* channel-map override by ALSA API? */
  91         unsigned char chmap[8]; /* ALSA API channel-map */
  92 #ifdef CONFIG_SND_PROC_FS
  93         struct snd_info_entry *proc_entry;
  94 #endif
  95 };
  96
  97 struct cea_channel_speaker_allocation;
  98
  99 /* operations used by generic code that can be overridden by patches */
 100 struct hdmi_ops {
 101         int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
 102                            unsigned char *buf, int *eld_size);
 103
 104         /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
 105         int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 106                                     int asp_slot);
 107         int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
 108                                     int asp_slot, int channel);
 109
 110         void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
 111                                     int ca, int active_channels, int conn_type);
 112
 113         /* enable/disable HBR (HD passthrough) */
 114         int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
 115
 116         int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
 117                             hda_nid_t pin_nid, u32 stream_tag, int format);
 118
 119         /* Helpers for producing the channel map TLVs. These can be overridden
 120          * for devices that have non-standard mapping requirements. */
 121         int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
 122                                                  int channels);
 123         void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
 124                                        unsigned int *chmap, int channels);
 125
 126         /* check that the user-given chmap is supported */
 127         int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
 128 };
 129
 130 struct hdmi_spec {
 131         int num_cvts;
 132         struct snd_array cvts; /* struct hdmi_spec_per_cvt */
 133         hda_nid_t cvt_nids[4]; /* only for haswell fix */
 134
 135         int num_pins;
 136         struct snd_array pins; /* struct hdmi_spec_per_pin */
 137         struct hda_pcm *pcm_rec[16];
 138         unsigned int channels_max; /* max over all cvts */
 139
 140         struct hdmi_eld temp_eld;
 141         struct hdmi_ops ops;
 142
 143         bool dyn_pin_out;
 144
 145         /*
 146          * Non-generic VIA/NVIDIA specific
 147          */
 148         struct hda_multi_out multiout;
 149         struct hda_pcm_stream pcm_playback;
 150
 151         /* i915/powerwell (Haswell+/Valleyview+) specific */
 152         struct i915_audio_component_audio_ops i915_audio_ops;
 153 };
 154
 155
 156 struct hdmi_audio_infoframe {
 157         u8 type; /* 0x84 */
 158         u8 ver;  /* 0x01 */
 159         u8 len;  /* 0x0a */
 160
 161         u8 checksum;
 162
 163         u8 CC02_CT47;   /* CC in bits 0:2, CT in 4:7 */
 164         u8 SS01_SF24;
 165         u8 CXT04;
 166         u8 CA;
 167         u8 LFEPBL01_LSV36_DM_INH7;
 168 };
 169
 170 struct dp_audio_infoframe {
 171         u8 type; /* 0x84 */
 172         u8 len;  /* 0x1b */
 173         u8 ver;  /* 0x11 << 2 */
 174
 175         u8 CC02_CT47;   /* match with HDMI infoframe from this on */
 176         u8 SS01_SF24;
 177         u8 CXT04;
 178         u8 CA;
 179         u8 LFEPBL01_LSV36_DM_INH7;
 180 };
 181
 182 union audio_infoframe {
 183         struct hdmi_audio_infoframe hdmi;
 184         struct dp_audio_infoframe dp;
 185         u8 bytes[0];
 186 };
 187
 188 /*
 189  * CEA speaker placement:
 190  *
 191  *        FLH       FCH        FRH
 192  *  FLW    FL  FLC   FC   FRC   FR   FRW
 193  *
 194  *                                  LFE
 195  *                     TC
 196  *
 197  *          RL  RLC   RC   RRC   RR
 198  *
 199  * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
 200  * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
 201  */
 202 enum cea_speaker_placement {
 203         FL  = (1 <<  0),        /* Front Left           */
 204         FC  = (1 <<  1),        /* Front Center         */
 205         FR  = (1 <<  2),        /* Front Right          */
 206         FLC = (1 <<  3),        /* Front Left Center    */
 207         FRC = (1 <<  4),        /* Front Right Center   */
 208         RL  = (1 <<  5),        /* Rear Left            */
 209         RC  = (1 <<  6),        /* Rear Center          */
 210         RR  = (1 <<  7),        /* Rear Right           */
 211         RLC = (1 <<  8),        /* Rear Left Center     */
 212         RRC = (1 <<  9),        /* Rear Right Center    */
 213         LFE = (1 << 10),        /* Low Frequency Effect */
 214         FLW = (1 << 11),        /* Front Left Wide      */
 215         FRW = (1 << 12),        /* Front Right Wide     */
 216         FLH = (1 << 13),        /* Front Left High      */
 217         FCH = (1 << 14),        /* Front Center High    */
 218         FRH = (1 << 15),        /* Front Right High     */
 219         TC  = (1 << 16),        /* Top Center           */
 220 };
 221
 222 /*
 223  * ELD SA bits in the CEA Speaker Allocation data block
 224  */
 225 static int eld_speaker_allocation_bits[] = {
 226         [0] = FL | FR,
 227         [1] = LFE,
 228         [2] = FC,
 229         [3] = RL | RR,
 230         [4] = RC,
 231         [5] = FLC | FRC,
 232         [6] = RLC | RRC,
 233         /* the following are not defined in ELD yet */
 234         [7] = FLW | FRW,
 235         [8] = FLH | FRH,
 236         [9] = TC,
 237         [10] = FCH,
 238 };
 239
 240 struct cea_channel_speaker_allocation {
 241         int ca_index;
 242         int speakers[8];
 243
 244         /* derived values, just for convenience */
 245         int channels;
 246         int spk_mask;
 247 };
 248
 249 /*
 250  * ALSA sequence is:
 251  *
 252  *       surround40   surround41   surround50   surround51   surround71
 253  * ch0   front left   =            =            =            =
 254  * ch1   front right  =            =            =            =
 255  * ch2   rear left    =            =            =            =
 256  * ch3   rear right   =            =            =            =
 257  * ch4                LFE          center       center       center
 258  * ch5                                          LFE          LFE
 259  * ch6                                                       side left
 260  * ch7                                                       side right
 261  *
 262  * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
 263  */
 264 static int hdmi_channel_mapping[0x32][8] = {
 265         /* stereo */
 266         [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 267         /* 2.1 */
 268         [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
 269         /* Dolby Surround */
 270         [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
 271         /* surround40 */
 272         [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
 273         /* 4ch */
 274         [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
 275         /* surround41 */
 276         [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
 277         /* surround50 */
 278         [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
 279         /* surround51 */
 280         [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
 281         /* 7.1 */
 282         [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
 283 };
 284
 285 /*
 286  * This is an ordered list!
 287  *
 288  * The preceding ones have better chances to be selected by
 289  * hdmi_channel_allocation().
 290  */
 291 static struct cea_channel_speaker_allocation channel_allocations[] = {
 292 /*                        channel:   7     6    5    4    3     2    1    0  */
 293 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
 294                                  /* 2.1 */
 295 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
 296                                  /* Dolby Surround */
 297 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
 298                                  /* surround40 */
 299 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
 300                                  /* surround41 */
 301 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
 302                                  /* surround50 */
 303 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 304                                  /* surround51 */
 305 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 306                                  /* 6.1 */
 307 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 308                                  /* surround71 */
 309 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 310
 311 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
 312 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
 313 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
 314 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
 315 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
 316 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
 317 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
 318 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 319 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
 320 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 321 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
 322 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
 323 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
 324 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
 325 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
 326 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
 327 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
 328 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
 329 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
 330 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
 331 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
 332 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
 333 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 334 { .ca_index = 0x20,  .speakers = {   0,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 335 { .ca_index = 0x21,  .speakers = {   0,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 336 { .ca_index = 0x22,  .speakers = {  TC,    0,  RR,  RL,  FC,    0,  FR,  FL } },
 337 { .ca_index = 0x23,  .speakers = {  TC,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
 338 { .ca_index = 0x24,  .speakers = { FRH,  FLH,  RR,  RL,   0,    0,  FR,  FL } },
 339 { .ca_index = 0x25,  .speakers = { FRH,  FLH,  RR,  RL,   0,  LFE,  FR,  FL } },
 340 { .ca_index = 0x26,  .speakers = { FRW,  FLW,  RR,  RL,   0,    0,  FR,  FL } },
 341 { .ca_index = 0x27,  .speakers = { FRW,  FLW,  RR,  RL,   0,  LFE,  FR,  FL } },
 342 { .ca_index = 0x28,  .speakers = {  TC,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 343 { .ca_index = 0x29,  .speakers = {  TC,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 344 { .ca_index = 0x2a,  .speakers = { FCH,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
 345 { .ca_index = 0x2b,  .speakers = { FCH,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
 346 { .ca_index = 0x2c,  .speakers = {  TC,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
 347 { .ca_index = 0x2d,  .speakers = {  TC,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 348 { .ca_index = 0x2e,  .speakers = { FRH,  FLH,  RR,  RL,  FC,    0,  FR,  FL } },
 349 { .ca_index = 0x2f,  .speakers = { FRH,  FLH,  RR,  RL,  FC,  LFE,  FR,  FL } },
 350 { .ca_index = 0x30,  .speakers = { FRW,  FLW,  RR,  RL,  FC,    0,  FR,  FL } },
 351 { .ca_index = 0x31,  .speakers = { FRW,  FLW,  RR,  RL,  FC,  LFE,  FR,  FL } },
 352 };
 353
 354
 355 /*
 356  * HDMI routines
 357  */
 358
 359 #define get_pin(spec, idx) \
 360         ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
 361 #define get_cvt(spec, idx) \
 362         ((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
 363 #define get_pcm_rec(spec, idx)  ((spec)->pcm_rec[idx])
 364
 365 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
 366 {
 367         struct hdmi_spec *spec = codec->spec;
 368         int pin_idx;
 369
 370         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 371                 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
 372                         return pin_idx;
 373
 374         codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
 375         return -EINVAL;
 376 }
 377
 378 static int hinfo_to_pin_index(struct hda_codec *codec,
 379                               struct hda_pcm_stream *hinfo)
 380 {
 381         struct hdmi_spec *spec = codec->spec;
 382         int pin_idx;
 383
 384         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
 385                 if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
 386                         return pin_idx;
 387
 388         codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
 389         return -EINVAL;
 390 }
 391
 392 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
 393 {
 394         struct hdmi_spec *spec = codec->spec;
 395         int cvt_idx;
 396
 397         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
 398                 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
 399                         return cvt_idx;
 400
 401         codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
 402         return -EINVAL;
 403 }
 404
 405 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
 406                         struct snd_ctl_elem_info *uinfo)
 407 {
 408         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 409         struct hdmi_spec *spec = codec->spec;
 410         struct hdmi_spec_per_pin *per_pin;
 411         struct hdmi_eld *eld;
 412         int pin_idx;
 413
 414         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
 415
 416         pin_idx = kcontrol->private_value;
 417         per_pin = get_pin(spec, pin_idx);
 418         eld = &per_pin->sink_eld;
 419
 420         mutex_lock(&per_pin->lock);
 421         uinfo->count = eld->eld_valid ? eld->eld_size : 0;
 422         mutex_unlock(&per_pin->lock);
 423
 424         return 0;
 425 }
 426
 427 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
 428                         struct snd_ctl_elem_value *ucontrol)
 429 {
 430         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
 431         struct hdmi_spec *spec = codec->spec;
 432         struct hdmi_spec_per_pin *per_pin;
 433         struct hdmi_eld *eld;
 434         int pin_idx;
 435
 436         pin_idx = kcontrol->private_value;
 437         per_pin = get_pin(spec, pin_idx);
 438         eld = &per_pin->sink_eld;
 439
 440         mutex_lock(&per_pin->lock);
 441         if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
 442                 mutex_unlock(&per_pin->lock);
 443                 snd_BUG();
 444                 return -EINVAL;
 445         }
 446
 447         memset(ucontrol->value.bytes.data, 0,
 448                ARRAY_SIZE(ucontrol->value.bytes.data));
 449         if (eld->eld_valid)
 450                 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
 451                        eld->eld_size);
 452         mutex_unlock(&per_pin->lock);
 453
 454         return 0;
 455 }
 456
 457 static struct snd_kcontrol_new eld_bytes_ctl = {
 458         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
 459         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 460         .name = "ELD",
 461         .info = hdmi_eld_ctl_info,
 462         .get = hdmi_eld_ctl_get,
 463 };
 464
 465 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
 466                         int device)
 467 {
 468         struct snd_kcontrol *kctl;
 469         struct hdmi_spec *spec = codec->spec;
 470         int err;
 471
 472         kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
 473         if (!kctl)
 474                 return -ENOMEM;
 475         kctl->private_value = pin_idx;
 476         kctl->id.device = device;
 477
 478         err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
 479         if (err < 0)
 480                 return err;
 481
 482         get_pin(spec, pin_idx)->eld_ctl = kctl;
 483         return 0;
 484 }
 485
 486 #ifdef BE_PARANOID
 487 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 488                                 int *packet_index, int *byte_index)
 489 {
 490         int val;
 491
 492         val = snd_hda_codec_read(codec, pin_nid, 0,
 493                                  AC_VERB_GET_HDMI_DIP_INDEX, 0);
 494
 495         *packet_index = val >> 5;
 496         *byte_index = val & 0x1f;
 497 }
 498 #endif
 499
 500 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
 501                                 int packet_index, int byte_index)
 502 {
 503         int val;
 504
 505         val = (packet_index << 5) | (byte_index & 0x1f);
 506
 507         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
 508 }
 509
 510 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
 511                                 unsigned char val)
 512 {
 513         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
 514 }
 515
 516 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
 517 {
 518         struct hdmi_spec *spec = codec->spec;
 519         int pin_out;
 520
 521         /* Unmute */
 522         if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
 523                 snd_hda_codec_write(codec, pin_nid, 0,
 524                                 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
 525
 526         if (spec->dyn_pin_out)
 527                 /* Disable pin out until stream is active */
 528                 pin_out = 0;
 529         else
 530                 /* Enable pin out: some machines with GM965 gets broken output
 531                  * when the pin is disabled or changed while using with HDMI
 532                  */
 533                 pin_out = PIN_OUT;
 534
 535         snd_hda_codec_write(codec, pin_nid, 0,
 536                             AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
 537 }
 538
 539 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
 540 {
 541         return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
 542                                         AC_VERB_GET_CVT_CHAN_COUNT, 0);
 543 }
 544
 545 static void hdmi_set_channel_count(struct hda_codec *codec,
 546                                    hda_nid_t cvt_nid, int chs)
 547 {
 548         if (chs != hdmi_get_channel_count(codec, cvt_nid))
 549                 snd_hda_codec_write(codec, cvt_nid, 0,
 550                                     AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
 551 }
 552
 553 /*
 554  * ELD proc files
 555  */
 556
 557 #ifdef CONFIG_SND_PROC_FS
 558 static void print_eld_info(struct snd_info_entry *entry,
 559                            struct snd_info_buffer *buffer)
 560 {
 561         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 562
 563         mutex_lock(&per_pin->lock);
 564         snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
 565         mutex_unlock(&per_pin->lock);
 566 }
 567
 568 static void write_eld_info(struct snd_info_entry *entry,
 569                            struct snd_info_buffer *buffer)
 570 {
 571         struct hdmi_spec_per_pin *per_pin = entry->private_data;
 572
 573         mutex_lock(&per_pin->lock);
 574         snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
 575         mutex_unlock(&per_pin->lock);
 576 }
 577
 578 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
 579 {
 580         char name[32];
 581         struct hda_codec *codec = per_pin->codec;
 582         struct snd_info_entry *entry;
 583         int err;
 584
 585         snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
 586         err = snd_card_proc_new(codec->card, name, &entry);
 587         if (err < 0)
 588                 return err;
 589
 590         snd_info_set_text_ops(entry, per_pin, print_eld_info);
 591         entry->c.text.write = write_eld_info;
 592         entry->mode |= S_IWUSR;
 593         per_pin->proc_entry = entry;
 594
 595         return 0;
 596 }
 597
 598 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 599 {
 600         if (!per_pin->codec->bus->shutdown) {
 601                 snd_info_free_entry(per_pin->proc_entry);
 602                 per_pin->proc_entry = NULL;
 603         }
 604 }
 605 #else
 606 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
 607                                int index)
 608 {
 609         return 0;
 610 }
 611 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
 612 {
 613 }
 614 #endif
 615
 616 /*
 617  * Channel mapping routines
 618  */
 619
 620 /*
 621  * Compute derived values in channel_allocations[].
 622  */
 623 static void init_channel_allocations(void)
 624 {
 625         int i, j;
 626         struct cea_channel_speaker_allocation *p;
 627
 628         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 629                 p = channel_allocations + i;
 630                 p->channels = 0;
 631                 p->spk_mask = 0;
 632                 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
 633                         if (p->speakers[j]) {
 634                                 p->channels++;
 635                                 p->spk_mask |= p->speakers[j];
 636                         }
 637         }
 638 }
 639
 640 static int get_channel_allocation_order(int ca)
 641 {
 642         int i;
 643
 644         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 645                 if (channel_allocations[i].ca_index == ca)
 646                         break;
 647         }
 648         return i;
 649 }
 650
 651 /*
 652  * The transformation takes two steps:
 653  *
 654  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
 655  *            spk_mask => (channel_allocations[])         => ai->CA
 656  *
 657  * TODO: it could select the wrong CA from multiple candidates.
 658 */
 659 static int hdmi_channel_allocation(struct hda_codec *codec,
 660                                    struct hdmi_eld *eld, int channels)
 661 {
 662         int i;
 663         int ca = 0;
 664         int spk_mask = 0;
 665         char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
 666
 667         /*
 668          * CA defaults to 0 for basic stereo audio
 669          */
 670         if (channels <= 2)
 671                 return 0;
 672
 673         /*
 674          * expand ELD's speaker allocation mask
 675          *
 676          * ELD tells the speaker mask in a compact(paired) form,
 677          * expand ELD's notions to match the ones used by Audio InfoFrame.
 678          */
 679         for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
 680                 if (eld->info.spk_alloc & (1 << i))
 681                         spk_mask |= eld_speaker_allocation_bits[i];
 682         }
 683
 684         /* search for the first working match in the CA table */
 685         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 686                 if (channels == channel_allocations[i].channels &&
 687                     (spk_mask & channel_allocations[i].spk_mask) ==
 688                                 channel_allocations[i].spk_mask) {
 689                         ca = channel_allocations[i].ca_index;
 690                         break;
 691                 }
 692         }
 693
 694         if (!ca) {
 695                 /* if there was no match, select the regular ALSA channel
 696                  * allocation with the matching number of channels */
 697                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 698                         if (channels == channel_allocations[i].channels) {
 699                                 ca = channel_allocations[i].ca_index;
 700                                 break;
 701                         }
 702                 }
 703         }
 704
 705         snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
 706         codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
 707                     ca, channels, buf);
 708
 709         return ca;
 710 }
 711
 712 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
 713                                        hda_nid_t pin_nid)
 714 {
 715 #ifdef CONFIG_SND_DEBUG_VERBOSE
 716         struct hdmi_spec *spec = codec->spec;
 717         int i;
 718         int channel;
 719
 720         for (i = 0; i < 8; i++) {
 721                 channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
 722                 codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
 723                                                 channel, i);
 724         }
 725 #endif
 726 }
 727
 728 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
 729                                        hda_nid_t pin_nid,
 730                                        bool non_pcm,
 731                                        int ca)
 732 {
 733         struct hdmi_spec *spec = codec->spec;
 734         struct cea_channel_speaker_allocation *ch_alloc;
 735         int i;
 736         int err;
 737         int order;
 738         int non_pcm_mapping[8];
 739
 740         order = get_channel_allocation_order(ca);
 741         ch_alloc = &channel_allocations[order];
 742
 743         if (hdmi_channel_mapping[ca][1] == 0) {
 744                 int hdmi_slot = 0;
 745                 /* fill actual channel mappings in ALSA channel (i) order */
 746                 for (i = 0; i < ch_alloc->channels; i++) {
 747                         while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
 748                                 hdmi_slot++; /* skip zero slots */
 749
 750                         hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
 751                 }
 752                 /* fill the rest of the slots with ALSA channel 0xf */
 753                 for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
 754                         if (!ch_alloc->speakers[7 - hdmi_slot])
 755                                 hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
 756         }
 757
 758         if (non_pcm) {
 759                 for (i = 0; i < ch_alloc->channels; i++)
 760                         non_pcm_mapping[i] = (i << 4) | i;
 761                 for (; i < 8; i++)
 762                         non_pcm_mapping[i] = (0xf << 4) | i;
 763         }
 764
 765         for (i = 0; i < 8; i++) {
 766                 int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
 767                 int hdmi_slot = slotsetup & 0x0f;
 768                 int channel = (slotsetup & 0xf0) >> 4;
 769                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
 770                 if (err) {
 771                         codec_dbg(codec, "HDMI: channel mapping failed\n");
 772                         break;
 773                 }
 774         }
 775 }
 776
 777 struct channel_map_table {
 778         unsigned char map;              /* ALSA API channel map position */
 779         int spk_mask;                   /* speaker position bit mask */
 780 };
 781
 782 static struct channel_map_table map_tables[] = {
 783         { SNDRV_CHMAP_FL,       FL },
 784         { SNDRV_CHMAP_FR,       FR },
 785         { SNDRV_CHMAP_RL,       RL },
 786         { SNDRV_CHMAP_RR,       RR },
 787         { SNDRV_CHMAP_LFE,      LFE },
 788         { SNDRV_CHMAP_FC,       FC },
 789         { SNDRV_CHMAP_RLC,      RLC },
 790         { SNDRV_CHMAP_RRC,      RRC },
 791         { SNDRV_CHMAP_RC,       RC },
 792         { SNDRV_CHMAP_FLC,      FLC },
 793         { SNDRV_CHMAP_FRC,      FRC },
 794         { SNDRV_CHMAP_TFL,      FLH },
 795         { SNDRV_CHMAP_TFR,      FRH },
 796         { SNDRV_CHMAP_FLW,      FLW },
 797         { SNDRV_CHMAP_FRW,      FRW },
 798         { SNDRV_CHMAP_TC,       TC },
 799         { SNDRV_CHMAP_TFC,      FCH },
 800         {} /* terminator */
 801 };
 802
 803 /* from ALSA API channel position to speaker bit mask */
 804 static int to_spk_mask(unsigned char c)
 805 {
 806         struct channel_map_table *t = map_tables;
 807         for (; t->map; t++) {
 808                 if (t->map == c)
 809                         return t->spk_mask;
 810         }
 811         return 0;
 812 }
 813
 814 /* from ALSA API channel position to CEA slot */
 815 static int to_cea_slot(int ordered_ca, unsigned char pos)
 816 {
 817         int mask = to_spk_mask(pos);
 818         int i;
 819
 820         if (mask) {
 821                 for (i = 0; i < 8; i++) {
 822                         if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
 823                                 return i;
 824                 }
 825         }
 826
 827         return -1;
 828 }
 829
 830 /* from speaker bit mask to ALSA API channel position */
 831 static int spk_to_chmap(int spk)
 832 {
 833         struct channel_map_table *t = map_tables;
 834         for (; t->map; t++) {
 835                 if (t->spk_mask == spk)
 836                         return t->map;
 837         }
 838         return 0;
 839 }
 840
 841 /* from CEA slot to ALSA API channel position */
 842 static int from_cea_slot(int ordered_ca, unsigned char slot)
 843 {
 844         int mask = channel_allocations[ordered_ca].speakers[7 - slot];
 845
 846         return spk_to_chmap(mask);
 847 }
 848
 849 /* get the CA index corresponding to the given ALSA API channel map */
 850 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
 851 {
 852         int i, spks = 0, spk_mask = 0;
 853
 854         for (i = 0; i < chs; i++) {
 855                 int mask = to_spk_mask(map[i]);
 856                 if (mask) {
 857                         spk_mask |= mask;
 858                         spks++;
 859                 }
 860         }
 861
 862         for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
 863                 if ((chs == channel_allocations[i].channels ||
 864                      spks == channel_allocations[i].channels) &&
 865                     (spk_mask & channel_allocations[i].spk_mask) ==
 866                                 channel_allocations[i].spk_mask)
 867                         return channel_allocations[i].ca_index;
 868         }
 869         return -1;
 870 }
 871
 872 /* set up the channel slots for the given ALSA API channel map */
 873 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
 874                                              hda_nid_t pin_nid,
 875                                              int chs, unsigned char *map,
 876                                              int ca)
 877 {
 878         struct hdmi_spec *spec = codec->spec;
 879         int ordered_ca = get_channel_allocation_order(ca);
 880         int alsa_pos, hdmi_slot;
 881         int assignments[8] = {[0 ... 7] = 0xf};
 882
 883         for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
 884
 885                 hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
 886
 887                 if (hdmi_slot < 0)
 888                         continue; /* unassigned channel */
 889
 890                 assignments[hdmi_slot] = alsa_pos;
 891         }
 892
 893         for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
 894                 int err;
 895
 896                 err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
 897                                                      assignments[hdmi_slot]);
 898                 if (err)
 899                         return -EINVAL;
 900         }
 901         return 0;
 902 }
 903
 904 /* store ALSA API channel map from the current default map */
 905 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
 906 {
 907         int i;
 908         int ordered_ca = get_channel_allocation_order(ca);
 909         for (i = 0; i < 8; i++) {
 910                 if (i < channel_allocations[ordered_ca].channels)
 911                         map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
 912                 else
 913                         map[i] = 0;
 914         }
 915 }
 916
 917 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
 918                                        hda_nid_t pin_nid, bool non_pcm, int ca,
 919                                        int channels, unsigned char *map,
 920                                        bool chmap_set)
 921 {
 922         if (!non_pcm && chmap_set) {
 923                 hdmi_manual_setup_channel_mapping(codec, pin_nid,
 924                                                   channels, map, ca);
 925         } else {
 926                 hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
 927                 hdmi_setup_fake_chmap(map, ca);
 928         }
 929
 930         hdmi_debug_channel_mapping(codec, pin_nid);
 931 }
 932
 933 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 934                                      int asp_slot, int channel)
 935 {
 936         return snd_hda_codec_write(codec, pin_nid, 0,
 937                                    AC_VERB_SET_HDMI_CHAN_SLOT,
 938                                    (channel << 4) | asp_slot);
 939 }
 940
 941 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
 942                                      int asp_slot)
 943 {
 944         return (snd_hda_codec_read(codec, pin_nid, 0,
 945                                    AC_VERB_GET_HDMI_CHAN_SLOT,
 946                                    asp_slot) & 0xf0) >> 4;
 947 }
 948
 949 /*
 950  * Audio InfoFrame routines
 951  */
 952
 953 /*
 954  * Enable Audio InfoFrame Transmission
 955  */
 956 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
 957                                        hda_nid_t pin_nid)
 958 {
 959         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 960         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 961                                                 AC_DIPXMIT_BEST);
 962 }
 963
 964 /*
 965  * Disable Audio InfoFrame Transmission
 966  */
 967 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
 968                                       hda_nid_t pin_nid)
 969 {
 970         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
 971         snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
 972                                                 AC_DIPXMIT_DISABLE);
 973 }
 974
 975 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
 976 {
 977 #ifdef CONFIG_SND_DEBUG_VERBOSE
 978         int i;
 979         int size;
 980
 981         size = snd_hdmi_get_eld_size(codec, pin_nid);
 982         codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
 983
 984         for (i = 0; i < 8; i++) {
 985                 size = snd_hda_codec_read(codec, pin_nid, 0,
 986                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
 987                 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
 988         }
 989 #endif
 990 }
 991
 992 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
 993 {
 994 #ifdef BE_PARANOID
 995         int i, j;
 996         int size;
 997         int pi, bi;
 998         for (i = 0; i < 8; i++) {
 999                 size = snd_hda_codec_read(codec, pin_nid, 0,
1000                                                 AC_VERB_GET_HDMI_DIP_SIZE, i);
1001                 if (size == 0)
1002                         continue;
1003
1004                 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
1005                 for (j = 1; j < 1000; j++) {
1006                         hdmi_write_dip_byte(codec, pin_nid, 0x0);
1007                         hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1008                         if (pi != i)
1009                                 codec_dbg(codec, "dip index %d: %d != %d\n",
1010                                                 bi, pi, i);
1011                         if (bi == 0) /* byte index wrapped around */
1012                                 break;
1013                 }
1014                 codec_dbg(codec,
1015                         "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1016                         i, size, j);
1017         }
1018 #endif
1019 }
1020
1021 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1022 {
1023         u8 *bytes = (u8 *)hdmi_ai;
1024         u8 sum = 0;
1025         int i;
1026
1027         hdmi_ai->checksum = 0;
1028
1029         for (i = 0; i < sizeof(*hdmi_ai); i++)
1030                 sum += bytes[i];
1031
1032         hdmi_ai->checksum = -sum;
1033 }
1034
1035 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1036                                       hda_nid_t pin_nid,
1037                                       u8 *dip, int size)
1038 {
1039         int i;
1040
1041         hdmi_debug_dip_size(codec, pin_nid);
1042         hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1043
1044         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1045         for (i = 0; i < size; i++)
1046                 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1047 }
1048
1049 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1050                                     u8 *dip, int size)
1051 {
1052         u8 val;
1053         int i;
1054
1055         if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1056                                                             != AC_DIPXMIT_BEST)
1057                 return false;
1058
1059         hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1060         for (i = 0; i < size; i++) {
1061                 val = snd_hda_codec_read(codec, pin_nid, 0,
1062                                          AC_VERB_GET_HDMI_DIP_DATA, 0);
1063                 if (val != dip[i])
1064                         return false;
1065         }
1066
1067         return true;
1068 }
1069
1070 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1071                                      hda_nid_t pin_nid,
1072                                      int ca, int active_channels,
1073                                      int conn_type)
1074 {
1075         union audio_infoframe ai;
1076
1077         memset(&ai, 0, sizeof(ai));
1078         if (conn_type == 0) { /* HDMI */
1079                 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1080
1081                 hdmi_ai->type           = 0x84;
1082                 hdmi_ai->ver            = 0x01;
1083                 hdmi_ai->len            = 0x0a;
1084                 hdmi_ai->CC02_CT47      = active_channels - 1;
1085                 hdmi_ai->CA             = ca;
1086                 hdmi_checksum_audio_infoframe(hdmi_ai);
1087         } else if (conn_type == 1) { /* DisplayPort */
1088                 struct dp_audio_infoframe *dp_ai = &ai.dp;
1089
1090                 dp_ai->type             = 0x84;
1091                 dp_ai->len              = 0x1b;
1092                 dp_ai->ver              = 0x11 << 2;
1093                 dp_ai->CC02_CT47        = active_channels - 1;
1094                 dp_ai->CA               = ca;
1095         } else {
1096                 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1097                             pin_nid);
1098                 return;
1099         }
1100
1101         /*
1102          * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1103          * sizeof(*dp_ai) to avoid partial match/update problems when
1104          * the user switches between HDMI/DP monitors.
1105          */
1106         if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1107                                         sizeof(ai))) {
1108                 codec_dbg(codec,
1109                           "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1110                             pin_nid,
1111                             active_channels, ca);
1112                 hdmi_stop_infoframe_trans(codec, pin_nid);
1113                 hdmi_fill_audio_infoframe(codec, pin_nid,
1114                                             ai.bytes, sizeof(ai));
1115                 hdmi_start_infoframe_trans(codec, pin_nid);
1116         }
1117 }
1118
1119 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1120                                        struct hdmi_spec_per_pin *per_pin,
1121                                        bool non_pcm)
1122 {
1123         struct hdmi_spec *spec = codec->spec;
1124         hda_nid_t pin_nid = per_pin->pin_nid;
1125         int channels = per_pin->channels;
1126         int active_channels;
1127         struct hdmi_eld *eld;
1128         int ca, ordered_ca;
1129
1130         if (!channels)
1131                 return;
1132
1133         if (is_haswell_plus(codec))
1134                 snd_hda_codec_write(codec, pin_nid, 0,
1135                                             AC_VERB_SET_AMP_GAIN_MUTE,
1136                                             AMP_OUT_UNMUTE);
1137
1138         eld = &per_pin->sink_eld;
1139
1140         if (!non_pcm && per_pin->chmap_set)
1141                 ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1142         else
1143                 ca = hdmi_channel_allocation(codec, eld, channels);
1144         if (ca < 0)
1145                 ca = 0;
1146
1147         ordered_ca = get_channel_allocation_order(ca);
1148         active_channels = channel_allocations[ordered_ca].channels;
1149
1150         hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1151
1152         /*
1153          * always configure channel mapping, it may have been changed by the
1154          * user in the meantime
1155          */
1156         hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1157                                    channels, per_pin->chmap,
1158                                    per_pin->chmap_set);
1159
1160         spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1161                                       eld->info.conn_type);
1162
1163         per_pin->non_pcm = non_pcm;
1164 }
1165
1166 /*
1167  * Unsolicited events
1168  */
1169
1170 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1171
1172 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1173 {
1174         struct hdmi_spec *spec = codec->spec;
1175         int pin_idx = pin_nid_to_pin_index(codec, nid);
1176
1177         if (pin_idx < 0)
1178                 return;
1179         if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1180                 snd_hda_jack_report_sync(codec);
1181 }
1182
1183 static void jack_callback(struct hda_codec *codec,
1184                           struct hda_jack_callback *jack)
1185 {
1186         check_presence_and_report(codec, jack->tbl->nid);
1187 }
1188
1189 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1190 {
1191         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1192         struct hda_jack_tbl *jack;
1193         int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1194
1195         jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1196         if (!jack)
1197                 return;
1198         jack->jack_dirty = 1;
1199
1200         codec_dbg(codec,
1201                 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1202                 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1203                 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1204
1205         check_presence_and_report(codec, jack->nid);
1206 }
1207
1208 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1209 {
1210         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1211         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1212         int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1213         int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1214
1215         codec_info(codec,
1216                 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1217                 codec->addr,
1218                 tag,
1219                 subtag,
1220                 cp_state,
1221                 cp_ready);
1222
1223         /* TODO */
1224         if (cp_state)
1225                 ;
1226         if (cp_ready)
1227                 ;
1228 }
1229
1230
1231 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1232 {
1233         int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1234         int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1235
1236         if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1237                 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1238                 return;
1239         }
1240
1241         if (subtag == 0)
1242                 hdmi_intrinsic_event(codec, res);
1243         else
1244                 hdmi_non_intrinsic_event(codec, res);
1245 }
1246
1247 static void haswell_verify_D0(struct hda_codec *codec,
1248                 hda_nid_t cvt_nid, hda_nid_t nid)
1249 {
1250         int pwr;
1251
1252         /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1253          * thus pins could only choose converter 0 for use. Make sure the
1254          * converters are in correct power state */
1255         if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1256                 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1257
1258         if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1259                 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1260                                     AC_PWRST_D0);
1261                 msleep(40);
1262                 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1263                 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1264                 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1265         }
1266 }
1267
1268 /*
1269  * Callbacks
1270  */
1271
1272 /* HBR should be Non-PCM, 8 channels */
1273 #define is_hbr_format(format) \
1274         ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1275
1276 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1277                               bool hbr)
1278 {
1279         int pinctl, new_pinctl;
1280
1281         if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1282                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1283                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1284
1285                 if (pinctl < 0)
1286                         return hbr ? -EINVAL : 0;
1287
1288                 new_pinctl = pinctl & ~AC_PINCTL_EPT;
1289                 if (hbr)
1290                         new_pinctl |= AC_PINCTL_EPT_HBR;
1291                 else
1292                         new_pinctl |= AC_PINCTL_EPT_NATIVE;
1293
1294                 codec_dbg(codec,
1295                           "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1296                             pin_nid,
1297                             pinctl == new_pinctl ? "" : "new-",
1298                             new_pinctl);
1299
1300                 if (pinctl != new_pinctl)
1301                         snd_hda_codec_write(codec, pin_nid, 0,
1302                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1303                                             new_pinctl);
1304         } else if (hbr)
1305                 return -EINVAL;
1306
1307         return 0;
1308 }
1309
1310 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1311                               hda_nid_t pin_nid, u32 stream_tag, int format)
1312 {
1313         struct hdmi_spec *spec = codec->spec;
1314         int err;
1315
1316         if (is_haswell_plus(codec))
1317                 haswell_verify_D0(codec, cvt_nid, pin_nid);
1318
1319         err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1320
1321         if (err) {
1322                 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1323                 return err;
1324         }
1325
1326         snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1327         return 0;
1328 }
1329
1330 static int hdmi_choose_cvt(struct hda_codec *codec,
1331                         int pin_idx, int *cvt_id, int *mux_id)
1332 {
1333         struct hdmi_spec *spec = codec->spec;
1334         struct hdmi_spec_per_pin *per_pin;
1335         struct hdmi_spec_per_cvt *per_cvt = NULL;
1336         int cvt_idx, mux_idx = 0;
1337
1338         per_pin = get_pin(spec, pin_idx);
1339
1340         /* Dynamically assign converter to stream */
1341         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1342                 per_cvt = get_cvt(spec, cvt_idx);
1343
1344                 /* Must not already be assigned */
1345                 if (per_cvt->assigned)
1346                         continue;
1347                 /* Must be in pin's mux's list of converters */
1348                 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1349                         if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1350                                 break;
1351                 /* Not in mux list */
1352                 if (mux_idx == per_pin->num_mux_nids)
1353                         continue;
1354                 break;
1355         }
1356
1357         /* No free converters */
1358         if (cvt_idx == spec->num_cvts)
1359                 return -ENODEV;
1360
1361         per_pin->mux_idx = mux_idx;
1362
1363         if (cvt_id)
1364                 *cvt_id = cvt_idx;
1365         if (mux_id)
1366                 *mux_id = mux_idx;
1367
1368         return 0;
1369 }
1370
1371 /* Assure the pin select the right convetor */
1372 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1373                         struct hdmi_spec_per_pin *per_pin)
1374 {
1375         hda_nid_t pin_nid = per_pin->pin_nid;
1376         int mux_idx, curr;
1377
1378         mux_idx = per_pin->mux_idx;
1379         curr = snd_hda_codec_read(codec, pin_nid, 0,
1380                                           AC_VERB_GET_CONNECT_SEL, 0);
1381         if (curr != mux_idx)
1382                 snd_hda_codec_write_cache(codec, pin_nid, 0,
1383                                             AC_VERB_SET_CONNECT_SEL,
1384                                             mux_idx);
1385 }
1386
1387 /* Intel HDMI workaround to fix audio routing issue:
1388  * For some Intel display codecs, pins share the same connection list.
1389  * So a conveter can be selected by multiple pins and playback on any of these
1390  * pins will generate sound on the external display, because audio flows from
1391  * the same converter to the display pipeline. Also muting one pin may make
1392  * other pins have no sound output.
1393  * So this function assures that an assigned converter for a pin is not selected
1394  * by any other pins.
1395  */
1396 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1397                         hda_nid_t pin_nid, int mux_idx)
1398 {
1399         struct hdmi_spec *spec = codec->spec;
1400         hda_nid_t nid;
1401         int cvt_idx, curr;
1402         struct hdmi_spec_per_cvt *per_cvt;
1403
1404         /* configure all pins, including "no physical connection" ones */
1405         for_each_hda_codec_node(nid, codec) {
1406                 unsigned int wid_caps = get_wcaps(codec, nid);
1407                 unsigned int wid_type = get_wcaps_type(wid_caps);
1408
1409                 if (wid_type != AC_WID_PIN)
1410                         continue;
1411
1412                 if (nid == pin_nid)
1413                         continue;
1414
1415                 curr = snd_hda_codec_read(codec, nid, 0,
1416                                           AC_VERB_GET_CONNECT_SEL, 0);
1417                 if (curr != mux_idx)
1418                         continue;
1419
1420                 /* choose an unassigned converter. The conveters in the
1421                  * connection list are in the same order as in the codec.
1422                  */
1423                 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1424                         per_cvt = get_cvt(spec, cvt_idx);
1425                         if (!per_cvt->assigned) {
1426                                 codec_dbg(codec,
1427                                           "choose cvt %d for pin nid %d\n",
1428                                         cvt_idx, nid);
1429                                 snd_hda_codec_write_cache(codec, nid, 0,
1430                                             AC_VERB_SET_CONNECT_SEL,
1431                                             cvt_idx);
1432                                 break;
1433                         }
1434                 }
1435         }
1436 }
1437
1438 /*
1439  * HDA PCM callbacks
1440  */
1441 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1442                          struct hda_codec *codec,
1443                          struct snd_pcm_substream *substream)
1444 {
1445         struct hdmi_spec *spec = codec->spec;
1446         struct snd_pcm_runtime *runtime = substream->runtime;
1447         int pin_idx, cvt_idx, mux_idx = 0;
1448         struct hdmi_spec_per_pin *per_pin;
1449         struct hdmi_eld *eld;
1450         struct hdmi_spec_per_cvt *per_cvt = NULL;
1451         int err;
1452
1453         /* Validate hinfo */
1454         pin_idx = hinfo_to_pin_index(codec, hinfo);
1455         if (snd_BUG_ON(pin_idx < 0))
1456                 return -EINVAL;
1457         per_pin = get_pin(spec, pin_idx);
1458         eld = &per_pin->sink_eld;
1459
1460         err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1461         if (err < 0)
1462                 return err;
1463
1464         per_cvt = get_cvt(spec, cvt_idx);
1465         /* Claim converter */
1466         per_cvt->assigned = 1;
1467         per_pin->cvt_nid = per_cvt->cvt_nid;
1468         hinfo->nid = per_cvt->cvt_nid;
1469
1470         snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1471                             AC_VERB_SET_CONNECT_SEL,
1472                             mux_idx);
1473
1474         /* configure unused pins to choose other converters */
1475         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1476                 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1477
1478         snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1479
1480         /* Initially set the converter's capabilities */
1481         hinfo->channels_min = per_cvt->channels_min;
1482         hinfo->channels_max = per_cvt->channels_max;
1483         hinfo->rates = per_cvt->rates;
1484         hinfo->formats = per_cvt->formats;
1485         hinfo->maxbps = per_cvt->maxbps;
1486
1487         /* Restrict capabilities by ELD if this isn't disabled */
1488         if (!static_hdmi_pcm && eld->eld_valid) {
1489                 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1490                 if (hinfo->channels_min > hinfo->channels_max ||
1491                     !hinfo->rates || !hinfo->formats) {
1492                         per_cvt->assigned = 0;
1493                         hinfo->nid = 0;
1494                         snd_hda_spdif_ctls_unassign(codec, pin_idx);
1495                         return -ENODEV;
1496                 }
1497         }
1498
1499         /* Store the updated parameters */
1500         runtime->hw.channels_min = hinfo->channels_min;
1501         runtime->hw.channels_max = hinfo->channels_max;
1502         runtime->hw.formats = hinfo->formats;
1503         runtime->hw.rates = hinfo->rates;
1504
1505         snd_pcm_hw_constraint_step(substream->runtime, 0,
1506                                    SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1507         return 0;
1508 }
1509
1510 /*
1511  * HDA/HDMI auto parsing
1512  */
1513 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1514 {
1515         struct hdmi_spec *spec = codec->spec;
1516         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1517         hda_nid_t pin_nid = per_pin->pin_nid;
1518
1519         if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1520                 codec_warn(codec,
1521                            "HDMI: pin %d wcaps %#x does not support connection list\n",
1522                            pin_nid, get_wcaps(codec, pin_nid));
1523                 return -EINVAL;
1524         }
1525
1526         per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1527                                                         per_pin->mux_nids,
1528                                                         HDA_MAX_CONNECTIONS);
1529
1530         return 0;
1531 }
1532
1533 /* update per_pin ELD from the given new ELD;
1534  * setup info frame and notification accordingly
1535  */
1536 static void update_eld(struct hda_codec *codec,
1537                        struct hdmi_spec_per_pin *per_pin,
1538                        struct hdmi_eld *eld)
1539 {
1540         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1541         bool old_eld_valid = pin_eld->eld_valid;
1542         bool eld_changed;
1543
1544         if (eld->eld_valid)
1545                 snd_hdmi_show_eld(codec, &eld->info);
1546
1547         eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1548         if (eld->eld_valid && pin_eld->eld_valid)
1549                 if (pin_eld->eld_size != eld->eld_size ||
1550                     memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1551                            eld->eld_size) != 0)
1552                         eld_changed = true;
1553
1554         pin_eld->eld_valid = eld->eld_valid;
1555         pin_eld->eld_size = eld->eld_size;
1556         if (eld->eld_valid)
1557                 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1558         pin_eld->info = eld->info;
1559
1560         /*
1561          * Re-setup pin and infoframe. This is needed e.g. when
1562          * - sink is first plugged-in
1563          * - transcoder can change during stream playback on Haswell
1564          *   and this can make HW reset converter selection on a pin.
1565          */
1566         if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1567                 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1568                         intel_verify_pin_cvt_connect(codec, per_pin);
1569                         intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1570                                                      per_pin->mux_idx);
1571                 }
1572
1573                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1574         }
1575
1576         if (eld_changed)
1577                 snd_ctl_notify(codec->card,
1578                                SNDRV_CTL_EVENT_MASK_VALUE |
1579                                SNDRV_CTL_EVENT_MASK_INFO,
1580                                &per_pin->eld_ctl->id);
1581 }
1582
1583 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1584 {
1585         struct hda_jack_tbl *jack;
1586         struct hda_codec *codec = per_pin->codec;
1587         struct hdmi_spec *spec = codec->spec;
1588         struct hdmi_eld *eld = &spec->temp_eld;
1589         struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1590         hda_nid_t pin_nid = per_pin->pin_nid;
1591         /*
1592          * Always execute a GetPinSense verb here, even when called from
1593          * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1594          * response's PD bit is not the real PD value, but indicates that
1595          * the real PD value changed. An older version of the HD-audio
1596          * specification worked this way. Hence, we just ignore the data in
1597          * the unsolicited response to avoid custom WARs.
1598          */
1599         int present;
1600         bool ret;
1601
1602         snd_hda_power_up_pm(codec);
1603         present = snd_hda_pin_sense(codec, pin_nid);
1604
1605         mutex_lock(&per_pin->lock);
1606         pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1607         if (pin_eld->monitor_present)
1608                 eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1609         else
1610                 eld->eld_valid = false;
1611
1612         codec_dbg(codec,
1613                 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1614                 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1615
1616         if (eld->eld_valid) {
1617                 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1618                                                      &eld->eld_size) < 0)
1619                         eld->eld_valid = false;
1620                 else {
1621                         if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1622                                                     eld->eld_size) < 0)
1623                                 eld->eld_valid = false;
1624                 }
1625         }
1626
1627         if (!eld->eld_valid && repoll)
1628                 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1629         else
1630                 update_eld(codec, per_pin, eld);
1631
1632         ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1633
1634         jack = snd_hda_jack_tbl_get(codec, pin_nid);
1635         if (jack)
1636                 jack->block_report = !ret;
1637
1638         mutex_unlock(&per_pin->lock);
1639         snd_hda_power_down_pm(codec);
1640         return ret;
1641 }
1642
1643 static void hdmi_repoll_eld(struct work_struct *work)
1644 {
1645         struct hdmi_spec_per_pin *per_pin =
1646         container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1647
1648         if (per_pin->repoll_count++ > 6)
1649                 per_pin->repoll_count = 0;
1650
1651         if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1652                 snd_hda_jack_report_sync(per_pin->codec);
1653 }
1654
1655 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1656                                              hda_nid_t nid);
1657
1658 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1659 {
1660         struct hdmi_spec *spec = codec->spec;
1661         unsigned int caps, config;
1662         int pin_idx;
1663         struct hdmi_spec_per_pin *per_pin;
1664         int err;
1665
1666         caps = snd_hda_query_pin_caps(codec, pin_nid);
1667         if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1668                 return 0;
1669
1670         config = snd_hda_codec_get_pincfg(codec, pin_nid);
1671         if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1672                 return 0;
1673
1674         if (is_haswell_plus(codec))
1675                 intel_haswell_fixup_connect_list(codec, pin_nid);
1676
1677         pin_idx = spec->num_pins;
1678         per_pin = snd_array_new(&spec->pins);
1679         if (!per_pin)
1680                 return -ENOMEM;
1681
1682         per_pin->pin_nid = pin_nid;
1683         per_pin->non_pcm = false;
1684
1685         err = hdmi_read_pin_conn(codec, pin_idx);
1686         if (err < 0)
1687                 return err;
1688
1689         spec->num_pins++;
1690
1691         return 0;
1692 }
1693
1694 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1695 {
1696         struct hdmi_spec *spec = codec->spec;
1697         struct hdmi_spec_per_cvt *per_cvt;
1698         unsigned int chans;
1699         int err;
1700
1701         chans = get_wcaps(codec, cvt_nid);
1702         chans = get_wcaps_channels(chans);
1703
1704         per_cvt = snd_array_new(&spec->cvts);
1705         if (!per_cvt)
1706                 return -ENOMEM;
1707
1708         per_cvt->cvt_nid = cvt_nid;
1709         per_cvt->channels_min = 2;
1710         if (chans <= 16) {
1711                 per_cvt->channels_max = chans;
1712                 if (chans > spec->channels_max)
1713                         spec->channels_max = chans;
1714         }
1715
1716         err = snd_hda_query_supported_pcm(codec, cvt_nid,
1717                                           &per_cvt->rates,
1718                                           &per_cvt->formats,
1719                                           &per_cvt->maxbps);
1720         if (err < 0)
1721                 return err;
1722
1723         if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1724                 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1725         spec->num_cvts++;
1726
1727         return 0;
1728 }
1729
1730 static int hdmi_parse_codec(struct hda_codec *codec)
1731 {
1732         hda_nid_t nid;
1733         int i, nodes;
1734
1735         nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1736         if (!nid || nodes < 0) {
1737                 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1738                 return -EINVAL;
1739         }
1740
1741         for (i = 0; i < nodes; i++, nid++) {
1742                 unsigned int caps;
1743                 unsigned int type;
1744
1745                 caps = get_wcaps(codec, nid);
1746                 type = get_wcaps_type(caps);
1747
1748                 if (!(caps & AC_WCAP_DIGITAL))
1749                         continue;
1750
1751                 switch (type) {
1752                 case AC_WID_AUD_OUT:
1753                         hdmi_add_cvt(codec, nid);
1754                         break;
1755                 case AC_WID_PIN:
1756                         hdmi_add_pin(codec, nid);
1757                         break;
1758                 }
1759         }
1760
1761         return 0;
1762 }
1763
1764 /*
1765  */
1766 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1767 {
1768         struct hda_spdif_out *spdif;
1769         bool non_pcm;
1770
1771         mutex_lock(&codec->spdif_mutex);
1772         spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1773         non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1774         mutex_unlock(&codec->spdif_mutex);
1775         return non_pcm;
1776 }
1777
1778 /* There is a fixed mapping between audio pin node and display port
1779  * on current Intel platforms:
1780  * Pin Widget 5 - PORT B (port = 1 in i915 driver)
1781  * Pin Widget 6 - PORT C (port = 2 in i915 driver)
1782  * Pin Widget 7 - PORT D (port = 3 in i915 driver)
1783  */
1784 static int intel_pin2port(hda_nid_t pin_nid)
1785 {
1786         return pin_nid - 4;
1787 }
1788
1789 /*
1790  * HDMI callbacks
1791  */
1792
1793 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1794                                            struct hda_codec *codec,
1795                                            unsigned int stream_tag,
1796                                            unsigned int format,
1797                                            struct snd_pcm_substream *substream)
1798 {
1799         hda_nid_t cvt_nid = hinfo->nid;
1800         struct hdmi_spec *spec = codec->spec;
1801         int pin_idx = hinfo_to_pin_index(codec, hinfo);
1802         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1803         hda_nid_t pin_nid = per_pin->pin_nid;
1804         struct snd_pcm_runtime *runtime = substream->runtime;
1805         struct i915_audio_component *acomp = codec->bus->core.audio_component;
1806         bool non_pcm;
1807         int pinctl;
1808
1809         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1810                 /* Verify pin:cvt selections to avoid silent audio after S3.
1811                  * After S3, the audio driver restores pin:cvt selections
1812                  * but this can happen before gfx is ready and such selection
1813                  * is overlooked by HW. Thus multiple pins can share a same
1814                  * default convertor and mute control will affect each other,
1815                  * which can cause a resumed audio playback become silent
1816                  * after S3.
1817                  */
1818                 intel_verify_pin_cvt_connect(codec, per_pin);
1819                 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1820         }
1821
1822         /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1823         /* Todo: add DP1.2 MST audio support later */
1824         if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
1825                 acomp->ops->sync_audio_rate(acomp->dev,
1826                                 intel_pin2port(pin_nid),
1827                                 runtime->rate);
1828
1829         non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1830         mutex_lock(&per_pin->lock);
1831         per_pin->channels = substream->runtime->channels;
1832         per_pin->setup = true;
1833
1834         hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1835         mutex_unlock(&per_pin->lock);
1836
1837         if (spec->dyn_pin_out) {
1838                 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1839                                             AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1840                 snd_hda_codec_write(codec, pin_nid, 0,
1841                                     AC_VERB_SET_PIN_WIDGET_CONTROL,
1842                                     pinctl | PIN_OUT);
1843         }
1844
1845         return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1846 }
1847
1848 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1849                                              struct hda_codec *codec,
1850                                              struct snd_pcm_substream *substream)
1851 {
1852         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1853         return 0;
1854 }
1855
1856 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1857                           struct hda_codec *codec,
1858                           struct snd_pcm_substream *substream)
1859 {
1860         struct hdmi_spec *spec = codec->spec;
1861         int cvt_idx, pin_idx;
1862         struct hdmi_spec_per_cvt *per_cvt;
1863         struct hdmi_spec_per_pin *per_pin;
1864         int pinctl;
1865
1866         if (hinfo->nid) {
1867                 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1868                 if (snd_BUG_ON(cvt_idx < 0))
1869                         return -EINVAL;
1870                 per_cvt = get_cvt(spec, cvt_idx);
1871
1872                 snd_BUG_ON(!per_cvt->assigned);
1873                 per_cvt->assigned = 0;
1874                 hinfo->nid = 0;
1875
1876                 pin_idx = hinfo_to_pin_index(codec, hinfo);
1877                 if (snd_BUG_ON(pin_idx < 0))
1878                         return -EINVAL;
1879                 per_pin = get_pin(spec, pin_idx);
1880
1881                 if (spec->dyn_pin_out) {
1882                         pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1883                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1884                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1885                                             AC_VERB_SET_PIN_WIDGET_CONTROL,
1886                                             pinctl & ~PIN_OUT);
1887                 }
1888
1889                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
1890
1891                 mutex_lock(&per_pin->lock);
1892                 per_pin->chmap_set = false;
1893                 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1894
1895                 per_pin->setup = false;
1896                 per_pin->channels = 0;
1897                 mutex_unlock(&per_pin->lock);
1898         }
1899
1900         return 0;
1901 }
1902
1903 static const struct hda_pcm_ops generic_ops = {
1904         .open = hdmi_pcm_open,
1905         .close = hdmi_pcm_close,
1906         .prepare = generic_hdmi_playback_pcm_prepare,
1907         .cleanup = generic_hdmi_playback_pcm_cleanup,
1908 };
1909
1910 /*
1911  * ALSA API channel-map control callbacks
1912  */
1913 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1914                                struct snd_ctl_elem_info *uinfo)
1915 {
1916         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1917         struct hda_codec *codec = info->private_data;
1918         struct hdmi_spec *spec = codec->spec;
1919         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1920         uinfo->count = spec->channels_max;
1921         uinfo->value.integer.min = 0;
1922         uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1923         return 0;
1924 }
1925
1926 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1927                                                   int channels)
1928 {
1929         /* If the speaker allocation matches the channel count, it is OK.*/
1930         if (cap->channels != channels)
1931                 return -1;
1932
1933         /* all channels are remappable freely */
1934         return SNDRV_CTL_TLVT_CHMAP_VAR;
1935 }
1936
1937 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1938                                         unsigned int *chmap, int channels)
1939 {
1940         int count = 0;
1941         int c;
1942
1943         for (c = 7; c >= 0; c--) {
1944                 int spk = cap->speakers[c];
1945                 if (!spk)
1946                         continue;
1947
1948                 chmap[count++] = spk_to_chmap(spk);
1949         }
1950
1951         WARN_ON(count != channels);
1952 }
1953
1954 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1955                               unsigned int size, unsigned int __user *tlv)
1956 {
1957         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1958         struct hda_codec *codec = info->private_data;
1959         struct hdmi_spec *spec = codec->spec;
1960         unsigned int __user *dst;
1961         int chs, count = 0;
1962
1963         if (size < 8)
1964                 return -ENOMEM;
1965         if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1966                 return -EFAULT;
1967         size -= 8;
1968         dst = tlv + 2;
1969         for (chs = 2; chs <= spec->channels_max; chs++) {
1970                 int i;
1971                 struct cea_channel_speaker_allocation *cap;
1972                 cap = channel_allocations;
1973                 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1974                         int chs_bytes = chs * 4;
1975                         int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1976                         unsigned int tlv_chmap[8];
1977
1978                         if (type < 0)
1979                                 continue;
1980                         if (size < 8)
1981                                 return -ENOMEM;
1982                         if (put_user(type, dst) ||
1983                             put_user(chs_bytes, dst + 1))
1984                                 return -EFAULT;
1985                         dst += 2;
1986                         size -= 8;
1987                         count += 8;
1988                         if (size < chs_bytes)
1989                                 return -ENOMEM;
1990                         size -= chs_bytes;
1991                         count += chs_bytes;
1992                         spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1993                         if (copy_to_user(dst, tlv_chmap, chs_bytes))
1994                                 return -EFAULT;
1995                         dst += chs;
1996                 }
1997         }
1998         if (put_user(count, tlv + 1))
1999                 return -EFAULT;
2000         return 0;
2001 }
2002
2003 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
2004                               struct snd_ctl_elem_value *ucontrol)
2005 {
2006         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2007         struct hda_codec *codec = info->private_data;
2008         struct hdmi_spec *spec = codec->spec;
2009         int pin_idx = kcontrol->private_value;
2010         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2011         int i;
2012
2013         for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
2014                 ucontrol->value.integer.value[i] = per_pin->chmap[i];
2015         return 0;
2016 }
2017
2018 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
2019                               struct snd_ctl_elem_value *ucontrol)
2020 {
2021         struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
2022         struct hda_codec *codec = info->private_data;
2023         struct hdmi_spec *spec = codec->spec;
2024         int pin_idx = kcontrol->private_value;
2025         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2026         unsigned int ctl_idx;
2027         struct snd_pcm_substream *substream;
2028         unsigned char chmap[8];
2029         int i, err, ca, prepared = 0;
2030
2031         ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2032         substream = snd_pcm_chmap_substream(info, ctl_idx);
2033         if (!substream || !substream->runtime)
2034                 return 0; /* just for avoiding error from alsactl restore */
2035         switch (substream->runtime->status->state) {
2036         case SNDRV_PCM_STATE_OPEN:
2037         case SNDRV_PCM_STATE_SETUP:
2038                 break;
2039         case SNDRV_PCM_STATE_PREPARED:
2040                 prepared = 1;
2041                 break;
2042         default:
2043                 return -EBUSY;
2044         }
2045         memset(chmap, 0, sizeof(chmap));
2046         for (i = 0; i < ARRAY_SIZE(chmap); i++)
2047                 chmap[i] = ucontrol->value.integer.value[i];
2048         if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2049                 return 0;
2050         ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2051         if (ca < 0)
2052                 return -EINVAL;
2053         if (spec->ops.chmap_validate) {
2054                 err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2055                 if (err)
2056                         return err;
2057         }
2058         mutex_lock(&per_pin->lock);
2059         per_pin->chmap_set = true;
2060         memcpy(per_pin->chmap, chmap, sizeof(chmap));
2061         if (prepared)
2062                 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2063         mutex_unlock(&per_pin->lock);
2064
2065         return 0;
2066 }
2067
2068 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2069 {
2070         struct hdmi_spec *spec = codec->spec;
2071         int pin_idx;
2072
2073         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2074                 struct hda_pcm *info;
2075                 struct hda_pcm_stream *pstr;
2076
2077                 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2078                 if (!info)
2079                         return -ENOMEM;
2080                 spec->pcm_rec[pin_idx] = info;
2081                 info->pcm_type = HDA_PCM_TYPE_HDMI;
2082                 info->own_chmap = true;
2083
2084                 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2085                 pstr->substreams = 1;
2086                 pstr->ops = generic_ops;
2087                 /* other pstr fields are set in open */
2088         }
2089
2090         return 0;
2091 }
2092
2093 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2094 {
2095         char hdmi_str[32] = "HDMI/DP";
2096         struct hdmi_spec *spec = codec->spec;
2097         struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2098         int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2099         bool phantom_jack;
2100
2101         if (pcmdev > 0)
2102                 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2103         phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2104         if (phantom_jack)
2105                 strncat(hdmi_str, " Phantom",
2106                         sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2107
2108         return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2109                                      phantom_jack);
2110 }
2111
2112 static int generic_hdmi_build_controls(struct hda_codec *codec)
2113 {
2114         struct hdmi_spec *spec = codec->spec;
2115         int err;
2116         int pin_idx;
2117
2118         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2119                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2120
2121                 err = generic_hdmi_build_jack(codec, pin_idx);
2122                 if (err < 0)
2123                         return err;
2124
2125                 err = snd_hda_create_dig_out_ctls(codec,
2126                                                   per_pin->pin_nid,
2127                                                   per_pin->mux_nids[0],
2128                                                   HDA_PCM_TYPE_HDMI);
2129                 if (err < 0)
2130                         return err;
2131                 snd_hda_spdif_ctls_unassign(codec, pin_idx);
2132
2133                 /* add control for ELD Bytes */
2134                 err = hdmi_create_eld_ctl(codec, pin_idx,
2135                                           get_pcm_rec(spec, pin_idx)->device);
2136
2137                 if (err < 0)
2138                         return err;
2139
2140                 hdmi_present_sense(per_pin, 0);
2141         }
2142
2143         /* add channel maps */
2144         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2145                 struct hda_pcm *pcm;
2146                 struct snd_pcm_chmap *chmap;
2147                 struct snd_kcontrol *kctl;
2148                 int i;
2149
2150                 pcm = spec->pcm_rec[pin_idx];
2151                 if (!pcm || !pcm->pcm)
2152                         break;
2153                 err = snd_pcm_add_chmap_ctls(pcm->pcm,
2154                                              SNDRV_PCM_STREAM_PLAYBACK,
2155                                              NULL, 0, pin_idx, &chmap);
2156                 if (err < 0)
2157                         return err;
2158                 /* override handlers */
2159                 chmap->private_data = codec;
2160                 kctl = chmap->kctl;
2161                 for (i = 0; i < kctl->count; i++)
2162                         kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2163                 kctl->info = hdmi_chmap_ctl_info;
2164                 kctl->get = hdmi_chmap_ctl_get;
2165                 kctl->put = hdmi_chmap_ctl_put;
2166                 kctl->tlv.c = hdmi_chmap_ctl_tlv;
2167         }
2168
2169         return 0;
2170 }
2171
2172 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2173 {
2174         struct hdmi_spec *spec = codec->spec;
2175         int pin_idx;
2176
2177         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2178                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2179
2180                 per_pin->codec = codec;
2181                 mutex_init(&per_pin->lock);
2182                 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2183                 eld_proc_new(per_pin, pin_idx);
2184         }
2185         return 0;
2186 }
2187
2188 static int generic_hdmi_init(struct hda_codec *codec)
2189 {
2190         struct hdmi_spec *spec = codec->spec;
2191         int pin_idx;
2192
2193         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2194                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2195                 hda_nid_t pin_nid = per_pin->pin_nid;
2196
2197                 hdmi_init_pin(codec, pin_nid);
2198                 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2199                         codec->jackpoll_interval > 0 ? jack_callback : NULL);
2200         }
2201         return 0;
2202 }
2203
2204 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2205 {
2206         snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2207         snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2208 }
2209
2210 static void hdmi_array_free(struct hdmi_spec *spec)
2211 {
2212         snd_array_free(&spec->pins);
2213         snd_array_free(&spec->cvts);
2214 }
2215
2216 static void generic_hdmi_free(struct hda_codec *codec)
2217 {
2218         struct hdmi_spec *spec = codec->spec;
2219         int pin_idx;
2220
2221         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2222                 snd_hdac_i915_register_notifier(NULL);
2223
2224         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2225                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2226
2227                 cancel_delayed_work_sync(&per_pin->work);
2228                 eld_proc_free(per_pin);
2229         }
2230
2231         hdmi_array_free(spec);
2232         kfree(spec);
2233 }
2234
2235 #ifdef CONFIG_PM
2236 static int generic_hdmi_resume(struct hda_codec *codec)
2237 {
2238         struct hdmi_spec *spec = codec->spec;
2239         int pin_idx;
2240
2241         codec->patch_ops.init(codec);
2242         regcache_sync(codec->core.regmap);
2243
2244         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2245                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2246                 hdmi_present_sense(per_pin, 1);
2247         }
2248         return 0;
2249 }
2250 #endif
2251
2252 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2253         .init                   = generic_hdmi_init,
2254         .free                   = generic_hdmi_free,
2255         .build_pcms             = generic_hdmi_build_pcms,
2256         .build_controls         = generic_hdmi_build_controls,
2257         .unsol_event            = hdmi_unsol_event,
2258 #ifdef CONFIG_PM
2259         .resume                 = generic_hdmi_resume,
2260 #endif
2261 };
2262
2263 static const struct hdmi_ops generic_standard_hdmi_ops = {
2264         .pin_get_eld                            = snd_hdmi_get_eld,
2265         .pin_get_slot_channel                   = hdmi_pin_get_slot_channel,
2266         .pin_set_slot_channel                   = hdmi_pin_set_slot_channel,
2267         .pin_setup_infoframe                    = hdmi_pin_setup_infoframe,
2268         .pin_hbr_setup                          = hdmi_pin_hbr_setup,
2269         .setup_stream                           = hdmi_setup_stream,
2270         .chmap_cea_alloc_validate_get_type      = hdmi_chmap_cea_alloc_validate_get_type,
2271         .cea_alloc_to_tlv_chmap                 = hdmi_cea_alloc_to_tlv_chmap,
2272 };
2273
2274
2275 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2276                                              hda_nid_t nid)
2277 {
2278         struct hdmi_spec *spec = codec->spec;
2279         hda_nid_t conns[4];
2280         int nconns;
2281
2282         nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2283         if (nconns == spec->num_cvts &&
2284             !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2285                 return;
2286
2287         /* override pins connection list */
2288         codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2289         snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2290 }
2291
2292 #define INTEL_VENDOR_NID 0x08
2293 #define INTEL_GET_VENDOR_VERB 0xf81
2294 #define INTEL_SET_VENDOR_VERB 0x781
2295 #define INTEL_EN_DP12                   0x02 /* enable DP 1.2 features */
2296 #define INTEL_EN_ALL_PIN_CVTS   0x01 /* enable 2nd & 3rd pins and convertors */
2297
2298 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2299                                           bool update_tree)
2300 {
2301         unsigned int vendor_param;
2302
2303         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2304                                 INTEL_GET_VENDOR_VERB, 0);
2305         if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2306                 return;
2307
2308         vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2309         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2310                                 INTEL_SET_VENDOR_VERB, vendor_param);
2311         if (vendor_param == -1)
2312                 return;
2313
2314         if (update_tree)
2315                 snd_hda_codec_update_widgets(codec);
2316 }
2317
2318 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2319 {
2320         unsigned int vendor_param;
2321
2322         vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2323                                 INTEL_GET_VENDOR_VERB, 0);
2324         if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2325                 return;
2326
2327         /* enable DP1.2 mode */
2328         vendor_param |= INTEL_EN_DP12;
2329         snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2330         snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2331                                 INTEL_SET_VENDOR_VERB, vendor_param);
2332 }
2333
2334 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2335  * Otherwise you may get severe h/w communication errors.
2336  */
2337 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2338                                 unsigned int power_state)
2339 {
2340         if (power_state == AC_PWRST_D0) {
2341                 intel_haswell_enable_all_pins(codec, false);
2342                 intel_haswell_fixup_enable_dp12(codec);
2343         }
2344
2345         snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2346         snd_hda_codec_set_power_to_all(codec, fg, power_state);
2347 }
2348
2349 static void intel_pin_eld_notify(void *audio_ptr, int port)
2350 {
2351         struct hda_codec *codec = audio_ptr;
2352         int pin_nid = port + 0x04;
2353
2354         /* skip notification during system suspend (but not in runtime PM);
2355          * the state will be updated at resume
2356          */
2357         if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2358                 return;
2359         /* ditto during suspend/resume process itself */
2360         if (atomic_read(&(codec)->core.in_pm))
2361                 return;
2362
2363         check_presence_and_report(codec, pin_nid);
2364 }
2365
2366 static int patch_generic_hdmi(struct hda_codec *codec)
2367 {
2368         struct hdmi_spec *spec;
2369
2370         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2371         if (spec == NULL)
2372                 return -ENOMEM;
2373
2374         spec->ops = generic_standard_hdmi_ops;
2375         codec->spec = spec;
2376         hdmi_array_init(spec, 4);
2377
2378         if (is_haswell_plus(codec)) {
2379                 intel_haswell_enable_all_pins(codec, true);
2380                 intel_haswell_fixup_enable_dp12(codec);
2381         }
2382
2383         /* For Valleyview/Cherryview, only the display codec is in the display
2384          * power well and can use link_power ops to request/release the power.
2385          * For Haswell/Broadwell, the controller is also in the power well and
2386          * can cover the codec power request, and so need not set this flag.
2387          * For previous platforms, there is no such power well feature.
2388          */
2389         if (is_valleyview_plus(codec) || is_skylake(codec) ||
2390                         is_broxton(codec))
2391                 codec->core.link_power_control = 1;
2392
2393         if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
2394                 codec->depop_delay = 0;
2395                 spec->i915_audio_ops.audio_ptr = codec;
2396                 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2397                 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2398         }
2399
2400         if (hdmi_parse_codec(codec) < 0) {
2401                 codec->spec = NULL;
2402                 kfree(spec);
2403                 return -EINVAL;
2404         }
2405         codec->patch_ops = generic_hdmi_patch_ops;
2406         if (is_haswell_plus(codec)) {
2407                 codec->patch_ops.set_power_state = haswell_set_power_state;
2408                 codec->dp_mst = true;
2409         }
2410
2411         /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2412         if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2413                 codec->auto_runtime_pm = 1;
2414
2415         generic_hdmi_init_per_pins(codec);
2416
2417         init_channel_allocations();
2418
2419         return 0;
2420 }
2421
2422 /*
2423  * Shared non-generic implementations
2424  */
2425
2426 static int simple_playback_build_pcms(struct hda_codec *codec)
2427 {
2428         struct hdmi_spec *spec = codec->spec;
2429         struct hda_pcm *info;
2430         unsigned int chans;
2431         struct hda_pcm_stream *pstr;
2432         struct hdmi_spec_per_cvt *per_cvt;
2433
2434         per_cvt = get_cvt(spec, 0);
2435         chans = get_wcaps(codec, per_cvt->cvt_nid);
2436         chans = get_wcaps_channels(chans);
2437
2438         info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2439         if (!info)
2440                 return -ENOMEM;
2441         spec->pcm_rec[0] = info;
2442         info->pcm_type = HDA_PCM_TYPE_HDMI;
2443         pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2444         *pstr = spec->pcm_playback;
2445         pstr->nid = per_cvt->cvt_nid;
2446         if (pstr->channels_max <= 2 && chans && chans <= 16)
2447                 pstr->channels_max = chans;
2448
2449         return 0;
2450 }
2451
2452 /* unsolicited event for jack sensing */
2453 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2454                                     unsigned int res)
2455 {
2456         snd_hda_jack_set_dirty_all(codec);
2457         snd_hda_jack_report_sync(codec);
2458 }
2459
2460 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2461  * as long as spec->pins[] is set correctly
2462  */
2463 #define simple_hdmi_build_jack  generic_hdmi_build_jack
2464
2465 static int simple_playback_build_controls(struct hda_codec *codec)
2466 {
2467         struct hdmi_spec *spec = codec->spec;
2468         struct hdmi_spec_per_cvt *per_cvt;
2469         int err;
2470
2471         per_cvt = get_cvt(spec, 0);
2472         err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2473                                           per_cvt->cvt_nid,
2474                                           HDA_PCM_TYPE_HDMI);
2475         if (err < 0)
2476                 return err;
2477         return simple_hdmi_build_jack(codec, 0);
2478 }
2479
2480 static int simple_playback_init(struct hda_codec *codec)
2481 {
2482         struct hdmi_spec *spec = codec->spec;
2483         struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2484         hda_nid_t pin = per_pin->pin_nid;
2485
2486         snd_hda_codec_write(codec, pin, 0,
2487                             AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2488         /* some codecs require to unmute the pin */
2489         if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2490                 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2491                                     AMP_OUT_UNMUTE);
2492         snd_hda_jack_detect_enable(codec, pin);
2493         return 0;
2494 }
2495
2496 static void simple_playback_free(struct hda_codec *codec)
2497 {
2498         struct hdmi_spec *spec = codec->spec;
2499
2500         hdmi_array_free(spec);
2501         kfree(spec);
2502 }
2503
2504 /*
2505  * Nvidia specific implementations
2506  */
2507
2508 #define Nv_VERB_SET_Channel_Allocation          0xF79
2509 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2510 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2511 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2512
2513 #define nvhdmi_master_con_nid_7x        0x04
2514 #define nvhdmi_master_pin_nid_7x        0x05
2515
2516 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2517         /*front, rear, clfe, rear_surr */
2518         0x6, 0x8, 0xa, 0xc,
2519 };
2520
2521 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2522         /* set audio protect on */
2523         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2524         /* enable digital output on pin widget */
2525         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2526         {} /* terminator */
2527 };
2528
2529 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2530         /* set audio protect on */
2531         { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2532         /* enable digital output on pin widget */
2533         { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2534         { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2535         { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2536         { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2537         { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2538         {} /* terminator */
2539 };
2540
2541 #ifdef LIMITED_RATE_FMT_SUPPORT
2542 /* support only the safe format and rate */
2543 #define SUPPORTED_RATES         SNDRV_PCM_RATE_48000
2544 #define SUPPORTED_MAXBPS        16
2545 #define SUPPORTED_FORMATS       SNDRV_PCM_FMTBIT_S16_LE
2546 #else
2547 /* support all rates and formats */
2548 #define SUPPORTED_RATES \
2549         (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2550         SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2551          SNDRV_PCM_RATE_192000)
2552 #define SUPPORTED_MAXBPS        24
2553 #define SUPPORTED_FORMATS \
2554         (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2555 #endif
2556
2557 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2558 {
2559         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2560         return 0;
2561 }
2562
2563 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2564 {
2565         snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2566         return 0;
2567 }
2568
2569 static unsigned int channels_2_6_8[] = {
2570         2, 6, 8
2571 };
2572
2573 static unsigned int channels_2_8[] = {
2574         2, 8
2575 };
2576
2577 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2578         .count = ARRAY_SIZE(channels_2_6_8),
2579         .list = channels_2_6_8,
2580         .mask = 0,
2581 };
2582
2583 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2584         .count = ARRAY_SIZE(channels_2_8),
2585         .list = channels_2_8,
2586         .mask = 0,
2587 };
2588
2589 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2590                                     struct hda_codec *codec,
2591                                     struct snd_pcm_substream *substream)
2592 {
2593         struct hdmi_spec *spec = codec->spec;
2594         struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2595
2596         switch (codec->preset->vendor_id) {
2597         case 0x10de0002:
2598         case 0x10de0003:
2599         case 0x10de0005:
2600         case 0x10de0006:
2601                 hw_constraints_channels = &hw_constraints_2_8_channels;
2602                 break;
2603         case 0x10de0007:
2604                 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2605                 break;
2606         default:
2607                 break;
2608         }
2609
2610         if (hw_constraints_channels != NULL) {
2611                 snd_pcm_hw_constraint_list(substream->runtime, 0,
2612                                 SNDRV_PCM_HW_PARAM_CHANNELS,
2613                                 hw_constraints_channels);
2614         } else {
2615                 snd_pcm_hw_constraint_step(substream->runtime, 0,
2616                                            SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2617         }
2618
2619         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2620 }
2621
2622 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2623                                      struct hda_codec *codec,
2624                                      struct snd_pcm_substream *substream)
2625 {
2626         struct hdmi_spec *spec = codec->spec;
2627         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2628 }
2629
2630 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2631                                        struct hda_codec *codec,
2632                                        unsigned int stream_tag,
2633                                        unsigned int format,
2634                                        struct snd_pcm_substream *substream)
2635 {
2636         struct hdmi_spec *spec = codec->spec;
2637         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2638                                              stream_tag, format, substream);
2639 }
2640
2641 static const struct hda_pcm_stream simple_pcm_playback = {
2642         .substreams = 1,
2643         .channels_min = 2,
2644         .channels_max = 2,
2645         .ops = {
2646                 .open = simple_playback_pcm_open,
2647                 .close = simple_playback_pcm_close,
2648                 .prepare = simple_playback_pcm_prepare
2649         },
2650 };
2651
2652 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2653         .build_controls = simple_playback_build_controls,
2654         .build_pcms = simple_playback_build_pcms,
2655         .init = simple_playback_init,
2656         .free = simple_playback_free,
2657         .unsol_event = simple_hdmi_unsol_event,
2658 };
2659
2660 static int patch_simple_hdmi(struct hda_codec *codec,
2661                              hda_nid_t cvt_nid, hda_nid_t pin_nid)
2662 {
2663         struct hdmi_spec *spec;
2664         struct hdmi_spec_per_cvt *per_cvt;
2665         struct hdmi_spec_per_pin *per_pin;
2666
2667         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2668         if (!spec)
2669                 return -ENOMEM;
2670
2671         codec->spec = spec;
2672         hdmi_array_init(spec, 1);
2673
2674         spec->multiout.num_dacs = 0;  /* no analog */
2675         spec->multiout.max_channels = 2;
2676         spec->multiout.dig_out_nid = cvt_nid;
2677         spec->num_cvts = 1;
2678         spec->num_pins = 1;
2679         per_pin = snd_array_new(&spec->pins);
2680         per_cvt = snd_array_new(&spec->cvts);
2681         if (!per_pin || !per_cvt) {
2682                 simple_playback_free(codec);
2683                 return -ENOMEM;
2684         }
2685         per_cvt->cvt_nid = cvt_nid;
2686         per_pin->pin_nid = pin_nid;
2687         spec->pcm_playback = simple_pcm_playback;
2688
2689         codec->patch_ops = simple_hdmi_patch_ops;
2690
2691         return 0;
2692 }
2693
2694 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2695                                                     int channels)
2696 {
2697         unsigned int chanmask;
2698         int chan = channels ? (channels - 1) : 1;
2699
2700         switch (channels) {
2701         default:
2702         case 0:
2703         case 2:
2704                 chanmask = 0x00;
2705                 break;
2706         case 4:
2707                 chanmask = 0x08;
2708                 break;
2709         case 6:
2710                 chanmask = 0x0b;
2711                 break;
2712         case 8:
2713                 chanmask = 0x13;
2714                 break;
2715         }
2716
2717         /* Set the audio infoframe channel allocation and checksum fields.  The
2718          * channel count is computed implicitly by the hardware. */
2719         snd_hda_codec_write(codec, 0x1, 0,
2720                         Nv_VERB_SET_Channel_Allocation, chanmask);
2721
2722         snd_hda_codec_write(codec, 0x1, 0,
2723                         Nv_VERB_SET_Info_Frame_Checksum,
2724                         (0x71 - chan - chanmask));
2725 }
2726
2727 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2728                                    struct hda_codec *codec,
2729                                    struct snd_pcm_substream *substream)
2730 {
2731         struct hdmi_spec *spec = codec->spec;
2732         int i;
2733
2734         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2735                         0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2736         for (i = 0; i < 4; i++) {
2737                 /* set the stream id */
2738                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2739                                 AC_VERB_SET_CHANNEL_STREAMID, 0);
2740                 /* set the stream format */
2741                 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2742                                 AC_VERB_SET_STREAM_FORMAT, 0);
2743         }
2744
2745         /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2746          * streams are disabled. */
2747         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2748
2749         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2750 }
2751
2752 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2753                                      struct hda_codec *codec,
2754                                      unsigned int stream_tag,
2755                                      unsigned int format,
2756                                      struct snd_pcm_substream *substream)
2757 {
2758         int chs;
2759         unsigned int dataDCC2, channel_id;
2760         int i;
2761         struct hdmi_spec *spec = codec->spec;
2762         struct hda_spdif_out *spdif;
2763         struct hdmi_spec_per_cvt *per_cvt;
2764
2765         mutex_lock(&codec->spdif_mutex);
2766         per_cvt = get_cvt(spec, 0);
2767         spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2768
2769         chs = substream->runtime->channels;
2770
2771         dataDCC2 = 0x2;
2772
2773         /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2774         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2775                 snd_hda_codec_write(codec,
2776                                 nvhdmi_master_con_nid_7x,
2777                                 0,
2778                                 AC_VERB_SET_DIGI_CONVERT_1,
2779                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2780
2781         /* set the stream id */
2782         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2783                         AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2784
2785         /* set the stream format */
2786         snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2787                         AC_VERB_SET_STREAM_FORMAT, format);
2788
2789         /* turn on again (if needed) */
2790         /* enable and set the channel status audio/data flag */
2791         if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2792                 snd_hda_codec_write(codec,
2793                                 nvhdmi_master_con_nid_7x,
2794                                 0,
2795                                 AC_VERB_SET_DIGI_CONVERT_1,
2796                                 spdif->ctls & 0xff);
2797                 snd_hda_codec_write(codec,
2798                                 nvhdmi_master_con_nid_7x,
2799                                 0,
2800                                 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2801         }
2802
2803         for (i = 0; i < 4; i++) {
2804                 if (chs == 2)
2805                         channel_id = 0;
2806                 else
2807                         channel_id = i * 2;
2808
2809                 /* turn off SPDIF once;
2810                  *otherwise the IEC958 bits won't be updated
2811                  */
2812                 if (codec->spdif_status_reset &&
2813                 (spdif->ctls & AC_DIG1_ENABLE))
2814                         snd_hda_codec_write(codec,
2815                                 nvhdmi_con_nids_7x[i],
2816                                 0,
2817                                 AC_VERB_SET_DIGI_CONVERT_1,
2818                                 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2819                 /* set the stream id */
2820                 snd_hda_codec_write(codec,
2821                                 nvhdmi_con_nids_7x[i],
2822                                 0,
2823                                 AC_VERB_SET_CHANNEL_STREAMID,
2824                                 (stream_tag << 4) | channel_id);
2825                 /* set the stream format */
2826                 snd_hda_codec_write(codec,
2827                                 nvhdmi_con_nids_7x[i],
2828                                 0,
2829                                 AC_VERB_SET_STREAM_FORMAT,
2830                                 format);
2831                 /* turn on again (if needed) */
2832                 /* enable and set the channel status audio/data flag */
2833                 if (codec->spdif_status_reset &&
2834                 (spdif->ctls & AC_DIG1_ENABLE)) {
2835                         snd_hda_codec_write(codec,
2836                                         nvhdmi_con_nids_7x[i],
2837                                         0,
2838                                         AC_VERB_SET_DIGI_CONVERT_1,
2839                                         spdif->ctls & 0xff);
2840                         snd_hda_codec_write(codec,
2841                                         nvhdmi_con_nids_7x[i],
2842                                         0,
2843                                         AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2844                 }
2845         }
2846
2847         nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2848
2849         mutex_unlock(&codec->spdif_mutex);
2850         return 0;
2851 }
2852
2853 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2854         .substreams = 1,
2855         .channels_min = 2,
2856         .channels_max = 8,
2857         .nid = nvhdmi_master_con_nid_7x,
2858         .rates = SUPPORTED_RATES,
2859         .maxbps = SUPPORTED_MAXBPS,
2860         .formats = SUPPORTED_FORMATS,
2861         .ops = {
2862                 .open = simple_playback_pcm_open,
2863                 .close = nvhdmi_8ch_7x_pcm_close,
2864                 .prepare = nvhdmi_8ch_7x_pcm_prepare
2865         },
2866 };
2867
2868 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2869 {
2870         struct hdmi_spec *spec;
2871         int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2872                                     nvhdmi_master_pin_nid_7x);
2873         if (err < 0)
2874                 return err;
2875
2876         codec->patch_ops.init = nvhdmi_7x_init_2ch;
2877         /* override the PCM rates, etc, as the codec doesn't give full list */
2878         spec = codec->spec;
2879         spec->pcm_playback.rates = SUPPORTED_RATES;
2880         spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2881         spec->pcm_playback.formats = SUPPORTED_FORMATS;
2882         return 0;
2883 }
2884
2885 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2886 {
2887         struct hdmi_spec *spec = codec->spec;
2888         int err = simple_playback_build_pcms(codec);
2889         if (!err) {
2890                 struct hda_pcm *info = get_pcm_rec(spec, 0);
2891                 info->own_chmap = true;
2892         }
2893         return err;
2894 }
2895
2896 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2897 {
2898         struct hdmi_spec *spec = codec->spec;
2899         struct hda_pcm *info;
2900         struct snd_pcm_chmap *chmap;
2901         int err;
2902
2903         err = simple_playback_build_controls(codec);
2904         if (err < 0)
2905                 return err;
2906
2907         /* add channel maps */
2908         info = get_pcm_rec(spec, 0);
2909         err = snd_pcm_add_chmap_ctls(info->pcm,
2910                                      SNDRV_PCM_STREAM_PLAYBACK,
2911                                      snd_pcm_alt_chmaps, 8, 0, &chmap);
2912         if (err < 0)
2913                 return err;
2914         switch (codec->preset->vendor_id) {
2915         case 0x10de0002:
2916         case 0x10de0003:
2917         case 0x10de0005:
2918         case 0x10de0006:
2919                 chmap->channel_mask = (1U << 2) | (1U << 8);
2920                 break;
2921         case 0x10de0007:
2922                 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2923         }
2924         return 0;
2925 }
2926
2927 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2928 {
2929         struct hdmi_spec *spec;
2930         int err = patch_nvhdmi_2ch(codec);
2931         if (err < 0)
2932                 return err;
2933         spec = codec->spec;
2934         spec->multiout.max_channels = 8;
2935         spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2936         codec->patch_ops.init = nvhdmi_7x_init_8ch;
2937         codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2938         codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2939
2940         /* Initialize the audio infoframe channel mask and checksum to something
2941          * valid */
2942         nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2943
2944         return 0;
2945 }
2946
2947 /*
2948  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2949  * - 0x10de0015
2950  * - 0x10de0040
2951  */
2952 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2953                                                     int channels)
2954 {
2955         if (cap->ca_index == 0x00 && channels == 2)
2956                 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2957
2958         return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2959 }
2960
2961 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2962 {
2963         if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2964                 return -EINVAL;
2965
2966         return 0;
2967 }
2968
2969 static int patch_nvhdmi(struct hda_codec *codec)
2970 {
2971         struct hdmi_spec *spec;
2972         int err;
2973
2974         err = patch_generic_hdmi(codec);
2975         if (err)
2976                 return err;
2977
2978         spec = codec->spec;
2979         spec->dyn_pin_out = true;
2980
2981         spec->ops.chmap_cea_alloc_validate_get_type =
2982                 nvhdmi_chmap_cea_alloc_validate_get_type;
2983         spec->ops.chmap_validate = nvhdmi_chmap_validate;
2984
2985         return 0;
2986 }
2987
2988 /*
2989  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2990  * accessed using vendor-defined verbs. These registers can be used for
2991  * interoperability between the HDA and HDMI drivers.
2992  */
2993
2994 /* Audio Function Group node */
2995 #define NVIDIA_AFG_NID 0x01
2996
2997 /*
2998  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2999  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3000  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3001  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3002  * additional bit (at position 30) to signal the validity of the format.
3003  *
3004  * | 31      | 30    | 29  16 | 15   0 |
3005  * +---------+-------+--------+--------+
3006  * | TRIGGER | VALID | UNUSED | FORMAT |
3007  * +-----------------------------------|
3008  *
3009  * Note that for the trigger bit to take effect it needs to change value
3010  * (i.e. it needs to be toggled).
3011  */
3012 #define NVIDIA_GET_SCRATCH0             0xfa6
3013 #define NVIDIA_SET_SCRATCH0_BYTE0       0xfa7
3014 #define NVIDIA_SET_SCRATCH0_BYTE1       0xfa8
3015 #define NVIDIA_SET_SCRATCH0_BYTE2       0xfa9
3016 #define NVIDIA_SET_SCRATCH0_BYTE3       0xfaa
3017 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3018 #define NVIDIA_SCRATCH_VALID   (1 << 6)
3019
3020 #define NVIDIA_GET_SCRATCH1             0xfab
3021 #define NVIDIA_SET_SCRATCH1_BYTE0       0xfac
3022 #define NVIDIA_SET_SCRATCH1_BYTE1       0xfad
3023 #define NVIDIA_SET_SCRATCH1_BYTE2       0xfae
3024 #define NVIDIA_SET_SCRATCH1_BYTE3       0xfaf
3025
3026 /*
3027  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3028  * the format is invalidated so that the HDMI codec can be disabled.
3029  */
3030 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3031 {
3032         unsigned int value;
3033
3034         /* bits [31:30] contain the trigger and valid bits */
3035         value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3036                                    NVIDIA_GET_SCRATCH0, 0);
3037         value = (value >> 24) & 0xff;
3038
3039         /* bits [15:0] are used to store the HDA format */
3040         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3041                             NVIDIA_SET_SCRATCH0_BYTE0,
3042                             (format >> 0) & 0xff);
3043         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3044                             NVIDIA_SET_SCRATCH0_BYTE1,
3045                             (format >> 8) & 0xff);
3046
3047         /* bits [16:24] are unused */
3048         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3049                             NVIDIA_SET_SCRATCH0_BYTE2, 0);
3050
3051         /*
3052          * Bit 30 signals that the data is valid and hence that HDMI audio can
3053          * be enabled.
3054          */
3055         if (format == 0)
3056                 value &= ~NVIDIA_SCRATCH_VALID;
3057         else
3058                 value |= NVIDIA_SCRATCH_VALID;
3059
3060         /*
3061          * Whenever the trigger bit is toggled, an interrupt is raised in the
3062          * HDMI codec. The HDMI driver will use that as trigger to update its
3063          * configuration.
3064          */
3065         value ^= NVIDIA_SCRATCH_TRIGGER;
3066
3067         snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3068                             NVIDIA_SET_SCRATCH0_BYTE3, value);
3069 }
3070
3071 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3072                                   struct hda_codec *codec,
3073                                   unsigned int stream_tag,
3074                                   unsigned int format,
3075                                   struct snd_pcm_substream *substream)
3076 {
3077         int err;
3078
3079         err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3080                                                 format, substream);
3081         if (err < 0)
3082                 return err;
3083
3084         /* notify the HDMI codec of the format change */
3085         tegra_hdmi_set_format(codec, format);
3086
3087         return 0;
3088 }
3089
3090 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3091                                   struct hda_codec *codec,
3092                                   struct snd_pcm_substream *substream)
3093 {
3094         /* invalidate the format in the HDMI codec */
3095         tegra_hdmi_set_format(codec, 0);
3096
3097         return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3098 }
3099
3100 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3101 {
3102         struct hdmi_spec *spec = codec->spec;
3103         unsigned int i;
3104
3105         for (i = 0; i < spec->num_pins; i++) {
3106                 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3107
3108                 if (pcm->pcm_type == type)
3109                         return pcm;
3110         }
3111
3112         return NULL;
3113 }
3114
3115 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3116 {
3117         struct hda_pcm_stream *stream;
3118         struct hda_pcm *pcm;
3119         int err;
3120
3121         err = generic_hdmi_build_pcms(codec);
3122         if (err < 0)
3123                 return err;
3124
3125         pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3126         if (!pcm)
3127                 return -ENODEV;
3128
3129         /*
3130          * Override ->prepare() and ->cleanup() operations to notify the HDMI
3131          * codec about format changes.
3132          */
3133         stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3134         stream->ops.prepare = tegra_hdmi_pcm_prepare;
3135         stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3136
3137         return 0;
3138 }
3139
3140 static int patch_tegra_hdmi(struct hda_codec *codec)
3141 {
3142         int err;
3143
3144         err = patch_generic_hdmi(codec);
3145         if (err)
3146                 return err;
3147
3148         codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3149
3150         return 0;
3151 }
3152
3153 /*
3154  * ATI/AMD-specific implementations
3155  */
3156
3157 #define is_amdhdmi_rev3_or_later(codec) \
3158         ((codec)->core.vendor_id == 0x1002aa01 && \
3159          ((codec)->core.revision_id & 0xff00) >= 0x0300)
3160 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3161
3162 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3163 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3164 #define ATI_VERB_SET_DOWNMIX_INFO       0x772
3165 #define ATI_VERB_SET_MULTICHANNEL_01    0x777
3166 #define ATI_VERB_SET_MULTICHANNEL_23    0x778
3167 #define ATI_VERB_SET_MULTICHANNEL_45    0x779
3168 #define ATI_VERB_SET_MULTICHANNEL_67    0x77a
3169 #define ATI_VERB_SET_HBR_CONTROL        0x77c
3170 #define ATI_VERB_SET_MULTICHANNEL_1     0x785
3171 #define ATI_VERB_SET_MULTICHANNEL_3     0x786
3172 #define ATI_VERB_SET_MULTICHANNEL_5     0x787
3173 #define ATI_VERB_SET_MULTICHANNEL_7     0x788
3174 #define ATI_VERB_SET_MULTICHANNEL_MODE  0x789
3175 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3176 #define ATI_VERB_GET_DOWNMIX_INFO       0xf72
3177 #define ATI_VERB_GET_MULTICHANNEL_01    0xf77
3178 #define ATI_VERB_GET_MULTICHANNEL_23    0xf78
3179 #define ATI_VERB_GET_MULTICHANNEL_45    0xf79
3180 #define ATI_VERB_GET_MULTICHANNEL_67    0xf7a
3181 #define ATI_VERB_GET_HBR_CONTROL        0xf7c
3182 #define ATI_VERB_GET_MULTICHANNEL_1     0xf85
3183 #define ATI_VERB_GET_MULTICHANNEL_3     0xf86
3184 #define ATI_VERB_GET_MULTICHANNEL_5     0xf87
3185 #define ATI_VERB_GET_MULTICHANNEL_7     0xf88
3186 #define ATI_VERB_GET_MULTICHANNEL_MODE  0xf89
3187
3188 /* AMD specific HDA cvt verbs */
3189 #define ATI_VERB_SET_RAMP_RATE          0x770
3190 #define ATI_VERB_GET_RAMP_RATE          0xf70
3191
3192 #define ATI_OUT_ENABLE 0x1
3193
3194 #define ATI_MULTICHANNEL_MODE_PAIRED    0
3195 #define ATI_MULTICHANNEL_MODE_SINGLE    1
3196
3197 #define ATI_HBR_CAPABLE 0x01
3198 #define ATI_HBR_ENABLE 0x10
3199
3200 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3201                            unsigned char *buf, int *eld_size)
3202 {
3203         /* call hda_eld.c ATI/AMD-specific function */
3204         return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3205                                     is_amdhdmi_rev3_or_later(codec));
3206 }
3207
3208 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3209                                         int active_channels, int conn_type)
3210 {
3211         snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3212 }
3213
3214 static int atihdmi_paired_swap_fc_lfe(int pos)
3215 {
3216         /*
3217          * ATI/AMD have automatic FC/LFE swap built-in
3218          * when in pairwise mapping mode.
3219          */
3220
3221         switch (pos) {
3222                 /* see channel_allocations[].speakers[] */
3223                 case 2: return 3;
3224                 case 3: return 2;
3225                 default: break;
3226         }
3227
3228         return pos;
3229 }
3230
3231 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3232 {
3233         struct cea_channel_speaker_allocation *cap;
3234         int i, j;
3235
3236         /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3237
3238         cap = &channel_allocations[get_channel_allocation_order(ca)];
3239         for (i = 0; i < chs; ++i) {
3240                 int mask = to_spk_mask(map[i]);
3241                 bool ok = false;
3242                 bool companion_ok = false;
3243
3244                 if (!mask)
3245                         continue;
3246
3247                 for (j = 0 + i % 2; j < 8; j += 2) {
3248                         int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3249                         if (cap->speakers[chan_idx] == mask) {
3250                                 /* channel is in a supported position */
3251                                 ok = true;
3252
3253                                 if (i % 2 == 0 && i + 1 < chs) {
3254                                         /* even channel, check the odd companion */
3255                                         int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3256                                         int comp_mask_req = to_spk_mask(map[i+1]);
3257                                         int comp_mask_act = cap->speakers[comp_chan_idx];
3258
3259                                         if (comp_mask_req == comp_mask_act)
3260                                                 companion_ok = true;
3261                                         else
3262                                                 return -EINVAL;
3263                                 }
3264                                 break;
3265                         }
3266                 }
3267
3268                 if (!ok)
3269                         return -EINVAL;
3270
3271                 if (companion_ok)
3272                         i++; /* companion channel already checked */
3273         }
3274
3275         return 0;
3276 }
3277
3278 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3279                                         int hdmi_slot, int stream_channel)
3280 {
3281         int verb;
3282         int ati_channel_setup = 0;
3283
3284         if (hdmi_slot > 7)
3285                 return -EINVAL;
3286
3287         if (!has_amd_full_remap_support(codec)) {
3288                 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3289
3290                 /* In case this is an odd slot but without stream channel, do not
3291                  * disable the slot since the corresponding even slot could have a
3292                  * channel. In case neither have a channel, the slot pair will be
3293                  * disabled when this function is called for the even slot. */
3294                 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3295                         return 0;
3296
3297                 hdmi_slot -= hdmi_slot % 2;
3298
3299                 if (stream_channel != 0xf)
3300                         stream_channel -= stream_channel % 2;
3301         }
3302
3303         verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3304
3305         /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3306
3307         if (stream_channel != 0xf)
3308                 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3309
3310         return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3311 }
3312
3313 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3314                                         int asp_slot)
3315 {
3316         bool was_odd = false;
3317         int ati_asp_slot = asp_slot;
3318         int verb;
3319         int ati_channel_setup;
3320
3321         if (asp_slot > 7)
3322                 return -EINVAL;
3323
3324         if (!has_amd_full_remap_support(codec)) {
3325                 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3326                 if (ati_asp_slot % 2 != 0) {
3327                         ati_asp_slot -= 1;
3328                         was_odd = true;
3329                 }
3330         }
3331
3332         verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3333
3334         ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3335
3336         if (!(ati_channel_setup & ATI_OUT_ENABLE))
3337                 return 0xf;
3338
3339         return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3340 }
3341
3342 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3343                                                             int channels)
3344 {
3345         int c;
3346
3347         /*
3348          * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3349          * we need to take that into account (a single channel may take 2
3350          * channel slots if we need to carry a silent channel next to it).
3351          * On Rev3+ AMD codecs this function is not used.
3352          */
3353         int chanpairs = 0;
3354
3355         /* We only produce even-numbered channel count TLVs */
3356         if ((channels % 2) != 0)
3357                 return -1;
3358
3359         for (c = 0; c < 7; c += 2) {
3360                 if (cap->speakers[c] || cap->speakers[c+1])
3361                         chanpairs++;
3362         }
3363
3364         if (chanpairs * 2 != channels)
3365                 return -1;
3366
3367         return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3368 }
3369
3370 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3371                                                   unsigned int *chmap, int channels)
3372 {
3373         /* produce paired maps for pre-rev3 ATI/AMD codecs */
3374         int count = 0;
3375         int c;
3376
3377         for (c = 7; c >= 0; c--) {
3378                 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3379                 int spk = cap->speakers[chan];
3380                 if (!spk) {
3381                         /* add N/A channel if the companion channel is occupied */
3382                         if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3383                                 chmap[count++] = SNDRV_CHMAP_NA;
3384
3385                         continue;
3386                 }
3387
3388                 chmap[count++] = spk_to_chmap(spk);
3389         }
3390
3391         WARN_ON(count != channels);
3392 }
3393
3394 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3395                                  bool hbr)
3396 {
3397         int hbr_ctl, hbr_ctl_new;
3398
3399         hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3400         if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3401                 if (hbr)
3402                         hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3403                 else
3404                         hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3405
3406                 codec_dbg(codec,
3407                           "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3408                                 pin_nid,
3409                                 hbr_ctl == hbr_ctl_new ? "" : "new-",
3410                                 hbr_ctl_new);
3411
3412                 if (hbr_ctl != hbr_ctl_new)
3413                         snd_hda_codec_write(codec, pin_nid, 0,
3414                                                 ATI_VERB_SET_HBR_CONTROL,
3415                                                 hbr_ctl_new);
3416
3417         } else if (hbr)
3418                 return -EINVAL;
3419
3420         return 0;
3421 }
3422
3423 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3424                                 hda_nid_t pin_nid, u32 stream_tag, int format)
3425 {
3426
3427         if (is_amdhdmi_rev3_or_later(codec)) {
3428                 int ramp_rate = 180; /* default as per AMD spec */
3429                 /* disable ramp-up/down for non-pcm as per AMD spec */
3430                 if (format & AC_FMT_TYPE_NON_PCM)
3431                         ramp_rate = 0;
3432
3433                 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3434         }
3435
3436         return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3437 }
3438
3439
3440 static int atihdmi_init(struct hda_codec *codec)
3441 {
3442         struct hdmi_spec *spec = codec->spec;
3443         int pin_idx, err;
3444
3445         err = generic_hdmi_init(codec);
3446
3447         if (err)
3448                 return err;
3449
3450         for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3451                 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3452
3453                 /* make sure downmix information in infoframe is zero */
3454                 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3455
3456                 /* enable channel-wise remap mode if supported */
3457                 if (has_amd_full_remap_support(codec))
3458                         snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3459                                             ATI_VERB_SET_MULTICHANNEL_MODE,
3460                                             ATI_MULTICHANNEL_MODE_SINGLE);
3461         }
3462
3463         return 0;
3464 }
3465
3466 static int patch_atihdmi(struct hda_codec *codec)
3467 {
3468         struct hdmi_spec *spec;
3469         struct hdmi_spec_per_cvt *per_cvt;
3470         int err, cvt_idx;
3471
3472         err = patch_generic_hdmi(codec);
3473
3474         if (err)
3475                 return err;
3476
3477         codec->patch_ops.init = atihdmi_init;
3478
3479         spec = codec->spec;
3480
3481         spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3482         spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3483         spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3484         spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3485         spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3486         spec->ops.setup_stream = atihdmi_setup_stream;
3487
3488         if (!has_amd_full_remap_support(codec)) {
3489                 /* override to ATI/AMD-specific versions with pairwise mapping */
3490                 spec->ops.chmap_cea_alloc_validate_get_type =
3491                         atihdmi_paired_chmap_cea_alloc_validate_get_type;
3492                 spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3493                 spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3494         }
3495
3496         /* ATI/AMD converters do not advertise all of their capabilities */
3497         for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3498                 per_cvt = get_cvt(spec, cvt_idx);
3499                 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3500                 per_cvt->rates |= SUPPORTED_RATES;
3501                 per_cvt->formats |= SUPPORTED_FORMATS;
3502                 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3503         }
3504
3505         spec->channels_max = max(spec->channels_max, 8u);
3506
3507         return 0;
3508 }
3509
3510 /* VIA HDMI Implementation */
3511 #define VIAHDMI_CVT_NID 0x02    /* audio converter1 */
3512 #define VIAHDMI_PIN_NID 0x03    /* HDMI output pin1 */
3513
3514 static int patch_via_hdmi(struct hda_codec *codec)
3515 {
3516         return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3517 }
3518
3519 /*
3520  * patch entries
3521  */
3522 static const struct hda_device_id snd_hda_id_hdmi[] = {
3523 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI",       patch_atihdmi),
3524 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI",       patch_atihdmi),
3525 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI",   patch_atihdmi),
3526 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI",        patch_atihdmi),
3527 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI",     patch_generic_hdmi),
3528 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI",     patch_generic_hdmi),
3529 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI",    patch_generic_hdmi),
3530 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3531 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3532 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3533 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI",    patch_nvhdmi_8ch_7x),
3534 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI",    patch_nvhdmi_8ch_7x),
3535 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP",   patch_nvhdmi),
3536 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP",   patch_nvhdmi),
3537 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI",       patch_nvhdmi),
3538 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP",   patch_nvhdmi),
3539 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP",   patch_nvhdmi),
3540 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP",   patch_nvhdmi),
3541 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP",   patch_nvhdmi),
3542 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP",   patch_nvhdmi),
3543 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP",   patch_nvhdmi),
3544 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP",   patch_nvhdmi),
3545 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP",   patch_nvhdmi),
3546 /* 17 is known to be absent */
3547 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP",   patch_nvhdmi),
3548 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP",   patch_nvhdmi),
3549 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP",   patch_nvhdmi),
3550 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP",   patch_nvhdmi),
3551 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP",   patch_nvhdmi),
3552 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI",     patch_tegra_hdmi),
3553 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI",    patch_tegra_hdmi),
3554 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI",    patch_tegra_hdmi),
3555 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3556 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP",   patch_nvhdmi),
3557 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP",   patch_nvhdmi),
3558 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP",   patch_nvhdmi),
3559 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP",   patch_nvhdmi),
3560 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP",   patch_nvhdmi),
3561 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP",   patch_nvhdmi),
3562 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP",   patch_nvhdmi),
3563 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI",       patch_nvhdmi_2ch),
3564 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP",   patch_nvhdmi),
3565 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP",   patch_nvhdmi),
3566 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP",   patch_nvhdmi),
3567 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP",   patch_nvhdmi),
3568 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI",       patch_nvhdmi_2ch),
3569 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP",    patch_via_hdmi),
3570 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP",    patch_via_hdmi),
3571 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP",     patch_generic_hdmi),
3572 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP",     patch_generic_hdmi),
3573 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI",    patch_generic_hdmi),
3574 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI",    patch_generic_hdmi),
3575 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI",     patch_generic_hdmi),
3576 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI",   patch_generic_hdmi),
3577 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI",    patch_generic_hdmi),
3578 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3579 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3580 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI",     patch_generic_hdmi),
3581 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI",   patch_generic_hdmi),
3582 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI",     patch_generic_hdmi),
3583 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI",     patch_generic_hdmi),
3584 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI",  patch_generic_hdmi),
3585 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3586 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI",    patch_generic_hdmi),
3587 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI",   patch_generic_hdmi),
3588 /* special ID for generic HDMI */
3589 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3590 {} /* terminator */
3591 };
3592 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3593
3594 MODULE_LICENSE("GPL");
3595 MODULE_DESCRIPTION("HDMI HD-audio codec");
3596 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3597 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3598 MODULE_ALIAS("snd-hda-codec-atihdmi");
3599
3600 static struct hda_codec_driver hdmi_driver = {
3601         .id = snd_hda_id_hdmi,
3602 };
3603
3604 module_hda_codec_driver(hdmi_driver);