sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41 #include <linux/init.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/module.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/math64.h>
  48 #include <asm/io.h>
  49
  50 #include <sound/core.h>
  51 #include <sound/control.h>
  52 #include <sound/pcm.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/info.h>
  55 #include <sound/asoundef.h>
  56 #include <sound/rawmidi.h>
  57 #include <sound/hwdep.h>
  58 #include <sound/initval.h>
  59
  60 #include <sound/hdspm.h>
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  68
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  71
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  74
  75
  76 MODULE_AUTHOR
  77 (
  78         "Winfried Ritsch <ritsch_AT_iem.at>, "
  79         "Paul Davis <paul@linuxaudiosystems.com>, "
  80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  81         "Remy Bruno <remy.bruno@trinnov.com>, "
  82         "Florian Faber <faberman@linuxproaudio.org>, "
  83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
  84 );
  85 MODULE_DESCRIPTION("RME HDSPM");
  86 MODULE_LICENSE("GPL");
  87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  88
  89 /* --- Write registers. ---
  90   These are defined as byte-offsets from the iobase value.  */
  91
  92 #define HDSPM_WR_SETTINGS             0
  93 #define HDSPM_outputBufferAddress    32
  94 #define HDSPM_inputBufferAddress     36
  95 #define HDSPM_controlRegister        64
  96 #define HDSPM_interruptConfirmation  96
  97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  98 #define HDSPM_freqReg                256  /* for AES32 */
  99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 100 #define HDSPM_midiDataOut1           356
 101 #define HDSPM_eeprom_wr              384  /* for AES32 */
 102
 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
 104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 106
 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 109 #define HDSPM_pageAddressBufferOut       8192
 110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 111
 112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 113
 114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 115
 116 /* --- Read registers. ---
 117    These are defined as byte-offsets from the iobase value */
 118 #define HDSPM_statusRegister    0
 119 /*#define HDSPM_statusRegister2  96 */
 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 121  * offset 192, for AES32 *and* MADI
 122  * => need to check that offset 192 is working on MADI */
 123 #define HDSPM_statusRegister2  192
 124 #define HDSPM_timecodeRegister 128
 125
 126 /* AIO, RayDAT */
 127 #define HDSPM_RD_STATUS_0 0
 128 #define HDSPM_RD_STATUS_1 64
 129 #define HDSPM_RD_STATUS_2 128
 130 #define HDSPM_RD_STATUS_3 192
 131
 132 #define HDSPM_RD_TCO           256
 133 #define HDSPM_RD_PLL_FREQ      512
 134 #define HDSPM_WR_TCO           128
 135
 136 #define HDSPM_TCO1_TCO_lock                     0x00000001
 137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 143
 144 #define HDSPM_TCO1_set_TC                       0x00000100
 145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 148
 149 #define HDSPM_TCO2_TC_run                       0x00010000
 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 155 #define HDSPM_TCO2_set_flywheel                 0x00400000
 156
 157 #define HDSPM_TCO2_set_01_4                     0x01000000
 158 #define HDSPM_TCO2_set_pull_down                0x02000000
 159 #define HDSPM_TCO2_set_pull_up                  0x04000000
 160 #define HDSPM_TCO2_set_freq                     0x08000000
 161 #define HDSPM_TCO2_set_term_75R                 0x10000000
 162 #define HDSPM_TCO2_set_input_LSB                0x20000000
 163 #define HDSPM_TCO2_set_input_MSB                0x40000000
 164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 165
 166
 167 #define HDSPM_midiDataOut0    352
 168 #define HDSPM_midiDataOut1    356
 169 #define HDSPM_midiDataOut2    368
 170
 171 #define HDSPM_midiDataIn0     360
 172 #define HDSPM_midiDataIn1     364
 173 #define HDSPM_midiDataIn2     372
 174 #define HDSPM_midiDataIn3     376
 175
 176 /* status is data bytes in MIDI-FIFO (0-128) */
 177 #define HDSPM_midiStatusOut0  384
 178 #define HDSPM_midiStatusOut1  388
 179 #define HDSPM_midiStatusOut2  400
 180
 181 #define HDSPM_midiStatusIn0   392
 182 #define HDSPM_midiStatusIn1   396
 183 #define HDSPM_midiStatusIn2   404
 184 #define HDSPM_midiStatusIn3   408
 185
 186
 187 /* the meters are regular i/o-mapped registers, but offset
 188    considerably from the rest. the peak registers are reset
 189    when read; the least-significant 4 bits are full-scale counters;
 190    the actual peak value is in the most-significant 24 bits.
 191 */
 192
 193 #define HDSPM_MADI_INPUT_PEAK           4096
 194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 195 #define HDSPM_MADI_OUTPUT_PEAK          4608
 196
 197 #define HDSPM_MADI_INPUT_RMS_L          6144
 198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 200
 201 #define HDSPM_MADI_INPUT_RMS_H          7168
 202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 204
 205 /* --- Control Register bits --------- */
 206 #define HDSPM_Start                (1<<0) /* start engine */
 207
 208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 211
 212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 214                                           register [RayDAT, AIO] */
 215
 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 217
 218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 222
 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 225                                      56channelMODE=0 */ /* MADI ONLY*/
 226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 227
 228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 229                                      0=off, 1=on  */ /* MADI ONLY */
 230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 231
 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 233                                     * -- MADI ONLY
 234                                     */
 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 236
 237 #define HDSPM_SyncRef2     (1<<13)
 238 #define HDSPM_SyncRef3     (1<<25)
 239
 240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 242                                       AES additional bits in
 243                                       lower 5 Audiodatabits ??? */
 244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 246
 247 #define HDSPM_Midi0InterruptEnable 0x0400000
 248 #define HDSPM_Midi1InterruptEnable 0x0800000
 249 #define HDSPM_Midi2InterruptEnable 0x0200000
 250 #define HDSPM_Midi3InterruptEnable 0x4000000
 251
 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 253 #define HDSPe_FLOAT_FORMAT         0x2000000
 254
 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 258
 259 #define HDSPM_wclk_sel (1<<30)
 260
 261 /* additional control register bits for AIO*/
 262 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
 263 #define HDSPM_c0_Input0                         0x1000
 264 #define HDSPM_c0_Input1                         0x2000
 265 #define HDSPM_c0_Spdif_Opt                      0x4000
 266 #define HDSPM_c0_Pro                            0x8000
 267 #define HDSPM_c0_clr_tms                        0x10000
 268 #define HDSPM_c0_AEB1                           0x20000
 269 #define HDSPM_c0_AEB2                           0x40000
 270 #define HDSPM_c0_LineOut                        0x80000
 271 #define HDSPM_c0_AD_GAIN0                       0x100000
 272 #define HDSPM_c0_AD_GAIN1                       0x200000
 273 #define HDSPM_c0_DA_GAIN0                       0x400000
 274 #define HDSPM_c0_DA_GAIN1                       0x800000
 275 #define HDSPM_c0_PH_GAIN0                       0x1000000
 276 #define HDSPM_c0_PH_GAIN1                       0x2000000
 277 #define HDSPM_c0_Sym6db                         0x4000000
 278
 279
 280 /* --- bit helper defines */
 281 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 282 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 283                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 284 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 285 #define HDSPM_InputOptical   0
 286 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 287 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 288                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 289
 290 #define HDSPM_c0_SyncRef0      0x2
 291 #define HDSPM_c0_SyncRef1      0x4
 292 #define HDSPM_c0_SyncRef2      0x8
 293 #define HDSPM_c0_SyncRef3      0x10
 294 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 295                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 296
 297 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 298 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 299 #define HDSPM_SYNC_FROM_TCO     2
 300 #define HDSPM_SYNC_FROM_SYNC_IN 3
 301
 302 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 303 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 304 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 305 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 307 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 308                                 HDSPM_Frequency0)
 309 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 310 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 311 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 312                                  HDSPM_Frequency0)
 313
 314
 315 /* Synccheck Status */
 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 317 #define HDSPM_SYNC_CHECK_LOCK    1
 318 #define HDSPM_SYNC_CHECK_SYNC    2
 319
 320 /* AutoSync References - used by "autosync_ref" control switch */
 321 #define HDSPM_AUTOSYNC_FROM_WORD      0
 322 #define HDSPM_AUTOSYNC_FROM_MADI      1
 323 #define HDSPM_AUTOSYNC_FROM_TCO       2
 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 325 #define HDSPM_AUTOSYNC_FROM_NONE      4
 326
 327 /* Possible sources of MADI input */
 328 #define HDSPM_OPTICAL 0         /* optical   */
 329 #define HDSPM_COAXIAL 1         /* BNC */
 330
 331 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 332 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 333
 334 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 335 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 336
 337 /* --- control2 register bits --- */
 338 #define HDSPM_TMS             (1<<0)
 339 #define HDSPM_TCK             (1<<1)
 340 #define HDSPM_TDI             (1<<2)
 341 #define HDSPM_JTAG            (1<<3)
 342 #define HDSPM_PWDN            (1<<4)
 343 #define HDSPM_PROGRAM         (1<<5)
 344 #define HDSPM_CONFIG_MODE_0   (1<<6)
 345 #define HDSPM_CONFIG_MODE_1   (1<<7)
 346 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 347 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 348 #define HDSPM_RD_MULTIPLE     (1<<10)
 349
 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 351      that do not conflict with specific bits for AES32 seem to be valid also
 352      for the AES32
 353  */
 354 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 355 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 356 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 357                                          * (like inp0)
 358                                          */
 359
 360 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 361 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 362
 363 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
 364 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
 365
 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
 368
 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 370                         /* since 64byte accurate, last 6 bits are not used */
 371
 372
 373
 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 375
 376 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 377 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 378 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 379 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 380
 381 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 382                                          * Interrupt
 383                                          */
 384 #define HDSPM_tco_detect         0x08000000
 385 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
 386
 387 #define HDSPM_s2_tco_detect      0x00000040
 388 #define HDSPM_s2_AEBO_D          0x00000080
 389 #define HDSPM_s2_AEBI_D          0x00000100
 390
 391
 392 #define HDSPM_midi0IRQPending    0x40000000
 393 #define HDSPM_midi1IRQPending    0x80000000
 394 #define HDSPM_midi2IRQPending    0x20000000
 395 #define HDSPM_midi2IRQPendingAES 0x00000020
 396 #define HDSPM_midi3IRQPending    0x00200000
 397
 398 /* --- status bit helpers */
 399 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 400                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 401 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 402 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 403 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 404 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 405 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 406 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 407 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 409 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 410
 411 /* Status2 Register bits */ /* MADI ONLY */
 412
 413 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 414 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 415 #define HDSPM_version2 (1<<2)
 416
 417 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 418 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 419
 420 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 421 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 422 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
 423 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
 424
 425 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 426 #define HDSPM_SyncRef1 0x20000
 427
 428 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 429 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 430 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 431
 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 433
 434 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
 435                             HDSPM_wc_freq3)
 436 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 437 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 438 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 439 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 440 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 441 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 442 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
 444 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
 445
 446 #define HDSPM_status1_F_0 0x0400000
 447 #define HDSPM_status1_F_1 0x0800000
 448 #define HDSPM_status1_F_2 0x1000000
 449 #define HDSPM_status1_F_3 0x2000000
 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 451
 452
 453 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 454                                     HDSPM_SelSyncRef2)
 455 #define HDSPM_SelSyncRef_WORD      0
 456 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 457 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 458 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 459 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 460                                     HDSPM_SelSyncRef2)
 461
 462 /*
 463    For AES32, bits for status, status2 and timecode are different
 464 */
 465 /* status */
 466 #define HDSPM_AES32_wcLock      0x0200000
 467 #define HDSPM_AES32_wcSync      0x0100000
 468 #define HDSPM_AES32_wcFreq_bit  22
 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 470   HDSPM_bit2freq */
 471 #define HDSPM_AES32_syncref_bit  16
 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 473
 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 483 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
 484 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
 485 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
 486
 487 /*  status2 */
 488 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 489 #define HDSPM_LockAES   0x80
 490 #define HDSPM_LockAES1  0x80
 491 #define HDSPM_LockAES2  0x40
 492 #define HDSPM_LockAES3  0x20
 493 #define HDSPM_LockAES4  0x10
 494 #define HDSPM_LockAES5  0x8
 495 #define HDSPM_LockAES6  0x4
 496 #define HDSPM_LockAES7  0x2
 497 #define HDSPM_LockAES8  0x1
 498 /*
 499    Timecode
 500    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 501    AES i+1
 502  bits 3210
 503       0001  32kHz
 504       0010  44.1kHz
 505       0011  48kHz
 506       0100  64kHz
 507       0101  88.2kHz
 508       0110  96kHz
 509       0111  128kHz
 510       1000  176.4kHz
 511       1001  192kHz
 512   NB: Timecode register doesn't seem to work on AES32 card revision 230
 513 */
 514
 515 /* Mixer Values */
 516 #define UNITY_GAIN          32768       /* = 65536/2 */
 517 #define MINUS_INFINITY_GAIN 0
 518
 519 /* Number of channels for different Speed Modes */
 520 #define MADI_SS_CHANNELS       64
 521 #define MADI_DS_CHANNELS       32
 522 #define MADI_QS_CHANNELS       16
 523
 524 #define RAYDAT_SS_CHANNELS     36
 525 #define RAYDAT_DS_CHANNELS     20
 526 #define RAYDAT_QS_CHANNELS     12
 527
 528 #define AIO_IN_SS_CHANNELS        14
 529 #define AIO_IN_DS_CHANNELS        10
 530 #define AIO_IN_QS_CHANNELS        8
 531 #define AIO_OUT_SS_CHANNELS        16
 532 #define AIO_OUT_DS_CHANNELS        12
 533 #define AIO_OUT_QS_CHANNELS        10
 534
 535 #define AES32_CHANNELS          16
 536
 537 /* the size of a substream (1 mono data stream) */
 538 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 539 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 540
 541 /* the size of the area we need to allocate for DMA transfers. the
 542    size is the same regardless of the number of channels, and
 543    also the latency to use.
 544    for one direction !!!
 545 */
 546 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 547 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 548
 549 #define HDSPM_RAYDAT_REV        211
 550 #define HDSPM_AIO_REV           212
 551 #define HDSPM_MADIFACE_REV      213
 552
 553 /* speed factor modes */
 554 #define HDSPM_SPEED_SINGLE 0
 555 #define HDSPM_SPEED_DOUBLE 1
 556 #define HDSPM_SPEED_QUAD   2
 557
 558 /* names for speed modes */
 559 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 560
 561 static char *texts_autosync_aes_tco[] = { "Word Clock",
 562                                           "AES1", "AES2", "AES3", "AES4",
 563                                           "AES5", "AES6", "AES7", "AES8",
 564                                           "TCO", "Sync In"
 565 };
 566 static char *texts_autosync_aes[] = { "Word Clock",
 567                                       "AES1", "AES2", "AES3", "AES4",
 568                                       "AES5", "AES6", "AES7", "AES8",
 569                                       "Sync In"
 570 };
 571 static char *texts_autosync_madi_tco[] = { "Word Clock",
 572                                            "MADI", "TCO", "Sync In" };
 573 static char *texts_autosync_madi[] = { "Word Clock",
 574                                        "MADI", "Sync In" };
 575
 576 static char *texts_autosync_raydat_tco[] = {
 577         "Word Clock",
 578         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 579         "AES", "SPDIF", "TCO", "Sync In"
 580 };
 581 static char *texts_autosync_raydat[] = {
 582         "Word Clock",
 583         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 584         "AES", "SPDIF", "Sync In"
 585 };
 586 static char *texts_autosync_aio_tco[] = {
 587         "Word Clock",
 588         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 589 };
 590 static char *texts_autosync_aio[] = { "Word Clock",
 591                                       "ADAT", "AES", "SPDIF", "Sync In" };
 592
 593 static char *texts_freq[] = {
 594         "No Lock",
 595         "32 kHz",
 596         "44.1 kHz",
 597         "48 kHz",
 598         "64 kHz",
 599         "88.2 kHz",
 600         "96 kHz",
 601         "128 kHz",
 602         "176.4 kHz",
 603         "192 kHz"
 604 };
 605
 606 static char *texts_ports_madi[] = {
 607         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 608         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 609         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 610         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 611         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 612         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 613         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 614         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 615         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 616         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 617         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 618 };
 619
 620
 621 static char *texts_ports_raydat_ss[] = {
 622         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 623         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 624         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 625         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 626         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 627         "ADAT4.7", "ADAT4.8",
 628         "AES.L", "AES.R",
 629         "SPDIF.L", "SPDIF.R"
 630 };
 631
 632 static char *texts_ports_raydat_ds[] = {
 633         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 634         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 635         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 636         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 637         "AES.L", "AES.R",
 638         "SPDIF.L", "SPDIF.R"
 639 };
 640
 641 static char *texts_ports_raydat_qs[] = {
 642         "ADAT1.1", "ADAT1.2",
 643         "ADAT2.1", "ADAT2.2",
 644         "ADAT3.1", "ADAT3.2",
 645         "ADAT4.1", "ADAT4.2",
 646         "AES.L", "AES.R",
 647         "SPDIF.L", "SPDIF.R"
 648 };
 649
 650
 651 static char *texts_ports_aio_in_ss[] = {
 652         "Analogue.L", "Analogue.R",
 653         "AES.L", "AES.R",
 654         "SPDIF.L", "SPDIF.R",
 655         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 656         "ADAT.7", "ADAT.8",
 657         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 658 };
 659
 660 static char *texts_ports_aio_out_ss[] = {
 661         "Analogue.L", "Analogue.R",
 662         "AES.L", "AES.R",
 663         "SPDIF.L", "SPDIF.R",
 664         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 665         "ADAT.7", "ADAT.8",
 666         "Phone.L", "Phone.R",
 667         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 668 };
 669
 670 static char *texts_ports_aio_in_ds[] = {
 671         "Analogue.L", "Analogue.R",
 672         "AES.L", "AES.R",
 673         "SPDIF.L", "SPDIF.R",
 674         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 675         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 676 };
 677
 678 static char *texts_ports_aio_out_ds[] = {
 679         "Analogue.L", "Analogue.R",
 680         "AES.L", "AES.R",
 681         "SPDIF.L", "SPDIF.R",
 682         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 683         "Phone.L", "Phone.R",
 684         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 685 };
 686
 687 static char *texts_ports_aio_in_qs[] = {
 688         "Analogue.L", "Analogue.R",
 689         "AES.L", "AES.R",
 690         "SPDIF.L", "SPDIF.R",
 691         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 692         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 693 };
 694
 695 static char *texts_ports_aio_out_qs[] = {
 696         "Analogue.L", "Analogue.R",
 697         "AES.L", "AES.R",
 698         "SPDIF.L", "SPDIF.R",
 699         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 700         "Phone.L", "Phone.R",
 701         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 702 };
 703
 704 static char *texts_ports_aes32[] = {
 705         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 706         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 707         "AES.15", "AES.16"
 708 };
 709
 710 /* These tables map the ALSA channels 1..N to the channels that we
 711    need to use in order to find the relevant channel buffer. RME
 712    refers to this kind of mapping as between "the ADAT channel and
 713    the DMA channel." We index it using the logical audio channel,
 714    and the value is the DMA channel (i.e. channel buffer number)
 715    where the data for that channel can be read/written from/to.
 716 */
 717
 718 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 719         0, 1, 2, 3, 4, 5, 6, 7,
 720         8, 9, 10, 11, 12, 13, 14, 15,
 721         16, 17, 18, 19, 20, 21, 22, 23,
 722         24, 25, 26, 27, 28, 29, 30, 31,
 723         32, 33, 34, 35, 36, 37, 38, 39,
 724         40, 41, 42, 43, 44, 45, 46, 47,
 725         48, 49, 50, 51, 52, 53, 54, 55,
 726         56, 57, 58, 59, 60, 61, 62, 63
 727 };
 728
 729 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 730         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 731         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 732         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 733         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 734         0, 1,                   /* AES */
 735         2, 3,                   /* SPDIF */
 736         -1, -1, -1, -1,
 737         -1, -1, -1, -1, -1, -1, -1, -1,
 738         -1, -1, -1, -1, -1, -1, -1, -1,
 739         -1, -1, -1, -1, -1, -1, -1, -1,
 740 };
 741
 742 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 743         4, 5, 6, 7,             /* ADAT 1 */
 744         8, 9, 10, 11,           /* ADAT 2 */
 745         12, 13, 14, 15,         /* ADAT 3 */
 746         16, 17, 18, 19,         /* ADAT 4 */
 747         0, 1,                   /* AES */
 748         2, 3,                   /* SPDIF */
 749         -1, -1, -1, -1,
 750         -1, -1, -1, -1, -1, -1, -1, -1,
 751         -1, -1, -1, -1, -1, -1, -1, -1,
 752         -1, -1, -1, -1, -1, -1, -1, -1,
 753         -1, -1, -1, -1, -1, -1, -1, -1,
 754         -1, -1, -1, -1, -1, -1, -1, -1,
 755 };
 756
 757 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 758         4, 5,                   /* ADAT 1 */
 759         6, 7,                   /* ADAT 2 */
 760         8, 9,                   /* ADAT 3 */
 761         10, 11,                 /* ADAT 4 */
 762         0, 1,                   /* AES */
 763         2, 3,                   /* SPDIF */
 764         -1, -1, -1, -1,
 765         -1, -1, -1, -1, -1, -1, -1, -1,
 766         -1, -1, -1, -1, -1, -1, -1, -1,
 767         -1, -1, -1, -1, -1, -1, -1, -1,
 768         -1, -1, -1, -1, -1, -1, -1, -1,
 769         -1, -1, -1, -1, -1, -1, -1, -1,
 770         -1, -1, -1, -1, -1, -1, -1, -1,
 771 };
 772
 773 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 774         0, 1,                   /* line in */
 775         8, 9,                   /* aes in, */
 776         10, 11,                 /* spdif in */
 777         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 778         2, 3, 4, 5,             /* AEB */
 779         -1, -1, -1, -1, -1, -1,
 780         -1, -1, -1, -1, -1, -1, -1, -1,
 781         -1, -1, -1, -1, -1, -1, -1, -1,
 782         -1, -1, -1, -1, -1, -1, -1, -1,
 783         -1, -1, -1, -1, -1, -1, -1, -1,
 784         -1, -1, -1, -1, -1, -1, -1, -1,
 785 };
 786
 787 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 788         0, 1,                   /* line out */
 789         8, 9,                   /* aes out */
 790         10, 11,                 /* spdif out */
 791         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 792         6, 7,                   /* phone out */
 793         2, 3, 4, 5,             /* AEB */
 794         -1, -1, -1, -1,
 795         -1, -1, -1, -1, -1, -1, -1, -1,
 796         -1, -1, -1, -1, -1, -1, -1, -1,
 797         -1, -1, -1, -1, -1, -1, -1, -1,
 798         -1, -1, -1, -1, -1, -1, -1, -1,
 799         -1, -1, -1, -1, -1, -1, -1, -1,
 800 };
 801
 802 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 803         0, 1,                   /* line in */
 804         8, 9,                   /* aes in */
 805         10, 11,                 /* spdif in */
 806         12, 14, 16, 18,         /* adat in */
 807         2, 3, 4, 5,             /* AEB */
 808         -1, -1,
 809         -1, -1, -1, -1, -1, -1, -1, -1,
 810         -1, -1, -1, -1, -1, -1, -1, -1,
 811         -1, -1, -1, -1, -1, -1, -1, -1,
 812         -1, -1, -1, -1, -1, -1, -1, -1,
 813         -1, -1, -1, -1, -1, -1, -1, -1,
 814         -1, -1, -1, -1, -1, -1, -1, -1
 815 };
 816
 817 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 818         0, 1,                   /* line out */
 819         8, 9,                   /* aes out */
 820         10, 11,                 /* spdif out */
 821         12, 14, 16, 18,         /* adat out */
 822         6, 7,                   /* phone out */
 823         2, 3, 4, 5,             /* AEB */
 824         -1, -1, -1, -1, -1, -1, -1, -1,
 825         -1, -1, -1, -1, -1, -1, -1, -1,
 826         -1, -1, -1, -1, -1, -1, -1, -1,
 827         -1, -1, -1, -1, -1, -1, -1, -1,
 828         -1, -1, -1, -1, -1, -1, -1, -1,
 829         -1, -1, -1, -1, -1, -1, -1, -1
 830 };
 831
 832 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 833         0, 1,                   /* line in */
 834         8, 9,                   /* aes in */
 835         10, 11,                 /* spdif in */
 836         12, 16,                 /* adat in */
 837         2, 3, 4, 5,             /* AEB */
 838         -1, -1, -1, -1,
 839         -1, -1, -1, -1, -1, -1, -1, -1,
 840         -1, -1, -1, -1, -1, -1, -1, -1,
 841         -1, -1, -1, -1, -1, -1, -1, -1,
 842         -1, -1, -1, -1, -1, -1, -1, -1,
 843         -1, -1, -1, -1, -1, -1, -1, -1,
 844         -1, -1, -1, -1, -1, -1, -1, -1
 845 };
 846
 847 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 848         0, 1,                   /* line out */
 849         8, 9,                   /* aes out */
 850         10, 11,                 /* spdif out */
 851         12, 16,                 /* adat out */
 852         6, 7,                   /* phone out */
 853         2, 3, 4, 5,             /* AEB */
 854         -1, -1,
 855         -1, -1, -1, -1, -1, -1, -1, -1,
 856         -1, -1, -1, -1, -1, -1, -1, -1,
 857         -1, -1, -1, -1, -1, -1, -1, -1,
 858         -1, -1, -1, -1, -1, -1, -1, -1,
 859         -1, -1, -1, -1, -1, -1, -1, -1,
 860         -1, -1, -1, -1, -1, -1, -1, -1
 861 };
 862
 863 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 864         0, 1, 2, 3, 4, 5, 6, 7,
 865         8, 9, 10, 11, 12, 13, 14, 15,
 866         -1, -1, -1, -1, -1, -1, -1, -1,
 867         -1, -1, -1, -1, -1, -1, -1, -1,
 868         -1, -1, -1, -1, -1, -1, -1, -1,
 869         -1, -1, -1, -1, -1, -1, -1, -1,
 870         -1, -1, -1, -1, -1, -1, -1, -1,
 871         -1, -1, -1, -1, -1, -1, -1, -1
 872 };
 873
 874 struct hdspm_midi {
 875         struct hdspm *hdspm;
 876         int id;
 877         struct snd_rawmidi *rmidi;
 878         struct snd_rawmidi_substream *input;
 879         struct snd_rawmidi_substream *output;
 880         char istimer;           /* timer in use */
 881         struct timer_list timer;
 882         spinlock_t lock;
 883         int pending;
 884         int dataIn;
 885         int statusIn;
 886         int dataOut;
 887         int statusOut;
 888         int ie;
 889         int irq;
 890 };
 891
 892 struct hdspm_tco {
 893         int input;
 894         int framerate;
 895         int wordclock;
 896         int samplerate;
 897         int pull;
 898         int term; /* 0 = off, 1 = on */
 899 };
 900
 901 struct hdspm {
 902         spinlock_t lock;
 903         /* only one playback and/or capture stream */
 904         struct snd_pcm_substream *capture_substream;
 905         struct snd_pcm_substream *playback_substream;
 906
 907         char *card_name;             /* for procinfo */
 908         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 909
 910         uint8_t io_type;
 911
 912         int monitor_outs;       /* set up monitoring outs init flag */
 913
 914         u32 control_register;   /* cached value */
 915         u32 control2_register;  /* cached value */
 916         u32 settings_register;
 917
 918         struct hdspm_midi midi[4];
 919         struct tasklet_struct midi_tasklet;
 920
 921         size_t period_bytes;
 922         unsigned char ss_in_channels;
 923         unsigned char ds_in_channels;
 924         unsigned char qs_in_channels;
 925         unsigned char ss_out_channels;
 926         unsigned char ds_out_channels;
 927         unsigned char qs_out_channels;
 928
 929         unsigned char max_channels_in;
 930         unsigned char max_channels_out;
 931
 932         signed char *channel_map_in;
 933         signed char *channel_map_out;
 934
 935         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 936         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 937
 938         char **port_names_in;
 939         char **port_names_out;
 940
 941         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 942         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
 943
 944         unsigned char *playback_buffer; /* suitably aligned address */
 945         unsigned char *capture_buffer;  /* suitably aligned address */
 946
 947         pid_t capture_pid;      /* process id which uses capture */
 948         pid_t playback_pid;     /* process id which uses capture */
 949         int running;            /* running status */
 950
 951         int last_external_sample_rate;  /* samplerate mystic ... */
 952         int last_internal_sample_rate;
 953         int system_sample_rate;
 954
 955         int dev;                /* Hardware vars... */
 956         int irq;
 957         unsigned long port;
 958         void __iomem *iobase;
 959
 960         int irq_count;          /* for debug */
 961         int midiPorts;
 962
 963         struct snd_card *card;  /* one card */
 964         struct snd_pcm *pcm;            /* has one pcm */
 965         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 966         struct pci_dev *pci;    /* and an pci info */
 967
 968         /* Mixer vars */
 969         /* fast alsa mixer */
 970         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 971         /* but input to much, so not used */
 972         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 973         /* full mixer accessible over mixer ioctl or hwdep-device */
 974         struct hdspm_mixer *mixer;
 975
 976         struct hdspm_tco *tco;  /* NULL if no TCO detected */
 977
 978         char **texts_autosync;
 979         int texts_autosync_items;
 980
 981         cycles_t last_interrupt;
 982
 983         unsigned int serial;
 984
 985         struct hdspm_peak_rms peak_rms;
 986 };
 987
 988
 989 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
 990         {
 991          .vendor = PCI_VENDOR_ID_XILINX,
 992          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 993          .subvendor = PCI_ANY_ID,
 994          .subdevice = PCI_ANY_ID,
 995          .class = 0,
 996          .class_mask = 0,
 997          .driver_data = 0},
 998         {0,}
 999 };
1000
1001 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1002
1003 /* prototypes */
1004 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1005                                          struct hdspm *hdspm);
1006 static int snd_hdspm_create_pcm(struct snd_card *card,
1007                                 struct hdspm *hdspm);
1008
1009 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1010 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1011 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1012 static int hdspm_autosync_ref(struct hdspm *hdspm);
1013 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1014 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1015 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1016 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1017                             struct snd_pcm_substream *substream,
1018                              unsigned int reg, int channels);
1019
1020 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1021 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1022 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1023 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1024
1025 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1026 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1027 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1028
1029
1030
1031 static inline int HDSPM_bit2freq(int n)
1032 {
1033         static const int bit2freq_tab[] = {
1034                 0, 32000, 44100, 48000, 64000, 88200,
1035                 96000, 128000, 176400, 192000 };
1036         if (n < 1 || n > 9)
1037                 return 0;
1038         return bit2freq_tab[n];
1039 }
1040
1041 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1042 {
1043         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1044 }
1045
1046
1047 /* Write/read to/from HDSPM with Adresses in Bytes
1048    not words but only 32Bit writes are allowed */
1049
1050 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1051                                unsigned int val)
1052 {
1053         writel(val, hdspm->iobase + reg);
1054 }
1055
1056 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1057 {
1058         return readl(hdspm->iobase + reg);
1059 }
1060
1061 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1062    mixer is write only on hardware so we have to cache him for read
1063    each fader is a u32, but uses only the first 16 bit */
1064
1065 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1066                                      unsigned int in)
1067 {
1068         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1069                 return 0;
1070
1071         return hdspm->mixer->ch[chan].in[in];
1072 }
1073
1074 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1075                                      unsigned int pb)
1076 {
1077         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1078                 return 0;
1079         return hdspm->mixer->ch[chan].pb[pb];
1080 }
1081
1082 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1083                                       unsigned int in, unsigned short data)
1084 {
1085         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1086                 return -1;
1087
1088         hdspm_write(hdspm,
1089                     HDSPM_MADI_mixerBase +
1090                     ((in + 128 * chan) * sizeof(u32)),
1091                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1092         return 0;
1093 }
1094
1095 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1096                                       unsigned int pb, unsigned short data)
1097 {
1098         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1099                 return -1;
1100
1101         hdspm_write(hdspm,
1102                     HDSPM_MADI_mixerBase +
1103                     ((64 + pb + 128 * chan) * sizeof(u32)),
1104                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1105         return 0;
1106 }
1107
1108
1109 /* enable DMA for specific channels, now available for DSP-MADI */
1110 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1111 {
1112         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1113 }
1114
1115 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1116 {
1117         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1118 }
1119
1120 /* check if same process is writing and reading */
1121 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1122 {
1123         unsigned long flags;
1124         int ret = 1;
1125
1126         spin_lock_irqsave(&hdspm->lock, flags);
1127         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1128             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1129                 ret = 0;
1130         }
1131         spin_unlock_irqrestore(&hdspm->lock, flags);
1132         return ret;
1133 }
1134
1135 /* round arbitary sample rates to commonly known rates */
1136 static int hdspm_round_frequency(int rate)
1137 {
1138         if (rate < 38050)
1139                 return 32000;
1140         if (rate < 46008)
1141                 return 44100;
1142         else
1143                 return 48000;
1144 }
1145
1146 /* QS and DS rates normally can not be detected
1147  * automatically by the card. Only exception is MADI
1148  * in 96k frame mode.
1149  *
1150  * So if we read SS values (32 .. 48k), check for
1151  * user-provided DS/QS bits in the control register
1152  * and multiply the base frequency accordingly.
1153  */
1154 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1155 {
1156         if (rate <= 48000) {
1157                 if (hdspm->control_register & HDSPM_QuadSpeed)
1158                         return rate * 4;
1159                 else if (hdspm->control_register &
1160                                 HDSPM_DoubleSpeed)
1161                         return rate * 2;
1162         };
1163         return rate;
1164 }
1165
1166 /* check for external sample rate, returns the sample rate in Hz*/
1167 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1168 {
1169         unsigned int status, status2, timecode;
1170         int syncref, rate = 0, rate_bits;
1171
1172         switch (hdspm->io_type) {
1173         case AES32:
1174                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1175                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1176                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1177
1178                 syncref = hdspm_autosync_ref(hdspm);
1179                 switch (syncref) {
1180                 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1181                 /* Check WC sync and get sample rate */
1182                         if (hdspm_wc_sync_check(hdspm))
1183                                 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1184                         break;
1185
1186                 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1187                 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1188                 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1189                 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1190                 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1191                 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1192                 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1193                 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1194                 /* Check AES sync and get sample rate */
1195                         if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1196                                 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1197                                                         syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1198                         break;
1199
1200
1201                 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1202                 /* Check TCO sync and get sample rate */
1203                         if (hdspm_tco_sync_check(hdspm))
1204                                 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1205                         break;
1206                 default:
1207                         return 0;
1208                 } /* end switch(syncref) */
1209                 break;
1210
1211         case MADIface:
1212                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1213
1214                 if (!(status & HDSPM_madiLock)) {
1215                         rate = 0;  /* no lock */
1216                 } else {
1217                         switch (status & (HDSPM_status1_freqMask)) {
1218                         case HDSPM_status1_F_0*1:
1219                                 rate = 32000; break;
1220                         case HDSPM_status1_F_0*2:
1221                                 rate = 44100; break;
1222                         case HDSPM_status1_F_0*3:
1223                                 rate = 48000; break;
1224                         case HDSPM_status1_F_0*4:
1225                                 rate = 64000; break;
1226                         case HDSPM_status1_F_0*5:
1227                                 rate = 88200; break;
1228                         case HDSPM_status1_F_0*6:
1229                                 rate = 96000; break;
1230                         case HDSPM_status1_F_0*7:
1231                                 rate = 128000; break;
1232                         case HDSPM_status1_F_0*8:
1233                                 rate = 176400; break;
1234                         case HDSPM_status1_F_0*9:
1235                                 rate = 192000; break;
1236                         default:
1237                                 rate = 0; break;
1238                         }
1239                 }
1240
1241                 break;
1242
1243         case MADI:
1244         case AIO:
1245         case RayDAT:
1246                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1247                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1248                 rate = 0;
1249
1250                 /* if wordclock has synced freq and wordclock is valid */
1251                 if ((status2 & HDSPM_wcLock) != 0 &&
1252                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1253
1254                         rate_bits = status2 & HDSPM_wcFreqMask;
1255
1256
1257                         switch (rate_bits) {
1258                         case HDSPM_wcFreq32:
1259                                 rate = 32000;
1260                                 break;
1261                         case HDSPM_wcFreq44_1:
1262                                 rate = 44100;
1263                                 break;
1264                         case HDSPM_wcFreq48:
1265                                 rate = 48000;
1266                                 break;
1267                         case HDSPM_wcFreq64:
1268                                 rate = 64000;
1269                                 break;
1270                         case HDSPM_wcFreq88_2:
1271                                 rate = 88200;
1272                                 break;
1273                         case HDSPM_wcFreq96:
1274                                 rate = 96000;
1275                                 break;
1276                         case HDSPM_wcFreq128:
1277                                 rate = 128000;
1278                                 break;
1279                         case HDSPM_wcFreq176_4:
1280                                 rate = 176400;
1281                                 break;
1282                         case HDSPM_wcFreq192:
1283                                 rate = 192000;
1284                                 break;
1285                         default:
1286                                 rate = 0;
1287                                 break;
1288                         }
1289                 }
1290
1291                 /* if rate detected and Syncref is Word than have it,
1292                  * word has priority to MADI
1293                  */
1294                 if (rate != 0 &&
1295                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1296                         return hdspm_rate_multiplier(hdspm, rate);
1297
1298                 /* maybe a madi input (which is taken if sel sync is madi) */
1299                 if (status & HDSPM_madiLock) {
1300                         rate_bits = status & HDSPM_madiFreqMask;
1301
1302                         switch (rate_bits) {
1303                         case HDSPM_madiFreq32:
1304                                 rate = 32000;
1305                                 break;
1306                         case HDSPM_madiFreq44_1:
1307                                 rate = 44100;
1308                                 break;
1309                         case HDSPM_madiFreq48:
1310                                 rate = 48000;
1311                                 break;
1312                         case HDSPM_madiFreq64:
1313                                 rate = 64000;
1314                                 break;
1315                         case HDSPM_madiFreq88_2:
1316                                 rate = 88200;
1317                                 break;
1318                         case HDSPM_madiFreq96:
1319                                 rate = 96000;
1320                                 break;
1321                         case HDSPM_madiFreq128:
1322                                 rate = 128000;
1323                                 break;
1324                         case HDSPM_madiFreq176_4:
1325                                 rate = 176400;
1326                                 break;
1327                         case HDSPM_madiFreq192:
1328                                 rate = 192000;
1329                                 break;
1330                         default:
1331                                 rate = 0;
1332                                 break;
1333                         }
1334
1335                 } /* endif HDSPM_madiLock */
1336
1337                 /* check sample rate from TCO or SYNC_IN */
1338                 {
1339                         bool is_valid_input = 0;
1340                         bool has_sync = 0;
1341
1342                         syncref = hdspm_autosync_ref(hdspm);
1343                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1344                                 is_valid_input = 1;
1345                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1346                                         hdspm_tco_sync_check(hdspm));
1347                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1348                                 is_valid_input = 1;
1349                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1350                                         hdspm_sync_in_sync_check(hdspm));
1351                         }
1352
1353                         if (is_valid_input && has_sync) {
1354                                 rate = hdspm_round_frequency(
1355                                         hdspm_get_pll_freq(hdspm));
1356                         }
1357                 }
1358
1359                 rate = hdspm_rate_multiplier(hdspm, rate);
1360
1361                 break;
1362         }
1363
1364         return rate;
1365 }
1366
1367 /* return latency in samples per period */
1368 static int hdspm_get_latency(struct hdspm *hdspm)
1369 {
1370         int n;
1371
1372         n = hdspm_decode_latency(hdspm->control_register);
1373
1374         /* Special case for new RME cards with 32 samples period size.
1375          * The three latency bits in the control register
1376          * (HDSP_LatencyMask) encode latency values of 64 samples as
1377          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1378          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1379          * it corresponds to 32 samples.
1380          */
1381         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1382                 n = -1;
1383
1384         return 1 << (n + 6);
1385 }
1386
1387 /* Latency function */
1388 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1389 {
1390         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1391 }
1392
1393
1394 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1395 {
1396         int position;
1397
1398         position = hdspm_read(hdspm, HDSPM_statusRegister);
1399
1400         switch (hdspm->io_type) {
1401         case RayDAT:
1402         case AIO:
1403                 position &= HDSPM_BufferPositionMask;
1404                 position /= 4; /* Bytes per sample */
1405                 break;
1406         default:
1407                 position = (position & HDSPM_BufferID) ?
1408                         (hdspm->period_bytes / 4) : 0;
1409         }
1410
1411         return position;
1412 }
1413
1414
1415 static inline void hdspm_start_audio(struct hdspm * s)
1416 {
1417         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1418         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1419 }
1420
1421 static inline void hdspm_stop_audio(struct hdspm * s)
1422 {
1423         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1424         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1425 }
1426
1427 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1428 static void hdspm_silence_playback(struct hdspm *hdspm)
1429 {
1430         int i;
1431         int n = hdspm->period_bytes;
1432         void *buf = hdspm->playback_buffer;
1433
1434         if (buf == NULL)
1435                 return;
1436
1437         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1438                 memset(buf, 0, n);
1439                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1440         }
1441 }
1442
1443 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1444 {
1445         int n;
1446
1447         spin_lock_irq(&s->lock);
1448
1449         if (32 == frames) {
1450                 /* Special case for new RME cards like RayDAT/AIO which
1451                  * support period sizes of 32 samples. Since latency is
1452                  * encoded in the three bits of HDSP_LatencyMask, we can only
1453                  * have values from 0 .. 7. While 0 still means 64 samples and
1454                  * 6 represents 4096 samples on all cards, 7 represents 8192
1455                  * on older cards and 32 samples on new cards.
1456                  *
1457                  * In other words, period size in samples is calculated by
1458                  * 2^(n+6) with n ranging from 0 .. 7.
1459                  */
1460                 n = 7;
1461         } else {
1462                 frames >>= 7;
1463                 n = 0;
1464                 while (frames) {
1465                         n++;
1466                         frames >>= 1;
1467                 }
1468         }
1469
1470         s->control_register &= ~HDSPM_LatencyMask;
1471         s->control_register |= hdspm_encode_latency(n);
1472
1473         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1474
1475         hdspm_compute_period_size(s);
1476
1477         spin_unlock_irq(&s->lock);
1478
1479         return 0;
1480 }
1481
1482 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1483 {
1484         u64 freq_const;
1485
1486         if (period == 0)
1487                 return 0;
1488
1489         switch (hdspm->io_type) {
1490         case MADI:
1491         case AES32:
1492                 freq_const = 110069313433624ULL;
1493                 break;
1494         case RayDAT:
1495         case AIO:
1496                 freq_const = 104857600000000ULL;
1497                 break;
1498         case MADIface:
1499                 freq_const = 131072000000000ULL;
1500                 break;
1501         default:
1502                 snd_BUG();
1503                 return 0;
1504         }
1505
1506         return div_u64(freq_const, period);
1507 }
1508
1509
1510 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1511 {
1512         u64 n;
1513
1514         if (rate >= 112000)
1515                 rate /= 4;
1516         else if (rate >= 56000)
1517                 rate /= 2;
1518
1519         switch (hdspm->io_type) {
1520         case MADIface:
1521                 n = 131072000000000ULL;  /* 125 MHz */
1522                 break;
1523         case MADI:
1524         case AES32:
1525                 n = 110069313433624ULL;  /* 105 MHz */
1526                 break;
1527         case RayDAT:
1528         case AIO:
1529                 n = 104857600000000ULL;  /* 100 MHz */
1530                 break;
1531         default:
1532                 snd_BUG();
1533                 return;
1534         }
1535
1536         n = div_u64(n, rate);
1537         /* n should be less than 2^32 for being written to FREQ register */
1538         snd_BUG_ON(n >> 32);
1539         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1540 }
1541
1542 /* dummy set rate lets see what happens */
1543 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1544 {
1545         int current_rate;
1546         int rate_bits;
1547         int not_set = 0;
1548         int current_speed, target_speed;
1549
1550         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1551            it (e.g. during module initialization).
1552          */
1553
1554         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1555
1556                 /* SLAVE --- */
1557                 if (called_internally) {
1558
1559                         /* request from ctl or card initialization
1560                            just make a warning an remember setting
1561                            for future master mode switching */
1562
1563                         snd_printk(KERN_WARNING "HDSPM: "
1564                                    "Warning: device is not running "
1565                                    "as a clock master.\n");
1566                         not_set = 1;
1567                 } else {
1568
1569                         /* hw_param request while in AutoSync mode */
1570                         int external_freq =
1571                             hdspm_external_sample_rate(hdspm);
1572
1573                         if (hdspm_autosync_ref(hdspm) ==
1574                             HDSPM_AUTOSYNC_FROM_NONE) {
1575
1576                                 snd_printk(KERN_WARNING "HDSPM: "
1577                                            "Detected no Externel Sync \n");
1578                                 not_set = 1;
1579
1580                         } else if (rate != external_freq) {
1581
1582                                 snd_printk(KERN_WARNING "HDSPM: "
1583                                            "Warning: No AutoSync source for "
1584                                            "requested rate\n");
1585                                 not_set = 1;
1586                         }
1587                 }
1588         }
1589
1590         current_rate = hdspm->system_sample_rate;
1591
1592         /* Changing between Singe, Double and Quad speed is not
1593            allowed if any substreams are open. This is because such a change
1594            causes a shift in the location of the DMA buffers and a reduction
1595            in the number of available buffers.
1596
1597            Note that a similar but essentially insoluble problem exists for
1598            externally-driven rate changes. All we can do is to flag rate
1599            changes in the read/write routines.
1600          */
1601
1602         if (current_rate <= 48000)
1603                 current_speed = HDSPM_SPEED_SINGLE;
1604         else if (current_rate <= 96000)
1605                 current_speed = HDSPM_SPEED_DOUBLE;
1606         else
1607                 current_speed = HDSPM_SPEED_QUAD;
1608
1609         if (rate <= 48000)
1610                 target_speed = HDSPM_SPEED_SINGLE;
1611         else if (rate <= 96000)
1612                 target_speed = HDSPM_SPEED_DOUBLE;
1613         else
1614                 target_speed = HDSPM_SPEED_QUAD;
1615
1616         switch (rate) {
1617         case 32000:
1618                 rate_bits = HDSPM_Frequency32KHz;
1619                 break;
1620         case 44100:
1621                 rate_bits = HDSPM_Frequency44_1KHz;
1622                 break;
1623         case 48000:
1624                 rate_bits = HDSPM_Frequency48KHz;
1625                 break;
1626         case 64000:
1627                 rate_bits = HDSPM_Frequency64KHz;
1628                 break;
1629         case 88200:
1630                 rate_bits = HDSPM_Frequency88_2KHz;
1631                 break;
1632         case 96000:
1633                 rate_bits = HDSPM_Frequency96KHz;
1634                 break;
1635         case 128000:
1636                 rate_bits = HDSPM_Frequency128KHz;
1637                 break;
1638         case 176400:
1639                 rate_bits = HDSPM_Frequency176_4KHz;
1640                 break;
1641         case 192000:
1642                 rate_bits = HDSPM_Frequency192KHz;
1643                 break;
1644         default:
1645                 return -EINVAL;
1646         }
1647
1648         if (current_speed != target_speed
1649             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1650                 snd_printk
1651                     (KERN_ERR "HDSPM: "
1652                      "cannot change from %s speed to %s speed mode "
1653                      "(capture PID = %d, playback PID = %d)\n",
1654                      hdspm_speed_names[current_speed],
1655                      hdspm_speed_names[target_speed],
1656                      hdspm->capture_pid, hdspm->playback_pid);
1657                 return -EBUSY;
1658         }
1659
1660         hdspm->control_register &= ~HDSPM_FrequencyMask;
1661         hdspm->control_register |= rate_bits;
1662         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1663
1664         /* For AES32, need to set DDS value in FREQ register
1665            For MADI, also apparently */
1666         hdspm_set_dds_value(hdspm, rate);
1667
1668         if (AES32 == hdspm->io_type && rate != current_rate)
1669                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1670
1671         hdspm->system_sample_rate = rate;
1672
1673         if (rate <= 48000) {
1674                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1675                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1676                 hdspm->max_channels_in = hdspm->ss_in_channels;
1677                 hdspm->max_channels_out = hdspm->ss_out_channels;
1678                 hdspm->port_names_in = hdspm->port_names_in_ss;
1679                 hdspm->port_names_out = hdspm->port_names_out_ss;
1680         } else if (rate <= 96000) {
1681                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1682                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1683                 hdspm->max_channels_in = hdspm->ds_in_channels;
1684                 hdspm->max_channels_out = hdspm->ds_out_channels;
1685                 hdspm->port_names_in = hdspm->port_names_in_ds;
1686                 hdspm->port_names_out = hdspm->port_names_out_ds;
1687         } else {
1688                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1689                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1690                 hdspm->max_channels_in = hdspm->qs_in_channels;
1691                 hdspm->max_channels_out = hdspm->qs_out_channels;
1692                 hdspm->port_names_in = hdspm->port_names_in_qs;
1693                 hdspm->port_names_out = hdspm->port_names_out_qs;
1694         }
1695
1696         if (not_set != 0)
1697                 return -1;
1698
1699         return 0;
1700 }
1701
1702 /* mainly for init to 0 on load */
1703 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1704 {
1705         int i, j;
1706         unsigned int gain;
1707
1708         if (sgain > UNITY_GAIN)
1709                 gain = UNITY_GAIN;
1710         else if (sgain < 0)
1711                 gain = 0;
1712         else
1713                 gain = sgain;
1714
1715         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1716                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1717                         hdspm_write_in_gain(hdspm, i, j, gain);
1718                         hdspm_write_pb_gain(hdspm, i, j, gain);
1719                 }
1720 }
1721
1722 /*----------------------------------------------------------------------------
1723    MIDI
1724   ----------------------------------------------------------------------------*/
1725
1726 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1727                                                       int id)
1728 {
1729         /* the hardware already does the relevant bit-mask with 0xff */
1730         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1731 }
1732
1733 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1734                                               int val)
1735 {
1736         /* the hardware already does the relevant bit-mask with 0xff */
1737         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1738 }
1739
1740 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1741 {
1742         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1743 }
1744
1745 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1746 {
1747         int fifo_bytes_used;
1748
1749         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1750
1751         if (fifo_bytes_used < 128)
1752                 return  128 - fifo_bytes_used;
1753         else
1754                 return 0;
1755 }
1756
1757 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1758 {
1759         while (snd_hdspm_midi_input_available (hdspm, id))
1760                 snd_hdspm_midi_read_byte (hdspm, id);
1761 }
1762
1763 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1764 {
1765         unsigned long flags;
1766         int n_pending;
1767         int to_write;
1768         int i;
1769         unsigned char buf[128];
1770
1771         /* Output is not interrupt driven */
1772
1773         spin_lock_irqsave (&hmidi->lock, flags);
1774         if (hmidi->output &&
1775             !snd_rawmidi_transmit_empty (hmidi->output)) {
1776                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1777                                                             hmidi->id);
1778                 if (n_pending > 0) {
1779                         if (n_pending > (int)sizeof (buf))
1780                                 n_pending = sizeof (buf);
1781
1782                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1783                                                          n_pending);
1784                         if (to_write > 0) {
1785                                 for (i = 0; i < to_write; ++i)
1786                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1787                                                                    hmidi->id,
1788                                                                    buf[i]);
1789                         }
1790                 }
1791         }
1792         spin_unlock_irqrestore (&hmidi->lock, flags);
1793         return 0;
1794 }
1795
1796 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1797 {
1798         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1799                                  * input FIFO size
1800                                  */
1801         unsigned long flags;
1802         int n_pending;
1803         int i;
1804
1805         spin_lock_irqsave (&hmidi->lock, flags);
1806         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1807         if (n_pending > 0) {
1808                 if (hmidi->input) {
1809                         if (n_pending > (int)sizeof (buf))
1810                                 n_pending = sizeof (buf);
1811                         for (i = 0; i < n_pending; ++i)
1812                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1813                                                                    hmidi->id);
1814                         if (n_pending)
1815                                 snd_rawmidi_receive (hmidi->input, buf,
1816                                                      n_pending);
1817                 } else {
1818                         /* flush the MIDI input FIFO */
1819                         while (n_pending--)
1820                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1821                                                           hmidi->id);
1822                 }
1823         }
1824         hmidi->pending = 0;
1825         spin_unlock_irqrestore(&hmidi->lock, flags);
1826
1827         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1828         hmidi->hdspm->control_register |= hmidi->ie;
1829         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1830                     hmidi->hdspm->control_register);
1831         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1832
1833         return snd_hdspm_midi_output_write (hmidi);
1834 }
1835
1836 static void
1837 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1838 {
1839         struct hdspm *hdspm;
1840         struct hdspm_midi *hmidi;
1841         unsigned long flags;
1842
1843         hmidi = substream->rmidi->private_data;
1844         hdspm = hmidi->hdspm;
1845
1846         spin_lock_irqsave (&hdspm->lock, flags);
1847         if (up) {
1848                 if (!(hdspm->control_register & hmidi->ie)) {
1849                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1850                         hdspm->control_register |= hmidi->ie;
1851                 }
1852         } else {
1853                 hdspm->control_register &= ~hmidi->ie;
1854         }
1855
1856         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1857         spin_unlock_irqrestore (&hdspm->lock, flags);
1858 }
1859
1860 static void snd_hdspm_midi_output_timer(unsigned long data)
1861 {
1862         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1863         unsigned long flags;
1864
1865         snd_hdspm_midi_output_write(hmidi);
1866         spin_lock_irqsave (&hmidi->lock, flags);
1867
1868         /* this does not bump hmidi->istimer, because the
1869            kernel automatically removed the timer when it
1870            expired, and we are now adding it back, thus
1871            leaving istimer wherever it was set before.
1872         */
1873
1874         if (hmidi->istimer) {
1875                 hmidi->timer.expires = 1 + jiffies;
1876                 add_timer(&hmidi->timer);
1877         }
1878
1879         spin_unlock_irqrestore (&hmidi->lock, flags);
1880 }
1881
1882 static void
1883 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1884 {
1885         struct hdspm_midi *hmidi;
1886         unsigned long flags;
1887
1888         hmidi = substream->rmidi->private_data;
1889         spin_lock_irqsave (&hmidi->lock, flags);
1890         if (up) {
1891                 if (!hmidi->istimer) {
1892                         init_timer(&hmidi->timer);
1893                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1894                         hmidi->timer.data = (unsigned long) hmidi;
1895                         hmidi->timer.expires = 1 + jiffies;
1896                         add_timer(&hmidi->timer);
1897                         hmidi->istimer++;
1898                 }
1899         } else {
1900                 if (hmidi->istimer && --hmidi->istimer <= 0)
1901                         del_timer (&hmidi->timer);
1902         }
1903         spin_unlock_irqrestore (&hmidi->lock, flags);
1904         if (up)
1905                 snd_hdspm_midi_output_write(hmidi);
1906 }
1907
1908 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1909 {
1910         struct hdspm_midi *hmidi;
1911
1912         hmidi = substream->rmidi->private_data;
1913         spin_lock_irq (&hmidi->lock);
1914         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1915         hmidi->input = substream;
1916         spin_unlock_irq (&hmidi->lock);
1917
1918         return 0;
1919 }
1920
1921 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1922 {
1923         struct hdspm_midi *hmidi;
1924
1925         hmidi = substream->rmidi->private_data;
1926         spin_lock_irq (&hmidi->lock);
1927         hmidi->output = substream;
1928         spin_unlock_irq (&hmidi->lock);
1929
1930         return 0;
1931 }
1932
1933 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1934 {
1935         struct hdspm_midi *hmidi;
1936
1937         snd_hdspm_midi_input_trigger (substream, 0);
1938
1939         hmidi = substream->rmidi->private_data;
1940         spin_lock_irq (&hmidi->lock);
1941         hmidi->input = NULL;
1942         spin_unlock_irq (&hmidi->lock);
1943
1944         return 0;
1945 }
1946
1947 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1948 {
1949         struct hdspm_midi *hmidi;
1950
1951         snd_hdspm_midi_output_trigger (substream, 0);
1952
1953         hmidi = substream->rmidi->private_data;
1954         spin_lock_irq (&hmidi->lock);
1955         hmidi->output = NULL;
1956         spin_unlock_irq (&hmidi->lock);
1957
1958         return 0;
1959 }
1960
1961 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1962 {
1963         .open =         snd_hdspm_midi_output_open,
1964         .close =        snd_hdspm_midi_output_close,
1965         .trigger =      snd_hdspm_midi_output_trigger,
1966 };
1967
1968 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1969 {
1970         .open =         snd_hdspm_midi_input_open,
1971         .close =        snd_hdspm_midi_input_close,
1972         .trigger =      snd_hdspm_midi_input_trigger,
1973 };
1974
1975 static int snd_hdspm_create_midi(struct snd_card *card,
1976                                  struct hdspm *hdspm, int id)
1977 {
1978         int err;
1979         char buf[32];
1980
1981         hdspm->midi[id].id = id;
1982         hdspm->midi[id].hdspm = hdspm;
1983         spin_lock_init (&hdspm->midi[id].lock);
1984
1985         if (0 == id) {
1986                 if (MADIface == hdspm->io_type) {
1987                         /* MIDI-over-MADI on HDSPe MADIface */
1988                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1989                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1990                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1991                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1992                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1993                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1994                 } else {
1995                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1996                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1997                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1998                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1999                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2000                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2001                 }
2002         } else if (1 == id) {
2003                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2004                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2005                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2006                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2007                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2008                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2009         } else if ((2 == id) && (MADI == hdspm->io_type)) {
2010                 /* MIDI-over-MADI on HDSPe MADI */
2011                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2012                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2013                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2014                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2015                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2016                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2017         } else if (2 == id) {
2018                 /* TCO MTC, read only */
2019                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2020                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2021                 hdspm->midi[2].dataOut = -1;
2022                 hdspm->midi[2].statusOut = -1;
2023                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2024                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2025         } else if (3 == id) {
2026                 /* TCO MTC on HDSPe MADI */
2027                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2028                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2029                 hdspm->midi[3].dataOut = -1;
2030                 hdspm->midi[3].statusOut = -1;
2031                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2032                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2033         }
2034
2035         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2036                                         (MADIface == hdspm->io_type)))) {
2037                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2038                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2039                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2040                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2041                 } else {
2042                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2043                 }
2044                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2045                                 &hdspm->midi[id].rmidi);
2046                 if (err < 0)
2047                         return err;
2048
2049                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2050                                 card->id, id+1);
2051                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2052
2053                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2054                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2055                                 &snd_hdspm_midi_output);
2056                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2057                                 SNDRV_RAWMIDI_STREAM_INPUT,
2058                                 &snd_hdspm_midi_input);
2059
2060                 hdspm->midi[id].rmidi->info_flags |=
2061                         SNDRV_RAWMIDI_INFO_OUTPUT |
2062                         SNDRV_RAWMIDI_INFO_INPUT |
2063                         SNDRV_RAWMIDI_INFO_DUPLEX;
2064         } else {
2065                 /* TCO MTC, read only */
2066                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2067                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2068                                 &hdspm->midi[id].rmidi);
2069                 if (err < 0)
2070                         return err;
2071
2072                 sprintf(hdspm->midi[id].rmidi->name,
2073                                 "%s MTC %d", card->id, id+1);
2074                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2075
2076                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2077                                 SNDRV_RAWMIDI_STREAM_INPUT,
2078                                 &snd_hdspm_midi_input);
2079
2080                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2081         }
2082
2083         return 0;
2084 }
2085
2086
2087 static void hdspm_midi_tasklet(unsigned long arg)
2088 {
2089         struct hdspm *hdspm = (struct hdspm *)arg;
2090         int i = 0;
2091
2092         while (i < hdspm->midiPorts) {
2093                 if (hdspm->midi[i].pending)
2094                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2095
2096                 i++;
2097         }
2098 }
2099
2100
2101 /*-----------------------------------------------------------------------------
2102   Status Interface
2103   ----------------------------------------------------------------------------*/
2104
2105 /* get the system sample rate which is set */
2106
2107
2108 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2109 {
2110         unsigned int period, rate;
2111
2112         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2113         rate = hdspm_calc_dds_value(hdspm, period);
2114
2115         return rate;
2116 }
2117
2118 /**
2119  * Calculate the real sample rate from the
2120  * current DDS value.
2121  **/
2122 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2123 {
2124         unsigned int rate;
2125
2126         rate = hdspm_get_pll_freq(hdspm);
2127
2128         if (rate > 207000) {
2129                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2130                 if (0 == hdspm_system_clock_mode(hdspm)) {
2131                         /* master mode, return internal sample rate */
2132                         rate = hdspm->system_sample_rate;
2133                 } else {
2134                         /* slave mode, return external sample rate */
2135                         rate = hdspm_external_sample_rate(hdspm);
2136                 }
2137         }
2138
2139         return rate;
2140 }
2141
2142
2143 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2144 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2145         .name = xname, \
2146         .index = xindex, \
2147         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2148                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2149         .info = snd_hdspm_info_system_sample_rate, \
2150         .put = snd_hdspm_put_system_sample_rate, \
2151         .get = snd_hdspm_get_system_sample_rate \
2152 }
2153
2154 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2155                                              struct snd_ctl_elem_info *uinfo)
2156 {
2157         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2158         uinfo->count = 1;
2159         uinfo->value.integer.min = 27000;
2160         uinfo->value.integer.max = 207000;
2161         uinfo->value.integer.step = 1;
2162         return 0;
2163 }
2164
2165
2166 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2167                                             struct snd_ctl_elem_value *
2168                                             ucontrol)
2169 {
2170         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2171
2172         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2173         return 0;
2174 }
2175
2176 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2177                                             struct snd_ctl_elem_value *
2178                                             ucontrol)
2179 {
2180         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2181
2182         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2183         return 0;
2184 }
2185
2186
2187 /**
2188  * Returns the WordClock sample rate class for the given card.
2189  **/
2190 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2191 {
2192         int status;
2193
2194         switch (hdspm->io_type) {
2195         case RayDAT:
2196         case AIO:
2197                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2198                 return (status >> 16) & 0xF;
2199                 break;
2200         case AES32:
2201                 status = hdspm_read(hdspm, HDSPM_statusRegister);
2202                 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2203         default:
2204                 break;
2205         }
2206
2207
2208         return 0;
2209 }
2210
2211
2212 /**
2213  * Returns the TCO sample rate class for the given card.
2214  **/
2215 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2216 {
2217         int status;
2218
2219         if (hdspm->tco) {
2220                 switch (hdspm->io_type) {
2221                 case RayDAT:
2222                 case AIO:
2223                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2224                         return (status >> 20) & 0xF;
2225                         break;
2226                 case AES32:
2227                         status = hdspm_read(hdspm, HDSPM_statusRegister);
2228                         return (status >> 1) & 0xF;
2229                 default:
2230                         break;
2231                 }
2232         }
2233
2234         return 0;
2235 }
2236
2237
2238 /**
2239  * Returns the SYNC_IN sample rate class for the given card.
2240  **/
2241 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2242 {
2243         int status;
2244
2245         if (hdspm->tco) {
2246                 switch (hdspm->io_type) {
2247                 case RayDAT:
2248                 case AIO:
2249                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2250                         return (status >> 12) & 0xF;
2251                         break;
2252                 default:
2253                         break;
2254                 }
2255         }
2256
2257         return 0;
2258 }
2259
2260 /**
2261  * Returns the AES sample rate class for the given card.
2262  **/
2263 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2264 {
2265         int timecode;
2266
2267         switch (hdspm->io_type) {
2268         case AES32:
2269                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2270                 return (timecode >> (4*index)) & 0xF;
2271                 break;
2272         default:
2273                 break;
2274         }
2275         return 0;
2276 }
2277
2278 /**
2279  * Returns the sample rate class for input source <idx> for
2280  * 'new style' cards like the AIO and RayDAT.
2281  **/
2282 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2283 {
2284         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2285
2286         return (status >> (idx*4)) & 0xF;
2287 }
2288
2289 static void snd_hdspm_set_infotext(struct snd_ctl_elem_info *uinfo,
2290                 char **texts, const int count)
2291 {
2292         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2293         uinfo->count = 1;
2294         uinfo->value.enumerated.items = count;
2295         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2296                 uinfo->value.enumerated.item =
2297                         uinfo->value.enumerated.items - 1;
2298         strcpy(uinfo->value.enumerated.name,
2299                         texts[uinfo->value.enumerated.item]);
2300 }
2301
2302 #define ENUMERATED_CTL_INFO(info, texts) \
2303         snd_hdspm_set_infotext(info, texts, ARRAY_SIZE(texts))
2304
2305
2306
2307 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2308 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2309         .name = xname, \
2310         .private_value = xindex, \
2311         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2312         .info = snd_hdspm_info_autosync_sample_rate, \
2313         .get = snd_hdspm_get_autosync_sample_rate \
2314 }
2315
2316
2317 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2318                                                struct snd_ctl_elem_info *uinfo)
2319 {
2320         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2321         return 0;
2322 }
2323
2324
2325 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2326                                               struct snd_ctl_elem_value *
2327                                               ucontrol)
2328 {
2329         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2330
2331         switch (hdspm->io_type) {
2332         case RayDAT:
2333                 switch (kcontrol->private_value) {
2334                 case 0:
2335                         ucontrol->value.enumerated.item[0] =
2336                                 hdspm_get_wc_sample_rate(hdspm);
2337                         break;
2338                 case 7:
2339                         ucontrol->value.enumerated.item[0] =
2340                                 hdspm_get_tco_sample_rate(hdspm);
2341                         break;
2342                 case 8:
2343                         ucontrol->value.enumerated.item[0] =
2344                                 hdspm_get_sync_in_sample_rate(hdspm);
2345                         break;
2346                 default:
2347                         ucontrol->value.enumerated.item[0] =
2348                                 hdspm_get_s1_sample_rate(hdspm,
2349                                                 kcontrol->private_value-1);
2350                 }
2351                 break;
2352
2353         case AIO:
2354                 switch (kcontrol->private_value) {
2355                 case 0: /* WC */
2356                         ucontrol->value.enumerated.item[0] =
2357                                 hdspm_get_wc_sample_rate(hdspm);
2358                         break;
2359                 case 4: /* TCO */
2360                         ucontrol->value.enumerated.item[0] =
2361                                 hdspm_get_tco_sample_rate(hdspm);
2362                         break;
2363                 case 5: /* SYNC_IN */
2364                         ucontrol->value.enumerated.item[0] =
2365                                 hdspm_get_sync_in_sample_rate(hdspm);
2366                         break;
2367                 default:
2368                         ucontrol->value.enumerated.item[0] =
2369                                 hdspm_get_s1_sample_rate(hdspm,
2370                                                 kcontrol->private_value-1);
2371                 }
2372                 break;
2373
2374         case AES32:
2375
2376                 switch (kcontrol->private_value) {
2377                 case 0: /* WC */
2378                         ucontrol->value.enumerated.item[0] =
2379                                 hdspm_get_wc_sample_rate(hdspm);
2380                         break;
2381                 case 9: /* TCO */
2382                         ucontrol->value.enumerated.item[0] =
2383                                 hdspm_get_tco_sample_rate(hdspm);
2384                         break;
2385                 case 10: /* SYNC_IN */
2386                         ucontrol->value.enumerated.item[0] =
2387                                 hdspm_get_sync_in_sample_rate(hdspm);
2388                         break;
2389                 default: /* AES1 to AES8 */
2390                         ucontrol->value.enumerated.item[0] =
2391                                 hdspm_get_s1_sample_rate(hdspm,
2392                                                 kcontrol->private_value-1);
2393                         break;
2394                 }
2395                 break;
2396
2397         case MADI:
2398         case MADIface:
2399                 {
2400                         int rate = hdspm_external_sample_rate(hdspm);
2401                         int i, selected_rate = 0;
2402                         for (i = 1; i < 10; i++)
2403                                 if (HDSPM_bit2freq(i) == rate) {
2404                                         selected_rate = i;
2405                                         break;
2406                                 }
2407                         ucontrol->value.enumerated.item[0] = selected_rate;
2408                 }
2409                 break;
2410
2411         default:
2412                 break;
2413         }
2414
2415         return 0;
2416 }
2417
2418
2419 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2420 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2421         .name = xname, \
2422         .index = xindex, \
2423         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2424                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2425         .info = snd_hdspm_info_system_clock_mode, \
2426         .get = snd_hdspm_get_system_clock_mode, \
2427         .put = snd_hdspm_put_system_clock_mode, \
2428 }
2429
2430
2431 /**
2432  * Returns the system clock mode for the given card.
2433  * @returns 0 - master, 1 - slave
2434  **/
2435 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2436 {
2437         switch (hdspm->io_type) {
2438         case AIO:
2439         case RayDAT:
2440                 if (hdspm->settings_register & HDSPM_c0Master)
2441                         return 0;
2442                 break;
2443
2444         default:
2445                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2446                         return 0;
2447         }
2448
2449         return 1;
2450 }
2451
2452
2453 /**
2454  * Sets the system clock mode.
2455  * @param mode 0 - master, 1 - slave
2456  **/
2457 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2458 {
2459         hdspm_set_toggle_setting(hdspm,
2460                         (hdspm_is_raydat_or_aio(hdspm)) ?
2461                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2462                         (0 == mode));
2463 }
2464
2465
2466 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2467                                             struct snd_ctl_elem_info *uinfo)
2468 {
2469         static char *texts[] = { "Master", "AutoSync" };
2470         ENUMERATED_CTL_INFO(uinfo, texts);
2471         return 0;
2472 }
2473
2474 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2475                                            struct snd_ctl_elem_value *ucontrol)
2476 {
2477         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2478
2479         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2480         return 0;
2481 }
2482
2483 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2484                                            struct snd_ctl_elem_value *ucontrol)
2485 {
2486         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2487         int val;
2488
2489         if (!snd_hdspm_use_is_exclusive(hdspm))
2490                 return -EBUSY;
2491
2492         val = ucontrol->value.enumerated.item[0];
2493         if (val < 0)
2494                 val = 0;
2495         else if (val > 1)
2496                 val = 1;
2497
2498         hdspm_set_system_clock_mode(hdspm, val);
2499
2500         return 0;
2501 }
2502
2503
2504 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2505 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2506         .name = xname, \
2507         .index = xindex, \
2508         .info = snd_hdspm_info_clock_source, \
2509         .get = snd_hdspm_get_clock_source, \
2510         .put = snd_hdspm_put_clock_source \
2511 }
2512
2513
2514 static int hdspm_clock_source(struct hdspm * hdspm)
2515 {
2516         switch (hdspm->system_sample_rate) {
2517         case 32000: return 0;
2518         case 44100: return 1;
2519         case 48000: return 2;
2520         case 64000: return 3;
2521         case 88200: return 4;
2522         case 96000: return 5;
2523         case 128000: return 6;
2524         case 176400: return 7;
2525         case 192000: return 8;
2526         }
2527
2528         return -1;
2529 }
2530
2531 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2532 {
2533         int rate;
2534         switch (mode) {
2535         case 0:
2536                 rate = 32000; break;
2537         case 1:
2538                 rate = 44100; break;
2539         case 2:
2540                 rate = 48000; break;
2541         case 3:
2542                 rate = 64000; break;
2543         case 4:
2544                 rate = 88200; break;
2545         case 5:
2546                 rate = 96000; break;
2547         case 6:
2548                 rate = 128000; break;
2549         case 7:
2550                 rate = 176400; break;
2551         case 8:
2552                 rate = 192000; break;
2553         default:
2554                 rate = 48000;
2555         }
2556         hdspm_set_rate(hdspm, rate, 1);
2557         return 0;
2558 }
2559
2560 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2561                                        struct snd_ctl_elem_info *uinfo)
2562 {
2563         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2564         uinfo->count = 1;
2565         uinfo->value.enumerated.items = 9;
2566
2567         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2568                 uinfo->value.enumerated.item =
2569                     uinfo->value.enumerated.items - 1;
2570
2571         strcpy(uinfo->value.enumerated.name,
2572                texts_freq[uinfo->value.enumerated.item+1]);
2573
2574         return 0;
2575 }
2576
2577 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2578                                       struct snd_ctl_elem_value *ucontrol)
2579 {
2580         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2581
2582         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2583         return 0;
2584 }
2585
2586 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2587                                       struct snd_ctl_elem_value *ucontrol)
2588 {
2589         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2590         int change;
2591         int val;
2592
2593         if (!snd_hdspm_use_is_exclusive(hdspm))
2594                 return -EBUSY;
2595         val = ucontrol->value.enumerated.item[0];
2596         if (val < 0)
2597                 val = 0;
2598         if (val > 9)
2599                 val = 9;
2600         spin_lock_irq(&hdspm->lock);
2601         if (val != hdspm_clock_source(hdspm))
2602                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2603         else
2604                 change = 0;
2605         spin_unlock_irq(&hdspm->lock);
2606         return change;
2607 }
2608
2609
2610 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2611 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2612         .name = xname, \
2613         .index = xindex, \
2614         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2615                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2616         .info = snd_hdspm_info_pref_sync_ref, \
2617         .get = snd_hdspm_get_pref_sync_ref, \
2618         .put = snd_hdspm_put_pref_sync_ref \
2619 }
2620
2621
2622 /**
2623  * Returns the current preferred sync reference setting.
2624  * The semantics of the return value are depending on the
2625  * card, please see the comments for clarification.
2626  **/
2627 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2628 {
2629         switch (hdspm->io_type) {
2630         case AES32:
2631                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2632                 case 0: return 0;  /* WC */
2633                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2634                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2635                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2636                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2637                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2638                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2639                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2640                                                     return 7; /* AES 7 */
2641                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2642                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2643                 }
2644                 break;
2645
2646         case MADI:
2647         case MADIface:
2648                 if (hdspm->tco) {
2649                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2650                         case 0: return 0;  /* WC */
2651                         case HDSPM_SyncRef0: return 1;  /* MADI */
2652                         case HDSPM_SyncRef1: return 2;  /* TCO */
2653                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2654                                              return 3;  /* SYNC_IN */
2655                         }
2656                 } else {
2657                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2658                         case 0: return 0;  /* WC */
2659                         case HDSPM_SyncRef0: return 1;  /* MADI */
2660                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2661                                              return 2;  /* SYNC_IN */
2662                         }
2663                 }
2664                 break;
2665
2666         case RayDAT:
2667                 if (hdspm->tco) {
2668                         switch ((hdspm->settings_register &
2669                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2670                         case 0: return 0;  /* WC */
2671                         case 3: return 1;  /* ADAT 1 */
2672                         case 4: return 2;  /* ADAT 2 */
2673                         case 5: return 3;  /* ADAT 3 */
2674                         case 6: return 4;  /* ADAT 4 */
2675                         case 1: return 5;  /* AES */
2676                         case 2: return 6;  /* SPDIF */
2677                         case 9: return 7;  /* TCO */
2678                         case 10: return 8; /* SYNC_IN */
2679                         }
2680                 } else {
2681                         switch ((hdspm->settings_register &
2682                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2683                         case 0: return 0;  /* WC */
2684                         case 3: return 1;  /* ADAT 1 */
2685                         case 4: return 2;  /* ADAT 2 */
2686                         case 5: return 3;  /* ADAT 3 */
2687                         case 6: return 4;  /* ADAT 4 */
2688                         case 1: return 5;  /* AES */
2689                         case 2: return 6;  /* SPDIF */
2690                         case 10: return 7; /* SYNC_IN */
2691                         }
2692                 }
2693
2694                 break;
2695
2696         case AIO:
2697                 if (hdspm->tco) {
2698                         switch ((hdspm->settings_register &
2699                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2700                         case 0: return 0;  /* WC */
2701                         case 3: return 1;  /* ADAT */
2702                         case 1: return 2;  /* AES */
2703                         case 2: return 3;  /* SPDIF */
2704                         case 9: return 4;  /* TCO */
2705                         case 10: return 5; /* SYNC_IN */
2706                         }
2707                 } else {
2708                         switch ((hdspm->settings_register &
2709                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2710                         case 0: return 0;  /* WC */
2711                         case 3: return 1;  /* ADAT */
2712                         case 1: return 2;  /* AES */
2713                         case 2: return 3;  /* SPDIF */
2714                         case 10: return 4; /* SYNC_IN */
2715                         }
2716                 }
2717
2718                 break;
2719         }
2720
2721         return -1;
2722 }
2723
2724
2725 /**
2726  * Set the preferred sync reference to <pref>. The semantics
2727  * of <pref> are depending on the card type, see the comments
2728  * for clarification.
2729  **/
2730 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2731 {
2732         int p = 0;
2733
2734         switch (hdspm->io_type) {
2735         case AES32:
2736                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2737                 switch (pref) {
2738                 case 0: /* WC  */
2739                         break;
2740                 case 1: /* AES 1 */
2741                         hdspm->control_register |= HDSPM_SyncRef0;
2742                         break;
2743                 case 2: /* AES 2 */
2744                         hdspm->control_register |= HDSPM_SyncRef1;
2745                         break;
2746                 case 3: /* AES 3 */
2747                         hdspm->control_register |=
2748                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2749                         break;
2750                 case 4: /* AES 4 */
2751                         hdspm->control_register |= HDSPM_SyncRef2;
2752                         break;
2753                 case 5: /* AES 5 */
2754                         hdspm->control_register |=
2755                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2756                         break;
2757                 case 6: /* AES 6 */
2758                         hdspm->control_register |=
2759                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2760                         break;
2761                 case 7: /* AES 7 */
2762                         hdspm->control_register |=
2763                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2764                         break;
2765                 case 8: /* AES 8 */
2766                         hdspm->control_register |= HDSPM_SyncRef3;
2767                         break;
2768                 case 9: /* TCO */
2769                         hdspm->control_register |=
2770                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2771                         break;
2772                 default:
2773                         return -1;
2774                 }
2775
2776                 break;
2777
2778         case MADI:
2779         case MADIface:
2780                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2781                 if (hdspm->tco) {
2782                         switch (pref) {
2783                         case 0: /* WC */
2784                                 break;
2785                         case 1: /* MADI */
2786                                 hdspm->control_register |= HDSPM_SyncRef0;
2787                                 break;
2788                         case 2: /* TCO */
2789                                 hdspm->control_register |= HDSPM_SyncRef1;
2790                                 break;
2791                         case 3: /* SYNC_IN */
2792                                 hdspm->control_register |=
2793                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2794                                 break;
2795                         default:
2796                                 return -1;
2797                         }
2798                 } else {
2799                         switch (pref) {
2800                         case 0: /* WC */
2801                                 break;
2802                         case 1: /* MADI */
2803                                 hdspm->control_register |= HDSPM_SyncRef0;
2804                                 break;
2805                         case 2: /* SYNC_IN */
2806                                 hdspm->control_register |=
2807                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2808                                 break;
2809                         default:
2810                                 return -1;
2811                         }
2812                 }
2813
2814                 break;
2815
2816         case RayDAT:
2817                 if (hdspm->tco) {
2818                         switch (pref) {
2819                         case 0: p = 0; break;  /* WC */
2820                         case 1: p = 3; break;  /* ADAT 1 */
2821                         case 2: p = 4; break;  /* ADAT 2 */
2822                         case 3: p = 5; break;  /* ADAT 3 */
2823                         case 4: p = 6; break;  /* ADAT 4 */
2824                         case 5: p = 1; break;  /* AES */
2825                         case 6: p = 2; break;  /* SPDIF */
2826                         case 7: p = 9; break;  /* TCO */
2827                         case 8: p = 10; break; /* SYNC_IN */
2828                         default: return -1;
2829                         }
2830                 } else {
2831                         switch (pref) {
2832                         case 0: p = 0; break;  /* WC */
2833                         case 1: p = 3; break;  /* ADAT 1 */
2834                         case 2: p = 4; break;  /* ADAT 2 */
2835                         case 3: p = 5; break;  /* ADAT 3 */
2836                         case 4: p = 6; break;  /* ADAT 4 */
2837                         case 5: p = 1; break;  /* AES */
2838                         case 6: p = 2; break;  /* SPDIF */
2839                         case 7: p = 10; break; /* SYNC_IN */
2840                         default: return -1;
2841                         }
2842                 }
2843                 break;
2844
2845         case AIO:
2846                 if (hdspm->tco) {
2847                         switch (pref) {
2848                         case 0: p = 0; break;  /* WC */
2849                         case 1: p = 3; break;  /* ADAT */
2850                         case 2: p = 1; break;  /* AES */
2851                         case 3: p = 2; break;  /* SPDIF */
2852                         case 4: p = 9; break;  /* TCO */
2853                         case 5: p = 10; break; /* SYNC_IN */
2854                         default: return -1;
2855                         }
2856                 } else {
2857                         switch (pref) {
2858                         case 0: p = 0; break;  /* WC */
2859                         case 1: p = 3; break;  /* ADAT */
2860                         case 2: p = 1; break;  /* AES */
2861                         case 3: p = 2; break;  /* SPDIF */
2862                         case 4: p = 10; break; /* SYNC_IN */
2863                         default: return -1;
2864                         }
2865                 }
2866                 break;
2867         }
2868
2869         switch (hdspm->io_type) {
2870         case RayDAT:
2871         case AIO:
2872                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2873                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2874                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2875                 break;
2876
2877         case MADI:
2878         case MADIface:
2879         case AES32:
2880                 hdspm_write(hdspm, HDSPM_controlRegister,
2881                                 hdspm->control_register);
2882         }
2883
2884         return 0;
2885 }
2886
2887
2888 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2889                                         struct snd_ctl_elem_info *uinfo)
2890 {
2891         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2892
2893         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2894         uinfo->count = 1;
2895         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2896
2897         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2898                 uinfo->value.enumerated.item =
2899                         uinfo->value.enumerated.items - 1;
2900
2901         strcpy(uinfo->value.enumerated.name,
2902                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2903
2904         return 0;
2905 }
2906
2907 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2908                                        struct snd_ctl_elem_value *ucontrol)
2909 {
2910         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2911         int psf = hdspm_pref_sync_ref(hdspm);
2912
2913         if (psf >= 0) {
2914                 ucontrol->value.enumerated.item[0] = psf;
2915                 return 0;
2916         }
2917
2918         return -1;
2919 }
2920
2921 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2922                                        struct snd_ctl_elem_value *ucontrol)
2923 {
2924         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2925         int val, change = 0;
2926
2927         if (!snd_hdspm_use_is_exclusive(hdspm))
2928                 return -EBUSY;
2929
2930         val = ucontrol->value.enumerated.item[0];
2931
2932         if (val < 0)
2933                 val = 0;
2934         else if (val >= hdspm->texts_autosync_items)
2935                 val = hdspm->texts_autosync_items-1;
2936
2937         spin_lock_irq(&hdspm->lock);
2938         if (val != hdspm_pref_sync_ref(hdspm))
2939                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2940
2941         spin_unlock_irq(&hdspm->lock);
2942         return change;
2943 }
2944
2945
2946 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2947 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2948         .name = xname, \
2949         .index = xindex, \
2950         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2951         .info = snd_hdspm_info_autosync_ref, \
2952         .get = snd_hdspm_get_autosync_ref, \
2953 }
2954
2955 static int hdspm_autosync_ref(struct hdspm *hdspm)
2956 {
2957         /* This looks at the autosync selected sync reference */
2958         if (AES32 == hdspm->io_type) {
2959
2960                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2961                 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
2962                 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
2963                                 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
2964                         return syncref;
2965                 }
2966                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2967
2968         } else if (MADI == hdspm->io_type) {
2969
2970                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2971                 switch (status2 & HDSPM_SelSyncRefMask) {
2972                 case HDSPM_SelSyncRef_WORD:
2973                         return HDSPM_AUTOSYNC_FROM_WORD;
2974                 case HDSPM_SelSyncRef_MADI:
2975                         return HDSPM_AUTOSYNC_FROM_MADI;
2976                 case HDSPM_SelSyncRef_TCO:
2977                         return HDSPM_AUTOSYNC_FROM_TCO;
2978                 case HDSPM_SelSyncRef_SyncIn:
2979                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2980                 case HDSPM_SelSyncRef_NVALID:
2981                         return HDSPM_AUTOSYNC_FROM_NONE;
2982                 default:
2983                         return HDSPM_AUTOSYNC_FROM_NONE;
2984                 }
2985
2986         }
2987         return 0;
2988 }
2989
2990
2991 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2992                                        struct snd_ctl_elem_info *uinfo)
2993 {
2994         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2995
2996         if (AES32 == hdspm->io_type) {
2997                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2998                         "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
2999
3000                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3001                 uinfo->count = 1;
3002                 uinfo->value.enumerated.items = ARRAY_SIZE(texts);
3003                 if (uinfo->value.enumerated.item >=
3004                     uinfo->value.enumerated.items)
3005                         uinfo->value.enumerated.item =
3006                                 uinfo->value.enumerated.items - 1;
3007                 strcpy(uinfo->value.enumerated.name,
3008                                 texts[uinfo->value.enumerated.item]);
3009         } else if (MADI == hdspm->io_type) {
3010                 static char *texts[] = {"Word Clock", "MADI", "TCO",
3011                         "Sync In", "None" };
3012
3013                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3014                 uinfo->count = 1;
3015                 uinfo->value.enumerated.items = 5;
3016                 if (uinfo->value.enumerated.item >=
3017                                 uinfo->value.enumerated.items)
3018                         uinfo->value.enumerated.item =
3019                                 uinfo->value.enumerated.items - 1;
3020                 strcpy(uinfo->value.enumerated.name,
3021                                 texts[uinfo->value.enumerated.item]);
3022         }
3023         return 0;
3024 }
3025
3026 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3027                                       struct snd_ctl_elem_value *ucontrol)
3028 {
3029         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3030
3031         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3032         return 0;
3033 }
3034
3035
3036
3037 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3038 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3039         .name = xname, \
3040         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3041                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3042         .info = snd_hdspm_info_tco_video_input_format, \
3043         .get = snd_hdspm_get_tco_video_input_format, \
3044 }
3045
3046 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3047                                        struct snd_ctl_elem_info *uinfo)
3048 {
3049         static char *texts[] = {"No video", "NTSC", "PAL"};
3050         ENUMERATED_CTL_INFO(uinfo, texts);
3051         return 0;
3052 }
3053
3054 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3055                                       struct snd_ctl_elem_value *ucontrol)
3056 {
3057         u32 status;
3058         int ret = 0;
3059
3060         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3061         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3062         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3063                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3064         case HDSPM_TCO1_Video_Input_Format_NTSC:
3065                 /* ntsc */
3066                 ret = 1;
3067                 break;
3068         case HDSPM_TCO1_Video_Input_Format_PAL:
3069                 /* pal */
3070                 ret = 2;
3071                 break;
3072         default:
3073                 /* no video */
3074                 ret = 0;
3075                 break;
3076         }
3077         ucontrol->value.enumerated.item[0] = ret;
3078         return 0;
3079 }
3080
3081
3082
3083 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3084 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3085         .name = xname, \
3086         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3087                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3088         .info = snd_hdspm_info_tco_ltc_frames, \
3089         .get = snd_hdspm_get_tco_ltc_frames, \
3090 }
3091
3092 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3093                                        struct snd_ctl_elem_info *uinfo)
3094 {
3095         static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3096                                 "30 fps"};
3097         ENUMERATED_CTL_INFO(uinfo, texts);
3098         return 0;
3099 }
3100
3101 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3102 {
3103         u32 status;
3104         int ret = 0;
3105
3106         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3107         if (status & HDSPM_TCO1_LTC_Input_valid) {
3108                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3109                                         HDSPM_TCO1_LTC_Format_MSB)) {
3110                 case 0:
3111                         /* 24 fps */
3112                         ret = 1;
3113                         break;
3114                 case HDSPM_TCO1_LTC_Format_LSB:
3115                         /* 25 fps */
3116                         ret = 2;
3117                         break;
3118                 case HDSPM_TCO1_LTC_Format_MSB:
3119                         /* 25 fps */
3120                         ret = 3;
3121                         break;
3122                 default:
3123                         /* 30 fps */
3124                         ret = 4;
3125                         break;
3126                 }
3127         }
3128
3129         return ret;
3130 }
3131
3132 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3133                                       struct snd_ctl_elem_value *ucontrol)
3134 {
3135         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3136
3137         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3138         return 0;
3139 }
3140
3141 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3142 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3143         .name = xname, \
3144         .private_value = xindex, \
3145         .info = snd_hdspm_info_toggle_setting, \
3146         .get = snd_hdspm_get_toggle_setting, \
3147         .put = snd_hdspm_put_toggle_setting \
3148 }
3149
3150 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3151 {
3152         u32 reg;
3153
3154         if (hdspm_is_raydat_or_aio(hdspm))
3155                 reg = hdspm->settings_register;
3156         else
3157                 reg = hdspm->control_register;
3158
3159         return (reg & regmask) ? 1 : 0;
3160 }
3161
3162 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3163 {
3164         u32 *reg;
3165         u32 target_reg;
3166
3167         if (hdspm_is_raydat_or_aio(hdspm)) {
3168                 reg = &(hdspm->settings_register);
3169                 target_reg = HDSPM_WR_SETTINGS;
3170         } else {
3171                 reg = &(hdspm->control_register);
3172                 target_reg = HDSPM_controlRegister;
3173         }
3174
3175         if (out)
3176                 *reg |= regmask;
3177         else
3178                 *reg &= ~regmask;
3179
3180         hdspm_write(hdspm, target_reg, *reg);
3181
3182         return 0;
3183 }
3184
3185 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3186
3187 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3188                                struct snd_ctl_elem_value *ucontrol)
3189 {
3190         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3191         u32 regmask = kcontrol->private_value;
3192
3193         spin_lock_irq(&hdspm->lock);
3194         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3195         spin_unlock_irq(&hdspm->lock);
3196         return 0;
3197 }
3198
3199 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3200                                struct snd_ctl_elem_value *ucontrol)
3201 {
3202         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3203         u32 regmask = kcontrol->private_value;
3204         int change;
3205         unsigned int val;
3206
3207         if (!snd_hdspm_use_is_exclusive(hdspm))
3208                 return -EBUSY;
3209         val = ucontrol->value.integer.value[0] & 1;
3210         spin_lock_irq(&hdspm->lock);
3211         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3212         hdspm_set_toggle_setting(hdspm, regmask, val);
3213         spin_unlock_irq(&hdspm->lock);
3214         return change;
3215 }
3216
3217 #define HDSPM_INPUT_SELECT(xname, xindex) \
3218 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3219         .name = xname, \
3220         .index = xindex, \
3221         .info = snd_hdspm_info_input_select, \
3222         .get = snd_hdspm_get_input_select, \
3223         .put = snd_hdspm_put_input_select \
3224 }
3225
3226 static int hdspm_input_select(struct hdspm * hdspm)
3227 {
3228         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3229 }
3230
3231 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3232 {
3233         if (out)
3234                 hdspm->control_register |= HDSPM_InputSelect0;
3235         else
3236                 hdspm->control_register &= ~HDSPM_InputSelect0;
3237         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3238
3239         return 0;
3240 }
3241
3242 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3243                                        struct snd_ctl_elem_info *uinfo)
3244 {
3245         static char *texts[] = { "optical", "coaxial" };
3246         ENUMERATED_CTL_INFO(uinfo, texts);
3247         return 0;
3248 }
3249
3250 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3251                                       struct snd_ctl_elem_value *ucontrol)
3252 {
3253         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3254
3255         spin_lock_irq(&hdspm->lock);
3256         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3257         spin_unlock_irq(&hdspm->lock);
3258         return 0;
3259 }
3260
3261 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3262                                       struct snd_ctl_elem_value *ucontrol)
3263 {
3264         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3265         int change;
3266         unsigned int val;
3267
3268         if (!snd_hdspm_use_is_exclusive(hdspm))
3269                 return -EBUSY;
3270         val = ucontrol->value.integer.value[0] & 1;
3271         spin_lock_irq(&hdspm->lock);
3272         change = (int) val != hdspm_input_select(hdspm);
3273         hdspm_set_input_select(hdspm, val);
3274         spin_unlock_irq(&hdspm->lock);
3275         return change;
3276 }
3277
3278
3279 #define HDSPM_DS_WIRE(xname, xindex) \
3280 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3281         .name = xname, \
3282         .index = xindex, \
3283         .info = snd_hdspm_info_ds_wire, \
3284         .get = snd_hdspm_get_ds_wire, \
3285         .put = snd_hdspm_put_ds_wire \
3286 }
3287
3288 static int hdspm_ds_wire(struct hdspm * hdspm)
3289 {
3290         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3291 }
3292
3293 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3294 {
3295         if (ds)
3296                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3297         else
3298                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3299         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3300
3301         return 0;
3302 }
3303
3304 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3305                                   struct snd_ctl_elem_info *uinfo)
3306 {
3307         static char *texts[] = { "Single", "Double" };
3308         ENUMERATED_CTL_INFO(uinfo, texts);
3309         return 0;
3310 }
3311
3312 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3313                                  struct snd_ctl_elem_value *ucontrol)
3314 {
3315         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3316
3317         spin_lock_irq(&hdspm->lock);
3318         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3319         spin_unlock_irq(&hdspm->lock);
3320         return 0;
3321 }
3322
3323 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3324                                  struct snd_ctl_elem_value *ucontrol)
3325 {
3326         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3327         int change;
3328         unsigned int val;
3329
3330         if (!snd_hdspm_use_is_exclusive(hdspm))
3331                 return -EBUSY;
3332         val = ucontrol->value.integer.value[0] & 1;
3333         spin_lock_irq(&hdspm->lock);
3334         change = (int) val != hdspm_ds_wire(hdspm);
3335         hdspm_set_ds_wire(hdspm, val);
3336         spin_unlock_irq(&hdspm->lock);
3337         return change;
3338 }
3339
3340
3341 #define HDSPM_QS_WIRE(xname, xindex) \
3342 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3343         .name = xname, \
3344         .index = xindex, \
3345         .info = snd_hdspm_info_qs_wire, \
3346         .get = snd_hdspm_get_qs_wire, \
3347         .put = snd_hdspm_put_qs_wire \
3348 }
3349
3350 static int hdspm_qs_wire(struct hdspm * hdspm)
3351 {
3352         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3353                 return 1;
3354         if (hdspm->control_register & HDSPM_QS_QuadWire)
3355                 return 2;
3356         return 0;
3357 }
3358
3359 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3360 {
3361         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3362         switch (mode) {
3363         case 0:
3364                 break;
3365         case 1:
3366                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3367                 break;
3368         case 2:
3369                 hdspm->control_register |= HDSPM_QS_QuadWire;
3370                 break;
3371         }
3372         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3373
3374         return 0;
3375 }
3376
3377 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3378                                        struct snd_ctl_elem_info *uinfo)
3379 {
3380         static char *texts[] = { "Single", "Double", "Quad" };
3381         ENUMERATED_CTL_INFO(uinfo, texts);
3382         return 0;
3383 }
3384
3385 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3386                                       struct snd_ctl_elem_value *ucontrol)
3387 {
3388         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3389
3390         spin_lock_irq(&hdspm->lock);
3391         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3392         spin_unlock_irq(&hdspm->lock);
3393         return 0;
3394 }
3395
3396 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3397                                       struct snd_ctl_elem_value *ucontrol)
3398 {
3399         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3400         int change;
3401         int val;
3402
3403         if (!snd_hdspm_use_is_exclusive(hdspm))
3404                 return -EBUSY;
3405         val = ucontrol->value.integer.value[0];
3406         if (val < 0)
3407                 val = 0;
3408         if (val > 2)
3409                 val = 2;
3410         spin_lock_irq(&hdspm->lock);
3411         change = val != hdspm_qs_wire(hdspm);
3412         hdspm_set_qs_wire(hdspm, val);
3413         spin_unlock_irq(&hdspm->lock);
3414         return change;
3415 }
3416
3417 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3418 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3419         .name = xname, \
3420         .private_value = xindex, \
3421         .info = snd_hdspm_info_tristate, \
3422         .get = snd_hdspm_get_tristate, \
3423         .put = snd_hdspm_put_tristate \
3424 }
3425
3426 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3427 {
3428         u32 reg = hdspm->settings_register & (regmask * 3);
3429         return reg / regmask;
3430 }
3431
3432 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3433 {
3434         hdspm->settings_register &= ~(regmask * 3);
3435         hdspm->settings_register |= (regmask * mode);
3436         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3437
3438         return 0;
3439 }
3440
3441 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3442                                        struct snd_ctl_elem_info *uinfo)
3443 {
3444         u32 regmask = kcontrol->private_value;
3445
3446         static char *texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3447         static char *texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3448
3449         switch (regmask) {
3450         case HDSPM_c0_Input0:
3451                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3452                 break;
3453         default:
3454                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3455                 break;
3456         }
3457         return 0;
3458 }
3459
3460 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3461                                       struct snd_ctl_elem_value *ucontrol)
3462 {
3463         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3464         u32 regmask = kcontrol->private_value;
3465
3466         spin_lock_irq(&hdspm->lock);
3467         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3468         spin_unlock_irq(&hdspm->lock);
3469         return 0;
3470 }
3471
3472 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3473                                       struct snd_ctl_elem_value *ucontrol)
3474 {
3475         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3476         u32 regmask = kcontrol->private_value;
3477         int change;
3478         int val;
3479
3480         if (!snd_hdspm_use_is_exclusive(hdspm))
3481                 return -EBUSY;
3482         val = ucontrol->value.integer.value[0];
3483         if (val < 0)
3484                 val = 0;
3485         if (val > 2)
3486                 val = 2;
3487
3488         spin_lock_irq(&hdspm->lock);
3489         change = val != hdspm_tristate(hdspm, regmask);
3490         hdspm_set_tristate(hdspm, val, regmask);
3491         spin_unlock_irq(&hdspm->lock);
3492         return change;
3493 }
3494
3495 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3496 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3497         .name = xname, \
3498         .index = xindex, \
3499         .info = snd_hdspm_info_madi_speedmode, \
3500         .get = snd_hdspm_get_madi_speedmode, \
3501         .put = snd_hdspm_put_madi_speedmode \
3502 }
3503
3504 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3505 {
3506         if (hdspm->control_register & HDSPM_QuadSpeed)
3507                 return 2;
3508         if (hdspm->control_register & HDSPM_DoubleSpeed)
3509                 return 1;
3510         return 0;
3511 }
3512
3513 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3514 {
3515         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3516         switch (mode) {
3517         case 0:
3518                 break;
3519         case 1:
3520                 hdspm->control_register |= HDSPM_DoubleSpeed;
3521                 break;
3522         case 2:
3523                 hdspm->control_register |= HDSPM_QuadSpeed;
3524                 break;
3525         }
3526         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3527
3528         return 0;
3529 }
3530
3531 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3532                                        struct snd_ctl_elem_info *uinfo)
3533 {
3534         static char *texts[] = { "Single", "Double", "Quad" };
3535         ENUMERATED_CTL_INFO(uinfo, texts);
3536         return 0;
3537 }
3538
3539 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3540                                       struct snd_ctl_elem_value *ucontrol)
3541 {
3542         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3543
3544         spin_lock_irq(&hdspm->lock);
3545         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3546         spin_unlock_irq(&hdspm->lock);
3547         return 0;
3548 }
3549
3550 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3551                                       struct snd_ctl_elem_value *ucontrol)
3552 {
3553         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3554         int change;
3555         int val;
3556
3557         if (!snd_hdspm_use_is_exclusive(hdspm))
3558                 return -EBUSY;
3559         val = ucontrol->value.integer.value[0];
3560         if (val < 0)
3561                 val = 0;
3562         if (val > 2)
3563                 val = 2;
3564         spin_lock_irq(&hdspm->lock);
3565         change = val != hdspm_madi_speedmode(hdspm);
3566         hdspm_set_madi_speedmode(hdspm, val);
3567         spin_unlock_irq(&hdspm->lock);
3568         return change;
3569 }
3570
3571 #define HDSPM_MIXER(xname, xindex) \
3572 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3573         .name = xname, \
3574         .index = xindex, \
3575         .device = 0, \
3576         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3577                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3578         .info = snd_hdspm_info_mixer, \
3579         .get = snd_hdspm_get_mixer, \
3580         .put = snd_hdspm_put_mixer \
3581 }
3582
3583 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3584                                 struct snd_ctl_elem_info *uinfo)
3585 {
3586         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3587         uinfo->count = 3;
3588         uinfo->value.integer.min = 0;
3589         uinfo->value.integer.max = 65535;
3590         uinfo->value.integer.step = 1;
3591         return 0;
3592 }
3593
3594 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3595                                struct snd_ctl_elem_value *ucontrol)
3596 {
3597         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3598         int source;
3599         int destination;
3600
3601         source = ucontrol->value.integer.value[0];
3602         if (source < 0)
3603                 source = 0;
3604         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3605                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3606
3607         destination = ucontrol->value.integer.value[1];
3608         if (destination < 0)
3609                 destination = 0;
3610         else if (destination >= HDSPM_MAX_CHANNELS)
3611                 destination = HDSPM_MAX_CHANNELS - 1;
3612
3613         spin_lock_irq(&hdspm->lock);
3614         if (source >= HDSPM_MAX_CHANNELS)
3615                 ucontrol->value.integer.value[2] =
3616                     hdspm_read_pb_gain(hdspm, destination,
3617                                        source - HDSPM_MAX_CHANNELS);
3618         else
3619                 ucontrol->value.integer.value[2] =
3620                     hdspm_read_in_gain(hdspm, destination, source);
3621
3622         spin_unlock_irq(&hdspm->lock);
3623
3624         return 0;
3625 }
3626
3627 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3628                                struct snd_ctl_elem_value *ucontrol)
3629 {
3630         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3631         int change;
3632         int source;
3633         int destination;
3634         int gain;
3635
3636         if (!snd_hdspm_use_is_exclusive(hdspm))
3637                 return -EBUSY;
3638
3639         source = ucontrol->value.integer.value[0];
3640         destination = ucontrol->value.integer.value[1];
3641
3642         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3643                 return -1;
3644         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3645                 return -1;
3646
3647         gain = ucontrol->value.integer.value[2];
3648
3649         spin_lock_irq(&hdspm->lock);
3650
3651         if (source >= HDSPM_MAX_CHANNELS)
3652                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3653                                                     source -
3654                                                     HDSPM_MAX_CHANNELS);
3655         else
3656                 change = gain != hdspm_read_in_gain(hdspm, destination,
3657                                                     source);
3658
3659         if (change) {
3660                 if (source >= HDSPM_MAX_CHANNELS)
3661                         hdspm_write_pb_gain(hdspm, destination,
3662                                             source - HDSPM_MAX_CHANNELS,
3663                                             gain);
3664                 else
3665                         hdspm_write_in_gain(hdspm, destination, source,
3666                                             gain);
3667         }
3668         spin_unlock_irq(&hdspm->lock);
3669
3670         return change;
3671 }
3672
3673 /* The simple mixer control(s) provide gain control for the
3674    basic 1:1 mappings of playback streams to output
3675    streams.
3676 */
3677
3678 #define HDSPM_PLAYBACK_MIXER \
3679 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3680         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3681                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3682         .info = snd_hdspm_info_playback_mixer, \
3683         .get = snd_hdspm_get_playback_mixer, \
3684         .put = snd_hdspm_put_playback_mixer \
3685 }
3686
3687 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3688                                          struct snd_ctl_elem_info *uinfo)
3689 {
3690         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3691         uinfo->count = 1;
3692         uinfo->value.integer.min = 0;
3693         uinfo->value.integer.max = 64;
3694         uinfo->value.integer.step = 1;
3695         return 0;
3696 }
3697
3698 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3699                                         struct snd_ctl_elem_value *ucontrol)
3700 {
3701         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3702         int channel;
3703
3704         channel = ucontrol->id.index - 1;
3705
3706         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3707                 return -EINVAL;
3708
3709         spin_lock_irq(&hdspm->lock);
3710         ucontrol->value.integer.value[0] =
3711           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3712         spin_unlock_irq(&hdspm->lock);
3713
3714         return 0;
3715 }
3716
3717 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3718                                         struct snd_ctl_elem_value *ucontrol)
3719 {
3720         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3721         int change;
3722         int channel;
3723         int gain;
3724
3725         if (!snd_hdspm_use_is_exclusive(hdspm))
3726                 return -EBUSY;
3727
3728         channel = ucontrol->id.index - 1;
3729
3730         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3731                 return -EINVAL;
3732
3733         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3734
3735         spin_lock_irq(&hdspm->lock);
3736         change =
3737             gain != hdspm_read_pb_gain(hdspm, channel,
3738                                        channel);
3739         if (change)
3740                 hdspm_write_pb_gain(hdspm, channel, channel,
3741                                     gain);
3742         spin_unlock_irq(&hdspm->lock);
3743         return change;
3744 }
3745
3746 #define HDSPM_SYNC_CHECK(xname, xindex) \
3747 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3748         .name = xname, \
3749         .private_value = xindex, \
3750         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3751         .info = snd_hdspm_info_sync_check, \
3752         .get = snd_hdspm_get_sync_check \
3753 }
3754
3755 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3756 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3757         .name = xname, \
3758         .private_value = xindex, \
3759         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3760         .info = snd_hdspm_tco_info_lock_check, \
3761         .get = snd_hdspm_get_sync_check \
3762 }
3763
3764
3765
3766 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3767                                      struct snd_ctl_elem_info *uinfo)
3768 {
3769         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3770         ENUMERATED_CTL_INFO(uinfo, texts);
3771         return 0;
3772 }
3773
3774 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3775                                      struct snd_ctl_elem_info *uinfo)
3776 {
3777         static char *texts[] = { "No Lock", "Lock" };
3778         ENUMERATED_CTL_INFO(uinfo, texts);
3779         return 0;
3780 }
3781
3782 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3783 {
3784         int status, status2;
3785
3786         switch (hdspm->io_type) {
3787         case AES32:
3788                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3789                 if (status & HDSPM_AES32_wcLock) {
3790                         if (status & HDSPM_AES32_wcSync)
3791                                 return 2;
3792                         else
3793                                 return 1;
3794                 }
3795                 return 0;
3796                 break;
3797
3798         case MADI:
3799                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3800                 if (status2 & HDSPM_wcLock) {
3801                         if (status2 & HDSPM_wcSync)
3802                                 return 2;
3803                         else
3804                                 return 1;
3805                 }
3806                 return 0;
3807                 break;
3808
3809         case RayDAT:
3810         case AIO:
3811                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3812
3813                 if (status & 0x2000000)
3814                         return 2;
3815                 else if (status & 0x1000000)
3816                         return 1;
3817                 return 0;
3818
3819                 break;
3820
3821         case MADIface:
3822                 break;
3823         }
3824
3825
3826         return 3;
3827 }
3828
3829
3830 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3831 {
3832         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3833         if (status & HDSPM_madiLock) {
3834                 if (status & HDSPM_madiSync)
3835                         return 2;
3836                 else
3837                         return 1;
3838         }
3839         return 0;
3840 }
3841
3842
3843 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3844 {
3845         int status, lock, sync;
3846
3847         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3848
3849         lock = (status & (0x1<<idx)) ? 1 : 0;
3850         sync = (status & (0x100<<idx)) ? 1 : 0;
3851
3852         if (lock && sync)
3853                 return 2;
3854         else if (lock)
3855                 return 1;
3856         return 0;
3857 }
3858
3859
3860 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3861 {
3862         int status, lock = 0, sync = 0;
3863
3864         switch (hdspm->io_type) {
3865         case RayDAT:
3866         case AIO:
3867                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3868                 lock = (status & 0x400) ? 1 : 0;
3869                 sync = (status & 0x800) ? 1 : 0;
3870                 break;
3871
3872         case MADI:
3873                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3874                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3875                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3876                 break;
3877
3878         case AES32:
3879                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3880                 lock = (status & 0x100000) ? 1 : 0;
3881                 sync = (status & 0x200000) ? 1 : 0;
3882                 break;
3883
3884         case MADIface:
3885                 break;
3886         }
3887
3888         if (lock && sync)
3889                 return 2;
3890         else if (lock)
3891                 return 1;
3892
3893         return 0;
3894 }
3895
3896 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3897 {
3898         int status2, lock, sync;
3899         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3900
3901         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3902         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3903
3904         if (sync)
3905                 return 2;
3906         else if (lock)
3907                 return 1;
3908         return 0;
3909 }
3910
3911 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3912 {
3913         u32 status;
3914         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3915
3916         return (status & mask) ? 1 : 0;
3917 }
3918
3919
3920 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3921 {
3922         int status;
3923
3924         if (hdspm->tco) {
3925                 switch (hdspm->io_type) {
3926                 case MADI:
3927                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3928                         if (status & HDSPM_tcoLockMadi) {
3929                                 if (status & HDSPM_tcoSync)
3930                                         return 2;
3931                                 else
3932                                         return 1;
3933                         }
3934                         return 0;
3935                         break;
3936                 case AES32:
3937                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3938                         if (status & HDSPM_tcoLockAes) {
3939                                 if (status & HDSPM_tcoSync)
3940                                         return 2;
3941                                 else
3942                                         return 1;
3943                         }
3944                         return 0;
3945
3946                         break;
3947
3948                 case RayDAT:
3949                 case AIO:
3950                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3951
3952                         if (status & 0x8000000)
3953                                 return 2; /* Sync */
3954                         if (status & 0x4000000)
3955                                 return 1; /* Lock */
3956                         return 0; /* No signal */
3957                         break;
3958
3959                 default:
3960                         break;
3961                 }
3962         }
3963
3964         return 3; /* N/A */
3965 }
3966
3967
3968 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3969                                     struct snd_ctl_elem_value *ucontrol)
3970 {
3971         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3972         int val = -1;
3973
3974         switch (hdspm->io_type) {
3975         case RayDAT:
3976                 switch (kcontrol->private_value) {
3977                 case 0: /* WC */
3978                         val = hdspm_wc_sync_check(hdspm); break;
3979                 case 7: /* TCO */
3980                         val = hdspm_tco_sync_check(hdspm); break;
3981                 case 8: /* SYNC IN */
3982                         val = hdspm_sync_in_sync_check(hdspm); break;
3983                 default:
3984                         val = hdspm_s1_sync_check(hdspm,
3985                                         kcontrol->private_value-1);
3986                 }
3987                 break;
3988
3989         case AIO:
3990                 switch (kcontrol->private_value) {
3991                 case 0: /* WC */
3992                         val = hdspm_wc_sync_check(hdspm); break;
3993                 case 4: /* TCO */
3994                         val = hdspm_tco_sync_check(hdspm); break;
3995                 case 5: /* SYNC IN */
3996                         val = hdspm_sync_in_sync_check(hdspm); break;
3997                 default:
3998                         val = hdspm_s1_sync_check(hdspm,
3999                                         kcontrol->private_value-1);
4000                 }
4001                 break;
4002
4003         case MADI:
4004                 switch (kcontrol->private_value) {
4005                 case 0: /* WC */
4006                         val = hdspm_wc_sync_check(hdspm); break;
4007                 case 1: /* MADI */
4008                         val = hdspm_madi_sync_check(hdspm); break;
4009                 case 2: /* TCO */
4010                         val = hdspm_tco_sync_check(hdspm); break;
4011                 case 3: /* SYNC_IN */
4012                         val = hdspm_sync_in_sync_check(hdspm); break;
4013                 }
4014                 break;
4015
4016         case MADIface:
4017                 val = hdspm_madi_sync_check(hdspm); /* MADI */
4018                 break;
4019
4020         case AES32:
4021                 switch (kcontrol->private_value) {
4022                 case 0: /* WC */
4023                         val = hdspm_wc_sync_check(hdspm); break;
4024                 case 9: /* TCO */
4025                         val = hdspm_tco_sync_check(hdspm); break;
4026                 case 10 /* SYNC IN */:
4027                         val = hdspm_sync_in_sync_check(hdspm); break;
4028                 default: /* AES1 to AES8 */
4029                          val = hdspm_aes_sync_check(hdspm,
4030                                          kcontrol->private_value-1);
4031                 }
4032                 break;
4033
4034         }
4035
4036         if (hdspm->tco) {
4037                 switch (kcontrol->private_value) {
4038                 case 11:
4039                         /* Check TCO for lock state of its current input */
4040                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4041                         break;
4042                 case 12:
4043                         /* Check TCO for valid time code on LTC input. */
4044                         val = hdspm_tco_input_check(hdspm,
4045                                 HDSPM_TCO1_LTC_Input_valid);
4046                         break;
4047                 default:
4048                         break;
4049                 }
4050         }
4051
4052         if (-1 == val)
4053                 val = 3;
4054
4055         ucontrol->value.enumerated.item[0] = val;
4056         return 0;
4057 }
4058
4059
4060
4061 /**
4062  * TCO controls
4063  **/
4064 static void hdspm_tco_write(struct hdspm *hdspm)
4065 {
4066         unsigned int tc[4] = { 0, 0, 0, 0};
4067
4068         switch (hdspm->tco->input) {
4069         case 0:
4070                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4071                 break;
4072         case 1:
4073                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4074                 break;
4075         default:
4076                 break;
4077         }
4078
4079         switch (hdspm->tco->framerate) {
4080         case 1:
4081                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4082                 break;
4083         case 2:
4084                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4085                 break;
4086         case 3:
4087                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4088                         HDSPM_TCO1_set_drop_frame_flag;
4089                 break;
4090         case 4:
4091                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4092                         HDSPM_TCO1_LTC_Format_MSB;
4093                 break;
4094         case 5:
4095                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4096                         HDSPM_TCO1_LTC_Format_MSB +
4097                         HDSPM_TCO1_set_drop_frame_flag;
4098                 break;
4099         default:
4100                 break;
4101         }
4102
4103         switch (hdspm->tco->wordclock) {
4104         case 1:
4105                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4106                 break;
4107         case 2:
4108                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4109                 break;
4110         default:
4111                 break;
4112         }
4113
4114         switch (hdspm->tco->samplerate) {
4115         case 1:
4116                 tc[2] |= HDSPM_TCO2_set_freq;
4117                 break;
4118         case 2:
4119                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4120                 break;
4121         default:
4122                 break;
4123         }
4124
4125         switch (hdspm->tco->pull) {
4126         case 1:
4127                 tc[2] |= HDSPM_TCO2_set_pull_up;
4128                 break;
4129         case 2:
4130                 tc[2] |= HDSPM_TCO2_set_pull_down;
4131                 break;
4132         case 3:
4133                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4134                 break;
4135         case 4:
4136                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4137                 break;
4138         default:
4139                 break;
4140         }
4141
4142         if (1 == hdspm->tco->term) {
4143                 tc[2] |= HDSPM_TCO2_set_term_75R;
4144         }
4145
4146         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4147         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4148         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4149         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4150 }
4151
4152
4153 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4154 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4155         .name = xname, \
4156         .index = xindex, \
4157         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4158                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4159         .info = snd_hdspm_info_tco_sample_rate, \
4160         .get = snd_hdspm_get_tco_sample_rate, \
4161         .put = snd_hdspm_put_tco_sample_rate \
4162 }
4163
4164 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4165                                           struct snd_ctl_elem_info *uinfo)
4166 {
4167         static char *texts[] = { "44.1 kHz", "48 kHz" };
4168         ENUMERATED_CTL_INFO(uinfo, texts);
4169         return 0;
4170 }
4171
4172 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4173                                       struct snd_ctl_elem_value *ucontrol)
4174 {
4175         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4176
4177         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4178
4179         return 0;
4180 }
4181
4182 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4183                                          struct snd_ctl_elem_value *ucontrol)
4184 {
4185         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4186
4187         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4188                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4189
4190                 hdspm_tco_write(hdspm);
4191
4192                 return 1;
4193         }
4194
4195         return 0;
4196 }
4197
4198
4199 #define HDSPM_TCO_PULL(xname, xindex) \
4200 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4201         .name = xname, \
4202         .index = xindex, \
4203         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4204                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4205         .info = snd_hdspm_info_tco_pull, \
4206         .get = snd_hdspm_get_tco_pull, \
4207         .put = snd_hdspm_put_tco_pull \
4208 }
4209
4210 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4211                                    struct snd_ctl_elem_info *uinfo)
4212 {
4213         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4214         ENUMERATED_CTL_INFO(uinfo, texts);
4215         return 0;
4216 }
4217
4218 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4219                                   struct snd_ctl_elem_value *ucontrol)
4220 {
4221         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4222
4223         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4224
4225         return 0;
4226 }
4227
4228 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4229                                   struct snd_ctl_elem_value *ucontrol)
4230 {
4231         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4232
4233         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4234                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4235
4236                 hdspm_tco_write(hdspm);
4237
4238                 return 1;
4239         }
4240
4241         return 0;
4242 }
4243
4244 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4245 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4246         .name = xname, \
4247         .index = xindex, \
4248         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4249                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4250         .info = snd_hdspm_info_tco_wck_conversion, \
4251         .get = snd_hdspm_get_tco_wck_conversion, \
4252         .put = snd_hdspm_put_tco_wck_conversion \
4253 }
4254
4255 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4256                                              struct snd_ctl_elem_info *uinfo)
4257 {
4258         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4259         ENUMERATED_CTL_INFO(uinfo, texts);
4260         return 0;
4261 }
4262
4263 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4264                                             struct snd_ctl_elem_value *ucontrol)
4265 {
4266         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4267
4268         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4269
4270         return 0;
4271 }
4272
4273 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4274                                             struct snd_ctl_elem_value *ucontrol)
4275 {
4276         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4277
4278         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4279                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4280
4281                 hdspm_tco_write(hdspm);
4282
4283                 return 1;
4284         }
4285
4286         return 0;
4287 }
4288
4289
4290 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4291 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4292         .name = xname, \
4293         .index = xindex, \
4294         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4295                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4296         .info = snd_hdspm_info_tco_frame_rate, \
4297         .get = snd_hdspm_get_tco_frame_rate, \
4298         .put = snd_hdspm_put_tco_frame_rate \
4299 }
4300
4301 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4302                                           struct snd_ctl_elem_info *uinfo)
4303 {
4304         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4305                 "29.97 dfps", "30 fps", "30 dfps" };
4306         ENUMERATED_CTL_INFO(uinfo, texts);
4307         return 0;
4308 }
4309
4310 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4311                                         struct snd_ctl_elem_value *ucontrol)
4312 {
4313         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4314
4315         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4316
4317         return 0;
4318 }
4319
4320 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4321                                         struct snd_ctl_elem_value *ucontrol)
4322 {
4323         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4324
4325         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4326                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4327
4328                 hdspm_tco_write(hdspm);
4329
4330                 return 1;
4331         }
4332
4333         return 0;
4334 }
4335
4336
4337 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4338 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4339         .name = xname, \
4340         .index = xindex, \
4341         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4342                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4343         .info = snd_hdspm_info_tco_sync_source, \
4344         .get = snd_hdspm_get_tco_sync_source, \
4345         .put = snd_hdspm_put_tco_sync_source \
4346 }
4347
4348 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4349                                           struct snd_ctl_elem_info *uinfo)
4350 {
4351         static char *texts[] = { "LTC", "Video", "WCK" };
4352         ENUMERATED_CTL_INFO(uinfo, texts);
4353         return 0;
4354 }
4355
4356 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4357                                          struct snd_ctl_elem_value *ucontrol)
4358 {
4359         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4360
4361         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4362
4363         return 0;
4364 }
4365
4366 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4367                                          struct snd_ctl_elem_value *ucontrol)
4368 {
4369         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4370
4371         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4372                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4373
4374                 hdspm_tco_write(hdspm);
4375
4376                 return 1;
4377         }
4378
4379         return 0;
4380 }
4381
4382
4383 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4384 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4385         .name = xname, \
4386         .index = xindex, \
4387         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4388                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4389         .info = snd_hdspm_info_tco_word_term, \
4390         .get = snd_hdspm_get_tco_word_term, \
4391         .put = snd_hdspm_put_tco_word_term \
4392 }
4393
4394 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4395                                         struct snd_ctl_elem_info *uinfo)
4396 {
4397         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4398         uinfo->count = 1;
4399         uinfo->value.integer.min = 0;
4400         uinfo->value.integer.max = 1;
4401
4402         return 0;
4403 }
4404
4405
4406 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4407                                        struct snd_ctl_elem_value *ucontrol)
4408 {
4409         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4410
4411         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4412
4413         return 0;
4414 }
4415
4416
4417 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4418                                        struct snd_ctl_elem_value *ucontrol)
4419 {
4420         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4421
4422         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4423                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4424
4425                 hdspm_tco_write(hdspm);
4426
4427                 return 1;
4428         }
4429
4430         return 0;
4431 }
4432
4433
4434
4435
4436 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4437         HDSPM_MIXER("Mixer", 0),
4438         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4439         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4440         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4441         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4442         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4443         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4444         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4445         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4446         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4447         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4448         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4449         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4450         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4451         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4452         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4453         HDSPM_INPUT_SELECT("Input Select", 0),
4454         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4455 };
4456
4457
4458 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4459         HDSPM_MIXER("Mixer", 0),
4460         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4461         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4462         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4463         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4464         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4465         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4466         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4467         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4468         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4469 };
4470
4471 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4472         HDSPM_MIXER("Mixer", 0),
4473         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4474         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4475         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4476         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4477         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4478         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4479         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4480         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4481         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4482         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4483         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4484         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4485         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4486         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4487         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4488         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4489         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4490         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4491         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4492         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4493         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4494         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4495         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4496         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4497         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4498         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4499
4500                 /*
4501                    HDSPM_INPUT_SELECT("Input Select", 0),
4502                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4503                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4504                    HDSPM_SPDIF_IN("SPDIF In", 0);
4505                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4506                    HDSPM_INPUT_LEVEL("Input Level", 0);
4507                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4508                    HDSPM_PHONES("Phones", 0);
4509                    */
4510 };
4511
4512 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4513         HDSPM_MIXER("Mixer", 0),
4514         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4515         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4516         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4517         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4518         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4519         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4520         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4521         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4522         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4523         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4524         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4525         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4526         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4527         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4528         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4529         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4530         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4531         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4532         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4533         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4534         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4535         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4536         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4537         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4538 };
4539
4540 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4541         HDSPM_MIXER("Mixer", 0),
4542         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4543         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4544         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4545         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4546         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4547         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4548         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4549         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4550         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4551         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4552         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4553         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4554         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4555         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4556         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4557         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4558         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4559         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4560         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4561         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4562         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4563         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4564         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4565         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4566         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4567         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4568         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4569         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4570         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4571         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4572         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4573         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4574         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4575         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4576         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4577 };
4578
4579
4580
4581 /* Control elements for the optional TCO module */
4582 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4583         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4584         HDSPM_TCO_PULL("TCO Pull", 0),
4585         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4586         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4587         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4588         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4589         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4590         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4591         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4592         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4593 };
4594
4595
4596 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4597
4598
4599 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4600 {
4601         int i;
4602
4603         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4604                 if (hdspm->system_sample_rate > 48000) {
4605                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4606                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4607                                 SNDRV_CTL_ELEM_ACCESS_READ |
4608                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4609                 } else {
4610                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4611                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4612                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4613                 }
4614                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4615                                 SNDRV_CTL_EVENT_MASK_INFO,
4616                                 &hdspm->playback_mixer_ctls[i]->id);
4617         }
4618
4619         return 0;
4620 }
4621
4622
4623 static int snd_hdspm_create_controls(struct snd_card *card,
4624                                         struct hdspm *hdspm)
4625 {
4626         unsigned int idx, limit;
4627         int err;
4628         struct snd_kcontrol *kctl;
4629         struct snd_kcontrol_new *list = NULL;
4630
4631         switch (hdspm->io_type) {
4632         case MADI:
4633                 list = snd_hdspm_controls_madi;
4634                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4635                 break;
4636         case MADIface:
4637                 list = snd_hdspm_controls_madiface;
4638                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4639                 break;
4640         case AIO:
4641                 list = snd_hdspm_controls_aio;
4642                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4643                 break;
4644         case RayDAT:
4645                 list = snd_hdspm_controls_raydat;
4646                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4647                 break;
4648         case AES32:
4649                 list = snd_hdspm_controls_aes32;
4650                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4651                 break;
4652         }
4653
4654         if (NULL != list) {
4655                 for (idx = 0; idx < limit; idx++) {
4656                         err = snd_ctl_add(card,
4657                                         snd_ctl_new1(&list[idx], hdspm));
4658                         if (err < 0)
4659                                 return err;
4660                 }
4661         }
4662
4663
4664         /* create simple 1:1 playback mixer controls */
4665         snd_hdspm_playback_mixer.name = "Chn";
4666         if (hdspm->system_sample_rate >= 128000) {
4667                 limit = hdspm->qs_out_channels;
4668         } else if (hdspm->system_sample_rate >= 64000) {
4669                 limit = hdspm->ds_out_channels;
4670         } else {
4671                 limit = hdspm->ss_out_channels;
4672         }
4673         for (idx = 0; idx < limit; ++idx) {
4674                 snd_hdspm_playback_mixer.index = idx + 1;
4675                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4676                 err = snd_ctl_add(card, kctl);
4677                 if (err < 0)
4678                         return err;
4679                 hdspm->playback_mixer_ctls[idx] = kctl;
4680         }
4681
4682
4683         if (hdspm->tco) {
4684                 /* add tco control elements */
4685                 list = snd_hdspm_controls_tco;
4686                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4687                 for (idx = 0; idx < limit; idx++) {
4688                         err = snd_ctl_add(card,
4689                                         snd_ctl_new1(&list[idx], hdspm));
4690                         if (err < 0)
4691                                 return err;
4692                 }
4693         }
4694
4695         return 0;
4696 }
4697
4698 /*------------------------------------------------------------
4699    /proc interface
4700  ------------------------------------------------------------*/
4701
4702 static void
4703 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4704                                         struct snd_info_buffer *buffer)
4705 {
4706         struct hdspm *hdspm = entry->private_data;
4707         unsigned int status, control;
4708         int a, ltc, frames, seconds, minutes, hours;
4709         unsigned int period;
4710         u64 freq_const = 0;
4711         u32 rate;
4712
4713         snd_iprintf(buffer, "--- TCO ---\n");
4714
4715         status = hdspm_read(hdspm, HDSPM_statusRegister);
4716         control = hdspm->control_register;
4717
4718
4719         if (status & HDSPM_tco_detect) {
4720                 snd_iprintf(buffer, "TCO module detected.\n");
4721                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4722                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4723                         snd_iprintf(buffer, "  LTC valid, ");
4724                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4725                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4726                         case 0:
4727                                 snd_iprintf(buffer, "24 fps, ");
4728                                 break;
4729                         case HDSPM_TCO1_LTC_Format_LSB:
4730                                 snd_iprintf(buffer, "25 fps, ");
4731                                 break;
4732                         case HDSPM_TCO1_LTC_Format_MSB:
4733                                 snd_iprintf(buffer, "29.97 fps, ");
4734                                 break;
4735                         default:
4736                                 snd_iprintf(buffer, "30 fps, ");
4737                                 break;
4738                         }
4739                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4740                                 snd_iprintf(buffer, "drop frame\n");
4741                         } else {
4742                                 snd_iprintf(buffer, "full frame\n");
4743                         }
4744                 } else {
4745                         snd_iprintf(buffer, "  no LTC\n");
4746                 }
4747                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4748                         snd_iprintf(buffer, "  Video: NTSC\n");
4749                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4750                         snd_iprintf(buffer, "  Video: PAL\n");
4751                 } else {
4752                         snd_iprintf(buffer, "  No video\n");
4753                 }
4754                 if (a & HDSPM_TCO1_TCO_lock) {
4755                         snd_iprintf(buffer, "  Sync: lock\n");
4756                 } else {
4757                         snd_iprintf(buffer, "  Sync: no lock\n");
4758                 }
4759
4760                 switch (hdspm->io_type) {
4761                 case MADI:
4762                 case AES32:
4763                         freq_const = 110069313433624ULL;
4764                         break;
4765                 case RayDAT:
4766                 case AIO:
4767                         freq_const = 104857600000000ULL;
4768                         break;
4769                 case MADIface:
4770                         break; /* no TCO possible */
4771                 }
4772
4773                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4774                 snd_iprintf(buffer, "    period: %u\n", period);
4775
4776
4777                 /* rate = freq_const/period; */
4778                 rate = div_u64(freq_const, period);
4779
4780                 if (control & HDSPM_QuadSpeed) {
4781                         rate *= 4;
4782                 } else if (control & HDSPM_DoubleSpeed) {
4783                         rate *= 2;
4784                 }
4785
4786                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4787                                 (unsigned int) rate);
4788
4789                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4790                 frames = ltc & 0xF;
4791                 ltc >>= 4;
4792                 frames += (ltc & 0x3) * 10;
4793                 ltc >>= 4;
4794                 seconds = ltc & 0xF;
4795                 ltc >>= 4;
4796                 seconds += (ltc & 0x7) * 10;
4797                 ltc >>= 4;
4798                 minutes = ltc & 0xF;
4799                 ltc >>= 4;
4800                 minutes += (ltc & 0x7) * 10;
4801                 ltc >>= 4;
4802                 hours = ltc & 0xF;
4803                 ltc >>= 4;
4804                 hours += (ltc & 0x3) * 10;
4805                 snd_iprintf(buffer,
4806                         "  LTC In: %02d:%02d:%02d:%02d\n",
4807                         hours, minutes, seconds, frames);
4808
4809         } else {
4810                 snd_iprintf(buffer, "No TCO module detected.\n");
4811         }
4812 }
4813
4814 static void
4815 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4816                          struct snd_info_buffer *buffer)
4817 {
4818         struct hdspm *hdspm = entry->private_data;
4819         unsigned int status, status2, control, freq;
4820
4821         char *pref_sync_ref;
4822         char *autosync_ref;
4823         char *system_clock_mode;
4824         char *insel;
4825         int x, x2;
4826
4827         status = hdspm_read(hdspm, HDSPM_statusRegister);
4828         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4829         control = hdspm->control_register;
4830         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4831
4832         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4833                         hdspm->card_name, hdspm->card->number + 1,
4834                         hdspm->firmware_rev,
4835                         (status2 & HDSPM_version0) |
4836                         (status2 & HDSPM_version1) | (status2 &
4837                                 HDSPM_version2));
4838
4839         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4840                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4841                         hdspm->serial);
4842
4843         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4844                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4845
4846         snd_iprintf(buffer, "--- System ---\n");
4847
4848         snd_iprintf(buffer,
4849                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4850                 status & HDSPM_audioIRQPending,
4851                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4852                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4853                 hdspm->irq_count);
4854         snd_iprintf(buffer,
4855                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4856                 "estimated= %ld (bytes)\n",
4857                 ((status & HDSPM_BufferID) ? 1 : 0),
4858                 (status & HDSPM_BufferPositionMask),
4859                 (status & HDSPM_BufferPositionMask) %
4860                 (2 * (int)hdspm->period_bytes),
4861                 ((status & HDSPM_BufferPositionMask) - 64) %
4862                 (2 * (int)hdspm->period_bytes),
4863                 (long) hdspm_hw_pointer(hdspm) * 4);
4864
4865         snd_iprintf(buffer,
4866                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4867                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4868                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4869                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4870                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4871         snd_iprintf(buffer,
4872                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4873                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4874                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4875         snd_iprintf(buffer,
4876                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4877                 "status2=0x%x\n",
4878                 hdspm->control_register, hdspm->control2_register,
4879                 status, status2);
4880
4881
4882         snd_iprintf(buffer, "--- Settings ---\n");
4883
4884         x = hdspm_get_latency(hdspm);
4885
4886         snd_iprintf(buffer,
4887                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4888                 x, (unsigned long) hdspm->period_bytes);
4889
4890         snd_iprintf(buffer, "Line out: %s\n",
4891                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4892
4893         switch (hdspm->control_register & HDSPM_InputMask) {
4894         case HDSPM_InputOptical:
4895                 insel = "Optical";
4896                 break;
4897         case HDSPM_InputCoaxial:
4898                 insel = "Coaxial";
4899                 break;
4900         default:
4901                 insel = "Unknown";
4902         }
4903
4904         snd_iprintf(buffer,
4905                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4906                 "Auto Input %s\n",
4907                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4908                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4909                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4910
4911
4912         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4913                 system_clock_mode = "AutoSync";
4914         else
4915                 system_clock_mode = "Master";
4916         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4917
4918         switch (hdspm_pref_sync_ref(hdspm)) {
4919         case HDSPM_SYNC_FROM_WORD:
4920                 pref_sync_ref = "Word Clock";
4921                 break;
4922         case HDSPM_SYNC_FROM_MADI:
4923                 pref_sync_ref = "MADI Sync";
4924                 break;
4925         case HDSPM_SYNC_FROM_TCO:
4926                 pref_sync_ref = "TCO";
4927                 break;
4928         case HDSPM_SYNC_FROM_SYNC_IN:
4929                 pref_sync_ref = "Sync In";
4930                 break;
4931         default:
4932                 pref_sync_ref = "XXXX Clock";
4933                 break;
4934         }
4935         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4936                         pref_sync_ref);
4937
4938         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4939                         hdspm->system_sample_rate);
4940
4941
4942         snd_iprintf(buffer, "--- Status:\n");
4943
4944         x = status & HDSPM_madiSync;
4945         x2 = status2 & HDSPM_wcSync;
4946
4947         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4948                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4949                         "NoLock",
4950                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4951                         "NoLock");
4952
4953         switch (hdspm_autosync_ref(hdspm)) {
4954         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4955                 autosync_ref = "Sync In";
4956                 break;
4957         case HDSPM_AUTOSYNC_FROM_TCO:
4958                 autosync_ref = "TCO";
4959                 break;
4960         case HDSPM_AUTOSYNC_FROM_WORD:
4961                 autosync_ref = "Word Clock";
4962                 break;
4963         case HDSPM_AUTOSYNC_FROM_MADI:
4964                 autosync_ref = "MADI Sync";
4965                 break;
4966         case HDSPM_AUTOSYNC_FROM_NONE:
4967                 autosync_ref = "Input not valid";
4968                 break;
4969         default:
4970                 autosync_ref = "---";
4971                 break;
4972         }
4973         snd_iprintf(buffer,
4974                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4975                 autosync_ref, hdspm_external_sample_rate(hdspm),
4976                 (status & HDSPM_madiFreqMask) >> 22,
4977                 (status2 & HDSPM_wcFreqMask) >> 5);
4978
4979         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4980                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4981                 (status & HDSPM_RX_64ch) ? "64 channels" :
4982                 "56 channels");
4983
4984         /* call readout function for TCO specific status */
4985         snd_hdspm_proc_read_tco(entry, buffer);
4986
4987         snd_iprintf(buffer, "\n");
4988 }
4989
4990 static void
4991 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4992                           struct snd_info_buffer *buffer)
4993 {
4994         struct hdspm *hdspm = entry->private_data;
4995         unsigned int status;
4996         unsigned int status2;
4997         unsigned int timecode;
4998         unsigned int wcLock, wcSync;
4999         int pref_syncref;
5000         char *autosync_ref;
5001         int x;
5002
5003         status = hdspm_read(hdspm, HDSPM_statusRegister);
5004         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5005         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5006
5007         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5008                     hdspm->card_name, hdspm->card->number + 1,
5009                     hdspm->firmware_rev);
5010
5011         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5012                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5013
5014         snd_iprintf(buffer, "--- System ---\n");
5015
5016         snd_iprintf(buffer,
5017                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5018                     status & HDSPM_audioIRQPending,
5019                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
5020                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
5021                     hdspm->irq_count);
5022         snd_iprintf(buffer,
5023                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
5024                     "estimated= %ld (bytes)\n",
5025                     ((status & HDSPM_BufferID) ? 1 : 0),
5026                     (status & HDSPM_BufferPositionMask),
5027                     (status & HDSPM_BufferPositionMask) %
5028                     (2 * (int)hdspm->period_bytes),
5029                     ((status & HDSPM_BufferPositionMask) - 64) %
5030                     (2 * (int)hdspm->period_bytes),
5031                     (long) hdspm_hw_pointer(hdspm) * 4);
5032
5033         snd_iprintf(buffer,
5034                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5035                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5036                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5037                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5038                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5039         snd_iprintf(buffer,
5040                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5041                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5042                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5043         snd_iprintf(buffer,
5044                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5045                     "status2=0x%x\n",
5046                     hdspm->control_register, hdspm->control2_register,
5047                     status, status2);
5048
5049         snd_iprintf(buffer, "--- Settings ---\n");
5050
5051         x = hdspm_get_latency(hdspm);
5052
5053         snd_iprintf(buffer,
5054                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5055                     x, (unsigned long) hdspm->period_bytes);
5056
5057         snd_iprintf(buffer, "Line out: %s\n",
5058                     (hdspm->
5059                      control_register & HDSPM_LineOut) ? "on " : "off");
5060
5061         snd_iprintf(buffer,
5062                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5063                     (hdspm->
5064                      control_register & HDSPM_clr_tms) ? "on" : "off",
5065                     (hdspm->
5066                      control_register & HDSPM_Emphasis) ? "on" : "off",
5067                     (hdspm->
5068                      control_register & HDSPM_Dolby) ? "on" : "off");
5069
5070
5071         pref_syncref = hdspm_pref_sync_ref(hdspm);
5072         if (pref_syncref == 0)
5073                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5074         else
5075                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5076                                 pref_syncref);
5077
5078         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5079                     hdspm->system_sample_rate);
5080
5081         snd_iprintf(buffer, "Double speed: %s\n",
5082                         hdspm->control_register & HDSPM_DS_DoubleWire?
5083                         "Double wire" : "Single wire");
5084         snd_iprintf(buffer, "Quad speed: %s\n",
5085                         hdspm->control_register & HDSPM_QS_DoubleWire?
5086                         "Double wire" :
5087                         hdspm->control_register & HDSPM_QS_QuadWire?
5088                         "Quad wire" : "Single wire");
5089
5090         snd_iprintf(buffer, "--- Status:\n");
5091
5092         wcLock = status & HDSPM_AES32_wcLock;
5093         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5094
5095         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5096                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5097                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5098
5099         for (x = 0; x < 8; x++) {
5100                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5101                             x+1,
5102                             (status2 & (HDSPM_LockAES >> x)) ?
5103                             "Sync   " : "No Lock",
5104                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5105         }
5106
5107         switch (hdspm_autosync_ref(hdspm)) {
5108         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5109                 autosync_ref = "None"; break;
5110         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5111                 autosync_ref = "Word Clock"; break;
5112         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5113                 autosync_ref = "AES1"; break;
5114         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5115                 autosync_ref = "AES2"; break;
5116         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5117                 autosync_ref = "AES3"; break;
5118         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5119                 autosync_ref = "AES4"; break;
5120         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5121                 autosync_ref = "AES5"; break;
5122         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5123                 autosync_ref = "AES6"; break;
5124         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5125                 autosync_ref = "AES7"; break;
5126         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5127                 autosync_ref = "AES8"; break;
5128         default:
5129                 autosync_ref = "---"; break;
5130         }
5131         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5132
5133         snd_iprintf(buffer, "\n");
5134 }
5135
5136 static void
5137 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5138                          struct snd_info_buffer *buffer)
5139 {
5140         struct hdspm *hdspm = entry->private_data;
5141         unsigned int status1, status2, status3, control, i;
5142         unsigned int lock, sync;
5143
5144         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5145         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5146         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5147
5148         control = hdspm->control_register;
5149
5150         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5151         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5152         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5153
5154
5155         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5156
5157         snd_iprintf(buffer, "Clock mode      : %s\n",
5158                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5159         snd_iprintf(buffer, "System frequency: %d Hz\n",
5160                 hdspm_get_system_sample_rate(hdspm));
5161
5162         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5163
5164         lock = 0x1;
5165         sync = 0x100;
5166
5167         for (i = 0; i < 8; i++) {
5168                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5169                                 i,
5170                                 (status1 & lock) ? 1 : 0,
5171                                 (status1 & sync) ? 1 : 0,
5172                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5173
5174                 lock = lock<<1;
5175                 sync = sync<<1;
5176         }
5177
5178         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5179                         (status1 & 0x1000000) ? 1 : 0,
5180                         (status1 & 0x2000000) ? 1 : 0,
5181                         texts_freq[(status1 >> 16) & 0xF]);
5182
5183         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5184                         (status1 & 0x4000000) ? 1 : 0,
5185                         (status1 & 0x8000000) ? 1 : 0,
5186                         texts_freq[(status1 >> 20) & 0xF]);
5187
5188         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5189                         (status3 & 0x400) ? 1 : 0,
5190                         (status3 & 0x800) ? 1 : 0,
5191                         texts_freq[(status2 >> 12) & 0xF]);
5192
5193 }
5194
5195 #ifdef CONFIG_SND_DEBUG
5196 static void
5197 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5198                           struct snd_info_buffer *buffer)
5199 {
5200         struct hdspm *hdspm = entry->private_data;
5201
5202         int j,i;
5203
5204         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5205                 snd_iprintf(buffer, "0x%08X: ", i);
5206                 for (j = 0; j < 16; j += 4)
5207                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5208                 snd_iprintf(buffer, "\n");
5209         }
5210 }
5211 #endif
5212
5213
5214 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5215                           struct snd_info_buffer *buffer)
5216 {
5217         struct hdspm *hdspm = entry->private_data;
5218         int i;
5219
5220         snd_iprintf(buffer, "# generated by hdspm\n");
5221
5222         for (i = 0; i < hdspm->max_channels_in; i++) {
5223                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5224         }
5225 }
5226
5227 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5228                           struct snd_info_buffer *buffer)
5229 {
5230         struct hdspm *hdspm = entry->private_data;
5231         int i;
5232
5233         snd_iprintf(buffer, "# generated by hdspm\n");
5234
5235         for (i = 0; i < hdspm->max_channels_out; i++) {
5236                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5237         }
5238 }
5239
5240
5241 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5242 {
5243         struct snd_info_entry *entry;
5244
5245         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5246                 switch (hdspm->io_type) {
5247                 case AES32:
5248                         snd_info_set_text_ops(entry, hdspm,
5249                                         snd_hdspm_proc_read_aes32);
5250                         break;
5251                 case MADI:
5252                         snd_info_set_text_ops(entry, hdspm,
5253                                         snd_hdspm_proc_read_madi);
5254                         break;
5255                 case MADIface:
5256                         /* snd_info_set_text_ops(entry, hdspm,
5257                          snd_hdspm_proc_read_madiface); */
5258                         break;
5259                 case RayDAT:
5260                         snd_info_set_text_ops(entry, hdspm,
5261                                         snd_hdspm_proc_read_raydat);
5262                         break;
5263                 case AIO:
5264                         break;
5265                 }
5266         }
5267
5268         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5269                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5270         }
5271
5272         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5273                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5274         }
5275
5276 #ifdef CONFIG_SND_DEBUG
5277         /* debug file to read all hdspm registers */
5278         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5279                 snd_info_set_text_ops(entry, hdspm,
5280                                 snd_hdspm_proc_read_debug);
5281 #endif
5282 }
5283
5284 /*------------------------------------------------------------
5285    hdspm intitialize
5286  ------------------------------------------------------------*/
5287
5288 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5289 {
5290         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5291            hold it (e.g. during module initialization).
5292            */
5293
5294         /* set defaults:       */
5295
5296         hdspm->settings_register = 0;
5297
5298         switch (hdspm->io_type) {
5299         case MADI:
5300         case MADIface:
5301                 hdspm->control_register =
5302                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5303                 break;
5304
5305         case RayDAT:
5306         case AIO:
5307                 hdspm->settings_register = 0x1 + 0x1000;
5308                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5309                  * line_out */
5310                 hdspm->control_register =
5311                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5312                 break;
5313
5314         case AES32:
5315                 hdspm->control_register =
5316                         HDSPM_ClockModeMaster | /* Master Clock Mode on */
5317                         hdspm_encode_latency(7) | /* latency max=8192samples */
5318                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5319                         HDSPM_LineOut | /* Analog output in */
5320                         HDSPM_Professional;  /* Professional mode */
5321                 break;
5322         }
5323
5324         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5325
5326         if (AES32 == hdspm->io_type) {
5327                 /* No control2 register for AES32 */
5328 #ifdef SNDRV_BIG_ENDIAN
5329                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5330 #else
5331                 hdspm->control2_register = 0;
5332 #endif
5333
5334                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5335         }
5336         hdspm_compute_period_size(hdspm);
5337
5338         /* silence everything */
5339
5340         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5341
5342         if (hdspm_is_raydat_or_aio(hdspm))
5343                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5344
5345         /* set a default rate so that the channel map is set up. */
5346         hdspm_set_rate(hdspm, 48000, 1);
5347
5348         return 0;
5349 }
5350
5351
5352 /*------------------------------------------------------------
5353    interrupt
5354  ------------------------------------------------------------*/
5355
5356 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5357 {
5358         struct hdspm *hdspm = (struct hdspm *) dev_id;
5359         unsigned int status;
5360         int i, audio, midi, schedule = 0;
5361         /* cycles_t now; */
5362
5363         status = hdspm_read(hdspm, HDSPM_statusRegister);
5364
5365         audio = status & HDSPM_audioIRQPending;
5366         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5367                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5368
5369         /* now = get_cycles(); */
5370         /**
5371          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5372          *          6       4096   ~256053425     ~514672358
5373          *          5       2048   ~128024983     ~257373821
5374          *          4       1024    ~64023706     ~128718089
5375          *          3        512    ~32005945      ~64385999
5376          *          2        256    ~16003039      ~32260176
5377          *          1        128     ~7998738      ~16194507
5378          *          0         64     ~3998231       ~8191558
5379          **/
5380         /*
5381            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5382            now-hdspm->last_interrupt, status & 0xFFC0);
5383            hdspm->last_interrupt = now;
5384         */
5385
5386         if (!audio && !midi)
5387                 return IRQ_NONE;
5388
5389         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5390         hdspm->irq_count++;
5391
5392
5393         if (audio) {
5394                 if (hdspm->capture_substream)
5395                         snd_pcm_period_elapsed(hdspm->capture_substream);
5396
5397                 if (hdspm->playback_substream)
5398                         snd_pcm_period_elapsed(hdspm->playback_substream);
5399         }
5400
5401         if (midi) {
5402                 i = 0;
5403                 while (i < hdspm->midiPorts) {
5404                         if ((hdspm_read(hdspm,
5405                                 hdspm->midi[i].statusIn) & 0xff) &&
5406                                         (status & hdspm->midi[i].irq)) {
5407                                 /* we disable interrupts for this input until
5408                                  * processing is done
5409                                  */
5410                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5411                                 hdspm_write(hdspm, HDSPM_controlRegister,
5412                                                 hdspm->control_register);
5413                                 hdspm->midi[i].pending = 1;
5414                                 schedule = 1;
5415                         }
5416
5417                         i++;
5418                 }
5419
5420                 if (schedule)
5421                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5422         }
5423
5424         return IRQ_HANDLED;
5425 }
5426
5427 /*------------------------------------------------------------
5428    pcm interface
5429   ------------------------------------------------------------*/
5430
5431
5432 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5433                                               *substream)
5434 {
5435         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5436         return hdspm_hw_pointer(hdspm);
5437 }
5438
5439
5440 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5441 {
5442         struct snd_pcm_runtime *runtime = substream->runtime;
5443         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5444         struct snd_pcm_substream *other;
5445
5446         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5447                 other = hdspm->capture_substream;
5448         else
5449                 other = hdspm->playback_substream;
5450
5451         if (hdspm->running)
5452                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5453         else
5454                 runtime->status->hw_ptr = 0;
5455         if (other) {
5456                 struct snd_pcm_substream *s;
5457                 struct snd_pcm_runtime *oruntime = other->runtime;
5458                 snd_pcm_group_for_each_entry(s, substream) {
5459                         if (s == other) {
5460                                 oruntime->status->hw_ptr =
5461                                         runtime->status->hw_ptr;
5462                                 break;
5463                         }
5464                 }
5465         }
5466         return 0;
5467 }
5468
5469 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5470                                struct snd_pcm_hw_params *params)
5471 {
5472         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5473         int err;
5474         int i;
5475         pid_t this_pid;
5476         pid_t other_pid;
5477
5478         spin_lock_irq(&hdspm->lock);
5479
5480         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5481                 this_pid = hdspm->playback_pid;
5482                 other_pid = hdspm->capture_pid;
5483         } else {
5484                 this_pid = hdspm->capture_pid;
5485                 other_pid = hdspm->playback_pid;
5486         }
5487
5488         if (other_pid > 0 && this_pid != other_pid) {
5489
5490                 /* The other stream is open, and not by the same
5491                    task as this one. Make sure that the parameters
5492                    that matter are the same.
5493                    */
5494
5495                 if (params_rate(params) != hdspm->system_sample_rate) {
5496                         spin_unlock_irq(&hdspm->lock);
5497                         _snd_pcm_hw_param_setempty(params,
5498                                         SNDRV_PCM_HW_PARAM_RATE);
5499                         return -EBUSY;
5500                 }
5501
5502                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5503                         spin_unlock_irq(&hdspm->lock);
5504                         _snd_pcm_hw_param_setempty(params,
5505                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5506                         return -EBUSY;
5507                 }
5508
5509         }
5510         /* We're fine. */
5511         spin_unlock_irq(&hdspm->lock);
5512
5513         /* how to make sure that the rate matches an externally-set one ?   */
5514
5515         spin_lock_irq(&hdspm->lock);
5516         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5517         if (err < 0) {
5518                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5519                 spin_unlock_irq(&hdspm->lock);
5520                 _snd_pcm_hw_param_setempty(params,
5521                                 SNDRV_PCM_HW_PARAM_RATE);
5522                 return err;
5523         }
5524         spin_unlock_irq(&hdspm->lock);
5525
5526         err = hdspm_set_interrupt_interval(hdspm,
5527                         params_period_size(params));
5528         if (err < 0) {
5529                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5530                 _snd_pcm_hw_param_setempty(params,
5531                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5532                 return err;
5533         }
5534
5535         /* Memory allocation, takashi's method, dont know if we should
5536          * spinlock
5537          */
5538         /* malloc all buffer even if not enabled to get sure */
5539         /* Update for MADI rev 204: we need to allocate for all channels,
5540          * otherwise it doesn't work at 96kHz */
5541
5542         err =
5543                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5544         if (err < 0) {
5545                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5546                 return err;
5547         }
5548
5549         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5550
5551                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5552                                 params_channels(params));
5553
5554                 for (i = 0; i < params_channels(params); ++i)
5555                         snd_hdspm_enable_out(hdspm, i, 1);
5556
5557                 hdspm->playback_buffer =
5558                         (unsigned char *) substream->runtime->dma_area;
5559                 snd_printdd("Allocated sample buffer for playback at %p\n",
5560                                 hdspm->playback_buffer);
5561         } else {
5562                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5563                                 params_channels(params));
5564
5565                 for (i = 0; i < params_channels(params); ++i)
5566                         snd_hdspm_enable_in(hdspm, i, 1);
5567
5568                 hdspm->capture_buffer =
5569                         (unsigned char *) substream->runtime->dma_area;
5570                 snd_printdd("Allocated sample buffer for capture at %p\n",
5571                                 hdspm->capture_buffer);
5572         }
5573
5574         /*
5575            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5576            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5577            "playback" : "capture",
5578            snd_pcm_sgbuf_get_addr(substream, 0));
5579            */
5580         /*
5581            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5582            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5583            "playback" : "capture",
5584            params_rate(params), params_channels(params),
5585            params_buffer_size(params));
5586            */
5587
5588
5589         /*  For AES cards, the float format bit is the same as the
5590          *  preferred sync reference. Since we don't want to break
5591          *  sync settings, we have to skip the remaining part of this
5592          *  function.
5593          */
5594         if (hdspm->io_type == AES32) {
5595                 return 0;
5596         }
5597
5598
5599         /* Switch to native float format if requested */
5600         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5601                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5602                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5603
5604                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5605         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5606                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5607                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5608
5609                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5610         }
5611         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5612
5613         return 0;
5614 }
5615
5616 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5617 {
5618         int i;
5619         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5620
5621         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5622
5623                 /* params_channels(params) should be enough,
5624                    but to get sure in case of error */
5625                 for (i = 0; i < hdspm->max_channels_out; ++i)
5626                         snd_hdspm_enable_out(hdspm, i, 0);
5627
5628                 hdspm->playback_buffer = NULL;
5629         } else {
5630                 for (i = 0; i < hdspm->max_channels_in; ++i)
5631                         snd_hdspm_enable_in(hdspm, i, 0);
5632
5633                 hdspm->capture_buffer = NULL;
5634
5635         }
5636
5637         snd_pcm_lib_free_pages(substream);
5638
5639         return 0;
5640 }
5641
5642
5643 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5644                 struct snd_pcm_channel_info *info)
5645 {
5646         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5647
5648         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5649                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5650                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5651                         return -EINVAL;
5652                 }
5653
5654                 if (hdspm->channel_map_out[info->channel] < 0) {
5655                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5656                         return -EINVAL;
5657                 }
5658
5659                 info->offset = hdspm->channel_map_out[info->channel] *
5660                         HDSPM_CHANNEL_BUFFER_BYTES;
5661         } else {
5662                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5663                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5664                         return -EINVAL;
5665                 }
5666
5667                 if (hdspm->channel_map_in[info->channel] < 0) {
5668                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5669                         return -EINVAL;
5670                 }
5671
5672                 info->offset = hdspm->channel_map_in[info->channel] *
5673                         HDSPM_CHANNEL_BUFFER_BYTES;
5674         }
5675
5676         info->first = 0;
5677         info->step = 32;
5678         return 0;
5679 }
5680
5681
5682 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5683                 unsigned int cmd, void *arg)
5684 {
5685         switch (cmd) {
5686         case SNDRV_PCM_IOCTL1_RESET:
5687                 return snd_hdspm_reset(substream);
5688
5689         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5690                 {
5691                         struct snd_pcm_channel_info *info = arg;
5692                         return snd_hdspm_channel_info(substream, info);
5693                 }
5694         default:
5695                 break;
5696         }
5697
5698         return snd_pcm_lib_ioctl(substream, cmd, arg);
5699 }
5700
5701 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5702 {
5703         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5704         struct snd_pcm_substream *other;
5705         int running;
5706
5707         spin_lock(&hdspm->lock);
5708         running = hdspm->running;
5709         switch (cmd) {
5710         case SNDRV_PCM_TRIGGER_START:
5711                 running |= 1 << substream->stream;
5712                 break;
5713         case SNDRV_PCM_TRIGGER_STOP:
5714                 running &= ~(1 << substream->stream);
5715                 break;
5716         default:
5717                 snd_BUG();
5718                 spin_unlock(&hdspm->lock);
5719                 return -EINVAL;
5720         }
5721         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5722                 other = hdspm->capture_substream;
5723         else
5724                 other = hdspm->playback_substream;
5725
5726         if (other) {
5727                 struct snd_pcm_substream *s;
5728                 snd_pcm_group_for_each_entry(s, substream) {
5729                         if (s == other) {
5730                                 snd_pcm_trigger_done(s, substream);
5731                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5732                                         running |= 1 << s->stream;
5733                                 else
5734                                         running &= ~(1 << s->stream);
5735                                 goto _ok;
5736                         }
5737                 }
5738                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5739                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5740                                         && substream->stream ==
5741                                         SNDRV_PCM_STREAM_CAPTURE)
5742                                 hdspm_silence_playback(hdspm);
5743                 } else {
5744                         if (running &&
5745                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5746                                 hdspm_silence_playback(hdspm);
5747                 }
5748         } else {
5749                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5750                         hdspm_silence_playback(hdspm);
5751         }
5752 _ok:
5753         snd_pcm_trigger_done(substream, substream);
5754         if (!hdspm->running && running)
5755                 hdspm_start_audio(hdspm);
5756         else if (hdspm->running && !running)
5757                 hdspm_stop_audio(hdspm);
5758         hdspm->running = running;
5759         spin_unlock(&hdspm->lock);
5760
5761         return 0;
5762 }
5763
5764 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5765 {
5766         return 0;
5767 }
5768
5769 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5770         .info = (SNDRV_PCM_INFO_MMAP |
5771                  SNDRV_PCM_INFO_MMAP_VALID |
5772                  SNDRV_PCM_INFO_NONINTERLEAVED |
5773                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5774         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5775         .rates = (SNDRV_PCM_RATE_32000 |
5776                   SNDRV_PCM_RATE_44100 |
5777                   SNDRV_PCM_RATE_48000 |
5778                   SNDRV_PCM_RATE_64000 |
5779                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5780                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5781         .rate_min = 32000,
5782         .rate_max = 192000,
5783         .channels_min = 1,
5784         .channels_max = HDSPM_MAX_CHANNELS,
5785         .buffer_bytes_max =
5786             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5787         .period_bytes_min = (32 * 4),
5788         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5789         .periods_min = 2,
5790         .periods_max = 512,
5791         .fifo_size = 0
5792 };
5793
5794 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5795         .info = (SNDRV_PCM_INFO_MMAP |
5796                  SNDRV_PCM_INFO_MMAP_VALID |
5797                  SNDRV_PCM_INFO_NONINTERLEAVED |
5798                  SNDRV_PCM_INFO_SYNC_START),
5799         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5800         .rates = (SNDRV_PCM_RATE_32000 |
5801                   SNDRV_PCM_RATE_44100 |
5802                   SNDRV_PCM_RATE_48000 |
5803                   SNDRV_PCM_RATE_64000 |
5804                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5805                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5806         .rate_min = 32000,
5807         .rate_max = 192000,
5808         .channels_min = 1,
5809         .channels_max = HDSPM_MAX_CHANNELS,
5810         .buffer_bytes_max =
5811             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5812         .period_bytes_min = (32 * 4),
5813         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5814         .periods_min = 2,
5815         .periods_max = 512,
5816         .fifo_size = 0
5817 };
5818
5819 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5820                                            struct snd_pcm_hw_rule *rule)
5821 {
5822         struct hdspm *hdspm = rule->private;
5823         struct snd_interval *c =
5824             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5825         struct snd_interval *r =
5826             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5827
5828         if (r->min > 96000 && r->max <= 192000) {
5829                 struct snd_interval t = {
5830                         .min = hdspm->qs_in_channels,
5831                         .max = hdspm->qs_in_channels,
5832                         .integer = 1,
5833                 };
5834                 return snd_interval_refine(c, &t);
5835         } else if (r->min > 48000 && r->max <= 96000) {
5836                 struct snd_interval t = {
5837                         .min = hdspm->ds_in_channels,
5838                         .max = hdspm->ds_in_channels,
5839                         .integer = 1,
5840                 };
5841                 return snd_interval_refine(c, &t);
5842         } else if (r->max < 64000) {
5843                 struct snd_interval t = {
5844                         .min = hdspm->ss_in_channels,
5845                         .max = hdspm->ss_in_channels,
5846                         .integer = 1,
5847                 };
5848                 return snd_interval_refine(c, &t);
5849         }
5850
5851         return 0;
5852 }
5853
5854 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5855                                            struct snd_pcm_hw_rule * rule)
5856 {
5857         struct hdspm *hdspm = rule->private;
5858         struct snd_interval *c =
5859             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5860         struct snd_interval *r =
5861             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5862
5863         if (r->min > 96000 && r->max <= 192000) {
5864                 struct snd_interval t = {
5865                         .min = hdspm->qs_out_channels,
5866                         .max = hdspm->qs_out_channels,
5867                         .integer = 1,
5868                 };
5869                 return snd_interval_refine(c, &t);
5870         } else if (r->min > 48000 && r->max <= 96000) {
5871                 struct snd_interval t = {
5872                         .min = hdspm->ds_out_channels,
5873                         .max = hdspm->ds_out_channels,
5874                         .integer = 1,
5875                 };
5876                 return snd_interval_refine(c, &t);
5877         } else if (r->max < 64000) {
5878                 struct snd_interval t = {
5879                         .min = hdspm->ss_out_channels,
5880                         .max = hdspm->ss_out_channels,
5881                         .integer = 1,
5882                 };
5883                 return snd_interval_refine(c, &t);
5884         } else {
5885         }
5886         return 0;
5887 }
5888
5889 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5890                                            struct snd_pcm_hw_rule * rule)
5891 {
5892         struct hdspm *hdspm = rule->private;
5893         struct snd_interval *c =
5894             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5895         struct snd_interval *r =
5896             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5897
5898         if (c->min >= hdspm->ss_in_channels) {
5899                 struct snd_interval t = {
5900                         .min = 32000,
5901                         .max = 48000,
5902                         .integer = 1,
5903                 };
5904                 return snd_interval_refine(r, &t);
5905         } else if (c->max <= hdspm->qs_in_channels) {
5906                 struct snd_interval t = {
5907                         .min = 128000,
5908                         .max = 192000,
5909                         .integer = 1,
5910                 };
5911                 return snd_interval_refine(r, &t);
5912         } else if (c->max <= hdspm->ds_in_channels) {
5913                 struct snd_interval t = {
5914                         .min = 64000,
5915                         .max = 96000,
5916                         .integer = 1,
5917                 };
5918                 return snd_interval_refine(r, &t);
5919         }
5920
5921         return 0;
5922 }
5923 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5924                                            struct snd_pcm_hw_rule *rule)
5925 {
5926         struct hdspm *hdspm = rule->private;
5927         struct snd_interval *c =
5928             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5929         struct snd_interval *r =
5930             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5931
5932         if (c->min >= hdspm->ss_out_channels) {
5933                 struct snd_interval t = {
5934                         .min = 32000,
5935                         .max = 48000,
5936                         .integer = 1,
5937                 };
5938                 return snd_interval_refine(r, &t);
5939         } else if (c->max <= hdspm->qs_out_channels) {
5940                 struct snd_interval t = {
5941                         .min = 128000,
5942                         .max = 192000,
5943                         .integer = 1,
5944                 };
5945                 return snd_interval_refine(r, &t);
5946         } else if (c->max <= hdspm->ds_out_channels) {
5947                 struct snd_interval t = {
5948                         .min = 64000,
5949                         .max = 96000,
5950                         .integer = 1,
5951                 };
5952                 return snd_interval_refine(r, &t);
5953         }
5954
5955         return 0;
5956 }
5957
5958 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5959                                       struct snd_pcm_hw_rule *rule)
5960 {
5961         unsigned int list[3];
5962         struct hdspm *hdspm = rule->private;
5963         struct snd_interval *c = hw_param_interval(params,
5964                         SNDRV_PCM_HW_PARAM_CHANNELS);
5965
5966         list[0] = hdspm->qs_in_channels;
5967         list[1] = hdspm->ds_in_channels;
5968         list[2] = hdspm->ss_in_channels;
5969         return snd_interval_list(c, 3, list, 0);
5970 }
5971
5972 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5973                                       struct snd_pcm_hw_rule *rule)
5974 {
5975         unsigned int list[3];
5976         struct hdspm *hdspm = rule->private;
5977         struct snd_interval *c = hw_param_interval(params,
5978                         SNDRV_PCM_HW_PARAM_CHANNELS);
5979
5980         list[0] = hdspm->qs_out_channels;
5981         list[1] = hdspm->ds_out_channels;
5982         list[2] = hdspm->ss_out_channels;
5983         return snd_interval_list(c, 3, list, 0);
5984 }
5985
5986
5987 static unsigned int hdspm_aes32_sample_rates[] = {
5988         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5989 };
5990
5991 static struct snd_pcm_hw_constraint_list
5992 hdspm_hw_constraints_aes32_sample_rates = {
5993         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5994         .list = hdspm_aes32_sample_rates,
5995         .mask = 0
5996 };
5997
5998 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5999 {
6000         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6001         struct snd_pcm_runtime *runtime = substream->runtime;
6002
6003         spin_lock_irq(&hdspm->lock);
6004
6005         snd_pcm_set_sync(substream);
6006
6007
6008         runtime->hw = snd_hdspm_playback_subinfo;
6009
6010         if (hdspm->capture_substream == NULL)
6011                 hdspm_stop_audio(hdspm);
6012
6013         hdspm->playback_pid = current->pid;
6014         hdspm->playback_substream = substream;
6015
6016         spin_unlock_irq(&hdspm->lock);
6017
6018         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6019         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6020
6021         switch (hdspm->io_type) {
6022         case AIO:
6023         case RayDAT:
6024                 snd_pcm_hw_constraint_minmax(runtime,
6025                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6026                                              32, 4096);
6027                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6028                 snd_pcm_hw_constraint_minmax(runtime,
6029                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6030                                              16384, 16384);
6031                 break;
6032
6033         default:
6034                 snd_pcm_hw_constraint_minmax(runtime,
6035                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6036                                              64, 8192);
6037                 break;
6038         }
6039
6040         if (AES32 == hdspm->io_type) {
6041                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6042                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6043                                 &hdspm_hw_constraints_aes32_sample_rates);
6044         } else {
6045                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6046                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6047                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6048         }
6049
6050         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6051                         snd_hdspm_hw_rule_out_channels, hdspm,
6052                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6053
6054         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6055                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
6056                         SNDRV_PCM_HW_PARAM_RATE, -1);
6057
6058         return 0;
6059 }
6060
6061 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6062 {
6063         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6064
6065         spin_lock_irq(&hdspm->lock);
6066
6067         hdspm->playback_pid = -1;
6068         hdspm->playback_substream = NULL;
6069
6070         spin_unlock_irq(&hdspm->lock);
6071
6072         return 0;
6073 }
6074
6075
6076 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6077 {
6078         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6079         struct snd_pcm_runtime *runtime = substream->runtime;
6080
6081         spin_lock_irq(&hdspm->lock);
6082         snd_pcm_set_sync(substream);
6083         runtime->hw = snd_hdspm_capture_subinfo;
6084
6085         if (hdspm->playback_substream == NULL)
6086                 hdspm_stop_audio(hdspm);
6087
6088         hdspm->capture_pid = current->pid;
6089         hdspm->capture_substream = substream;
6090
6091         spin_unlock_irq(&hdspm->lock);
6092
6093         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6094         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6095
6096         switch (hdspm->io_type) {
6097         case AIO:
6098         case RayDAT:
6099                 snd_pcm_hw_constraint_minmax(runtime,
6100                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6101                                              32, 4096);
6102                 snd_pcm_hw_constraint_minmax(runtime,
6103                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6104                                              16384, 16384);
6105                 break;
6106
6107         default:
6108                 snd_pcm_hw_constraint_minmax(runtime,
6109                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6110                                              64, 8192);
6111                 break;
6112         }
6113
6114         if (AES32 == hdspm->io_type) {
6115                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6116                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6117                                 &hdspm_hw_constraints_aes32_sample_rates);
6118         } else {
6119                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6120                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6121                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6122         }
6123
6124         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6125                         snd_hdspm_hw_rule_in_channels, hdspm,
6126                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6127
6128         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6129                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6130                         SNDRV_PCM_HW_PARAM_RATE, -1);
6131
6132         return 0;
6133 }
6134
6135 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6136 {
6137         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6138
6139         spin_lock_irq(&hdspm->lock);
6140
6141         hdspm->capture_pid = -1;
6142         hdspm->capture_substream = NULL;
6143
6144         spin_unlock_irq(&hdspm->lock);
6145         return 0;
6146 }
6147
6148 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6149 {
6150         /* we have nothing to initialize but the call is required */
6151         return 0;
6152 }
6153
6154 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6155 {
6156         u32 val = readl(src);
6157         return copy_to_user(dest, &val, 4);
6158 }
6159
6160 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6161                 unsigned int cmd, unsigned long arg)
6162 {
6163         void __user *argp = (void __user *)arg;
6164         struct hdspm *hdspm = hw->private_data;
6165         struct hdspm_mixer_ioctl mixer;
6166         struct hdspm_config info;
6167         struct hdspm_status status;
6168         struct hdspm_version hdspm_version;
6169         struct hdspm_peak_rms *levels;
6170         struct hdspm_ltc ltc;
6171         unsigned int statusregister;
6172         long unsigned int s;
6173         int i = 0;
6174
6175         switch (cmd) {
6176
6177         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6178                 levels = &hdspm->peak_rms;
6179                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6180                         levels->input_peaks[i] =
6181                                 readl(hdspm->iobase +
6182                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6183                         levels->playback_peaks[i] =
6184                                 readl(hdspm->iobase +
6185                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6186                         levels->output_peaks[i] =
6187                                 readl(hdspm->iobase +
6188                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6189
6190                         levels->input_rms[i] =
6191                                 ((uint64_t) readl(hdspm->iobase +
6192                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6193                                 (uint64_t) readl(hdspm->iobase +
6194                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6195                         levels->playback_rms[i] =
6196                                 ((uint64_t)readl(hdspm->iobase +
6197                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6198                                 (uint64_t)readl(hdspm->iobase +
6199                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6200                         levels->output_rms[i] =
6201                                 ((uint64_t)readl(hdspm->iobase +
6202                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6203                                 (uint64_t)readl(hdspm->iobase +
6204                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6205                 }
6206
6207                 if (hdspm->system_sample_rate > 96000) {
6208                         levels->speed = qs;
6209                 } else if (hdspm->system_sample_rate > 48000) {
6210                         levels->speed = ds;
6211                 } else {
6212                         levels->speed = ss;
6213                 }
6214                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6215
6216                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6217                 if (0 != s) {
6218                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6219                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6220                          */
6221                         return -EFAULT;
6222                 }
6223                 break;
6224
6225         case SNDRV_HDSPM_IOCTL_GET_LTC:
6226                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6227                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6228                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6229                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6230                                 HDSPM_TCO1_LTC_Format_MSB)) {
6231                         case 0:
6232                                 ltc.format = fps_24;
6233                                 break;
6234                         case HDSPM_TCO1_LTC_Format_LSB:
6235                                 ltc.format = fps_25;
6236                                 break;
6237                         case HDSPM_TCO1_LTC_Format_MSB:
6238                                 ltc.format = fps_2997;
6239                                 break;
6240                         default:
6241                                 ltc.format = 30;
6242                                 break;
6243                         }
6244                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6245                                 ltc.frame = drop_frame;
6246                         } else {
6247                                 ltc.frame = full_frame;
6248                         }
6249                 } else {
6250                         ltc.format = format_invalid;
6251                         ltc.frame = frame_invalid;
6252                 }
6253                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6254                         ltc.input_format = ntsc;
6255                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6256                         ltc.input_format = pal;
6257                 } else {
6258                         ltc.input_format = no_video;
6259                 }
6260
6261                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6262                 if (0 != s) {
6263                         /*
6264                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6265                         return -EFAULT;
6266                 }
6267
6268                 break;
6269
6270         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6271
6272                 memset(&info, 0, sizeof(info));
6273                 spin_lock_irq(&hdspm->lock);
6274                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6275                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6276
6277                 info.system_sample_rate = hdspm->system_sample_rate;
6278                 info.autosync_sample_rate =
6279                         hdspm_external_sample_rate(hdspm);
6280                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6281                 info.clock_source = hdspm_clock_source(hdspm);
6282                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6283                 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6284                 info.passthru = 0;
6285                 spin_unlock_irq(&hdspm->lock);
6286                 if (copy_to_user(argp, &info, sizeof(info)))
6287                         return -EFAULT;
6288                 break;
6289
6290         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6291                 memset(&status, 0, sizeof(status));
6292
6293                 status.card_type = hdspm->io_type;
6294
6295                 status.autosync_source = hdspm_autosync_ref(hdspm);
6296
6297                 status.card_clock = 110069313433624ULL;
6298                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6299
6300                 switch (hdspm->io_type) {
6301                 case MADI:
6302                 case MADIface:
6303                         status.card_specific.madi.sync_wc =
6304                                 hdspm_wc_sync_check(hdspm);
6305                         status.card_specific.madi.sync_madi =
6306                                 hdspm_madi_sync_check(hdspm);
6307                         status.card_specific.madi.sync_tco =
6308                                 hdspm_tco_sync_check(hdspm);
6309                         status.card_specific.madi.sync_in =
6310                                 hdspm_sync_in_sync_check(hdspm);
6311
6312                         statusregister =
6313                                 hdspm_read(hdspm, HDSPM_statusRegister);
6314                         status.card_specific.madi.madi_input =
6315                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6316                         status.card_specific.madi.channel_format =
6317                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6318                         /* TODO: Mac driver sets it when f_s>48kHz */
6319                         status.card_specific.madi.frame_format = 0;
6320
6321                 default:
6322                         break;
6323                 }
6324
6325                 if (copy_to_user(argp, &status, sizeof(status)))
6326                         return -EFAULT;
6327
6328
6329                 break;
6330
6331         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6332                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6333
6334                 hdspm_version.card_type = hdspm->io_type;
6335                 strncpy(hdspm_version.cardname, hdspm->card_name,
6336                                 sizeof(hdspm_version.cardname));
6337                 hdspm_version.serial = hdspm->serial;
6338                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6339                 hdspm_version.addons = 0;
6340                 if (hdspm->tco)
6341                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6342
6343                 if (copy_to_user(argp, &hdspm_version,
6344                                         sizeof(hdspm_version)))
6345                         return -EFAULT;
6346                 break;
6347
6348         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6349                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6350                         return -EFAULT;
6351                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6352                                         sizeof(struct hdspm_mixer)))
6353                         return -EFAULT;
6354                 break;
6355
6356         default:
6357                 return -EINVAL;
6358         }
6359         return 0;
6360 }
6361
6362 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6363         .open = snd_hdspm_playback_open,
6364         .close = snd_hdspm_playback_release,
6365         .ioctl = snd_hdspm_ioctl,
6366         .hw_params = snd_hdspm_hw_params,
6367         .hw_free = snd_hdspm_hw_free,
6368         .prepare = snd_hdspm_prepare,
6369         .trigger = snd_hdspm_trigger,
6370         .pointer = snd_hdspm_hw_pointer,
6371         .page = snd_pcm_sgbuf_ops_page,
6372 };
6373
6374 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6375         .open = snd_hdspm_capture_open,
6376         .close = snd_hdspm_capture_release,
6377         .ioctl = snd_hdspm_ioctl,
6378         .hw_params = snd_hdspm_hw_params,
6379         .hw_free = snd_hdspm_hw_free,
6380         .prepare = snd_hdspm_prepare,
6381         .trigger = snd_hdspm_trigger,
6382         .pointer = snd_hdspm_hw_pointer,
6383         .page = snd_pcm_sgbuf_ops_page,
6384 };
6385
6386 static int snd_hdspm_create_hwdep(struct snd_card *card,
6387                                   struct hdspm *hdspm)
6388 {
6389         struct snd_hwdep *hw;
6390         int err;
6391
6392         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6393         if (err < 0)
6394                 return err;
6395
6396         hdspm->hwdep = hw;
6397         hw->private_data = hdspm;
6398         strcpy(hw->name, "HDSPM hwdep interface");
6399
6400         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6401         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6402         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6403         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6404
6405         return 0;
6406 }
6407
6408
6409 /*------------------------------------------------------------
6410    memory interface
6411  ------------------------------------------------------------*/
6412 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6413 {
6414         int err;
6415         struct snd_pcm *pcm;
6416         size_t wanted;
6417
6418         pcm = hdspm->pcm;
6419
6420         wanted = HDSPM_DMA_AREA_BYTES;
6421
6422         err =
6423              snd_pcm_lib_preallocate_pages_for_all(pcm,
6424                                                    SNDRV_DMA_TYPE_DEV_SG,
6425                                                    snd_dma_pci_data(hdspm->pci),
6426                                                    wanted,
6427                                                    wanted);
6428         if (err < 0) {
6429                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6430
6431                 return err;
6432         } else
6433                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6434
6435         return 0;
6436 }
6437
6438
6439 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6440                             struct snd_pcm_substream *substream,
6441                              unsigned int reg, int channels)
6442 {
6443         int i;
6444
6445         /* continuous memory segment */
6446         for (i = 0; i < (channels * 16); i++)
6447                 hdspm_write(hdspm, reg + 4 * i,
6448                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6449 }
6450
6451
6452 /* ------------- ALSA Devices ---------------------------- */
6453 static int snd_hdspm_create_pcm(struct snd_card *card,
6454                                 struct hdspm *hdspm)
6455 {
6456         struct snd_pcm *pcm;
6457         int err;
6458
6459         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6460         if (err < 0)
6461                 return err;
6462
6463         hdspm->pcm = pcm;
6464         pcm->private_data = hdspm;
6465         strcpy(pcm->name, hdspm->card_name);
6466
6467         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6468                         &snd_hdspm_playback_ops);
6469         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6470                         &snd_hdspm_capture_ops);
6471
6472         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6473
6474         err = snd_hdspm_preallocate_memory(hdspm);
6475         if (err < 0)
6476                 return err;
6477
6478         return 0;
6479 }
6480
6481 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6482 {
6483         int i;
6484
6485         for (i = 0; i < hdspm->midiPorts; i++)
6486                 snd_hdspm_flush_midi_input(hdspm, i);
6487 }
6488
6489 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6490                                          struct hdspm *hdspm)
6491 {
6492         int err, i;
6493
6494         snd_printdd("Create card...\n");
6495         err = snd_hdspm_create_pcm(card, hdspm);
6496         if (err < 0)
6497                 return err;
6498
6499         i = 0;
6500         while (i < hdspm->midiPorts) {
6501                 err = snd_hdspm_create_midi(card, hdspm, i);
6502                 if (err < 0) {
6503                         return err;
6504                 }
6505                 i++;
6506         }
6507
6508         err = snd_hdspm_create_controls(card, hdspm);
6509         if (err < 0)
6510                 return err;
6511
6512         err = snd_hdspm_create_hwdep(card, hdspm);
6513         if (err < 0)
6514                 return err;
6515
6516         snd_printdd("proc init...\n");
6517         snd_hdspm_proc_init(hdspm);
6518
6519         hdspm->system_sample_rate = -1;
6520         hdspm->last_external_sample_rate = -1;
6521         hdspm->last_internal_sample_rate = -1;
6522         hdspm->playback_pid = -1;
6523         hdspm->capture_pid = -1;
6524         hdspm->capture_substream = NULL;
6525         hdspm->playback_substream = NULL;
6526
6527         snd_printdd("Set defaults...\n");
6528         err = snd_hdspm_set_defaults(hdspm);
6529         if (err < 0)
6530                 return err;
6531
6532         snd_printdd("Update mixer controls...\n");
6533         hdspm_update_simple_mixer_controls(hdspm);
6534
6535         snd_printdd("Initializeing complete ???\n");
6536
6537         err = snd_card_register(card);
6538         if (err < 0) {
6539                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6540                 return err;
6541         }
6542
6543         snd_printdd("... yes now\n");
6544
6545         return 0;
6546 }
6547
6548 static int snd_hdspm_create(struct snd_card *card,
6549                             struct hdspm *hdspm)
6550 {
6551
6552         struct pci_dev *pci = hdspm->pci;
6553         int err;
6554         unsigned long io_extent;
6555
6556         hdspm->irq = -1;
6557         hdspm->card = card;
6558
6559         spin_lock_init(&hdspm->lock);
6560
6561         pci_read_config_word(hdspm->pci,
6562                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6563
6564         strcpy(card->mixername, "Xilinx FPGA");
6565         strcpy(card->driver, "HDSPM");
6566
6567         switch (hdspm->firmware_rev) {
6568         case HDSPM_RAYDAT_REV:
6569                 hdspm->io_type = RayDAT;
6570                 hdspm->card_name = "RME RayDAT";
6571                 hdspm->midiPorts = 2;
6572                 break;
6573         case HDSPM_AIO_REV:
6574                 hdspm->io_type = AIO;
6575                 hdspm->card_name = "RME AIO";
6576                 hdspm->midiPorts = 1;
6577                 break;
6578         case HDSPM_MADIFACE_REV:
6579                 hdspm->io_type = MADIface;
6580                 hdspm->card_name = "RME MADIface";
6581                 hdspm->midiPorts = 1;
6582                 break;
6583         default:
6584                 if ((hdspm->firmware_rev == 0xf0) ||
6585                         ((hdspm->firmware_rev >= 0xe6) &&
6586                                         (hdspm->firmware_rev <= 0xea))) {
6587                         hdspm->io_type = AES32;
6588                         hdspm->card_name = "RME AES32";
6589                         hdspm->midiPorts = 2;
6590                 } else if ((hdspm->firmware_rev == 0xd2) ||
6591                         ((hdspm->firmware_rev >= 0xc8)  &&
6592                                 (hdspm->firmware_rev <= 0xcf))) {
6593                         hdspm->io_type = MADI;
6594                         hdspm->card_name = "RME MADI";
6595                         hdspm->midiPorts = 3;
6596                 } else {
6597                         snd_printk(KERN_ERR
6598                                 "HDSPM: unknown firmware revision %x\n",
6599                                 hdspm->firmware_rev);
6600                         return -ENODEV;
6601                 }
6602         }
6603
6604         err = pci_enable_device(pci);
6605         if (err < 0)
6606                 return err;
6607
6608         pci_set_master(hdspm->pci);
6609
6610         err = pci_request_regions(pci, "hdspm");
6611         if (err < 0)
6612                 return err;
6613
6614         hdspm->port = pci_resource_start(pci, 0);
6615         io_extent = pci_resource_len(pci, 0);
6616
6617         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6618                         hdspm->port, hdspm->port + io_extent - 1);
6619
6620         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6621         if (!hdspm->iobase) {
6622                 snd_printk(KERN_ERR "HDSPM: "
6623                                 "unable to remap region 0x%lx-0x%lx\n",
6624                                 hdspm->port, hdspm->port + io_extent - 1);
6625                 return -EBUSY;
6626         }
6627         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6628                         (unsigned long)hdspm->iobase, hdspm->port,
6629                         hdspm->port + io_extent - 1);
6630
6631         if (request_irq(pci->irq, snd_hdspm_interrupt,
6632                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6633                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6634                 return -EBUSY;
6635         }
6636
6637         snd_printdd("use IRQ %d\n", pci->irq);
6638
6639         hdspm->irq = pci->irq;
6640
6641         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6642                         sizeof(struct hdspm_mixer));
6643         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6644         if (!hdspm->mixer) {
6645                 snd_printk(KERN_ERR "HDSPM: "
6646                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6647                                 (int)sizeof(struct hdspm_mixer));
6648                 return -ENOMEM;
6649         }
6650
6651         hdspm->port_names_in = NULL;
6652         hdspm->port_names_out = NULL;
6653
6654         switch (hdspm->io_type) {
6655         case AES32:
6656                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6657                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6658                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6659
6660                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6661                         channel_map_aes32;
6662                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6663                         channel_map_aes32;
6664                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6665                         channel_map_aes32;
6666                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6667                         texts_ports_aes32;
6668                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6669                         texts_ports_aes32;
6670                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6671                         texts_ports_aes32;
6672
6673                 hdspm->max_channels_out = hdspm->max_channels_in =
6674                         AES32_CHANNELS;
6675                 hdspm->port_names_in = hdspm->port_names_out =
6676                         texts_ports_aes32;
6677                 hdspm->channel_map_in = hdspm->channel_map_out =
6678                         channel_map_aes32;
6679
6680                 break;
6681
6682         case MADI:
6683         case MADIface:
6684                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6685                         MADI_SS_CHANNELS;
6686                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6687                         MADI_DS_CHANNELS;
6688                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6689                         MADI_QS_CHANNELS;
6690
6691                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6692                         channel_map_unity_ss;
6693                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6694                         channel_map_unity_ss;
6695                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6696                         channel_map_unity_ss;
6697
6698                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6699                         texts_ports_madi;
6700                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6701                         texts_ports_madi;
6702                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6703                         texts_ports_madi;
6704                 break;
6705
6706         case AIO:
6707                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6708                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6709                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6710                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6711                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6712                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6713
6714                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6715                         snd_printk(KERN_INFO "HDSPM: AEB input board found\n");
6716                         hdspm->ss_in_channels += 4;
6717                         hdspm->ds_in_channels += 4;
6718                         hdspm->qs_in_channels += 4;
6719                 }
6720
6721                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6722                         snd_printk(KERN_INFO "HDSPM: AEB output board found\n");
6723                         hdspm->ss_out_channels += 4;
6724                         hdspm->ds_out_channels += 4;
6725                         hdspm->qs_out_channels += 4;
6726                 }
6727
6728                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6729                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6730                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6731
6732                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6733                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6734                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6735
6736                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6737                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6738                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6739                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6740                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6741                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6742
6743                 break;
6744
6745         case RayDAT:
6746                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6747                         RAYDAT_SS_CHANNELS;
6748                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6749                         RAYDAT_DS_CHANNELS;
6750                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6751                         RAYDAT_QS_CHANNELS;
6752
6753                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6754                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6755
6756                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6757                         channel_map_raydat_ss;
6758                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6759                         channel_map_raydat_ds;
6760                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6761                         channel_map_raydat_qs;
6762                 hdspm->channel_map_in = hdspm->channel_map_out =
6763                         channel_map_raydat_ss;
6764
6765                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6766                         texts_ports_raydat_ss;
6767                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6768                         texts_ports_raydat_ds;
6769                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6770                         texts_ports_raydat_qs;
6771
6772
6773                 break;
6774
6775         }
6776
6777         /* TCO detection */
6778         switch (hdspm->io_type) {
6779         case AIO:
6780         case RayDAT:
6781                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6782                                 HDSPM_s2_tco_detect) {
6783                         hdspm->midiPorts++;
6784                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6785                                         GFP_KERNEL);
6786                         if (NULL != hdspm->tco) {
6787                                 hdspm_tco_write(hdspm);
6788                         }
6789                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6790                 } else {
6791                         hdspm->tco = NULL;
6792                 }
6793                 break;
6794
6795         case MADI:
6796                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6797                         hdspm->midiPorts++;
6798                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6799                                         GFP_KERNEL);
6800                         if (NULL != hdspm->tco) {
6801                                 hdspm_tco_write(hdspm);
6802                         }
6803                         snd_printk(KERN_INFO "HDSPM: MADI/AES TCO module found\n");
6804                 } else {
6805                         hdspm->tco = NULL;
6806                 }
6807                 break;
6808
6809         default:
6810                 hdspm->tco = NULL;
6811         }
6812
6813         /* texts */
6814         switch (hdspm->io_type) {
6815         case AES32:
6816                 if (hdspm->tco) {
6817                         hdspm->texts_autosync = texts_autosync_aes_tco;
6818                         hdspm->texts_autosync_items =
6819                                 ARRAY_SIZE(texts_autosync_aes_tco);
6820                 } else {
6821                         hdspm->texts_autosync = texts_autosync_aes;
6822                         hdspm->texts_autosync_items =
6823                                 ARRAY_SIZE(texts_autosync_aes);
6824                 }
6825                 break;
6826
6827         case MADI:
6828                 if (hdspm->tco) {
6829                         hdspm->texts_autosync = texts_autosync_madi_tco;
6830                         hdspm->texts_autosync_items = 4;
6831                 } else {
6832                         hdspm->texts_autosync = texts_autosync_madi;
6833                         hdspm->texts_autosync_items = 3;
6834                 }
6835                 break;
6836
6837         case MADIface:
6838
6839                 break;
6840
6841         case RayDAT:
6842                 if (hdspm->tco) {
6843                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6844                         hdspm->texts_autosync_items = 9;
6845                 } else {
6846                         hdspm->texts_autosync = texts_autosync_raydat;
6847                         hdspm->texts_autosync_items = 8;
6848                 }
6849                 break;
6850
6851         case AIO:
6852                 if (hdspm->tco) {
6853                         hdspm->texts_autosync = texts_autosync_aio_tco;
6854                         hdspm->texts_autosync_items = 6;
6855                 } else {
6856                         hdspm->texts_autosync = texts_autosync_aio;
6857                         hdspm->texts_autosync_items = 5;
6858                 }
6859                 break;
6860
6861         }
6862
6863         tasklet_init(&hdspm->midi_tasklet,
6864                         hdspm_midi_tasklet, (unsigned long) hdspm);
6865
6866
6867         if (hdspm->io_type != MADIface) {
6868                 hdspm->serial = (hdspm_read(hdspm,
6869                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6870                 /* id contains either a user-provided value or the default
6871                  * NULL. If it's the default, we're safe to
6872                  * fill card->id with the serial number.
6873                  *
6874                  * If the serial number is 0xFFFFFF, then we're dealing with
6875                  * an old PCI revision that comes without a sane number. In
6876                  * this case, we don't set card->id to avoid collisions
6877                  * when running with multiple cards.
6878                  */
6879                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6880                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6881                         snd_card_set_id(card, card->id);
6882                 }
6883         }
6884
6885         snd_printdd("create alsa devices.\n");
6886         err = snd_hdspm_create_alsa_devices(card, hdspm);
6887         if (err < 0)
6888                 return err;
6889
6890         snd_hdspm_initialize_midi_flush(hdspm);
6891
6892         return 0;
6893 }
6894
6895
6896 static int snd_hdspm_free(struct hdspm * hdspm)
6897 {
6898
6899         if (hdspm->port) {
6900
6901                 /* stop th audio, and cancel all interrupts */
6902                 hdspm->control_register &=
6903                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6904                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6905                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6906                 hdspm_write(hdspm, HDSPM_controlRegister,
6907                             hdspm->control_register);
6908         }
6909
6910         if (hdspm->irq >= 0)
6911                 free_irq(hdspm->irq, (void *) hdspm);
6912
6913         kfree(hdspm->mixer);
6914
6915         if (hdspm->iobase)
6916                 iounmap(hdspm->iobase);
6917
6918         if (hdspm->port)
6919                 pci_release_regions(hdspm->pci);
6920
6921         pci_disable_device(hdspm->pci);
6922         return 0;
6923 }
6924
6925
6926 static void snd_hdspm_card_free(struct snd_card *card)
6927 {
6928         struct hdspm *hdspm = card->private_data;
6929
6930         if (hdspm)
6931                 snd_hdspm_free(hdspm);
6932 }
6933
6934
6935 static int snd_hdspm_probe(struct pci_dev *pci,
6936                            const struct pci_device_id *pci_id)
6937 {
6938         static int dev;
6939         struct hdspm *hdspm;
6940         struct snd_card *card;
6941         int err;
6942
6943         if (dev >= SNDRV_CARDS)
6944                 return -ENODEV;
6945         if (!enable[dev]) {
6946                 dev++;
6947                 return -ENOENT;
6948         }
6949
6950         err = snd_card_create(index[dev], id[dev],
6951                         THIS_MODULE, sizeof(struct hdspm), &card);
6952         if (err < 0)
6953                 return err;
6954
6955         hdspm = card->private_data;
6956         card->private_free = snd_hdspm_card_free;
6957         hdspm->dev = dev;
6958         hdspm->pci = pci;
6959
6960         snd_card_set_dev(card, &pci->dev);
6961
6962         err = snd_hdspm_create(card, hdspm);
6963         if (err < 0) {
6964                 snd_card_free(card);
6965                 return err;
6966         }
6967
6968         if (hdspm->io_type != MADIface) {
6969                 sprintf(card->shortname, "%s_%x",
6970                         hdspm->card_name,
6971                         hdspm->serial);
6972                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6973                         hdspm->card_name,
6974                         hdspm->serial,
6975                         hdspm->port, hdspm->irq);
6976         } else {
6977                 sprintf(card->shortname, "%s", hdspm->card_name);
6978                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6979                                 hdspm->card_name, hdspm->port, hdspm->irq);
6980         }
6981
6982         err = snd_card_register(card);
6983         if (err < 0) {
6984                 snd_card_free(card);
6985                 return err;
6986         }
6987
6988         pci_set_drvdata(pci, card);
6989
6990         dev++;
6991         return 0;
6992 }
6993
6994 static void snd_hdspm_remove(struct pci_dev *pci)
6995 {
6996         snd_card_free(pci_get_drvdata(pci));
6997 }
6998
6999 static struct pci_driver hdspm_driver = {
7000         .name = KBUILD_MODNAME,
7001         .id_table = snd_hdspm_ids,
7002         .probe = snd_hdspm_probe,
7003         .remove = snd_hdspm_remove,
7004 };
7005
7006 module_pci_driver(hdspm_driver);