sound/pci/rme9652/hdspm.c

   1 /*
   2  *   ALSA driver for RME Hammerfall DSP MADI audio interface(s)
   3  *
   4  *      Copyright (c) 2003 Winfried Ritsch (IEM)
   5  *      code based on hdsp.c   Paul Davis
   6  *                             Marcus Andersson
   7  *                             Thomas Charbonnel
   8  *      Modified 2006-06-01 for AES32 support by Remy Bruno
   9  *                                               <remy.bruno@trinnov.com>
  10  *
  11  *      Modified 2009-04-13 for proper metering by Florian Faber
  12  *                                               <faber@faberman.de>
  13  *
  14  *      Modified 2009-04-14 for native float support by Florian Faber
  15  *                                               <faber@faberman.de>
  16  *
  17  *      Modified 2009-04-26 fixed bug in rms metering by Florian Faber
  18  *                                               <faber@faberman.de>
  19  *
  20  *      Modified 2009-04-30 added hw serial number support by Florian Faber
  21  *
  22  *      Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
  23  *
  24  *      Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
  25  *
  26  *   This program is free software; you can redistribute it and/or modify
  27  *   it under the terms of the GNU General Public License as published by
  28  *   the Free Software Foundation; either version 2 of the License, or
  29  *   (at your option) any later version.
  30  *
  31  *   This program is distributed in the hope that it will be useful,
  32  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  33  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  34  *   GNU General Public License for more details.
  35  *
  36  *   You should have received a copy of the GNU General Public License
  37  *   along with this program; if not, write to the Free Software
  38  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  39  *
  40  */
  41 #include <linux/init.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/module.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/math64.h>
  48 #include <asm/io.h>
  49
  50 #include <sound/core.h>
  51 #include <sound/control.h>
  52 #include <sound/pcm.h>
  53 #include <sound/pcm_params.h>
  54 #include <sound/info.h>
  55 #include <sound/asoundef.h>
  56 #include <sound/rawmidi.h>
  57 #include <sound/hwdep.h>
  58 #include <sound/initval.h>
  59
  60 #include <sound/hdspm.h>
  61
  62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;        /* Index 0-MAX */
  63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;         /* ID for this card */
  64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  65
  66 module_param_array(index, int, NULL, 0444);
  67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
  68
  69 module_param_array(id, charp, NULL, 0444);
  70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
  71
  72 module_param_array(enable, bool, NULL, 0444);
  73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
  74
  75
  76 MODULE_AUTHOR
  77 (
  78         "Winfried Ritsch <ritsch_AT_iem.at>, "
  79         "Paul Davis <paul@linuxaudiosystems.com>, "
  80         "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
  81         "Remy Bruno <remy.bruno@trinnov.com>, "
  82         "Florian Faber <faberman@linuxproaudio.org>, "
  83         "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
  84 );
  85 MODULE_DESCRIPTION("RME HDSPM");
  86 MODULE_LICENSE("GPL");
  87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
  88
  89 /* --- Write registers. ---
  90   These are defined as byte-offsets from the iobase value.  */
  91
  92 #define HDSPM_WR_SETTINGS             0
  93 #define HDSPM_outputBufferAddress    32
  94 #define HDSPM_inputBufferAddress     36
  95 #define HDSPM_controlRegister        64
  96 #define HDSPM_interruptConfirmation  96
  97 #define HDSPM_control2Reg            256  /* not in specs ???????? */
  98 #define HDSPM_freqReg                256  /* for AES32 */
  99 #define HDSPM_midiDataOut0           352  /* just believe in old code */
 100 #define HDSPM_midiDataOut1           356
 101 #define HDSPM_eeprom_wr              384  /* for AES32 */
 102
 103 /* DMA enable for 64 channels, only Bit 0 is relevant */
 104 #define HDSPM_outputEnableBase       512  /* 512-767  input  DMA */
 105 #define HDSPM_inputEnableBase        768  /* 768-1023 output DMA */
 106
 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
 108    (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
 109 #define HDSPM_pageAddressBufferOut       8192
 110 #define HDSPM_pageAddressBufferIn        (HDSPM_pageAddressBufferOut+64*16*4)
 111
 112 #define HDSPM_MADI_mixerBase    32768   /* 32768-65535 for 2x64x64 Fader */
 113
 114 #define HDSPM_MATRIX_MIXER_SIZE  8192   /* = 2*64*64 * 4 Byte => 32kB */
 115
 116 /* --- Read registers. ---
 117    These are defined as byte-offsets from the iobase value */
 118 #define HDSPM_statusRegister    0
 119 /*#define HDSPM_statusRegister2  96 */
 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
 121  * offset 192, for AES32 *and* MADI
 122  * => need to check that offset 192 is working on MADI */
 123 #define HDSPM_statusRegister2  192
 124 #define HDSPM_timecodeRegister 128
 125
 126 /* AIO, RayDAT */
 127 #define HDSPM_RD_STATUS_0 0
 128 #define HDSPM_RD_STATUS_1 64
 129 #define HDSPM_RD_STATUS_2 128
 130 #define HDSPM_RD_STATUS_3 192
 131
 132 #define HDSPM_RD_TCO           256
 133 #define HDSPM_RD_PLL_FREQ      512
 134 #define HDSPM_WR_TCO           128
 135
 136 #define HDSPM_TCO1_TCO_lock                     0x00000001
 137 #define HDSPM_TCO1_WCK_Input_Range_LSB          0x00000002
 138 #define HDSPM_TCO1_WCK_Input_Range_MSB          0x00000004
 139 #define HDSPM_TCO1_LTC_Input_valid              0x00000008
 140 #define HDSPM_TCO1_WCK_Input_valid              0x00000010
 141 #define HDSPM_TCO1_Video_Input_Format_NTSC      0x00000020
 142 #define HDSPM_TCO1_Video_Input_Format_PAL       0x00000040
 143
 144 #define HDSPM_TCO1_set_TC                       0x00000100
 145 #define HDSPM_TCO1_set_drop_frame_flag          0x00000200
 146 #define HDSPM_TCO1_LTC_Format_LSB               0x00000400
 147 #define HDSPM_TCO1_LTC_Format_MSB               0x00000800
 148
 149 #define HDSPM_TCO2_TC_run                       0x00010000
 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB             0x00020000
 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB             0x00040000
 152 #define HDSPM_TCO2_set_num_drop_frames_LSB      0x00080000
 153 #define HDSPM_TCO2_set_num_drop_frames_MSB      0x00100000
 154 #define HDSPM_TCO2_set_jam_sync                 0x00200000
 155 #define HDSPM_TCO2_set_flywheel                 0x00400000
 156
 157 #define HDSPM_TCO2_set_01_4                     0x01000000
 158 #define HDSPM_TCO2_set_pull_down                0x02000000
 159 #define HDSPM_TCO2_set_pull_up                  0x04000000
 160 #define HDSPM_TCO2_set_freq                     0x08000000
 161 #define HDSPM_TCO2_set_term_75R                 0x10000000
 162 #define HDSPM_TCO2_set_input_LSB                0x20000000
 163 #define HDSPM_TCO2_set_input_MSB                0x40000000
 164 #define HDSPM_TCO2_set_freq_from_app            0x80000000
 165
 166
 167 #define HDSPM_midiDataOut0    352
 168 #define HDSPM_midiDataOut1    356
 169 #define HDSPM_midiDataOut2    368
 170
 171 #define HDSPM_midiDataIn0     360
 172 #define HDSPM_midiDataIn1     364
 173 #define HDSPM_midiDataIn2     372
 174 #define HDSPM_midiDataIn3     376
 175
 176 /* status is data bytes in MIDI-FIFO (0-128) */
 177 #define HDSPM_midiStatusOut0  384
 178 #define HDSPM_midiStatusOut1  388
 179 #define HDSPM_midiStatusOut2  400
 180
 181 #define HDSPM_midiStatusIn0   392
 182 #define HDSPM_midiStatusIn1   396
 183 #define HDSPM_midiStatusIn2   404
 184 #define HDSPM_midiStatusIn3   408
 185
 186
 187 /* the meters are regular i/o-mapped registers, but offset
 188    considerably from the rest. the peak registers are reset
 189    when read; the least-significant 4 bits are full-scale counters;
 190    the actual peak value is in the most-significant 24 bits.
 191 */
 192
 193 #define HDSPM_MADI_INPUT_PEAK           4096
 194 #define HDSPM_MADI_PLAYBACK_PEAK        4352
 195 #define HDSPM_MADI_OUTPUT_PEAK          4608
 196
 197 #define HDSPM_MADI_INPUT_RMS_L          6144
 198 #define HDSPM_MADI_PLAYBACK_RMS_L       6400
 199 #define HDSPM_MADI_OUTPUT_RMS_L         6656
 200
 201 #define HDSPM_MADI_INPUT_RMS_H          7168
 202 #define HDSPM_MADI_PLAYBACK_RMS_H       7424
 203 #define HDSPM_MADI_OUTPUT_RMS_H         7680
 204
 205 /* --- Control Register bits --------- */
 206 #define HDSPM_Start                (1<<0) /* start engine */
 207
 208 #define HDSPM_Latency0             (1<<1) /* buffer size = 2^n */
 209 #define HDSPM_Latency1             (1<<2) /* where n is defined */
 210 #define HDSPM_Latency2             (1<<3) /* by Latency{2,1,0} */
 211
 212 #define HDSPM_ClockModeMaster      (1<<4) /* 1=Master, 0=Autosync */
 213 #define HDSPM_c0Master          0x1    /* Master clock bit in settings
 214                                           register [RayDAT, AIO] */
 215
 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
 217
 218 #define HDSPM_Frequency0  (1<<6)  /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
 219 #define HDSPM_Frequency1  (1<<7)  /* 0=32kHz/64kHz */
 220 #define HDSPM_DoubleSpeed (1<<8)  /* 0=normal speed, 1=double speed */
 221 #define HDSPM_QuadSpeed   (1<<31) /* quad speed bit */
 222
 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
 224 #define HDSPM_TX_64ch     (1<<10) /* Output 64channel MODE=1,
 225                                      56channelMODE=0 */ /* MADI ONLY*/
 226 #define HDSPM_Emphasis    (1<<10) /* Emphasis */ /* AES32 ONLY */
 227
 228 #define HDSPM_AutoInp     (1<<11) /* Auto Input (takeover) == Safe Mode,
 229                                      0=off, 1=on  */ /* MADI ONLY */
 230 #define HDSPM_Dolby       (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
 231
 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
 233                                     * -- MADI ONLY
 234                                     */
 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
 236
 237 #define HDSPM_SyncRef2     (1<<13)
 238 #define HDSPM_SyncRef3     (1<<25)
 239
 240 #define HDSPM_SMUX         (1<<18) /* Frame ??? */ /* MADI ONY */
 241 #define HDSPM_clr_tms      (1<<19) /* clear track marker, do not use
 242                                       AES additional bits in
 243                                       lower 5 Audiodatabits ??? */
 244 #define HDSPM_taxi_reset   (1<<20) /* ??? */ /* MADI ONLY ? */
 245 #define HDSPM_WCK48        (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
 246
 247 #define HDSPM_Midi0InterruptEnable 0x0400000
 248 #define HDSPM_Midi1InterruptEnable 0x0800000
 249 #define HDSPM_Midi2InterruptEnable 0x0200000
 250 #define HDSPM_Midi3InterruptEnable 0x4000000
 251
 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
 253 #define HDSPe_FLOAT_FORMAT         0x2000000
 254
 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
 257 #define HDSPM_QS_QuadWire   (1<<28) /* AES32 ONLY */
 258
 259 #define HDSPM_wclk_sel (1<<30)
 260
 261 /* additional control register bits for AIO*/
 262 #define HDSPM_c0_Wck48                          0x20 /* also RayDAT */
 263 #define HDSPM_c0_Input0                         0x1000
 264 #define HDSPM_c0_Input1                         0x2000
 265 #define HDSPM_c0_Spdif_Opt                      0x4000
 266 #define HDSPM_c0_Pro                            0x8000
 267 #define HDSPM_c0_clr_tms                        0x10000
 268 #define HDSPM_c0_AEB1                           0x20000
 269 #define HDSPM_c0_AEB2                           0x40000
 270 #define HDSPM_c0_LineOut                        0x80000
 271 #define HDSPM_c0_AD_GAIN0                       0x100000
 272 #define HDSPM_c0_AD_GAIN1                       0x200000
 273 #define HDSPM_c0_DA_GAIN0                       0x400000
 274 #define HDSPM_c0_DA_GAIN1                       0x800000
 275 #define HDSPM_c0_PH_GAIN0                       0x1000000
 276 #define HDSPM_c0_PH_GAIN1                       0x2000000
 277 #define HDSPM_c0_Sym6db                         0x4000000
 278
 279
 280 /* --- bit helper defines */
 281 #define HDSPM_LatencyMask    (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
 282 #define HDSPM_FrequencyMask  (HDSPM_Frequency0|HDSPM_Frequency1|\
 283                               HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
 284 #define HDSPM_InputMask      (HDSPM_InputSelect0|HDSPM_InputSelect1)
 285 #define HDSPM_InputOptical   0
 286 #define HDSPM_InputCoaxial   (HDSPM_InputSelect0)
 287 #define HDSPM_SyncRefMask    (HDSPM_SyncRef0|HDSPM_SyncRef1|\
 288                               HDSPM_SyncRef2|HDSPM_SyncRef3)
 289
 290 #define HDSPM_c0_SyncRef0      0x2
 291 #define HDSPM_c0_SyncRef1      0x4
 292 #define HDSPM_c0_SyncRef2      0x8
 293 #define HDSPM_c0_SyncRef3      0x10
 294 #define HDSPM_c0_SyncRefMask   (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
 295                                 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
 296
 297 #define HDSPM_SYNC_FROM_WORD    0       /* Preferred sync reference */
 298 #define HDSPM_SYNC_FROM_MADI    1       /* choices - used by "pref_sync_ref" */
 299 #define HDSPM_SYNC_FROM_TCO     2
 300 #define HDSPM_SYNC_FROM_SYNC_IN 3
 301
 302 #define HDSPM_Frequency32KHz    HDSPM_Frequency0
 303 #define HDSPM_Frequency44_1KHz  HDSPM_Frequency1
 304 #define HDSPM_Frequency48KHz   (HDSPM_Frequency1|HDSPM_Frequency0)
 305 #define HDSPM_Frequency64KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency0)
 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
 307 #define HDSPM_Frequency96KHz   (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
 308                                 HDSPM_Frequency0)
 309 #define HDSPM_Frequency128KHz   (HDSPM_QuadSpeed|HDSPM_Frequency0)
 310 #define HDSPM_Frequency176_4KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1)
 311 #define HDSPM_Frequency192KHz   (HDSPM_QuadSpeed|HDSPM_Frequency1|\
 312                                  HDSPM_Frequency0)
 313
 314
 315 /* Synccheck Status */
 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0
 317 #define HDSPM_SYNC_CHECK_LOCK    1
 318 #define HDSPM_SYNC_CHECK_SYNC    2
 319
 320 /* AutoSync References - used by "autosync_ref" control switch */
 321 #define HDSPM_AUTOSYNC_FROM_WORD      0
 322 #define HDSPM_AUTOSYNC_FROM_MADI      1
 323 #define HDSPM_AUTOSYNC_FROM_TCO       2
 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN   3
 325 #define HDSPM_AUTOSYNC_FROM_NONE      4
 326
 327 /* Possible sources of MADI input */
 328 #define HDSPM_OPTICAL 0         /* optical   */
 329 #define HDSPM_COAXIAL 1         /* BNC */
 330
 331 #define hdspm_encode_latency(x)       (((x)<<1) & HDSPM_LatencyMask)
 332 #define hdspm_decode_latency(x)       ((((x) & HDSPM_LatencyMask)>>1))
 333
 334 #define hdspm_encode_in(x) (((x)&0x3)<<14)
 335 #define hdspm_decode_in(x) (((x)>>14)&0x3)
 336
 337 /* --- control2 register bits --- */
 338 #define HDSPM_TMS             (1<<0)
 339 #define HDSPM_TCK             (1<<1)
 340 #define HDSPM_TDI             (1<<2)
 341 #define HDSPM_JTAG            (1<<3)
 342 #define HDSPM_PWDN            (1<<4)
 343 #define HDSPM_PROGRAM         (1<<5)
 344 #define HDSPM_CONFIG_MODE_0   (1<<6)
 345 #define HDSPM_CONFIG_MODE_1   (1<<7)
 346 /*#define HDSPM_VERSION_BIT     (1<<8) not defined any more*/
 347 #define HDSPM_BIGENDIAN_MODE  (1<<9)
 348 #define HDSPM_RD_MULTIPLE     (1<<10)
 349
 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
 351      that do not conflict with specific bits for AES32 seem to be valid also
 352      for the AES32
 353  */
 354 #define HDSPM_audioIRQPending    (1<<0) /* IRQ is high and pending */
 355 #define HDSPM_RX_64ch            (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
 356 #define HDSPM_AB_int             (1<<2) /* InputChannel Opt=0, Coax=1
 357                                          * (like inp0)
 358                                          */
 359
 360 #define HDSPM_madiLock           (1<<3) /* MADI Locked =1, no=0 */
 361 #define HDSPM_madiSync          (1<<18) /* MADI is in sync */
 362
 363 #define HDSPM_tcoLockMadi    0x00000020 /* Optional TCO locked status for HDSPe MADI*/
 364 #define HDSPM_tcoSync    0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
 365
 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
 368
 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
 370                         /* since 64byte accurate, last 6 bits are not used */
 371
 372
 373
 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
 375
 376 #define HDSPM_madiFreq0         (1<<22) /* system freq 0=error */
 377 #define HDSPM_madiFreq1         (1<<23) /* 1=32, 2=44.1 3=48 */
 378 #define HDSPM_madiFreq2         (1<<24) /* 4=64, 5=88.2 6=96 */
 379 #define HDSPM_madiFreq3         (1<<25) /* 7=128, 8=176.4 9=192 */
 380
 381 #define HDSPM_BufferID          (1<<26) /* (Double)Buffer ID toggles with
 382                                          * Interrupt
 383                                          */
 384 #define HDSPM_tco_detect         0x08000000
 385 #define HDSPM_tcoLockAes         0x20000000 /* Optional TCO locked status for HDSPe AES */
 386
 387 #define HDSPM_s2_tco_detect      0x00000040
 388 #define HDSPM_s2_AEBO_D          0x00000080
 389 #define HDSPM_s2_AEBI_D          0x00000100
 390
 391
 392 #define HDSPM_midi0IRQPending    0x40000000
 393 #define HDSPM_midi1IRQPending    0x80000000
 394 #define HDSPM_midi2IRQPending    0x20000000
 395 #define HDSPM_midi2IRQPendingAES 0x00000020
 396 #define HDSPM_midi3IRQPending    0x00200000
 397
 398 /* --- status bit helpers */
 399 #define HDSPM_madiFreqMask  (HDSPM_madiFreq0|HDSPM_madiFreq1|\
 400                              HDSPM_madiFreq2|HDSPM_madiFreq3)
 401 #define HDSPM_madiFreq32    (HDSPM_madiFreq0)
 402 #define HDSPM_madiFreq44_1  (HDSPM_madiFreq1)
 403 #define HDSPM_madiFreq48    (HDSPM_madiFreq0|HDSPM_madiFreq1)
 404 #define HDSPM_madiFreq64    (HDSPM_madiFreq2)
 405 #define HDSPM_madiFreq88_2  (HDSPM_madiFreq0|HDSPM_madiFreq2)
 406 #define HDSPM_madiFreq96    (HDSPM_madiFreq1|HDSPM_madiFreq2)
 407 #define HDSPM_madiFreq128   (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
 409 #define HDSPM_madiFreq192   (HDSPM_madiFreq3|HDSPM_madiFreq0)
 410
 411 /* Status2 Register bits */ /* MADI ONLY */
 412
 413 #define HDSPM_version0 (1<<0)   /* not really defined but I guess */
 414 #define HDSPM_version1 (1<<1)   /* in former cards it was ??? */
 415 #define HDSPM_version2 (1<<2)
 416
 417 #define HDSPM_wcLock (1<<3)     /* Wordclock is detected and locked */
 418 #define HDSPM_wcSync (1<<4)     /* Wordclock is in sync with systemclock */
 419
 420 #define HDSPM_wc_freq0 (1<<5)   /* input freq detected via autosync  */
 421 #define HDSPM_wc_freq1 (1<<6)   /* 001=32, 010==44.1, 011=48, */
 422 #define HDSPM_wc_freq2 (1<<7)   /* 100=64, 101=88.2, 110=96, 111=128 */
 423 #define HDSPM_wc_freq3 0x800    /* 1000=176.4, 1001=192 */
 424
 425 #define HDSPM_SyncRef0 0x10000  /* Sync Reference */
 426 #define HDSPM_SyncRef1 0x20000
 427
 428 #define HDSPM_SelSyncRef0 (1<<8)        /* AutoSync Source */
 429 #define HDSPM_SelSyncRef1 (1<<9)        /* 000=word, 001=MADI, */
 430 #define HDSPM_SelSyncRef2 (1<<10)       /* 111=no valid signal */
 431
 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
 433
 434 #define HDSPM_wcFreqMask  (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
 435                             HDSPM_wc_freq3)
 436 #define HDSPM_wcFreq32    (HDSPM_wc_freq0)
 437 #define HDSPM_wcFreq44_1  (HDSPM_wc_freq1)
 438 #define HDSPM_wcFreq48    (HDSPM_wc_freq0|HDSPM_wc_freq1)
 439 #define HDSPM_wcFreq64    (HDSPM_wc_freq2)
 440 #define HDSPM_wcFreq88_2  (HDSPM_wc_freq0|HDSPM_wc_freq2)
 441 #define HDSPM_wcFreq96    (HDSPM_wc_freq1|HDSPM_wc_freq2)
 442 #define HDSPM_wcFreq128   (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
 444 #define HDSPM_wcFreq192   (HDSPM_wc_freq0|HDSPM_wc_freq3)
 445
 446 #define HDSPM_status1_F_0 0x0400000
 447 #define HDSPM_status1_F_1 0x0800000
 448 #define HDSPM_status1_F_2 0x1000000
 449 #define HDSPM_status1_F_3 0x2000000
 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
 451
 452
 453 #define HDSPM_SelSyncRefMask       (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 454                                     HDSPM_SelSyncRef2)
 455 #define HDSPM_SelSyncRef_WORD      0
 456 #define HDSPM_SelSyncRef_MADI      (HDSPM_SelSyncRef0)
 457 #define HDSPM_SelSyncRef_TCO       (HDSPM_SelSyncRef1)
 458 #define HDSPM_SelSyncRef_SyncIn    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
 459 #define HDSPM_SelSyncRef_NVALID    (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
 460                                     HDSPM_SelSyncRef2)
 461
 462 /*
 463    For AES32, bits for status, status2 and timecode are different
 464 */
 465 /* status */
 466 #define HDSPM_AES32_wcLock      0x0200000
 467 #define HDSPM_AES32_wcSync      0x0100000
 468 #define HDSPM_AES32_wcFreq_bit  22
 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
 470   HDSPM_bit2freq */
 471 #define HDSPM_AES32_syncref_bit  16
 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
 473
 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
 483 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
 484 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
 485 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
 486
 487 /*  status2 */
 488 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
 489 #define HDSPM_LockAES   0x80
 490 #define HDSPM_LockAES1  0x80
 491 #define HDSPM_LockAES2  0x40
 492 #define HDSPM_LockAES3  0x20
 493 #define HDSPM_LockAES4  0x10
 494 #define HDSPM_LockAES5  0x8
 495 #define HDSPM_LockAES6  0x4
 496 #define HDSPM_LockAES7  0x2
 497 #define HDSPM_LockAES8  0x1
 498 /*
 499    Timecode
 500    After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
 501    AES i+1
 502  bits 3210
 503       0001  32kHz
 504       0010  44.1kHz
 505       0011  48kHz
 506       0100  64kHz
 507       0101  88.2kHz
 508       0110  96kHz
 509       0111  128kHz
 510       1000  176.4kHz
 511       1001  192kHz
 512   NB: Timecode register doesn't seem to work on AES32 card revision 230
 513 */
 514
 515 /* Mixer Values */
 516 #define UNITY_GAIN          32768       /* = 65536/2 */
 517 #define MINUS_INFINITY_GAIN 0
 518
 519 /* Number of channels for different Speed Modes */
 520 #define MADI_SS_CHANNELS       64
 521 #define MADI_DS_CHANNELS       32
 522 #define MADI_QS_CHANNELS       16
 523
 524 #define RAYDAT_SS_CHANNELS     36
 525 #define RAYDAT_DS_CHANNELS     20
 526 #define RAYDAT_QS_CHANNELS     12
 527
 528 #define AIO_IN_SS_CHANNELS        14
 529 #define AIO_IN_DS_CHANNELS        10
 530 #define AIO_IN_QS_CHANNELS        8
 531 #define AIO_OUT_SS_CHANNELS        16
 532 #define AIO_OUT_DS_CHANNELS        12
 533 #define AIO_OUT_QS_CHANNELS        10
 534
 535 #define AES32_CHANNELS          16
 536
 537 /* the size of a substream (1 mono data stream) */
 538 #define HDSPM_CHANNEL_BUFFER_SAMPLES  (16*1024)
 539 #define HDSPM_CHANNEL_BUFFER_BYTES    (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
 540
 541 /* the size of the area we need to allocate for DMA transfers. the
 542    size is the same regardless of the number of channels, and
 543    also the latency to use.
 544    for one direction !!!
 545 */
 546 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
 547 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
 548
 549 #define HDSPM_RAYDAT_REV        211
 550 #define HDSPM_AIO_REV           212
 551 #define HDSPM_MADIFACE_REV      213
 552
 553 /* speed factor modes */
 554 #define HDSPM_SPEED_SINGLE 0
 555 #define HDSPM_SPEED_DOUBLE 1
 556 #define HDSPM_SPEED_QUAD   2
 557
 558 /* names for speed modes */
 559 static char *hdspm_speed_names[] = { "single", "double", "quad" };
 560
 561 static char *texts_autosync_aes_tco[] = { "Word Clock",
 562                                           "AES1", "AES2", "AES3", "AES4",
 563                                           "AES5", "AES6", "AES7", "AES8",
 564                                           "TCO", "Sync In"
 565 };
 566 static char *texts_autosync_aes[] = { "Word Clock",
 567                                       "AES1", "AES2", "AES3", "AES4",
 568                                       "AES5", "AES6", "AES7", "AES8",
 569                                       "Sync In"
 570 };
 571 static char *texts_autosync_madi_tco[] = { "Word Clock",
 572                                            "MADI", "TCO", "Sync In" };
 573 static char *texts_autosync_madi[] = { "Word Clock",
 574                                        "MADI", "Sync In" };
 575
 576 static char *texts_autosync_raydat_tco[] = {
 577         "Word Clock",
 578         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 579         "AES", "SPDIF", "TCO", "Sync In"
 580 };
 581 static char *texts_autosync_raydat[] = {
 582         "Word Clock",
 583         "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
 584         "AES", "SPDIF", "Sync In"
 585 };
 586 static char *texts_autosync_aio_tco[] = {
 587         "Word Clock",
 588         "ADAT", "AES", "SPDIF", "TCO", "Sync In"
 589 };
 590 static char *texts_autosync_aio[] = { "Word Clock",
 591                                       "ADAT", "AES", "SPDIF", "Sync In" };
 592
 593 static char *texts_freq[] = {
 594         "No Lock",
 595         "32 kHz",
 596         "44.1 kHz",
 597         "48 kHz",
 598         "64 kHz",
 599         "88.2 kHz",
 600         "96 kHz",
 601         "128 kHz",
 602         "176.4 kHz",
 603         "192 kHz"
 604 };
 605
 606 static char *texts_ports_madi[] = {
 607         "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
 608         "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
 609         "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
 610         "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
 611         "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
 612         "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
 613         "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
 614         "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
 615         "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
 616         "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
 617         "MADI.61", "MADI.62", "MADI.63", "MADI.64",
 618 };
 619
 620
 621 static char *texts_ports_raydat_ss[] = {
 622         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
 623         "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 624         "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
 625         "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
 626         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
 627         "ADAT4.7", "ADAT4.8",
 628         "AES.L", "AES.R",
 629         "SPDIF.L", "SPDIF.R"
 630 };
 631
 632 static char *texts_ports_raydat_ds[] = {
 633         "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
 634         "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
 635         "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
 636         "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
 637         "AES.L", "AES.R",
 638         "SPDIF.L", "SPDIF.R"
 639 };
 640
 641 static char *texts_ports_raydat_qs[] = {
 642         "ADAT1.1", "ADAT1.2",
 643         "ADAT2.1", "ADAT2.2",
 644         "ADAT3.1", "ADAT3.2",
 645         "ADAT4.1", "ADAT4.2",
 646         "AES.L", "AES.R",
 647         "SPDIF.L", "SPDIF.R"
 648 };
 649
 650
 651 static char *texts_ports_aio_in_ss[] = {
 652         "Analogue.L", "Analogue.R",
 653         "AES.L", "AES.R",
 654         "SPDIF.L", "SPDIF.R",
 655         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 656         "ADAT.7", "ADAT.8",
 657         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 658 };
 659
 660 static char *texts_ports_aio_out_ss[] = {
 661         "Analogue.L", "Analogue.R",
 662         "AES.L", "AES.R",
 663         "SPDIF.L", "SPDIF.R",
 664         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
 665         "ADAT.7", "ADAT.8",
 666         "Phone.L", "Phone.R",
 667         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 668 };
 669
 670 static char *texts_ports_aio_in_ds[] = {
 671         "Analogue.L", "Analogue.R",
 672         "AES.L", "AES.R",
 673         "SPDIF.L", "SPDIF.R",
 674         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 675         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 676 };
 677
 678 static char *texts_ports_aio_out_ds[] = {
 679         "Analogue.L", "Analogue.R",
 680         "AES.L", "AES.R",
 681         "SPDIF.L", "SPDIF.R",
 682         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 683         "Phone.L", "Phone.R",
 684         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 685 };
 686
 687 static char *texts_ports_aio_in_qs[] = {
 688         "Analogue.L", "Analogue.R",
 689         "AES.L", "AES.R",
 690         "SPDIF.L", "SPDIF.R",
 691         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 692         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 693 };
 694
 695 static char *texts_ports_aio_out_qs[] = {
 696         "Analogue.L", "Analogue.R",
 697         "AES.L", "AES.R",
 698         "SPDIF.L", "SPDIF.R",
 699         "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
 700         "Phone.L", "Phone.R",
 701         "AEB.1", "AEB.2", "AEB.3", "AEB.4"
 702 };
 703
 704 static char *texts_ports_aes32[] = {
 705         "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
 706         "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
 707         "AES.15", "AES.16"
 708 };
 709
 710 /* These tables map the ALSA channels 1..N to the channels that we
 711    need to use in order to find the relevant channel buffer. RME
 712    refers to this kind of mapping as between "the ADAT channel and
 713    the DMA channel." We index it using the logical audio channel,
 714    and the value is the DMA channel (i.e. channel buffer number)
 715    where the data for that channel can be read/written from/to.
 716 */
 717
 718 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
 719         0, 1, 2, 3, 4, 5, 6, 7,
 720         8, 9, 10, 11, 12, 13, 14, 15,
 721         16, 17, 18, 19, 20, 21, 22, 23,
 722         24, 25, 26, 27, 28, 29, 30, 31,
 723         32, 33, 34, 35, 36, 37, 38, 39,
 724         40, 41, 42, 43, 44, 45, 46, 47,
 725         48, 49, 50, 51, 52, 53, 54, 55,
 726         56, 57, 58, 59, 60, 61, 62, 63
 727 };
 728
 729 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
 730         4, 5, 6, 7, 8, 9, 10, 11,       /* ADAT 1 */
 731         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
 732         20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
 733         28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
 734         0, 1,                   /* AES */
 735         2, 3,                   /* SPDIF */
 736         -1, -1, -1, -1,
 737         -1, -1, -1, -1, -1, -1, -1, -1,
 738         -1, -1, -1, -1, -1, -1, -1, -1,
 739         -1, -1, -1, -1, -1, -1, -1, -1,
 740 };
 741
 742 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
 743         4, 5, 6, 7,             /* ADAT 1 */
 744         8, 9, 10, 11,           /* ADAT 2 */
 745         12, 13, 14, 15,         /* ADAT 3 */
 746         16, 17, 18, 19,         /* ADAT 4 */
 747         0, 1,                   /* AES */
 748         2, 3,                   /* SPDIF */
 749         -1, -1, -1, -1,
 750         -1, -1, -1, -1, -1, -1, -1, -1,
 751         -1, -1, -1, -1, -1, -1, -1, -1,
 752         -1, -1, -1, -1, -1, -1, -1, -1,
 753         -1, -1, -1, -1, -1, -1, -1, -1,
 754         -1, -1, -1, -1, -1, -1, -1, -1,
 755 };
 756
 757 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
 758         4, 5,                   /* ADAT 1 */
 759         6, 7,                   /* ADAT 2 */
 760         8, 9,                   /* ADAT 3 */
 761         10, 11,                 /* ADAT 4 */
 762         0, 1,                   /* AES */
 763         2, 3,                   /* SPDIF */
 764         -1, -1, -1, -1,
 765         -1, -1, -1, -1, -1, -1, -1, -1,
 766         -1, -1, -1, -1, -1, -1, -1, -1,
 767         -1, -1, -1, -1, -1, -1, -1, -1,
 768         -1, -1, -1, -1, -1, -1, -1, -1,
 769         -1, -1, -1, -1, -1, -1, -1, -1,
 770         -1, -1, -1, -1, -1, -1, -1, -1,
 771 };
 772
 773 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
 774         0, 1,                   /* line in */
 775         8, 9,                   /* aes in, */
 776         10, 11,                 /* spdif in */
 777         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
 778         2, 3, 4, 5,             /* AEB */
 779         -1, -1, -1, -1, -1, -1,
 780         -1, -1, -1, -1, -1, -1, -1, -1,
 781         -1, -1, -1, -1, -1, -1, -1, -1,
 782         -1, -1, -1, -1, -1, -1, -1, -1,
 783         -1, -1, -1, -1, -1, -1, -1, -1,
 784         -1, -1, -1, -1, -1, -1, -1, -1,
 785 };
 786
 787 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
 788         0, 1,                   /* line out */
 789         8, 9,                   /* aes out */
 790         10, 11,                 /* spdif out */
 791         12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
 792         6, 7,                   /* phone out */
 793         2, 3, 4, 5,             /* AEB */
 794         -1, -1, -1, -1,
 795         -1, -1, -1, -1, -1, -1, -1, -1,
 796         -1, -1, -1, -1, -1, -1, -1, -1,
 797         -1, -1, -1, -1, -1, -1, -1, -1,
 798         -1, -1, -1, -1, -1, -1, -1, -1,
 799         -1, -1, -1, -1, -1, -1, -1, -1,
 800 };
 801
 802 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
 803         0, 1,                   /* line in */
 804         8, 9,                   /* aes in */
 805         10, 11,                 /* spdif in */
 806         12, 14, 16, 18,         /* adat in */
 807         2, 3, 4, 5,             /* AEB */
 808         -1, -1,
 809         -1, -1, -1, -1, -1, -1, -1, -1,
 810         -1, -1, -1, -1, -1, -1, -1, -1,
 811         -1, -1, -1, -1, -1, -1, -1, -1,
 812         -1, -1, -1, -1, -1, -1, -1, -1,
 813         -1, -1, -1, -1, -1, -1, -1, -1,
 814         -1, -1, -1, -1, -1, -1, -1, -1
 815 };
 816
 817 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
 818         0, 1,                   /* line out */
 819         8, 9,                   /* aes out */
 820         10, 11,                 /* spdif out */
 821         12, 14, 16, 18,         /* adat out */
 822         6, 7,                   /* phone out */
 823         2, 3, 4, 5,             /* AEB */
 824         -1, -1, -1, -1, -1, -1, -1, -1,
 825         -1, -1, -1, -1, -1, -1, -1, -1,
 826         -1, -1, -1, -1, -1, -1, -1, -1,
 827         -1, -1, -1, -1, -1, -1, -1, -1,
 828         -1, -1, -1, -1, -1, -1, -1, -1,
 829         -1, -1, -1, -1, -1, -1, -1, -1
 830 };
 831
 832 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
 833         0, 1,                   /* line in */
 834         8, 9,                   /* aes in */
 835         10, 11,                 /* spdif in */
 836         12, 16,                 /* adat in */
 837         2, 3, 4, 5,             /* AEB */
 838         -1, -1, -1, -1,
 839         -1, -1, -1, -1, -1, -1, -1, -1,
 840         -1, -1, -1, -1, -1, -1, -1, -1,
 841         -1, -1, -1, -1, -1, -1, -1, -1,
 842         -1, -1, -1, -1, -1, -1, -1, -1,
 843         -1, -1, -1, -1, -1, -1, -1, -1,
 844         -1, -1, -1, -1, -1, -1, -1, -1
 845 };
 846
 847 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
 848         0, 1,                   /* line out */
 849         8, 9,                   /* aes out */
 850         10, 11,                 /* spdif out */
 851         12, 16,                 /* adat out */
 852         6, 7,                   /* phone out */
 853         2, 3, 4, 5,             /* AEB */
 854         -1, -1,
 855         -1, -1, -1, -1, -1, -1, -1, -1,
 856         -1, -1, -1, -1, -1, -1, -1, -1,
 857         -1, -1, -1, -1, -1, -1, -1, -1,
 858         -1, -1, -1, -1, -1, -1, -1, -1,
 859         -1, -1, -1, -1, -1, -1, -1, -1,
 860         -1, -1, -1, -1, -1, -1, -1, -1
 861 };
 862
 863 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
 864         0, 1, 2, 3, 4, 5, 6, 7,
 865         8, 9, 10, 11, 12, 13, 14, 15,
 866         -1, -1, -1, -1, -1, -1, -1, -1,
 867         -1, -1, -1, -1, -1, -1, -1, -1,
 868         -1, -1, -1, -1, -1, -1, -1, -1,
 869         -1, -1, -1, -1, -1, -1, -1, -1,
 870         -1, -1, -1, -1, -1, -1, -1, -1,
 871         -1, -1, -1, -1, -1, -1, -1, -1
 872 };
 873
 874 struct hdspm_midi {
 875         struct hdspm *hdspm;
 876         int id;
 877         struct snd_rawmidi *rmidi;
 878         struct snd_rawmidi_substream *input;
 879         struct snd_rawmidi_substream *output;
 880         char istimer;           /* timer in use */
 881         struct timer_list timer;
 882         spinlock_t lock;
 883         int pending;
 884         int dataIn;
 885         int statusIn;
 886         int dataOut;
 887         int statusOut;
 888         int ie;
 889         int irq;
 890 };
 891
 892 struct hdspm_tco {
 893         int input;
 894         int framerate;
 895         int wordclock;
 896         int samplerate;
 897         int pull;
 898         int term; /* 0 = off, 1 = on */
 899 };
 900
 901 struct hdspm {
 902         spinlock_t lock;
 903         /* only one playback and/or capture stream */
 904         struct snd_pcm_substream *capture_substream;
 905         struct snd_pcm_substream *playback_substream;
 906
 907         char *card_name;             /* for procinfo */
 908         unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
 909
 910         uint8_t io_type;
 911
 912         int monitor_outs;       /* set up monitoring outs init flag */
 913
 914         u32 control_register;   /* cached value */
 915         u32 control2_register;  /* cached value */
 916         u32 settings_register;
 917
 918         struct hdspm_midi midi[4];
 919         struct tasklet_struct midi_tasklet;
 920
 921         size_t period_bytes;
 922         unsigned char ss_in_channels;
 923         unsigned char ds_in_channels;
 924         unsigned char qs_in_channels;
 925         unsigned char ss_out_channels;
 926         unsigned char ds_out_channels;
 927         unsigned char qs_out_channels;
 928
 929         unsigned char max_channels_in;
 930         unsigned char max_channels_out;
 931
 932         signed char *channel_map_in;
 933         signed char *channel_map_out;
 934
 935         signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
 936         signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
 937
 938         char **port_names_in;
 939         char **port_names_out;
 940
 941         char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
 942         char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
 943
 944         unsigned char *playback_buffer; /* suitably aligned address */
 945         unsigned char *capture_buffer;  /* suitably aligned address */
 946
 947         pid_t capture_pid;      /* process id which uses capture */
 948         pid_t playback_pid;     /* process id which uses capture */
 949         int running;            /* running status */
 950
 951         int last_external_sample_rate;  /* samplerate mystic ... */
 952         int last_internal_sample_rate;
 953         int system_sample_rate;
 954
 955         int dev;                /* Hardware vars... */
 956         int irq;
 957         unsigned long port;
 958         void __iomem *iobase;
 959
 960         int irq_count;          /* for debug */
 961         int midiPorts;
 962
 963         struct snd_card *card;  /* one card */
 964         struct snd_pcm *pcm;            /* has one pcm */
 965         struct snd_hwdep *hwdep;        /* and a hwdep for additional ioctl */
 966         struct pci_dev *pci;    /* and an pci info */
 967
 968         /* Mixer vars */
 969         /* fast alsa mixer */
 970         struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
 971         /* but input to much, so not used */
 972         struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
 973         /* full mixer accessible over mixer ioctl or hwdep-device */
 974         struct hdspm_mixer *mixer;
 975
 976         struct hdspm_tco *tco;  /* NULL if no TCO detected */
 977
 978         char **texts_autosync;
 979         int texts_autosync_items;
 980
 981         cycles_t last_interrupt;
 982
 983         unsigned int serial;
 984
 985         struct hdspm_peak_rms peak_rms;
 986 };
 987
 988
 989 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = {
 990         {
 991          .vendor = PCI_VENDOR_ID_XILINX,
 992          .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
 993          .subvendor = PCI_ANY_ID,
 994          .subdevice = PCI_ANY_ID,
 995          .class = 0,
 996          .class_mask = 0,
 997          .driver_data = 0},
 998         {0,}
 999 };
1000
1001 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1002
1003 /* prototypes */
1004 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1005                                          struct hdspm *hdspm);
1006 static int snd_hdspm_create_pcm(struct snd_card *card,
1007                                 struct hdspm *hdspm);
1008
1009 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1010 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1011 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1012 static int hdspm_autosync_ref(struct hdspm *hdspm);
1013 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1014 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1015 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1016 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1017                             struct snd_pcm_substream *substream,
1018                              unsigned int reg, int channels);
1019
1020 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1021 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1022 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1023 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1024
1025 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1026 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1027 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1028
1029
1030
1031 static inline int HDSPM_bit2freq(int n)
1032 {
1033         static const int bit2freq_tab[] = {
1034                 0, 32000, 44100, 48000, 64000, 88200,
1035                 96000, 128000, 176400, 192000 };
1036         if (n < 1 || n > 9)
1037                 return 0;
1038         return bit2freq_tab[n];
1039 }
1040
1041 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1042 {
1043         return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1044 }
1045
1046
1047 /* Write/read to/from HDSPM with Adresses in Bytes
1048    not words but only 32Bit writes are allowed */
1049
1050 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1051                                unsigned int val)
1052 {
1053         writel(val, hdspm->iobase + reg);
1054 }
1055
1056 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1057 {
1058         return readl(hdspm->iobase + reg);
1059 }
1060
1061 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1062    mixer is write only on hardware so we have to cache him for read
1063    each fader is a u32, but uses only the first 16 bit */
1064
1065 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1066                                      unsigned int in)
1067 {
1068         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1069                 return 0;
1070
1071         return hdspm->mixer->ch[chan].in[in];
1072 }
1073
1074 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1075                                      unsigned int pb)
1076 {
1077         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1078                 return 0;
1079         return hdspm->mixer->ch[chan].pb[pb];
1080 }
1081
1082 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1083                                       unsigned int in, unsigned short data)
1084 {
1085         if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1086                 return -1;
1087
1088         hdspm_write(hdspm,
1089                     HDSPM_MADI_mixerBase +
1090                     ((in + 128 * chan) * sizeof(u32)),
1091                     (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1092         return 0;
1093 }
1094
1095 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1096                                       unsigned int pb, unsigned short data)
1097 {
1098         if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1099                 return -1;
1100
1101         hdspm_write(hdspm,
1102                     HDSPM_MADI_mixerBase +
1103                     ((64 + pb + 128 * chan) * sizeof(u32)),
1104                     (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1105         return 0;
1106 }
1107
1108
1109 /* enable DMA for specific channels, now available for DSP-MADI */
1110 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1111 {
1112         hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1113 }
1114
1115 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1116 {
1117         hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1118 }
1119
1120 /* check if same process is writing and reading */
1121 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1122 {
1123         unsigned long flags;
1124         int ret = 1;
1125
1126         spin_lock_irqsave(&hdspm->lock, flags);
1127         if ((hdspm->playback_pid != hdspm->capture_pid) &&
1128             (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1129                 ret = 0;
1130         }
1131         spin_unlock_irqrestore(&hdspm->lock, flags);
1132         return ret;
1133 }
1134
1135 /* round arbitary sample rates to commonly known rates */
1136 static int hdspm_round_frequency(int rate)
1137 {
1138         if (rate < 38050)
1139                 return 32000;
1140         if (rate < 46008)
1141                 return 44100;
1142         else
1143                 return 48000;
1144 }
1145
1146 /* QS and DS rates normally can not be detected
1147  * automatically by the card. Only exception is MADI
1148  * in 96k frame mode.
1149  *
1150  * So if we read SS values (32 .. 48k), check for
1151  * user-provided DS/QS bits in the control register
1152  * and multiply the base frequency accordingly.
1153  */
1154 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1155 {
1156         if (rate <= 48000) {
1157                 if (hdspm->control_register & HDSPM_QuadSpeed)
1158                         return rate * 4;
1159                 else if (hdspm->control_register &
1160                                 HDSPM_DoubleSpeed)
1161                         return rate * 2;
1162         };
1163         return rate;
1164 }
1165
1166 /* check for external sample rate, returns the sample rate in Hz*/
1167 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1168 {
1169         unsigned int status, status2, timecode;
1170         int syncref, rate = 0, rate_bits;
1171
1172         switch (hdspm->io_type) {
1173         case AES32:
1174                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1175                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1176                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
1177
1178                 syncref = hdspm_autosync_ref(hdspm);
1179
1180                 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD &&
1181                                 status & HDSPM_AES32_wcLock)
1182                         return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF);
1183
1184                 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 &&
1185                                 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 &&
1186                                 status2 & (HDSPM_LockAES >>
1187                                 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)))
1188                         return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF);
1189                 return 0;
1190                 break;
1191
1192         case MADIface:
1193                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1194
1195                 if (!(status & HDSPM_madiLock)) {
1196                         rate = 0;  /* no lock */
1197                 } else {
1198                         switch (status & (HDSPM_status1_freqMask)) {
1199                         case HDSPM_status1_F_0*1:
1200                                 rate = 32000; break;
1201                         case HDSPM_status1_F_0*2:
1202                                 rate = 44100; break;
1203                         case HDSPM_status1_F_0*3:
1204                                 rate = 48000; break;
1205                         case HDSPM_status1_F_0*4:
1206                                 rate = 64000; break;
1207                         case HDSPM_status1_F_0*5:
1208                                 rate = 88200; break;
1209                         case HDSPM_status1_F_0*6:
1210                                 rate = 96000; break;
1211                         case HDSPM_status1_F_0*7:
1212                                 rate = 128000; break;
1213                         case HDSPM_status1_F_0*8:
1214                                 rate = 176400; break;
1215                         case HDSPM_status1_F_0*9:
1216                                 rate = 192000; break;
1217                         default:
1218                                 rate = 0; break;
1219                         }
1220                 }
1221
1222                 break;
1223
1224         case MADI:
1225         case AIO:
1226         case RayDAT:
1227                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1228                 status = hdspm_read(hdspm, HDSPM_statusRegister);
1229                 rate = 0;
1230
1231                 /* if wordclock has synced freq and wordclock is valid */
1232                 if ((status2 & HDSPM_wcLock) != 0 &&
1233                                 (status2 & HDSPM_SelSyncRef0) == 0) {
1234
1235                         rate_bits = status2 & HDSPM_wcFreqMask;
1236
1237
1238                         switch (rate_bits) {
1239                         case HDSPM_wcFreq32:
1240                                 rate = 32000;
1241                                 break;
1242                         case HDSPM_wcFreq44_1:
1243                                 rate = 44100;
1244                                 break;
1245                         case HDSPM_wcFreq48:
1246                                 rate = 48000;
1247                                 break;
1248                         case HDSPM_wcFreq64:
1249                                 rate = 64000;
1250                                 break;
1251                         case HDSPM_wcFreq88_2:
1252                                 rate = 88200;
1253                                 break;
1254                         case HDSPM_wcFreq96:
1255                                 rate = 96000;
1256                                 break;
1257                         case HDSPM_wcFreq128:
1258                                 rate = 128000;
1259                                 break;
1260                         case HDSPM_wcFreq176_4:
1261                                 rate = 176400;
1262                                 break;
1263                         case HDSPM_wcFreq192:
1264                                 rate = 192000;
1265                                 break;
1266                         default:
1267                                 rate = 0;
1268                                 break;
1269                         }
1270                 }
1271
1272                 /* if rate detected and Syncref is Word than have it,
1273                  * word has priority to MADI
1274                  */
1275                 if (rate != 0 &&
1276                 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1277                         return hdspm_rate_multiplier(hdspm, rate);
1278
1279                 /* maybe a madi input (which is taken if sel sync is madi) */
1280                 if (status & HDSPM_madiLock) {
1281                         rate_bits = status & HDSPM_madiFreqMask;
1282
1283                         switch (rate_bits) {
1284                         case HDSPM_madiFreq32:
1285                                 rate = 32000;
1286                                 break;
1287                         case HDSPM_madiFreq44_1:
1288                                 rate = 44100;
1289                                 break;
1290                         case HDSPM_madiFreq48:
1291                                 rate = 48000;
1292                                 break;
1293                         case HDSPM_madiFreq64:
1294                                 rate = 64000;
1295                                 break;
1296                         case HDSPM_madiFreq88_2:
1297                                 rate = 88200;
1298                                 break;
1299                         case HDSPM_madiFreq96:
1300                                 rate = 96000;
1301                                 break;
1302                         case HDSPM_madiFreq128:
1303                                 rate = 128000;
1304                                 break;
1305                         case HDSPM_madiFreq176_4:
1306                                 rate = 176400;
1307                                 break;
1308                         case HDSPM_madiFreq192:
1309                                 rate = 192000;
1310                                 break;
1311                         default:
1312                                 rate = 0;
1313                                 break;
1314                         }
1315
1316                 } /* endif HDSPM_madiLock */
1317
1318                 /* check sample rate from TCO or SYNC_IN */
1319                 {
1320                         bool is_valid_input = 0;
1321                         bool has_sync = 0;
1322
1323                         syncref = hdspm_autosync_ref(hdspm);
1324                         if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1325                                 is_valid_input = 1;
1326                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1327                                         hdspm_tco_sync_check(hdspm));
1328                         } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1329                                 is_valid_input = 1;
1330                                 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1331                                         hdspm_sync_in_sync_check(hdspm));
1332                         }
1333
1334                         if (is_valid_input && has_sync) {
1335                                 rate = hdspm_round_frequency(
1336                                         hdspm_get_pll_freq(hdspm));
1337                         }
1338                 }
1339
1340                 rate = hdspm_rate_multiplier(hdspm, rate);
1341
1342                 break;
1343         }
1344
1345         return rate;
1346 }
1347
1348 /* return latency in samples per period */
1349 static int hdspm_get_latency(struct hdspm *hdspm)
1350 {
1351         int n;
1352
1353         n = hdspm_decode_latency(hdspm->control_register);
1354
1355         /* Special case for new RME cards with 32 samples period size.
1356          * The three latency bits in the control register
1357          * (HDSP_LatencyMask) encode latency values of 64 samples as
1358          * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1359          * denotes 8192 samples, but on new cards like RayDAT or AIO,
1360          * it corresponds to 32 samples.
1361          */
1362         if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1363                 n = -1;
1364
1365         return 1 << (n + 6);
1366 }
1367
1368 /* Latency function */
1369 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1370 {
1371         hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1372 }
1373
1374
1375 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1376 {
1377         int position;
1378
1379         position = hdspm_read(hdspm, HDSPM_statusRegister);
1380
1381         switch (hdspm->io_type) {
1382         case RayDAT:
1383         case AIO:
1384                 position &= HDSPM_BufferPositionMask;
1385                 position /= 4; /* Bytes per sample */
1386                 break;
1387         default:
1388                 position = (position & HDSPM_BufferID) ?
1389                         (hdspm->period_bytes / 4) : 0;
1390         }
1391
1392         return position;
1393 }
1394
1395
1396 static inline void hdspm_start_audio(struct hdspm * s)
1397 {
1398         s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1399         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1400 }
1401
1402 static inline void hdspm_stop_audio(struct hdspm * s)
1403 {
1404         s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1405         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1406 }
1407
1408 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1409 static void hdspm_silence_playback(struct hdspm *hdspm)
1410 {
1411         int i;
1412         int n = hdspm->period_bytes;
1413         void *buf = hdspm->playback_buffer;
1414
1415         if (buf == NULL)
1416                 return;
1417
1418         for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1419                 memset(buf, 0, n);
1420                 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1421         }
1422 }
1423
1424 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1425 {
1426         int n;
1427
1428         spin_lock_irq(&s->lock);
1429
1430         if (32 == frames) {
1431                 /* Special case for new RME cards like RayDAT/AIO which
1432                  * support period sizes of 32 samples. Since latency is
1433                  * encoded in the three bits of HDSP_LatencyMask, we can only
1434                  * have values from 0 .. 7. While 0 still means 64 samples and
1435                  * 6 represents 4096 samples on all cards, 7 represents 8192
1436                  * on older cards and 32 samples on new cards.
1437                  *
1438                  * In other words, period size in samples is calculated by
1439                  * 2^(n+6) with n ranging from 0 .. 7.
1440                  */
1441                 n = 7;
1442         } else {
1443                 frames >>= 7;
1444                 n = 0;
1445                 while (frames) {
1446                         n++;
1447                         frames >>= 1;
1448                 }
1449         }
1450
1451         s->control_register &= ~HDSPM_LatencyMask;
1452         s->control_register |= hdspm_encode_latency(n);
1453
1454         hdspm_write(s, HDSPM_controlRegister, s->control_register);
1455
1456         hdspm_compute_period_size(s);
1457
1458         spin_unlock_irq(&s->lock);
1459
1460         return 0;
1461 }
1462
1463 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1464 {
1465         u64 freq_const;
1466
1467         if (period == 0)
1468                 return 0;
1469
1470         switch (hdspm->io_type) {
1471         case MADI:
1472         case AES32:
1473                 freq_const = 110069313433624ULL;
1474                 break;
1475         case RayDAT:
1476         case AIO:
1477                 freq_const = 104857600000000ULL;
1478                 break;
1479         case MADIface:
1480                 freq_const = 131072000000000ULL;
1481                 break;
1482         default:
1483                 snd_BUG();
1484                 return 0;
1485         }
1486
1487         return div_u64(freq_const, period);
1488 }
1489
1490
1491 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1492 {
1493         u64 n;
1494
1495         if (rate >= 112000)
1496                 rate /= 4;
1497         else if (rate >= 56000)
1498                 rate /= 2;
1499
1500         switch (hdspm->io_type) {
1501         case MADIface:
1502                 n = 131072000000000ULL;  /* 125 MHz */
1503                 break;
1504         case MADI:
1505         case AES32:
1506                 n = 110069313433624ULL;  /* 105 MHz */
1507                 break;
1508         case RayDAT:
1509         case AIO:
1510                 n = 104857600000000ULL;  /* 100 MHz */
1511                 break;
1512         default:
1513                 snd_BUG();
1514                 return;
1515         }
1516
1517         n = div_u64(n, rate);
1518         /* n should be less than 2^32 for being written to FREQ register */
1519         snd_BUG_ON(n >> 32);
1520         hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1521 }
1522
1523 /* dummy set rate lets see what happens */
1524 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1525 {
1526         int current_rate;
1527         int rate_bits;
1528         int not_set = 0;
1529         int current_speed, target_speed;
1530
1531         /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1532            it (e.g. during module initialization).
1533          */
1534
1535         if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1536
1537                 /* SLAVE --- */
1538                 if (called_internally) {
1539
1540                         /* request from ctl or card initialization
1541                            just make a warning an remember setting
1542                            for future master mode switching */
1543
1544                         snd_printk(KERN_WARNING "HDSPM: "
1545                                    "Warning: device is not running "
1546                                    "as a clock master.\n");
1547                         not_set = 1;
1548                 } else {
1549
1550                         /* hw_param request while in AutoSync mode */
1551                         int external_freq =
1552                             hdspm_external_sample_rate(hdspm);
1553
1554                         if (hdspm_autosync_ref(hdspm) ==
1555                             HDSPM_AUTOSYNC_FROM_NONE) {
1556
1557                                 snd_printk(KERN_WARNING "HDSPM: "
1558                                            "Detected no Externel Sync \n");
1559                                 not_set = 1;
1560
1561                         } else if (rate != external_freq) {
1562
1563                                 snd_printk(KERN_WARNING "HDSPM: "
1564                                            "Warning: No AutoSync source for "
1565                                            "requested rate\n");
1566                                 not_set = 1;
1567                         }
1568                 }
1569         }
1570
1571         current_rate = hdspm->system_sample_rate;
1572
1573         /* Changing between Singe, Double and Quad speed is not
1574            allowed if any substreams are open. This is because such a change
1575            causes a shift in the location of the DMA buffers and a reduction
1576            in the number of available buffers.
1577
1578            Note that a similar but essentially insoluble problem exists for
1579            externally-driven rate changes. All we can do is to flag rate
1580            changes in the read/write routines.
1581          */
1582
1583         if (current_rate <= 48000)
1584                 current_speed = HDSPM_SPEED_SINGLE;
1585         else if (current_rate <= 96000)
1586                 current_speed = HDSPM_SPEED_DOUBLE;
1587         else
1588                 current_speed = HDSPM_SPEED_QUAD;
1589
1590         if (rate <= 48000)
1591                 target_speed = HDSPM_SPEED_SINGLE;
1592         else if (rate <= 96000)
1593                 target_speed = HDSPM_SPEED_DOUBLE;
1594         else
1595                 target_speed = HDSPM_SPEED_QUAD;
1596
1597         switch (rate) {
1598         case 32000:
1599                 rate_bits = HDSPM_Frequency32KHz;
1600                 break;
1601         case 44100:
1602                 rate_bits = HDSPM_Frequency44_1KHz;
1603                 break;
1604         case 48000:
1605                 rate_bits = HDSPM_Frequency48KHz;
1606                 break;
1607         case 64000:
1608                 rate_bits = HDSPM_Frequency64KHz;
1609                 break;
1610         case 88200:
1611                 rate_bits = HDSPM_Frequency88_2KHz;
1612                 break;
1613         case 96000:
1614                 rate_bits = HDSPM_Frequency96KHz;
1615                 break;
1616         case 128000:
1617                 rate_bits = HDSPM_Frequency128KHz;
1618                 break;
1619         case 176400:
1620                 rate_bits = HDSPM_Frequency176_4KHz;
1621                 break;
1622         case 192000:
1623                 rate_bits = HDSPM_Frequency192KHz;
1624                 break;
1625         default:
1626                 return -EINVAL;
1627         }
1628
1629         if (current_speed != target_speed
1630             && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1631                 snd_printk
1632                     (KERN_ERR "HDSPM: "
1633                      "cannot change from %s speed to %s speed mode "
1634                      "(capture PID = %d, playback PID = %d)\n",
1635                      hdspm_speed_names[current_speed],
1636                      hdspm_speed_names[target_speed],
1637                      hdspm->capture_pid, hdspm->playback_pid);
1638                 return -EBUSY;
1639         }
1640
1641         hdspm->control_register &= ~HDSPM_FrequencyMask;
1642         hdspm->control_register |= rate_bits;
1643         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1644
1645         /* For AES32, need to set DDS value in FREQ register
1646            For MADI, also apparently */
1647         hdspm_set_dds_value(hdspm, rate);
1648
1649         if (AES32 == hdspm->io_type && rate != current_rate)
1650                 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1651
1652         hdspm->system_sample_rate = rate;
1653
1654         if (rate <= 48000) {
1655                 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1656                 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1657                 hdspm->max_channels_in = hdspm->ss_in_channels;
1658                 hdspm->max_channels_out = hdspm->ss_out_channels;
1659                 hdspm->port_names_in = hdspm->port_names_in_ss;
1660                 hdspm->port_names_out = hdspm->port_names_out_ss;
1661         } else if (rate <= 96000) {
1662                 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1663                 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1664                 hdspm->max_channels_in = hdspm->ds_in_channels;
1665                 hdspm->max_channels_out = hdspm->ds_out_channels;
1666                 hdspm->port_names_in = hdspm->port_names_in_ds;
1667                 hdspm->port_names_out = hdspm->port_names_out_ds;
1668         } else {
1669                 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1670                 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1671                 hdspm->max_channels_in = hdspm->qs_in_channels;
1672                 hdspm->max_channels_out = hdspm->qs_out_channels;
1673                 hdspm->port_names_in = hdspm->port_names_in_qs;
1674                 hdspm->port_names_out = hdspm->port_names_out_qs;
1675         }
1676
1677         if (not_set != 0)
1678                 return -1;
1679
1680         return 0;
1681 }
1682
1683 /* mainly for init to 0 on load */
1684 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1685 {
1686         int i, j;
1687         unsigned int gain;
1688
1689         if (sgain > UNITY_GAIN)
1690                 gain = UNITY_GAIN;
1691         else if (sgain < 0)
1692                 gain = 0;
1693         else
1694                 gain = sgain;
1695
1696         for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1697                 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1698                         hdspm_write_in_gain(hdspm, i, j, gain);
1699                         hdspm_write_pb_gain(hdspm, i, j, gain);
1700                 }
1701 }
1702
1703 /*----------------------------------------------------------------------------
1704    MIDI
1705   ----------------------------------------------------------------------------*/
1706
1707 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1708                                                       int id)
1709 {
1710         /* the hardware already does the relevant bit-mask with 0xff */
1711         return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1712 }
1713
1714 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1715                                               int val)
1716 {
1717         /* the hardware already does the relevant bit-mask with 0xff */
1718         return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1719 }
1720
1721 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1722 {
1723         return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1724 }
1725
1726 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1727 {
1728         int fifo_bytes_used;
1729
1730         fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1731
1732         if (fifo_bytes_used < 128)
1733                 return  128 - fifo_bytes_used;
1734         else
1735                 return 0;
1736 }
1737
1738 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1739 {
1740         while (snd_hdspm_midi_input_available (hdspm, id))
1741                 snd_hdspm_midi_read_byte (hdspm, id);
1742 }
1743
1744 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1745 {
1746         unsigned long flags;
1747         int n_pending;
1748         int to_write;
1749         int i;
1750         unsigned char buf[128];
1751
1752         /* Output is not interrupt driven */
1753
1754         spin_lock_irqsave (&hmidi->lock, flags);
1755         if (hmidi->output &&
1756             !snd_rawmidi_transmit_empty (hmidi->output)) {
1757                 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1758                                                             hmidi->id);
1759                 if (n_pending > 0) {
1760                         if (n_pending > (int)sizeof (buf))
1761                                 n_pending = sizeof (buf);
1762
1763                         to_write = snd_rawmidi_transmit (hmidi->output, buf,
1764                                                          n_pending);
1765                         if (to_write > 0) {
1766                                 for (i = 0; i < to_write; ++i)
1767                                         snd_hdspm_midi_write_byte (hmidi->hdspm,
1768                                                                    hmidi->id,
1769                                                                    buf[i]);
1770                         }
1771                 }
1772         }
1773         spin_unlock_irqrestore (&hmidi->lock, flags);
1774         return 0;
1775 }
1776
1777 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1778 {
1779         unsigned char buf[128]; /* this buffer is designed to match the MIDI
1780                                  * input FIFO size
1781                                  */
1782         unsigned long flags;
1783         int n_pending;
1784         int i;
1785
1786         spin_lock_irqsave (&hmidi->lock, flags);
1787         n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1788         if (n_pending > 0) {
1789                 if (hmidi->input) {
1790                         if (n_pending > (int)sizeof (buf))
1791                                 n_pending = sizeof (buf);
1792                         for (i = 0; i < n_pending; ++i)
1793                                 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1794                                                                    hmidi->id);
1795                         if (n_pending)
1796                                 snd_rawmidi_receive (hmidi->input, buf,
1797                                                      n_pending);
1798                 } else {
1799                         /* flush the MIDI input FIFO */
1800                         while (n_pending--)
1801                                 snd_hdspm_midi_read_byte (hmidi->hdspm,
1802                                                           hmidi->id);
1803                 }
1804         }
1805         hmidi->pending = 0;
1806         spin_unlock_irqrestore(&hmidi->lock, flags);
1807
1808         spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1809         hmidi->hdspm->control_register |= hmidi->ie;
1810         hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1811                     hmidi->hdspm->control_register);
1812         spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1813
1814         return snd_hdspm_midi_output_write (hmidi);
1815 }
1816
1817 static void
1818 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1819 {
1820         struct hdspm *hdspm;
1821         struct hdspm_midi *hmidi;
1822         unsigned long flags;
1823
1824         hmidi = substream->rmidi->private_data;
1825         hdspm = hmidi->hdspm;
1826
1827         spin_lock_irqsave (&hdspm->lock, flags);
1828         if (up) {
1829                 if (!(hdspm->control_register & hmidi->ie)) {
1830                         snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1831                         hdspm->control_register |= hmidi->ie;
1832                 }
1833         } else {
1834                 hdspm->control_register &= ~hmidi->ie;
1835         }
1836
1837         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1838         spin_unlock_irqrestore (&hdspm->lock, flags);
1839 }
1840
1841 static void snd_hdspm_midi_output_timer(unsigned long data)
1842 {
1843         struct hdspm_midi *hmidi = (struct hdspm_midi *) data;
1844         unsigned long flags;
1845
1846         snd_hdspm_midi_output_write(hmidi);
1847         spin_lock_irqsave (&hmidi->lock, flags);
1848
1849         /* this does not bump hmidi->istimer, because the
1850            kernel automatically removed the timer when it
1851            expired, and we are now adding it back, thus
1852            leaving istimer wherever it was set before.
1853         */
1854
1855         if (hmidi->istimer) {
1856                 hmidi->timer.expires = 1 + jiffies;
1857                 add_timer(&hmidi->timer);
1858         }
1859
1860         spin_unlock_irqrestore (&hmidi->lock, flags);
1861 }
1862
1863 static void
1864 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1865 {
1866         struct hdspm_midi *hmidi;
1867         unsigned long flags;
1868
1869         hmidi = substream->rmidi->private_data;
1870         spin_lock_irqsave (&hmidi->lock, flags);
1871         if (up) {
1872                 if (!hmidi->istimer) {
1873                         init_timer(&hmidi->timer);
1874                         hmidi->timer.function = snd_hdspm_midi_output_timer;
1875                         hmidi->timer.data = (unsigned long) hmidi;
1876                         hmidi->timer.expires = 1 + jiffies;
1877                         add_timer(&hmidi->timer);
1878                         hmidi->istimer++;
1879                 }
1880         } else {
1881                 if (hmidi->istimer && --hmidi->istimer <= 0)
1882                         del_timer (&hmidi->timer);
1883         }
1884         spin_unlock_irqrestore (&hmidi->lock, flags);
1885         if (up)
1886                 snd_hdspm_midi_output_write(hmidi);
1887 }
1888
1889 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1890 {
1891         struct hdspm_midi *hmidi;
1892
1893         hmidi = substream->rmidi->private_data;
1894         spin_lock_irq (&hmidi->lock);
1895         snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1896         hmidi->input = substream;
1897         spin_unlock_irq (&hmidi->lock);
1898
1899         return 0;
1900 }
1901
1902 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
1903 {
1904         struct hdspm_midi *hmidi;
1905
1906         hmidi = substream->rmidi->private_data;
1907         spin_lock_irq (&hmidi->lock);
1908         hmidi->output = substream;
1909         spin_unlock_irq (&hmidi->lock);
1910
1911         return 0;
1912 }
1913
1914 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
1915 {
1916         struct hdspm_midi *hmidi;
1917
1918         snd_hdspm_midi_input_trigger (substream, 0);
1919
1920         hmidi = substream->rmidi->private_data;
1921         spin_lock_irq (&hmidi->lock);
1922         hmidi->input = NULL;
1923         spin_unlock_irq (&hmidi->lock);
1924
1925         return 0;
1926 }
1927
1928 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
1929 {
1930         struct hdspm_midi *hmidi;
1931
1932         snd_hdspm_midi_output_trigger (substream, 0);
1933
1934         hmidi = substream->rmidi->private_data;
1935         spin_lock_irq (&hmidi->lock);
1936         hmidi->output = NULL;
1937         spin_unlock_irq (&hmidi->lock);
1938
1939         return 0;
1940 }
1941
1942 static struct snd_rawmidi_ops snd_hdspm_midi_output =
1943 {
1944         .open =         snd_hdspm_midi_output_open,
1945         .close =        snd_hdspm_midi_output_close,
1946         .trigger =      snd_hdspm_midi_output_trigger,
1947 };
1948
1949 static struct snd_rawmidi_ops snd_hdspm_midi_input =
1950 {
1951         .open =         snd_hdspm_midi_input_open,
1952         .close =        snd_hdspm_midi_input_close,
1953         .trigger =      snd_hdspm_midi_input_trigger,
1954 };
1955
1956 static int snd_hdspm_create_midi(struct snd_card *card,
1957                                  struct hdspm *hdspm, int id)
1958 {
1959         int err;
1960         char buf[32];
1961
1962         hdspm->midi[id].id = id;
1963         hdspm->midi[id].hdspm = hdspm;
1964         spin_lock_init (&hdspm->midi[id].lock);
1965
1966         if (0 == id) {
1967                 if (MADIface == hdspm->io_type) {
1968                         /* MIDI-over-MADI on HDSPe MADIface */
1969                         hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
1970                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
1971                         hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
1972                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
1973                         hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
1974                         hdspm->midi[0].irq = HDSPM_midi2IRQPending;
1975                 } else {
1976                         hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
1977                         hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
1978                         hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
1979                         hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
1980                         hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
1981                         hdspm->midi[0].irq = HDSPM_midi0IRQPending;
1982                 }
1983         } else if (1 == id) {
1984                 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
1985                 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
1986                 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
1987                 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
1988                 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
1989                 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
1990         } else if ((2 == id) && (MADI == hdspm->io_type)) {
1991                 /* MIDI-over-MADI on HDSPe MADI */
1992                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
1993                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
1994                 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
1995                 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
1996                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
1997                 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
1998         } else if (2 == id) {
1999                 /* TCO MTC, read only */
2000                 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2001                 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2002                 hdspm->midi[2].dataOut = -1;
2003                 hdspm->midi[2].statusOut = -1;
2004                 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2005                 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2006         } else if (3 == id) {
2007                 /* TCO MTC on HDSPe MADI */
2008                 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2009                 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2010                 hdspm->midi[3].dataOut = -1;
2011                 hdspm->midi[3].statusOut = -1;
2012                 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2013                 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2014         }
2015
2016         if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2017                                         (MADIface == hdspm->io_type)))) {
2018                 if ((id == 0) && (MADIface == hdspm->io_type)) {
2019                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2020                 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2021                         sprintf(buf, "%s MIDIoverMADI", card->shortname);
2022                 } else {
2023                         sprintf(buf, "%s MIDI %d", card->shortname, id+1);
2024                 }
2025                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2026                                 &hdspm->midi[id].rmidi);
2027                 if (err < 0)
2028                         return err;
2029
2030                 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d",
2031                                 card->id, id+1);
2032                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2033
2034                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2035                                 SNDRV_RAWMIDI_STREAM_OUTPUT,
2036                                 &snd_hdspm_midi_output);
2037                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2038                                 SNDRV_RAWMIDI_STREAM_INPUT,
2039                                 &snd_hdspm_midi_input);
2040
2041                 hdspm->midi[id].rmidi->info_flags |=
2042                         SNDRV_RAWMIDI_INFO_OUTPUT |
2043                         SNDRV_RAWMIDI_INFO_INPUT |
2044                         SNDRV_RAWMIDI_INFO_DUPLEX;
2045         } else {
2046                 /* TCO MTC, read only */
2047                 sprintf(buf, "%s MTC %d", card->shortname, id+1);
2048                 err = snd_rawmidi_new(card, buf, id, 1, 1,
2049                                 &hdspm->midi[id].rmidi);
2050                 if (err < 0)
2051                         return err;
2052
2053                 sprintf(hdspm->midi[id].rmidi->name,
2054                                 "%s MTC %d", card->id, id+1);
2055                 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2056
2057                 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2058                                 SNDRV_RAWMIDI_STREAM_INPUT,
2059                                 &snd_hdspm_midi_input);
2060
2061                 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2062         }
2063
2064         return 0;
2065 }
2066
2067
2068 static void hdspm_midi_tasklet(unsigned long arg)
2069 {
2070         struct hdspm *hdspm = (struct hdspm *)arg;
2071         int i = 0;
2072
2073         while (i < hdspm->midiPorts) {
2074                 if (hdspm->midi[i].pending)
2075                         snd_hdspm_midi_input_read(&hdspm->midi[i]);
2076
2077                 i++;
2078         }
2079 }
2080
2081
2082 /*-----------------------------------------------------------------------------
2083   Status Interface
2084   ----------------------------------------------------------------------------*/
2085
2086 /* get the system sample rate which is set */
2087
2088
2089 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2090 {
2091         unsigned int period, rate;
2092
2093         period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2094         rate = hdspm_calc_dds_value(hdspm, period);
2095
2096         return rate;
2097 }
2098
2099 /**
2100  * Calculate the real sample rate from the
2101  * current DDS value.
2102  **/
2103 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2104 {
2105         unsigned int rate;
2106
2107         rate = hdspm_get_pll_freq(hdspm);
2108
2109         if (rate > 207000) {
2110                 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2111                 if (0 == hdspm_system_clock_mode(hdspm)) {
2112                         /* master mode, return internal sample rate */
2113                         rate = hdspm->system_sample_rate;
2114                 } else {
2115                         /* slave mode, return external sample rate */
2116                         rate = hdspm_external_sample_rate(hdspm);
2117                 }
2118         }
2119
2120         return rate;
2121 }
2122
2123
2124 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2125 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2126         .name = xname, \
2127         .index = xindex, \
2128         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2129                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2130         .info = snd_hdspm_info_system_sample_rate, \
2131         .put = snd_hdspm_put_system_sample_rate, \
2132         .get = snd_hdspm_get_system_sample_rate \
2133 }
2134
2135 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2136                                              struct snd_ctl_elem_info *uinfo)
2137 {
2138         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2139         uinfo->count = 1;
2140         uinfo->value.integer.min = 27000;
2141         uinfo->value.integer.max = 207000;
2142         uinfo->value.integer.step = 1;
2143         return 0;
2144 }
2145
2146
2147 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2148                                             struct snd_ctl_elem_value *
2149                                             ucontrol)
2150 {
2151         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2152
2153         ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2154         return 0;
2155 }
2156
2157 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2158                                             struct snd_ctl_elem_value *
2159                                             ucontrol)
2160 {
2161         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2162
2163         hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]);
2164         return 0;
2165 }
2166
2167
2168 /**
2169  * Returns the WordClock sample rate class for the given card.
2170  **/
2171 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2172 {
2173         int status;
2174
2175         switch (hdspm->io_type) {
2176         case RayDAT:
2177         case AIO:
2178                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2179                 return (status >> 16) & 0xF;
2180                 break;
2181         case AES32:
2182                 status = hdspm_read(hdspm, HDSPM_statusRegister);
2183                 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2184         default:
2185                 break;
2186         }
2187
2188
2189         return 0;
2190 }
2191
2192
2193 /**
2194  * Returns the TCO sample rate class for the given card.
2195  **/
2196 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2197 {
2198         int status;
2199
2200         if (hdspm->tco) {
2201                 switch (hdspm->io_type) {
2202                 case RayDAT:
2203                 case AIO:
2204                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2205                         return (status >> 20) & 0xF;
2206                         break;
2207                 case AES32:
2208                         status = hdspm_read(hdspm, HDSPM_statusRegister);
2209                         return (status >> 1) & 0xF;
2210                 default:
2211                         break;
2212                 }
2213         }
2214
2215         return 0;
2216 }
2217
2218
2219 /**
2220  * Returns the SYNC_IN sample rate class for the given card.
2221  **/
2222 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2223 {
2224         int status;
2225
2226         if (hdspm->tco) {
2227                 switch (hdspm->io_type) {
2228                 case RayDAT:
2229                 case AIO:
2230                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2231                         return (status >> 12) & 0xF;
2232                         break;
2233                 default:
2234                         break;
2235                 }
2236         }
2237
2238         return 0;
2239 }
2240
2241 /**
2242  * Returns the AES sample rate class for the given card.
2243  **/
2244 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2245 {
2246         int timecode;
2247
2248         switch (hdspm->io_type) {
2249         case AES32:
2250                 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2251                 return (timecode >> (4*index)) & 0xF;
2252                 break;
2253         default:
2254                 break;
2255         }
2256         return 0;
2257 }
2258
2259 /**
2260  * Returns the sample rate class for input source <idx> for
2261  * 'new style' cards like the AIO and RayDAT.
2262  **/
2263 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2264 {
2265         int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2266
2267         return (status >> (idx*4)) & 0xF;
2268 }
2269
2270 static void snd_hdspm_set_infotext(struct snd_ctl_elem_info *uinfo,
2271                 char **texts, const int count)
2272 {
2273         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2274         uinfo->count = 1;
2275         uinfo->value.enumerated.items = count;
2276         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2277                 uinfo->value.enumerated.item =
2278                         uinfo->value.enumerated.items - 1;
2279         strcpy(uinfo->value.enumerated.name,
2280                         texts[uinfo->value.enumerated.item]);
2281 }
2282
2283 #define ENUMERATED_CTL_INFO(info, texts) \
2284         snd_hdspm_set_infotext(info, texts, ARRAY_SIZE(texts))
2285
2286
2287
2288 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2289 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2290         .name = xname, \
2291         .private_value = xindex, \
2292         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2293         .info = snd_hdspm_info_autosync_sample_rate, \
2294         .get = snd_hdspm_get_autosync_sample_rate \
2295 }
2296
2297
2298 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2299                                                struct snd_ctl_elem_info *uinfo)
2300 {
2301         ENUMERATED_CTL_INFO(uinfo, texts_freq);
2302         return 0;
2303 }
2304
2305
2306 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2307                                               struct snd_ctl_elem_value *
2308                                               ucontrol)
2309 {
2310         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2311
2312         switch (hdspm->io_type) {
2313         case RayDAT:
2314                 switch (kcontrol->private_value) {
2315                 case 0:
2316                         ucontrol->value.enumerated.item[0] =
2317                                 hdspm_get_wc_sample_rate(hdspm);
2318                         break;
2319                 case 7:
2320                         ucontrol->value.enumerated.item[0] =
2321                                 hdspm_get_tco_sample_rate(hdspm);
2322                         break;
2323                 case 8:
2324                         ucontrol->value.enumerated.item[0] =
2325                                 hdspm_get_sync_in_sample_rate(hdspm);
2326                         break;
2327                 default:
2328                         ucontrol->value.enumerated.item[0] =
2329                                 hdspm_get_s1_sample_rate(hdspm,
2330                                                 kcontrol->private_value-1);
2331                 }
2332                 break;
2333
2334         case AIO:
2335                 switch (kcontrol->private_value) {
2336                 case 0: /* WC */
2337                         ucontrol->value.enumerated.item[0] =
2338                                 hdspm_get_wc_sample_rate(hdspm);
2339                         break;
2340                 case 4: /* TCO */
2341                         ucontrol->value.enumerated.item[0] =
2342                                 hdspm_get_tco_sample_rate(hdspm);
2343                         break;
2344                 case 5: /* SYNC_IN */
2345                         ucontrol->value.enumerated.item[0] =
2346                                 hdspm_get_sync_in_sample_rate(hdspm);
2347                         break;
2348                 default:
2349                         ucontrol->value.enumerated.item[0] =
2350                                 hdspm_get_s1_sample_rate(hdspm,
2351                                                 kcontrol->private_value-1);
2352                 }
2353                 break;
2354
2355         case AES32:
2356
2357                 switch (kcontrol->private_value) {
2358                 case 0: /* WC */
2359                         ucontrol->value.enumerated.item[0] =
2360                                 hdspm_get_wc_sample_rate(hdspm);
2361                         break;
2362                 case 9: /* TCO */
2363                         ucontrol->value.enumerated.item[0] =
2364                                 hdspm_get_tco_sample_rate(hdspm);
2365                         break;
2366                 case 10: /* SYNC_IN */
2367                         ucontrol->value.enumerated.item[0] =
2368                                 hdspm_get_sync_in_sample_rate(hdspm);
2369                         break;
2370                 default: /* AES1 to AES8 */
2371                         ucontrol->value.enumerated.item[0] =
2372                                 hdspm_get_s1_sample_rate(hdspm,
2373                                                 kcontrol->private_value-1);
2374                         break;
2375                 }
2376                 break;
2377
2378         case MADI:
2379         case MADIface:
2380                 {
2381                         int rate = hdspm_external_sample_rate(hdspm);
2382                         int i, selected_rate = 0;
2383                         for (i = 1; i < 10; i++)
2384                                 if (HDSPM_bit2freq(i) == rate) {
2385                                         selected_rate = i;
2386                                         break;
2387                                 }
2388                         ucontrol->value.enumerated.item[0] = selected_rate;
2389                 }
2390                 break;
2391
2392         default:
2393                 break;
2394         }
2395
2396         return 0;
2397 }
2398
2399
2400 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2401 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2402         .name = xname, \
2403         .index = xindex, \
2404         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2405                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2406         .info = snd_hdspm_info_system_clock_mode, \
2407         .get = snd_hdspm_get_system_clock_mode, \
2408         .put = snd_hdspm_put_system_clock_mode, \
2409 }
2410
2411
2412 /**
2413  * Returns the system clock mode for the given card.
2414  * @returns 0 - master, 1 - slave
2415  **/
2416 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2417 {
2418         switch (hdspm->io_type) {
2419         case AIO:
2420         case RayDAT:
2421                 if (hdspm->settings_register & HDSPM_c0Master)
2422                         return 0;
2423                 break;
2424
2425         default:
2426                 if (hdspm->control_register & HDSPM_ClockModeMaster)
2427                         return 0;
2428         }
2429
2430         return 1;
2431 }
2432
2433
2434 /**
2435  * Sets the system clock mode.
2436  * @param mode 0 - master, 1 - slave
2437  **/
2438 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2439 {
2440         hdspm_set_toggle_setting(hdspm,
2441                         (hdspm_is_raydat_or_aio(hdspm)) ?
2442                         HDSPM_c0Master : HDSPM_ClockModeMaster,
2443                         (0 == mode));
2444 }
2445
2446
2447 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2448                                             struct snd_ctl_elem_info *uinfo)
2449 {
2450         static char *texts[] = { "Master", "AutoSync" };
2451         ENUMERATED_CTL_INFO(uinfo, texts);
2452         return 0;
2453 }
2454
2455 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2456                                            struct snd_ctl_elem_value *ucontrol)
2457 {
2458         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2459
2460         ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2461         return 0;
2462 }
2463
2464 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2465                                            struct snd_ctl_elem_value *ucontrol)
2466 {
2467         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2468         int val;
2469
2470         if (!snd_hdspm_use_is_exclusive(hdspm))
2471                 return -EBUSY;
2472
2473         val = ucontrol->value.enumerated.item[0];
2474         if (val < 0)
2475                 val = 0;
2476         else if (val > 1)
2477                 val = 1;
2478
2479         hdspm_set_system_clock_mode(hdspm, val);
2480
2481         return 0;
2482 }
2483
2484
2485 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2486 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2487         .name = xname, \
2488         .index = xindex, \
2489         .info = snd_hdspm_info_clock_source, \
2490         .get = snd_hdspm_get_clock_source, \
2491         .put = snd_hdspm_put_clock_source \
2492 }
2493
2494
2495 static int hdspm_clock_source(struct hdspm * hdspm)
2496 {
2497         switch (hdspm->system_sample_rate) {
2498         case 32000: return 0;
2499         case 44100: return 1;
2500         case 48000: return 2;
2501         case 64000: return 3;
2502         case 88200: return 4;
2503         case 96000: return 5;
2504         case 128000: return 6;
2505         case 176400: return 7;
2506         case 192000: return 8;
2507         }
2508
2509         return -1;
2510 }
2511
2512 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2513 {
2514         int rate;
2515         switch (mode) {
2516         case 0:
2517                 rate = 32000; break;
2518         case 1:
2519                 rate = 44100; break;
2520         case 2:
2521                 rate = 48000; break;
2522         case 3:
2523                 rate = 64000; break;
2524         case 4:
2525                 rate = 88200; break;
2526         case 5:
2527                 rate = 96000; break;
2528         case 6:
2529                 rate = 128000; break;
2530         case 7:
2531                 rate = 176400; break;
2532         case 8:
2533                 rate = 192000; break;
2534         default:
2535                 rate = 48000;
2536         }
2537         hdspm_set_rate(hdspm, rate, 1);
2538         return 0;
2539 }
2540
2541 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2542                                        struct snd_ctl_elem_info *uinfo)
2543 {
2544         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2545         uinfo->count = 1;
2546         uinfo->value.enumerated.items = 9;
2547
2548         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2549                 uinfo->value.enumerated.item =
2550                     uinfo->value.enumerated.items - 1;
2551
2552         strcpy(uinfo->value.enumerated.name,
2553                texts_freq[uinfo->value.enumerated.item+1]);
2554
2555         return 0;
2556 }
2557
2558 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2559                                       struct snd_ctl_elem_value *ucontrol)
2560 {
2561         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2562
2563         ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2564         return 0;
2565 }
2566
2567 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2568                                       struct snd_ctl_elem_value *ucontrol)
2569 {
2570         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2571         int change;
2572         int val;
2573
2574         if (!snd_hdspm_use_is_exclusive(hdspm))
2575                 return -EBUSY;
2576         val = ucontrol->value.enumerated.item[0];
2577         if (val < 0)
2578                 val = 0;
2579         if (val > 9)
2580                 val = 9;
2581         spin_lock_irq(&hdspm->lock);
2582         if (val != hdspm_clock_source(hdspm))
2583                 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2584         else
2585                 change = 0;
2586         spin_unlock_irq(&hdspm->lock);
2587         return change;
2588 }
2589
2590
2591 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2592 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2593         .name = xname, \
2594         .index = xindex, \
2595         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2596                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2597         .info = snd_hdspm_info_pref_sync_ref, \
2598         .get = snd_hdspm_get_pref_sync_ref, \
2599         .put = snd_hdspm_put_pref_sync_ref \
2600 }
2601
2602
2603 /**
2604  * Returns the current preferred sync reference setting.
2605  * The semantics of the return value are depending on the
2606  * card, please see the comments for clarification.
2607  **/
2608 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2609 {
2610         switch (hdspm->io_type) {
2611         case AES32:
2612                 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2613                 case 0: return 0;  /* WC */
2614                 case HDSPM_SyncRef0: return 1; /* AES 1 */
2615                 case HDSPM_SyncRef1: return 2; /* AES 2 */
2616                 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2617                 case HDSPM_SyncRef2: return 4; /* AES 4 */
2618                 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2619                 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2620                 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2621                                                     return 7; /* AES 7 */
2622                 case HDSPM_SyncRef3: return 8; /* AES 8 */
2623                 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2624                 }
2625                 break;
2626
2627         case MADI:
2628         case MADIface:
2629                 if (hdspm->tco) {
2630                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2631                         case 0: return 0;  /* WC */
2632                         case HDSPM_SyncRef0: return 1;  /* MADI */
2633                         case HDSPM_SyncRef1: return 2;  /* TCO */
2634                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2635                                              return 3;  /* SYNC_IN */
2636                         }
2637                 } else {
2638                         switch (hdspm->control_register & HDSPM_SyncRefMask) {
2639                         case 0: return 0;  /* WC */
2640                         case HDSPM_SyncRef0: return 1;  /* MADI */
2641                         case HDSPM_SyncRef1+HDSPM_SyncRef0:
2642                                              return 2;  /* SYNC_IN */
2643                         }
2644                 }
2645                 break;
2646
2647         case RayDAT:
2648                 if (hdspm->tco) {
2649                         switch ((hdspm->settings_register &
2650                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2651                         case 0: return 0;  /* WC */
2652                         case 3: return 1;  /* ADAT 1 */
2653                         case 4: return 2;  /* ADAT 2 */
2654                         case 5: return 3;  /* ADAT 3 */
2655                         case 6: return 4;  /* ADAT 4 */
2656                         case 1: return 5;  /* AES */
2657                         case 2: return 6;  /* SPDIF */
2658                         case 9: return 7;  /* TCO */
2659                         case 10: return 8; /* SYNC_IN */
2660                         }
2661                 } else {
2662                         switch ((hdspm->settings_register &
2663                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2664                         case 0: return 0;  /* WC */
2665                         case 3: return 1;  /* ADAT 1 */
2666                         case 4: return 2;  /* ADAT 2 */
2667                         case 5: return 3;  /* ADAT 3 */
2668                         case 6: return 4;  /* ADAT 4 */
2669                         case 1: return 5;  /* AES */
2670                         case 2: return 6;  /* SPDIF */
2671                         case 10: return 7; /* SYNC_IN */
2672                         }
2673                 }
2674
2675                 break;
2676
2677         case AIO:
2678                 if (hdspm->tco) {
2679                         switch ((hdspm->settings_register &
2680                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2681                         case 0: return 0;  /* WC */
2682                         case 3: return 1;  /* ADAT */
2683                         case 1: return 2;  /* AES */
2684                         case 2: return 3;  /* SPDIF */
2685                         case 9: return 4;  /* TCO */
2686                         case 10: return 5; /* SYNC_IN */
2687                         }
2688                 } else {
2689                         switch ((hdspm->settings_register &
2690                                 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2691                         case 0: return 0;  /* WC */
2692                         case 3: return 1;  /* ADAT */
2693                         case 1: return 2;  /* AES */
2694                         case 2: return 3;  /* SPDIF */
2695                         case 10: return 4; /* SYNC_IN */
2696                         }
2697                 }
2698
2699                 break;
2700         }
2701
2702         return -1;
2703 }
2704
2705
2706 /**
2707  * Set the preferred sync reference to <pref>. The semantics
2708  * of <pref> are depending on the card type, see the comments
2709  * for clarification.
2710  **/
2711 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2712 {
2713         int p = 0;
2714
2715         switch (hdspm->io_type) {
2716         case AES32:
2717                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2718                 switch (pref) {
2719                 case 0: /* WC  */
2720                         break;
2721                 case 1: /* AES 1 */
2722                         hdspm->control_register |= HDSPM_SyncRef0;
2723                         break;
2724                 case 2: /* AES 2 */
2725                         hdspm->control_register |= HDSPM_SyncRef1;
2726                         break;
2727                 case 3: /* AES 3 */
2728                         hdspm->control_register |=
2729                                 HDSPM_SyncRef1+HDSPM_SyncRef0;
2730                         break;
2731                 case 4: /* AES 4 */
2732                         hdspm->control_register |= HDSPM_SyncRef2;
2733                         break;
2734                 case 5: /* AES 5 */
2735                         hdspm->control_register |=
2736                                 HDSPM_SyncRef2+HDSPM_SyncRef0;
2737                         break;
2738                 case 6: /* AES 6 */
2739                         hdspm->control_register |=
2740                                 HDSPM_SyncRef2+HDSPM_SyncRef1;
2741                         break;
2742                 case 7: /* AES 7 */
2743                         hdspm->control_register |=
2744                                 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2745                         break;
2746                 case 8: /* AES 8 */
2747                         hdspm->control_register |= HDSPM_SyncRef3;
2748                         break;
2749                 case 9: /* TCO */
2750                         hdspm->control_register |=
2751                                 HDSPM_SyncRef3+HDSPM_SyncRef0;
2752                         break;
2753                 default:
2754                         return -1;
2755                 }
2756
2757                 break;
2758
2759         case MADI:
2760         case MADIface:
2761                 hdspm->control_register &= ~HDSPM_SyncRefMask;
2762                 if (hdspm->tco) {
2763                         switch (pref) {
2764                         case 0: /* WC */
2765                                 break;
2766                         case 1: /* MADI */
2767                                 hdspm->control_register |= HDSPM_SyncRef0;
2768                                 break;
2769                         case 2: /* TCO */
2770                                 hdspm->control_register |= HDSPM_SyncRef1;
2771                                 break;
2772                         case 3: /* SYNC_IN */
2773                                 hdspm->control_register |=
2774                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2775                                 break;
2776                         default:
2777                                 return -1;
2778                         }
2779                 } else {
2780                         switch (pref) {
2781                         case 0: /* WC */
2782                                 break;
2783                         case 1: /* MADI */
2784                                 hdspm->control_register |= HDSPM_SyncRef0;
2785                                 break;
2786                         case 2: /* SYNC_IN */
2787                                 hdspm->control_register |=
2788                                         HDSPM_SyncRef0+HDSPM_SyncRef1;
2789                                 break;
2790                         default:
2791                                 return -1;
2792                         }
2793                 }
2794
2795                 break;
2796
2797         case RayDAT:
2798                 if (hdspm->tco) {
2799                         switch (pref) {
2800                         case 0: p = 0; break;  /* WC */
2801                         case 1: p = 3; break;  /* ADAT 1 */
2802                         case 2: p = 4; break;  /* ADAT 2 */
2803                         case 3: p = 5; break;  /* ADAT 3 */
2804                         case 4: p = 6; break;  /* ADAT 4 */
2805                         case 5: p = 1; break;  /* AES */
2806                         case 6: p = 2; break;  /* SPDIF */
2807                         case 7: p = 9; break;  /* TCO */
2808                         case 8: p = 10; break; /* SYNC_IN */
2809                         default: return -1;
2810                         }
2811                 } else {
2812                         switch (pref) {
2813                         case 0: p = 0; break;  /* WC */
2814                         case 1: p = 3; break;  /* ADAT 1 */
2815                         case 2: p = 4; break;  /* ADAT 2 */
2816                         case 3: p = 5; break;  /* ADAT 3 */
2817                         case 4: p = 6; break;  /* ADAT 4 */
2818                         case 5: p = 1; break;  /* AES */
2819                         case 6: p = 2; break;  /* SPDIF */
2820                         case 7: p = 10; break; /* SYNC_IN */
2821                         default: return -1;
2822                         }
2823                 }
2824                 break;
2825
2826         case AIO:
2827                 if (hdspm->tco) {
2828                         switch (pref) {
2829                         case 0: p = 0; break;  /* WC */
2830                         case 1: p = 3; break;  /* ADAT */
2831                         case 2: p = 1; break;  /* AES */
2832                         case 3: p = 2; break;  /* SPDIF */
2833                         case 4: p = 9; break;  /* TCO */
2834                         case 5: p = 10; break; /* SYNC_IN */
2835                         default: return -1;
2836                         }
2837                 } else {
2838                         switch (pref) {
2839                         case 0: p = 0; break;  /* WC */
2840                         case 1: p = 3; break;  /* ADAT */
2841                         case 2: p = 1; break;  /* AES */
2842                         case 3: p = 2; break;  /* SPDIF */
2843                         case 4: p = 10; break; /* SYNC_IN */
2844                         default: return -1;
2845                         }
2846                 }
2847                 break;
2848         }
2849
2850         switch (hdspm->io_type) {
2851         case RayDAT:
2852         case AIO:
2853                 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2854                 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2855                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2856                 break;
2857
2858         case MADI:
2859         case MADIface:
2860         case AES32:
2861                 hdspm_write(hdspm, HDSPM_controlRegister,
2862                                 hdspm->control_register);
2863         }
2864
2865         return 0;
2866 }
2867
2868
2869 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2870                                         struct snd_ctl_elem_info *uinfo)
2871 {
2872         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2873
2874         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2875         uinfo->count = 1;
2876         uinfo->value.enumerated.items = hdspm->texts_autosync_items;
2877
2878         if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2879                 uinfo->value.enumerated.item =
2880                         uinfo->value.enumerated.items - 1;
2881
2882         strcpy(uinfo->value.enumerated.name,
2883                         hdspm->texts_autosync[uinfo->value.enumerated.item]);
2884
2885         return 0;
2886 }
2887
2888 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2889                                        struct snd_ctl_elem_value *ucontrol)
2890 {
2891         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2892         int psf = hdspm_pref_sync_ref(hdspm);
2893
2894         if (psf >= 0) {
2895                 ucontrol->value.enumerated.item[0] = psf;
2896                 return 0;
2897         }
2898
2899         return -1;
2900 }
2901
2902 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2903                                        struct snd_ctl_elem_value *ucontrol)
2904 {
2905         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2906         int val, change = 0;
2907
2908         if (!snd_hdspm_use_is_exclusive(hdspm))
2909                 return -EBUSY;
2910
2911         val = ucontrol->value.enumerated.item[0];
2912
2913         if (val < 0)
2914                 val = 0;
2915         else if (val >= hdspm->texts_autosync_items)
2916                 val = hdspm->texts_autosync_items-1;
2917
2918         spin_lock_irq(&hdspm->lock);
2919         if (val != hdspm_pref_sync_ref(hdspm))
2920                 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
2921
2922         spin_unlock_irq(&hdspm->lock);
2923         return change;
2924 }
2925
2926
2927 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2928 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2929         .name = xname, \
2930         .index = xindex, \
2931         .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2932         .info = snd_hdspm_info_autosync_ref, \
2933         .get = snd_hdspm_get_autosync_ref, \
2934 }
2935
2936 static int hdspm_autosync_ref(struct hdspm *hdspm)
2937 {
2938         if (AES32 == hdspm->io_type) {
2939                 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
2940                 unsigned int syncref =
2941                         (status >> HDSPM_AES32_syncref_bit) & 0xF;
2942                 if (syncref == 0)
2943                         return HDSPM_AES32_AUTOSYNC_FROM_WORD;
2944                 if (syncref <= 8)
2945                         return syncref;
2946                 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
2947         } else if (MADI == hdspm->io_type) {
2948                 /* This looks at the autosync selected sync reference */
2949                 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
2950
2951                 switch (status2 & HDSPM_SelSyncRefMask) {
2952                 case HDSPM_SelSyncRef_WORD:
2953                         return HDSPM_AUTOSYNC_FROM_WORD;
2954                 case HDSPM_SelSyncRef_MADI:
2955                         return HDSPM_AUTOSYNC_FROM_MADI;
2956                 case HDSPM_SelSyncRef_TCO:
2957                         return HDSPM_AUTOSYNC_FROM_TCO;
2958                 case HDSPM_SelSyncRef_SyncIn:
2959                         return HDSPM_AUTOSYNC_FROM_SYNC_IN;
2960                 case HDSPM_SelSyncRef_NVALID:
2961                         return HDSPM_AUTOSYNC_FROM_NONE;
2962                 default:
2963                         return HDSPM_AUTOSYNC_FROM_NONE;
2964                 }
2965
2966         }
2967         return 0;
2968 }
2969
2970
2971 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
2972                                        struct snd_ctl_elem_info *uinfo)
2973 {
2974         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2975
2976         if (AES32 == hdspm->io_type) {
2977                 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3",
2978                         "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
2979
2980                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2981                 uinfo->count = 1;
2982                 uinfo->value.enumerated.items = ARRAY_SIZE(texts);
2983                 if (uinfo->value.enumerated.item >=
2984                     uinfo->value.enumerated.items)
2985                         uinfo->value.enumerated.item =
2986                                 uinfo->value.enumerated.items - 1;
2987                 strcpy(uinfo->value.enumerated.name,
2988                                 texts[uinfo->value.enumerated.item]);
2989         } else if (MADI == hdspm->io_type) {
2990                 static char *texts[] = {"Word Clock", "MADI", "TCO",
2991                         "Sync In", "None" };
2992
2993                 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2994                 uinfo->count = 1;
2995                 uinfo->value.enumerated.items = 5;
2996                 if (uinfo->value.enumerated.item >=
2997                                 uinfo->value.enumerated.items)
2998                         uinfo->value.enumerated.item =
2999                                 uinfo->value.enumerated.items - 1;
3000                 strcpy(uinfo->value.enumerated.name,
3001                                 texts[uinfo->value.enumerated.item]);
3002         }
3003         return 0;
3004 }
3005
3006 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3007                                       struct snd_ctl_elem_value *ucontrol)
3008 {
3009         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3010
3011         ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3012         return 0;
3013 }
3014
3015
3016
3017 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3018 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3019         .name = xname, \
3020         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3021                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3022         .info = snd_hdspm_info_tco_video_input_format, \
3023         .get = snd_hdspm_get_tco_video_input_format, \
3024 }
3025
3026 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3027                                        struct snd_ctl_elem_info *uinfo)
3028 {
3029         static char *texts[] = {"No video", "NTSC", "PAL"};
3030         ENUMERATED_CTL_INFO(uinfo, texts);
3031         return 0;
3032 }
3033
3034 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3035                                       struct snd_ctl_elem_value *ucontrol)
3036 {
3037         u32 status;
3038         int ret = 0;
3039
3040         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3041         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3042         switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3043                         HDSPM_TCO1_Video_Input_Format_PAL)) {
3044         case HDSPM_TCO1_Video_Input_Format_NTSC:
3045                 /* ntsc */
3046                 ret = 1;
3047                 break;
3048         case HDSPM_TCO1_Video_Input_Format_PAL:
3049                 /* pal */
3050                 ret = 2;
3051                 break;
3052         default:
3053                 /* no video */
3054                 ret = 0;
3055                 break;
3056         }
3057         ucontrol->value.enumerated.item[0] = ret;
3058         return 0;
3059 }
3060
3061
3062
3063 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3064 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3065         .name = xname, \
3066         .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3067                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3068         .info = snd_hdspm_info_tco_ltc_frames, \
3069         .get = snd_hdspm_get_tco_ltc_frames, \
3070 }
3071
3072 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3073                                        struct snd_ctl_elem_info *uinfo)
3074 {
3075         static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3076                                 "30 fps"};
3077         ENUMERATED_CTL_INFO(uinfo, texts);
3078         return 0;
3079 }
3080
3081 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3082 {
3083         u32 status;
3084         int ret = 0;
3085
3086         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3087         if (status & HDSPM_TCO1_LTC_Input_valid) {
3088                 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3089                                         HDSPM_TCO1_LTC_Format_MSB)) {
3090                 case 0:
3091                         /* 24 fps */
3092                         ret = 1;
3093                         break;
3094                 case HDSPM_TCO1_LTC_Format_LSB:
3095                         /* 25 fps */
3096                         ret = 2;
3097                         break;
3098                 case HDSPM_TCO1_LTC_Format_MSB:
3099                         /* 25 fps */
3100                         ret = 3;
3101                         break;
3102                 default:
3103                         /* 30 fps */
3104                         ret = 4;
3105                         break;
3106                 }
3107         }
3108
3109         return ret;
3110 }
3111
3112 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3113                                       struct snd_ctl_elem_value *ucontrol)
3114 {
3115         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3116
3117         ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3118         return 0;
3119 }
3120
3121 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3122 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3123         .name = xname, \
3124         .private_value = xindex, \
3125         .info = snd_hdspm_info_toggle_setting, \
3126         .get = snd_hdspm_get_toggle_setting, \
3127         .put = snd_hdspm_put_toggle_setting \
3128 }
3129
3130 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3131 {
3132         u32 reg;
3133
3134         if (hdspm_is_raydat_or_aio(hdspm))
3135                 reg = hdspm->settings_register;
3136         else
3137                 reg = hdspm->control_register;
3138
3139         return (reg & regmask) ? 1 : 0;
3140 }
3141
3142 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3143 {
3144         u32 *reg;
3145         u32 target_reg;
3146
3147         if (hdspm_is_raydat_or_aio(hdspm)) {
3148                 reg = &(hdspm->settings_register);
3149                 target_reg = HDSPM_WR_SETTINGS;
3150         } else {
3151                 reg = &(hdspm->control_register);
3152                 target_reg = HDSPM_controlRegister;
3153         }
3154
3155         if (out)
3156                 *reg |= regmask;
3157         else
3158                 *reg &= ~regmask;
3159
3160         hdspm_write(hdspm, target_reg, *reg);
3161
3162         return 0;
3163 }
3164
3165 #define snd_hdspm_info_toggle_setting           snd_ctl_boolean_mono_info
3166
3167 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3168                                struct snd_ctl_elem_value *ucontrol)
3169 {
3170         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3171         u32 regmask = kcontrol->private_value;
3172
3173         spin_lock_irq(&hdspm->lock);
3174         ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3175         spin_unlock_irq(&hdspm->lock);
3176         return 0;
3177 }
3178
3179 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3180                                struct snd_ctl_elem_value *ucontrol)
3181 {
3182         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3183         u32 regmask = kcontrol->private_value;
3184         int change;
3185         unsigned int val;
3186
3187         if (!snd_hdspm_use_is_exclusive(hdspm))
3188                 return -EBUSY;
3189         val = ucontrol->value.integer.value[0] & 1;
3190         spin_lock_irq(&hdspm->lock);
3191         change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3192         hdspm_set_toggle_setting(hdspm, regmask, val);
3193         spin_unlock_irq(&hdspm->lock);
3194         return change;
3195 }
3196
3197 #define HDSPM_INPUT_SELECT(xname, xindex) \
3198 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3199         .name = xname, \
3200         .index = xindex, \
3201         .info = snd_hdspm_info_input_select, \
3202         .get = snd_hdspm_get_input_select, \
3203         .put = snd_hdspm_put_input_select \
3204 }
3205
3206 static int hdspm_input_select(struct hdspm * hdspm)
3207 {
3208         return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3209 }
3210
3211 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3212 {
3213         if (out)
3214                 hdspm->control_register |= HDSPM_InputSelect0;
3215         else
3216                 hdspm->control_register &= ~HDSPM_InputSelect0;
3217         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3218
3219         return 0;
3220 }
3221
3222 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3223                                        struct snd_ctl_elem_info *uinfo)
3224 {
3225         static char *texts[] = { "optical", "coaxial" };
3226         ENUMERATED_CTL_INFO(uinfo, texts);
3227         return 0;
3228 }
3229
3230 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3231                                       struct snd_ctl_elem_value *ucontrol)
3232 {
3233         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3234
3235         spin_lock_irq(&hdspm->lock);
3236         ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3237         spin_unlock_irq(&hdspm->lock);
3238         return 0;
3239 }
3240
3241 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3242                                       struct snd_ctl_elem_value *ucontrol)
3243 {
3244         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3245         int change;
3246         unsigned int val;
3247
3248         if (!snd_hdspm_use_is_exclusive(hdspm))
3249                 return -EBUSY;
3250         val = ucontrol->value.integer.value[0] & 1;
3251         spin_lock_irq(&hdspm->lock);
3252         change = (int) val != hdspm_input_select(hdspm);
3253         hdspm_set_input_select(hdspm, val);
3254         spin_unlock_irq(&hdspm->lock);
3255         return change;
3256 }
3257
3258
3259 #define HDSPM_DS_WIRE(xname, xindex) \
3260 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3261         .name = xname, \
3262         .index = xindex, \
3263         .info = snd_hdspm_info_ds_wire, \
3264         .get = snd_hdspm_get_ds_wire, \
3265         .put = snd_hdspm_put_ds_wire \
3266 }
3267
3268 static int hdspm_ds_wire(struct hdspm * hdspm)
3269 {
3270         return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3271 }
3272
3273 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3274 {
3275         if (ds)
3276                 hdspm->control_register |= HDSPM_DS_DoubleWire;
3277         else
3278                 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3279         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3280
3281         return 0;
3282 }
3283
3284 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3285                                   struct snd_ctl_elem_info *uinfo)
3286 {
3287         static char *texts[] = { "Single", "Double" };
3288         ENUMERATED_CTL_INFO(uinfo, texts);
3289         return 0;
3290 }
3291
3292 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3293                                  struct snd_ctl_elem_value *ucontrol)
3294 {
3295         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3296
3297         spin_lock_irq(&hdspm->lock);
3298         ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3299         spin_unlock_irq(&hdspm->lock);
3300         return 0;
3301 }
3302
3303 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3304                                  struct snd_ctl_elem_value *ucontrol)
3305 {
3306         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3307         int change;
3308         unsigned int val;
3309
3310         if (!snd_hdspm_use_is_exclusive(hdspm))
3311                 return -EBUSY;
3312         val = ucontrol->value.integer.value[0] & 1;
3313         spin_lock_irq(&hdspm->lock);
3314         change = (int) val != hdspm_ds_wire(hdspm);
3315         hdspm_set_ds_wire(hdspm, val);
3316         spin_unlock_irq(&hdspm->lock);
3317         return change;
3318 }
3319
3320
3321 #define HDSPM_QS_WIRE(xname, xindex) \
3322 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3323         .name = xname, \
3324         .index = xindex, \
3325         .info = snd_hdspm_info_qs_wire, \
3326         .get = snd_hdspm_get_qs_wire, \
3327         .put = snd_hdspm_put_qs_wire \
3328 }
3329
3330 static int hdspm_qs_wire(struct hdspm * hdspm)
3331 {
3332         if (hdspm->control_register & HDSPM_QS_DoubleWire)
3333                 return 1;
3334         if (hdspm->control_register & HDSPM_QS_QuadWire)
3335                 return 2;
3336         return 0;
3337 }
3338
3339 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3340 {
3341         hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3342         switch (mode) {
3343         case 0:
3344                 break;
3345         case 1:
3346                 hdspm->control_register |= HDSPM_QS_DoubleWire;
3347                 break;
3348         case 2:
3349                 hdspm->control_register |= HDSPM_QS_QuadWire;
3350                 break;
3351         }
3352         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3353
3354         return 0;
3355 }
3356
3357 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3358                                        struct snd_ctl_elem_info *uinfo)
3359 {
3360         static char *texts[] = { "Single", "Double", "Quad" };
3361         ENUMERATED_CTL_INFO(uinfo, texts);
3362         return 0;
3363 }
3364
3365 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3366                                       struct snd_ctl_elem_value *ucontrol)
3367 {
3368         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3369
3370         spin_lock_irq(&hdspm->lock);
3371         ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3372         spin_unlock_irq(&hdspm->lock);
3373         return 0;
3374 }
3375
3376 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3377                                       struct snd_ctl_elem_value *ucontrol)
3378 {
3379         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3380         int change;
3381         int val;
3382
3383         if (!snd_hdspm_use_is_exclusive(hdspm))
3384                 return -EBUSY;
3385         val = ucontrol->value.integer.value[0];
3386         if (val < 0)
3387                 val = 0;
3388         if (val > 2)
3389                 val = 2;
3390         spin_lock_irq(&hdspm->lock);
3391         change = val != hdspm_qs_wire(hdspm);
3392         hdspm_set_qs_wire(hdspm, val);
3393         spin_unlock_irq(&hdspm->lock);
3394         return change;
3395 }
3396
3397 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3398 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3399         .name = xname, \
3400         .private_value = xindex, \
3401         .info = snd_hdspm_info_tristate, \
3402         .get = snd_hdspm_get_tristate, \
3403         .put = snd_hdspm_put_tristate \
3404 }
3405
3406 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3407 {
3408         u32 reg = hdspm->settings_register & (regmask * 3);
3409         return reg / regmask;
3410 }
3411
3412 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3413 {
3414         hdspm->settings_register &= ~(regmask * 3);
3415         hdspm->settings_register |= (regmask * mode);
3416         hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3417
3418         return 0;
3419 }
3420
3421 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3422                                        struct snd_ctl_elem_info *uinfo)
3423 {
3424         u32 regmask = kcontrol->private_value;
3425
3426         static char *texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3427         static char *texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3428
3429         switch (regmask) {
3430         case HDSPM_c0_Input0:
3431                 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3432                 break;
3433         default:
3434                 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3435                 break;
3436         }
3437         return 0;
3438 }
3439
3440 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3441                                       struct snd_ctl_elem_value *ucontrol)
3442 {
3443         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3444         u32 regmask = kcontrol->private_value;
3445
3446         spin_lock_irq(&hdspm->lock);
3447         ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3448         spin_unlock_irq(&hdspm->lock);
3449         return 0;
3450 }
3451
3452 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3453                                       struct snd_ctl_elem_value *ucontrol)
3454 {
3455         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3456         u32 regmask = kcontrol->private_value;
3457         int change;
3458         int val;
3459
3460         if (!snd_hdspm_use_is_exclusive(hdspm))
3461                 return -EBUSY;
3462         val = ucontrol->value.integer.value[0];
3463         if (val < 0)
3464                 val = 0;
3465         if (val > 2)
3466                 val = 2;
3467
3468         spin_lock_irq(&hdspm->lock);
3469         change = val != hdspm_tristate(hdspm, regmask);
3470         hdspm_set_tristate(hdspm, val, regmask);
3471         spin_unlock_irq(&hdspm->lock);
3472         return change;
3473 }
3474
3475 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3476 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3477         .name = xname, \
3478         .index = xindex, \
3479         .info = snd_hdspm_info_madi_speedmode, \
3480         .get = snd_hdspm_get_madi_speedmode, \
3481         .put = snd_hdspm_put_madi_speedmode \
3482 }
3483
3484 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3485 {
3486         if (hdspm->control_register & HDSPM_QuadSpeed)
3487                 return 2;
3488         if (hdspm->control_register & HDSPM_DoubleSpeed)
3489                 return 1;
3490         return 0;
3491 }
3492
3493 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3494 {
3495         hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3496         switch (mode) {
3497         case 0:
3498                 break;
3499         case 1:
3500                 hdspm->control_register |= HDSPM_DoubleSpeed;
3501                 break;
3502         case 2:
3503                 hdspm->control_register |= HDSPM_QuadSpeed;
3504                 break;
3505         }
3506         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3507
3508         return 0;
3509 }
3510
3511 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3512                                        struct snd_ctl_elem_info *uinfo)
3513 {
3514         static char *texts[] = { "Single", "Double", "Quad" };
3515         ENUMERATED_CTL_INFO(uinfo, texts);
3516         return 0;
3517 }
3518
3519 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3520                                       struct snd_ctl_elem_value *ucontrol)
3521 {
3522         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3523
3524         spin_lock_irq(&hdspm->lock);
3525         ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3526         spin_unlock_irq(&hdspm->lock);
3527         return 0;
3528 }
3529
3530 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3531                                       struct snd_ctl_elem_value *ucontrol)
3532 {
3533         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3534         int change;
3535         int val;
3536
3537         if (!snd_hdspm_use_is_exclusive(hdspm))
3538                 return -EBUSY;
3539         val = ucontrol->value.integer.value[0];
3540         if (val < 0)
3541                 val = 0;
3542         if (val > 2)
3543                 val = 2;
3544         spin_lock_irq(&hdspm->lock);
3545         change = val != hdspm_madi_speedmode(hdspm);
3546         hdspm_set_madi_speedmode(hdspm, val);
3547         spin_unlock_irq(&hdspm->lock);
3548         return change;
3549 }
3550
3551 #define HDSPM_MIXER(xname, xindex) \
3552 {       .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3553         .name = xname, \
3554         .index = xindex, \
3555         .device = 0, \
3556         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3557                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3558         .info = snd_hdspm_info_mixer, \
3559         .get = snd_hdspm_get_mixer, \
3560         .put = snd_hdspm_put_mixer \
3561 }
3562
3563 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3564                                 struct snd_ctl_elem_info *uinfo)
3565 {
3566         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3567         uinfo->count = 3;
3568         uinfo->value.integer.min = 0;
3569         uinfo->value.integer.max = 65535;
3570         uinfo->value.integer.step = 1;
3571         return 0;
3572 }
3573
3574 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3575                                struct snd_ctl_elem_value *ucontrol)
3576 {
3577         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3578         int source;
3579         int destination;
3580
3581         source = ucontrol->value.integer.value[0];
3582         if (source < 0)
3583                 source = 0;
3584         else if (source >= 2 * HDSPM_MAX_CHANNELS)
3585                 source = 2 * HDSPM_MAX_CHANNELS - 1;
3586
3587         destination = ucontrol->value.integer.value[1];
3588         if (destination < 0)
3589                 destination = 0;
3590         else if (destination >= HDSPM_MAX_CHANNELS)
3591                 destination = HDSPM_MAX_CHANNELS - 1;
3592
3593         spin_lock_irq(&hdspm->lock);
3594         if (source >= HDSPM_MAX_CHANNELS)
3595                 ucontrol->value.integer.value[2] =
3596                     hdspm_read_pb_gain(hdspm, destination,
3597                                        source - HDSPM_MAX_CHANNELS);
3598         else
3599                 ucontrol->value.integer.value[2] =
3600                     hdspm_read_in_gain(hdspm, destination, source);
3601
3602         spin_unlock_irq(&hdspm->lock);
3603
3604         return 0;
3605 }
3606
3607 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3608                                struct snd_ctl_elem_value *ucontrol)
3609 {
3610         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3611         int change;
3612         int source;
3613         int destination;
3614         int gain;
3615
3616         if (!snd_hdspm_use_is_exclusive(hdspm))
3617                 return -EBUSY;
3618
3619         source = ucontrol->value.integer.value[0];
3620         destination = ucontrol->value.integer.value[1];
3621
3622         if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3623                 return -1;
3624         if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3625                 return -1;
3626
3627         gain = ucontrol->value.integer.value[2];
3628
3629         spin_lock_irq(&hdspm->lock);
3630
3631         if (source >= HDSPM_MAX_CHANNELS)
3632                 change = gain != hdspm_read_pb_gain(hdspm, destination,
3633                                                     source -
3634                                                     HDSPM_MAX_CHANNELS);
3635         else
3636                 change = gain != hdspm_read_in_gain(hdspm, destination,
3637                                                     source);
3638
3639         if (change) {
3640                 if (source >= HDSPM_MAX_CHANNELS)
3641                         hdspm_write_pb_gain(hdspm, destination,
3642                                             source - HDSPM_MAX_CHANNELS,
3643                                             gain);
3644                 else
3645                         hdspm_write_in_gain(hdspm, destination, source,
3646                                             gain);
3647         }
3648         spin_unlock_irq(&hdspm->lock);
3649
3650         return change;
3651 }
3652
3653 /* The simple mixer control(s) provide gain control for the
3654    basic 1:1 mappings of playback streams to output
3655    streams.
3656 */
3657
3658 #define HDSPM_PLAYBACK_MIXER \
3659 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3660         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3661                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3662         .info = snd_hdspm_info_playback_mixer, \
3663         .get = snd_hdspm_get_playback_mixer, \
3664         .put = snd_hdspm_put_playback_mixer \
3665 }
3666
3667 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3668                                          struct snd_ctl_elem_info *uinfo)
3669 {
3670         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3671         uinfo->count = 1;
3672         uinfo->value.integer.min = 0;
3673         uinfo->value.integer.max = 64;
3674         uinfo->value.integer.step = 1;
3675         return 0;
3676 }
3677
3678 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3679                                         struct snd_ctl_elem_value *ucontrol)
3680 {
3681         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3682         int channel;
3683
3684         channel = ucontrol->id.index - 1;
3685
3686         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3687                 return -EINVAL;
3688
3689         spin_lock_irq(&hdspm->lock);
3690         ucontrol->value.integer.value[0] =
3691           (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3692         spin_unlock_irq(&hdspm->lock);
3693
3694         return 0;
3695 }
3696
3697 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3698                                         struct snd_ctl_elem_value *ucontrol)
3699 {
3700         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3701         int change;
3702         int channel;
3703         int gain;
3704
3705         if (!snd_hdspm_use_is_exclusive(hdspm))
3706                 return -EBUSY;
3707
3708         channel = ucontrol->id.index - 1;
3709
3710         if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3711                 return -EINVAL;
3712
3713         gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3714
3715         spin_lock_irq(&hdspm->lock);
3716         change =
3717             gain != hdspm_read_pb_gain(hdspm, channel,
3718                                        channel);
3719         if (change)
3720                 hdspm_write_pb_gain(hdspm, channel, channel,
3721                                     gain);
3722         spin_unlock_irq(&hdspm->lock);
3723         return change;
3724 }
3725
3726 #define HDSPM_SYNC_CHECK(xname, xindex) \
3727 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3728         .name = xname, \
3729         .private_value = xindex, \
3730         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3731         .info = snd_hdspm_info_sync_check, \
3732         .get = snd_hdspm_get_sync_check \
3733 }
3734
3735 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3736 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3737         .name = xname, \
3738         .private_value = xindex, \
3739         .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3740         .info = snd_hdspm_tco_info_lock_check, \
3741         .get = snd_hdspm_get_sync_check \
3742 }
3743
3744
3745
3746 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3747                                      struct snd_ctl_elem_info *uinfo)
3748 {
3749         static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3750         ENUMERATED_CTL_INFO(uinfo, texts);
3751         return 0;
3752 }
3753
3754 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3755                                      struct snd_ctl_elem_info *uinfo)
3756 {
3757         static char *texts[] = { "No Lock", "Lock" };
3758         ENUMERATED_CTL_INFO(uinfo, texts);
3759         return 0;
3760 }
3761
3762 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3763 {
3764         int status, status2;
3765
3766         switch (hdspm->io_type) {
3767         case AES32:
3768                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3769                 if (status & HDSPM_AES32_wcLock) {
3770                         if (status & HDSPM_AES32_wcSync)
3771                                 return 2;
3772                         else
3773                                 return 1;
3774                 }
3775                 return 0;
3776                 break;
3777
3778         case MADI:
3779                 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3780                 if (status2 & HDSPM_wcLock) {
3781                         if (status2 & HDSPM_wcSync)
3782                                 return 2;
3783                         else
3784                                 return 1;
3785                 }
3786                 return 0;
3787                 break;
3788
3789         case RayDAT:
3790         case AIO:
3791                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3792
3793                 if (status & 0x2000000)
3794                         return 2;
3795                 else if (status & 0x1000000)
3796                         return 1;
3797                 return 0;
3798
3799                 break;
3800
3801         case MADIface:
3802                 break;
3803         }
3804
3805
3806         return 3;
3807 }
3808
3809
3810 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3811 {
3812         int status = hdspm_read(hdspm, HDSPM_statusRegister);
3813         if (status & HDSPM_madiLock) {
3814                 if (status & HDSPM_madiSync)
3815                         return 2;
3816                 else
3817                         return 1;
3818         }
3819         return 0;
3820 }
3821
3822
3823 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3824 {
3825         int status, lock, sync;
3826
3827         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3828
3829         lock = (status & (0x1<<idx)) ? 1 : 0;
3830         sync = (status & (0x100<<idx)) ? 1 : 0;
3831
3832         if (lock && sync)
3833                 return 2;
3834         else if (lock)
3835                 return 1;
3836         return 0;
3837 }
3838
3839
3840 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3841 {
3842         int status, lock = 0, sync = 0;
3843
3844         switch (hdspm->io_type) {
3845         case RayDAT:
3846         case AIO:
3847                 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3848                 lock = (status & 0x400) ? 1 : 0;
3849                 sync = (status & 0x800) ? 1 : 0;
3850                 break;
3851
3852         case MADI:
3853                 status = hdspm_read(hdspm, HDSPM_statusRegister);
3854                 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3855                 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3856                 break;
3857
3858         case AES32:
3859                 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3860                 lock = (status & 0x100000) ? 1 : 0;
3861                 sync = (status & 0x200000) ? 1 : 0;
3862                 break;
3863
3864         case MADIface:
3865                 break;
3866         }
3867
3868         if (lock && sync)
3869                 return 2;
3870         else if (lock)
3871                 return 1;
3872
3873         return 0;
3874 }
3875
3876 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3877 {
3878         int status2, lock, sync;
3879         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3880
3881         lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3882         sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3883
3884         if (sync)
3885                 return 2;
3886         else if (lock)
3887                 return 1;
3888         return 0;
3889 }
3890
3891 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3892 {
3893         u32 status;
3894         status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3895
3896         return (status & mask) ? 1 : 0;
3897 }
3898
3899
3900 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3901 {
3902         int status;
3903
3904         if (hdspm->tco) {
3905                 switch (hdspm->io_type) {
3906                 case MADI:
3907                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3908                         if (status & HDSPM_tcoLockMadi) {
3909                                 if (status & HDSPM_tcoSync)
3910                                         return 2;
3911                                 else
3912                                         return 1;
3913                         }
3914                         return 0;
3915                         break;
3916                 case AES32:
3917                         status = hdspm_read(hdspm, HDSPM_statusRegister);
3918                         if (status & HDSPM_tcoLockAes) {
3919                                 if (status & HDSPM_tcoSync)
3920                                         return 2;
3921                                 else
3922                                         return 1;
3923                         }
3924                         return 0;
3925
3926                         break;
3927
3928                 case RayDAT:
3929                 case AIO:
3930                         status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3931
3932                         if (status & 0x8000000)
3933                                 return 2; /* Sync */
3934                         if (status & 0x4000000)
3935                                 return 1; /* Lock */
3936                         return 0; /* No signal */
3937                         break;
3938
3939                 default:
3940                         break;
3941                 }
3942         }
3943
3944         return 3; /* N/A */
3945 }
3946
3947
3948 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
3949                                     struct snd_ctl_elem_value *ucontrol)
3950 {
3951         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3952         int val = -1;
3953
3954         switch (hdspm->io_type) {
3955         case RayDAT:
3956                 switch (kcontrol->private_value) {
3957                 case 0: /* WC */
3958                         val = hdspm_wc_sync_check(hdspm); break;
3959                 case 7: /* TCO */
3960                         val = hdspm_tco_sync_check(hdspm); break;
3961                 case 8: /* SYNC IN */
3962                         val = hdspm_sync_in_sync_check(hdspm); break;
3963                 default:
3964                         val = hdspm_s1_sync_check(hdspm,
3965                                         kcontrol->private_value-1);
3966                 }
3967                 break;
3968
3969         case AIO:
3970                 switch (kcontrol->private_value) {
3971                 case 0: /* WC */
3972                         val = hdspm_wc_sync_check(hdspm); break;
3973                 case 4: /* TCO */
3974                         val = hdspm_tco_sync_check(hdspm); break;
3975                 case 5: /* SYNC IN */
3976                         val = hdspm_sync_in_sync_check(hdspm); break;
3977                 default:
3978                         val = hdspm_s1_sync_check(hdspm,
3979                                         kcontrol->private_value-1);
3980                 }
3981                 break;
3982
3983         case MADI:
3984                 switch (kcontrol->private_value) {
3985                 case 0: /* WC */
3986                         val = hdspm_wc_sync_check(hdspm); break;
3987                 case 1: /* MADI */
3988                         val = hdspm_madi_sync_check(hdspm); break;
3989                 case 2: /* TCO */
3990                         val = hdspm_tco_sync_check(hdspm); break;
3991                 case 3: /* SYNC_IN */
3992                         val = hdspm_sync_in_sync_check(hdspm); break;
3993                 }
3994                 break;
3995
3996         case MADIface:
3997                 val = hdspm_madi_sync_check(hdspm); /* MADI */
3998                 break;
3999
4000         case AES32:
4001                 switch (kcontrol->private_value) {
4002                 case 0: /* WC */
4003                         val = hdspm_wc_sync_check(hdspm); break;
4004                 case 9: /* TCO */
4005                         val = hdspm_tco_sync_check(hdspm); break;
4006                 case 10 /* SYNC IN */:
4007                         val = hdspm_sync_in_sync_check(hdspm); break;
4008                 default: /* AES1 to AES8 */
4009                          val = hdspm_aes_sync_check(hdspm,
4010                                          kcontrol->private_value-1);
4011                 }
4012                 break;
4013
4014         }
4015
4016         if (hdspm->tco) {
4017                 switch (kcontrol->private_value) {
4018                 case 11:
4019                         /* Check TCO for lock state of its current input */
4020                         val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4021                         break;
4022                 case 12:
4023                         /* Check TCO for valid time code on LTC input. */
4024                         val = hdspm_tco_input_check(hdspm,
4025                                 HDSPM_TCO1_LTC_Input_valid);
4026                         break;
4027                 default:
4028                         break;
4029                 }
4030         }
4031
4032         if (-1 == val)
4033                 val = 3;
4034
4035         ucontrol->value.enumerated.item[0] = val;
4036         return 0;
4037 }
4038
4039
4040
4041 /**
4042  * TCO controls
4043  **/
4044 static void hdspm_tco_write(struct hdspm *hdspm)
4045 {
4046         unsigned int tc[4] = { 0, 0, 0, 0};
4047
4048         switch (hdspm->tco->input) {
4049         case 0:
4050                 tc[2] |= HDSPM_TCO2_set_input_MSB;
4051                 break;
4052         case 1:
4053                 tc[2] |= HDSPM_TCO2_set_input_LSB;
4054                 break;
4055         default:
4056                 break;
4057         }
4058
4059         switch (hdspm->tco->framerate) {
4060         case 1:
4061                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4062                 break;
4063         case 2:
4064                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4065                 break;
4066         case 3:
4067                 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4068                         HDSPM_TCO1_set_drop_frame_flag;
4069                 break;
4070         case 4:
4071                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4072                         HDSPM_TCO1_LTC_Format_MSB;
4073                 break;
4074         case 5:
4075                 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4076                         HDSPM_TCO1_LTC_Format_MSB +
4077                         HDSPM_TCO1_set_drop_frame_flag;
4078                 break;
4079         default:
4080                 break;
4081         }
4082
4083         switch (hdspm->tco->wordclock) {
4084         case 1:
4085                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4086                 break;
4087         case 2:
4088                 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4089                 break;
4090         default:
4091                 break;
4092         }
4093
4094         switch (hdspm->tco->samplerate) {
4095         case 1:
4096                 tc[2] |= HDSPM_TCO2_set_freq;
4097                 break;
4098         case 2:
4099                 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4100                 break;
4101         default:
4102                 break;
4103         }
4104
4105         switch (hdspm->tco->pull) {
4106         case 1:
4107                 tc[2] |= HDSPM_TCO2_set_pull_up;
4108                 break;
4109         case 2:
4110                 tc[2] |= HDSPM_TCO2_set_pull_down;
4111                 break;
4112         case 3:
4113                 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4114                 break;
4115         case 4:
4116                 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4117                 break;
4118         default:
4119                 break;
4120         }
4121
4122         if (1 == hdspm->tco->term) {
4123                 tc[2] |= HDSPM_TCO2_set_term_75R;
4124         }
4125
4126         hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4127         hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4128         hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4129         hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4130 }
4131
4132
4133 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4134 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4135         .name = xname, \
4136         .index = xindex, \
4137         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4138                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4139         .info = snd_hdspm_info_tco_sample_rate, \
4140         .get = snd_hdspm_get_tco_sample_rate, \
4141         .put = snd_hdspm_put_tco_sample_rate \
4142 }
4143
4144 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4145                                           struct snd_ctl_elem_info *uinfo)
4146 {
4147         static char *texts[] = { "44.1 kHz", "48 kHz" };
4148         ENUMERATED_CTL_INFO(uinfo, texts);
4149         return 0;
4150 }
4151
4152 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4153                                       struct snd_ctl_elem_value *ucontrol)
4154 {
4155         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4156
4157         ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4158
4159         return 0;
4160 }
4161
4162 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4163                                          struct snd_ctl_elem_value *ucontrol)
4164 {
4165         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4166
4167         if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4168                 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4169
4170                 hdspm_tco_write(hdspm);
4171
4172                 return 1;
4173         }
4174
4175         return 0;
4176 }
4177
4178
4179 #define HDSPM_TCO_PULL(xname, xindex) \
4180 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4181         .name = xname, \
4182         .index = xindex, \
4183         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4184                 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4185         .info = snd_hdspm_info_tco_pull, \
4186         .get = snd_hdspm_get_tco_pull, \
4187         .put = snd_hdspm_put_tco_pull \
4188 }
4189
4190 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4191                                    struct snd_ctl_elem_info *uinfo)
4192 {
4193         static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4194         ENUMERATED_CTL_INFO(uinfo, texts);
4195         return 0;
4196 }
4197
4198 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4199                                   struct snd_ctl_elem_value *ucontrol)
4200 {
4201         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4202
4203         ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4204
4205         return 0;
4206 }
4207
4208 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4209                                   struct snd_ctl_elem_value *ucontrol)
4210 {
4211         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4212
4213         if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4214                 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4215
4216                 hdspm_tco_write(hdspm);
4217
4218                 return 1;
4219         }
4220
4221         return 0;
4222 }
4223
4224 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4225 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4226         .name = xname, \
4227         .index = xindex, \
4228         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4229                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4230         .info = snd_hdspm_info_tco_wck_conversion, \
4231         .get = snd_hdspm_get_tco_wck_conversion, \
4232         .put = snd_hdspm_put_tco_wck_conversion \
4233 }
4234
4235 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4236                                              struct snd_ctl_elem_info *uinfo)
4237 {
4238         static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4239         ENUMERATED_CTL_INFO(uinfo, texts);
4240         return 0;
4241 }
4242
4243 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4244                                             struct snd_ctl_elem_value *ucontrol)
4245 {
4246         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4247
4248         ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4249
4250         return 0;
4251 }
4252
4253 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4254                                             struct snd_ctl_elem_value *ucontrol)
4255 {
4256         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4257
4258         if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4259                 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4260
4261                 hdspm_tco_write(hdspm);
4262
4263                 return 1;
4264         }
4265
4266         return 0;
4267 }
4268
4269
4270 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4271 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4272         .name = xname, \
4273         .index = xindex, \
4274         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4275                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4276         .info = snd_hdspm_info_tco_frame_rate, \
4277         .get = snd_hdspm_get_tco_frame_rate, \
4278         .put = snd_hdspm_put_tco_frame_rate \
4279 }
4280
4281 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4282                                           struct snd_ctl_elem_info *uinfo)
4283 {
4284         static char *texts[] = { "24 fps", "25 fps", "29.97fps",
4285                 "29.97 dfps", "30 fps", "30 dfps" };
4286         ENUMERATED_CTL_INFO(uinfo, texts);
4287         return 0;
4288 }
4289
4290 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4291                                         struct snd_ctl_elem_value *ucontrol)
4292 {
4293         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4294
4295         ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4296
4297         return 0;
4298 }
4299
4300 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4301                                         struct snd_ctl_elem_value *ucontrol)
4302 {
4303         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4304
4305         if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4306                 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4307
4308                 hdspm_tco_write(hdspm);
4309
4310                 return 1;
4311         }
4312
4313         return 0;
4314 }
4315
4316
4317 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4318 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4319         .name = xname, \
4320         .index = xindex, \
4321         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4322                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4323         .info = snd_hdspm_info_tco_sync_source, \
4324         .get = snd_hdspm_get_tco_sync_source, \
4325         .put = snd_hdspm_put_tco_sync_source \
4326 }
4327
4328 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4329                                           struct snd_ctl_elem_info *uinfo)
4330 {
4331         static char *texts[] = { "LTC", "Video", "WCK" };
4332         ENUMERATED_CTL_INFO(uinfo, texts);
4333         return 0;
4334 }
4335
4336 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4337                                          struct snd_ctl_elem_value *ucontrol)
4338 {
4339         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4340
4341         ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4342
4343         return 0;
4344 }
4345
4346 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4347                                          struct snd_ctl_elem_value *ucontrol)
4348 {
4349         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4350
4351         if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4352                 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4353
4354                 hdspm_tco_write(hdspm);
4355
4356                 return 1;
4357         }
4358
4359         return 0;
4360 }
4361
4362
4363 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4364 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4365         .name = xname, \
4366         .index = xindex, \
4367         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4368                         SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4369         .info = snd_hdspm_info_tco_word_term, \
4370         .get = snd_hdspm_get_tco_word_term, \
4371         .put = snd_hdspm_put_tco_word_term \
4372 }
4373
4374 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4375                                         struct snd_ctl_elem_info *uinfo)
4376 {
4377         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4378         uinfo->count = 1;
4379         uinfo->value.integer.min = 0;
4380         uinfo->value.integer.max = 1;
4381
4382         return 0;
4383 }
4384
4385
4386 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4387                                        struct snd_ctl_elem_value *ucontrol)
4388 {
4389         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4390
4391         ucontrol->value.enumerated.item[0] = hdspm->tco->term;
4392
4393         return 0;
4394 }
4395
4396
4397 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4398                                        struct snd_ctl_elem_value *ucontrol)
4399 {
4400         struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4401
4402         if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) {
4403                 hdspm->tco->term = ucontrol->value.enumerated.item[0];
4404
4405                 hdspm_tco_write(hdspm);
4406
4407                 return 1;
4408         }
4409
4410         return 0;
4411 }
4412
4413
4414
4415
4416 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4417         HDSPM_MIXER("Mixer", 0),
4418         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4419         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4420         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4421         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4422         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4423         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4424         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4425         HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4426         HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4427         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4428         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4429         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4430         HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4431         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4432         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4433         HDSPM_INPUT_SELECT("Input Select", 0),
4434         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4435 };
4436
4437
4438 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4439         HDSPM_MIXER("Mixer", 0),
4440         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4441         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4442         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4443         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4444         HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4445         HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4446         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4447         HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4448         HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4449 };
4450
4451 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4452         HDSPM_MIXER("Mixer", 0),
4453         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4454         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4455         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4456         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4457         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4458         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4459         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4460         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4461         HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4462         HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4463         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4464         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4465         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4466         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4467         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4468         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4469         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4470         HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4471         HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4472         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4473         HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4474         HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4475         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4476         HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4477         HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4478         HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4479
4480                 /*
4481                    HDSPM_INPUT_SELECT("Input Select", 0),
4482                    HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4483                    HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4484                    HDSPM_SPDIF_IN("SPDIF In", 0);
4485                    HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4486                    HDSPM_INPUT_LEVEL("Input Level", 0);
4487                    HDSPM_OUTPUT_LEVEL("Output Level", 0);
4488                    HDSPM_PHONES("Phones", 0);
4489                    */
4490 };
4491
4492 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4493         HDSPM_MIXER("Mixer", 0),
4494         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4495         HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4496         HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4497         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4498         HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4499         HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4500         HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4501         HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4502         HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4503         HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4504         HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4505         HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4506         HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4507         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4508         HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4509         HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4510         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4511         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4512         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4513         HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4514         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4515         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4516         HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4517         HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4518 };
4519
4520 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4521         HDSPM_MIXER("Mixer", 0),
4522         HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4523         HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4524         HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4525         HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4526         HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4527         HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4528         HDSPM_SYNC_CHECK("WC Sync Check", 0),
4529         HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4530         HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4531         HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4532         HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4533         HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4534         HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4535         HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4536         HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4537         HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4538         HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4539         HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4540         HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4541         HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4542         HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4543         HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4544         HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4545         HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4546         HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4547         HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4548         HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4549         HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4550         HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4551         HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4552         HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4553         HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4554         HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4555         HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4556         HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4557 };
4558
4559
4560
4561 /* Control elements for the optional TCO module */
4562 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4563         HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4564         HDSPM_TCO_PULL("TCO Pull", 0),
4565         HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4566         HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4567         HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4568         HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4569         HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4570         HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4571         HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4572         HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4573 };
4574
4575
4576 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4577
4578
4579 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4580 {
4581         int i;
4582
4583         for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4584                 if (hdspm->system_sample_rate > 48000) {
4585                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4586                                 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4587                                 SNDRV_CTL_ELEM_ACCESS_READ |
4588                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4589                 } else {
4590                         hdspm->playback_mixer_ctls[i]->vd[0].access =
4591                                 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4592                                 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4593                 }
4594                 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4595                                 SNDRV_CTL_EVENT_MASK_INFO,
4596                                 &hdspm->playback_mixer_ctls[i]->id);
4597         }
4598
4599         return 0;
4600 }
4601
4602
4603 static int snd_hdspm_create_controls(struct snd_card *card,
4604                                         struct hdspm *hdspm)
4605 {
4606         unsigned int idx, limit;
4607         int err;
4608         struct snd_kcontrol *kctl;
4609         struct snd_kcontrol_new *list = NULL;
4610
4611         switch (hdspm->io_type) {
4612         case MADI:
4613                 list = snd_hdspm_controls_madi;
4614                 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4615                 break;
4616         case MADIface:
4617                 list = snd_hdspm_controls_madiface;
4618                 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4619                 break;
4620         case AIO:
4621                 list = snd_hdspm_controls_aio;
4622                 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4623                 break;
4624         case RayDAT:
4625                 list = snd_hdspm_controls_raydat;
4626                 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4627                 break;
4628         case AES32:
4629                 list = snd_hdspm_controls_aes32;
4630                 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4631                 break;
4632         }
4633
4634         if (NULL != list) {
4635                 for (idx = 0; idx < limit; idx++) {
4636                         err = snd_ctl_add(card,
4637                                         snd_ctl_new1(&list[idx], hdspm));
4638                         if (err < 0)
4639                                 return err;
4640                 }
4641         }
4642
4643
4644         /* create simple 1:1 playback mixer controls */
4645         snd_hdspm_playback_mixer.name = "Chn";
4646         if (hdspm->system_sample_rate >= 128000) {
4647                 limit = hdspm->qs_out_channels;
4648         } else if (hdspm->system_sample_rate >= 64000) {
4649                 limit = hdspm->ds_out_channels;
4650         } else {
4651                 limit = hdspm->ss_out_channels;
4652         }
4653         for (idx = 0; idx < limit; ++idx) {
4654                 snd_hdspm_playback_mixer.index = idx + 1;
4655                 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4656                 err = snd_ctl_add(card, kctl);
4657                 if (err < 0)
4658                         return err;
4659                 hdspm->playback_mixer_ctls[idx] = kctl;
4660         }
4661
4662
4663         if (hdspm->tco) {
4664                 /* add tco control elements */
4665                 list = snd_hdspm_controls_tco;
4666                 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4667                 for (idx = 0; idx < limit; idx++) {
4668                         err = snd_ctl_add(card,
4669                                         snd_ctl_new1(&list[idx], hdspm));
4670                         if (err < 0)
4671                                 return err;
4672                 }
4673         }
4674
4675         return 0;
4676 }
4677
4678 /*------------------------------------------------------------
4679    /proc interface
4680  ------------------------------------------------------------*/
4681
4682 static void
4683 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4684                                         struct snd_info_buffer *buffer)
4685 {
4686         struct hdspm *hdspm = entry->private_data;
4687         unsigned int status, control;
4688         int a, ltc, frames, seconds, minutes, hours;
4689         unsigned int period;
4690         u64 freq_const = 0;
4691         u32 rate;
4692
4693         snd_iprintf(buffer, "--- TCO ---\n");
4694
4695         status = hdspm_read(hdspm, HDSPM_statusRegister);
4696         control = hdspm->control_register;
4697
4698
4699         if (status & HDSPM_tco_detect) {
4700                 snd_iprintf(buffer, "TCO module detected.\n");
4701                 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4702                 if (a & HDSPM_TCO1_LTC_Input_valid) {
4703                         snd_iprintf(buffer, "  LTC valid, ");
4704                         switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4705                                                 HDSPM_TCO1_LTC_Format_MSB)) {
4706                         case 0:
4707                                 snd_iprintf(buffer, "24 fps, ");
4708                                 break;
4709                         case HDSPM_TCO1_LTC_Format_LSB:
4710                                 snd_iprintf(buffer, "25 fps, ");
4711                                 break;
4712                         case HDSPM_TCO1_LTC_Format_MSB:
4713                                 snd_iprintf(buffer, "29.97 fps, ");
4714                                 break;
4715                         default:
4716                                 snd_iprintf(buffer, "30 fps, ");
4717                                 break;
4718                         }
4719                         if (a & HDSPM_TCO1_set_drop_frame_flag) {
4720                                 snd_iprintf(buffer, "drop frame\n");
4721                         } else {
4722                                 snd_iprintf(buffer, "full frame\n");
4723                         }
4724                 } else {
4725                         snd_iprintf(buffer, "  no LTC\n");
4726                 }
4727                 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4728                         snd_iprintf(buffer, "  Video: NTSC\n");
4729                 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4730                         snd_iprintf(buffer, "  Video: PAL\n");
4731                 } else {
4732                         snd_iprintf(buffer, "  No video\n");
4733                 }
4734                 if (a & HDSPM_TCO1_TCO_lock) {
4735                         snd_iprintf(buffer, "  Sync: lock\n");
4736                 } else {
4737                         snd_iprintf(buffer, "  Sync: no lock\n");
4738                 }
4739
4740                 switch (hdspm->io_type) {
4741                 case MADI:
4742                 case AES32:
4743                         freq_const = 110069313433624ULL;
4744                         break;
4745                 case RayDAT:
4746                 case AIO:
4747                         freq_const = 104857600000000ULL;
4748                         break;
4749                 case MADIface:
4750                         break; /* no TCO possible */
4751                 }
4752
4753                 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4754                 snd_iprintf(buffer, "    period: %u\n", period);
4755
4756
4757                 /* rate = freq_const/period; */
4758                 rate = div_u64(freq_const, period);
4759
4760                 if (control & HDSPM_QuadSpeed) {
4761                         rate *= 4;
4762                 } else if (control & HDSPM_DoubleSpeed) {
4763                         rate *= 2;
4764                 }
4765
4766                 snd_iprintf(buffer, "  Frequency: %u Hz\n",
4767                                 (unsigned int) rate);
4768
4769                 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4770                 frames = ltc & 0xF;
4771                 ltc >>= 4;
4772                 frames += (ltc & 0x3) * 10;
4773                 ltc >>= 4;
4774                 seconds = ltc & 0xF;
4775                 ltc >>= 4;
4776                 seconds += (ltc & 0x7) * 10;
4777                 ltc >>= 4;
4778                 minutes = ltc & 0xF;
4779                 ltc >>= 4;
4780                 minutes += (ltc & 0x7) * 10;
4781                 ltc >>= 4;
4782                 hours = ltc & 0xF;
4783                 ltc >>= 4;
4784                 hours += (ltc & 0x3) * 10;
4785                 snd_iprintf(buffer,
4786                         "  LTC In: %02d:%02d:%02d:%02d\n",
4787                         hours, minutes, seconds, frames);
4788
4789         } else {
4790                 snd_iprintf(buffer, "No TCO module detected.\n");
4791         }
4792 }
4793
4794 static void
4795 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4796                          struct snd_info_buffer *buffer)
4797 {
4798         struct hdspm *hdspm = entry->private_data;
4799         unsigned int status, status2, control, freq;
4800
4801         char *pref_sync_ref;
4802         char *autosync_ref;
4803         char *system_clock_mode;
4804         char *insel;
4805         int x, x2;
4806
4807         status = hdspm_read(hdspm, HDSPM_statusRegister);
4808         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4809         control = hdspm->control_register;
4810         freq = hdspm_read(hdspm, HDSPM_timecodeRegister);
4811
4812         snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4813                         hdspm->card_name, hdspm->card->number + 1,
4814                         hdspm->firmware_rev,
4815                         (status2 & HDSPM_version0) |
4816                         (status2 & HDSPM_version1) | (status2 &
4817                                 HDSPM_version2));
4818
4819         snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4820                         (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4821                         hdspm->serial);
4822
4823         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4824                         hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4825
4826         snd_iprintf(buffer, "--- System ---\n");
4827
4828         snd_iprintf(buffer,
4829                 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4830                 status & HDSPM_audioIRQPending,
4831                 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4832                 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4833                 hdspm->irq_count);
4834         snd_iprintf(buffer,
4835                 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4836                 "estimated= %ld (bytes)\n",
4837                 ((status & HDSPM_BufferID) ? 1 : 0),
4838                 (status & HDSPM_BufferPositionMask),
4839                 (status & HDSPM_BufferPositionMask) %
4840                 (2 * (int)hdspm->period_bytes),
4841                 ((status & HDSPM_BufferPositionMask) - 64) %
4842                 (2 * (int)hdspm->period_bytes),
4843                 (long) hdspm_hw_pointer(hdspm) * 4);
4844
4845         snd_iprintf(buffer,
4846                 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4847                 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4848                 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4849                 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4850                 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4851         snd_iprintf(buffer,
4852                 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4853                 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4854                 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4855         snd_iprintf(buffer,
4856                 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4857                 "status2=0x%x\n",
4858                 hdspm->control_register, hdspm->control2_register,
4859                 status, status2);
4860
4861
4862         snd_iprintf(buffer, "--- Settings ---\n");
4863
4864         x = hdspm_get_latency(hdspm);
4865
4866         snd_iprintf(buffer,
4867                 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4868                 x, (unsigned long) hdspm->period_bytes);
4869
4870         snd_iprintf(buffer, "Line out: %s\n",
4871                 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4872
4873         switch (hdspm->control_register & HDSPM_InputMask) {
4874         case HDSPM_InputOptical:
4875                 insel = "Optical";
4876                 break;
4877         case HDSPM_InputCoaxial:
4878                 insel = "Coaxial";
4879                 break;
4880         default:
4881                 insel = "Unknown";
4882         }
4883
4884         snd_iprintf(buffer,
4885                 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4886                 "Auto Input %s\n",
4887                 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4888                 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4889                 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4890
4891
4892         if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4893                 system_clock_mode = "AutoSync";
4894         else
4895                 system_clock_mode = "Master";
4896         snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4897
4898         switch (hdspm_pref_sync_ref(hdspm)) {
4899         case HDSPM_SYNC_FROM_WORD:
4900                 pref_sync_ref = "Word Clock";
4901                 break;
4902         case HDSPM_SYNC_FROM_MADI:
4903                 pref_sync_ref = "MADI Sync";
4904                 break;
4905         case HDSPM_SYNC_FROM_TCO:
4906                 pref_sync_ref = "TCO";
4907                 break;
4908         case HDSPM_SYNC_FROM_SYNC_IN:
4909                 pref_sync_ref = "Sync In";
4910                 break;
4911         default:
4912                 pref_sync_ref = "XXXX Clock";
4913                 break;
4914         }
4915         snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4916                         pref_sync_ref);
4917
4918         snd_iprintf(buffer, "System Clock Frequency: %d\n",
4919                         hdspm->system_sample_rate);
4920
4921
4922         snd_iprintf(buffer, "--- Status:\n");
4923
4924         x = status & HDSPM_madiSync;
4925         x2 = status2 & HDSPM_wcSync;
4926
4927         snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4928                         (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4929                         "NoLock",
4930                         (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4931                         "NoLock");
4932
4933         switch (hdspm_autosync_ref(hdspm)) {
4934         case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4935                 autosync_ref = "Sync In";
4936                 break;
4937         case HDSPM_AUTOSYNC_FROM_TCO:
4938                 autosync_ref = "TCO";
4939                 break;
4940         case HDSPM_AUTOSYNC_FROM_WORD:
4941                 autosync_ref = "Word Clock";
4942                 break;
4943         case HDSPM_AUTOSYNC_FROM_MADI:
4944                 autosync_ref = "MADI Sync";
4945                 break;
4946         case HDSPM_AUTOSYNC_FROM_NONE:
4947                 autosync_ref = "Input not valid";
4948                 break;
4949         default:
4950                 autosync_ref = "---";
4951                 break;
4952         }
4953         snd_iprintf(buffer,
4954                 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4955                 autosync_ref, hdspm_external_sample_rate(hdspm),
4956                 (status & HDSPM_madiFreqMask) >> 22,
4957                 (status2 & HDSPM_wcFreqMask) >> 5);
4958
4959         snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4960                 (status & HDSPM_AB_int) ? "Coax" : "Optical",
4961                 (status & HDSPM_RX_64ch) ? "64 channels" :
4962                 "56 channels");
4963
4964         /* call readout function for TCO specific status */
4965         snd_hdspm_proc_read_tco(entry, buffer);
4966
4967         snd_iprintf(buffer, "\n");
4968 }
4969
4970 static void
4971 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
4972                           struct snd_info_buffer *buffer)
4973 {
4974         struct hdspm *hdspm = entry->private_data;
4975         unsigned int status;
4976         unsigned int status2;
4977         unsigned int timecode;
4978         unsigned int wcLock, wcSync;
4979         int pref_syncref;
4980         char *autosync_ref;
4981         int x;
4982
4983         status = hdspm_read(hdspm, HDSPM_statusRegister);
4984         status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4985         timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
4986
4987         snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
4988                     hdspm->card_name, hdspm->card->number + 1,
4989                     hdspm->firmware_rev);
4990
4991         snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4992                     hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4993
4994         snd_iprintf(buffer, "--- System ---\n");
4995
4996         snd_iprintf(buffer,
4997                     "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4998                     status & HDSPM_audioIRQPending,
4999                     (status & HDSPM_midi0IRQPending) ? 1 : 0,
5000                     (status & HDSPM_midi1IRQPending) ? 1 : 0,
5001                     hdspm->irq_count);
5002         snd_iprintf(buffer,
5003                     "HW pointer: id = %d, rawptr = %d (%d->%d) "
5004                     "estimated= %ld (bytes)\n",
5005                     ((status & HDSPM_BufferID) ? 1 : 0),
5006                     (status & HDSPM_BufferPositionMask),
5007                     (status & HDSPM_BufferPositionMask) %
5008                     (2 * (int)hdspm->period_bytes),
5009                     ((status & HDSPM_BufferPositionMask) - 64) %
5010                     (2 * (int)hdspm->period_bytes),
5011                     (long) hdspm_hw_pointer(hdspm) * 4);
5012
5013         snd_iprintf(buffer,
5014                     "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5015                     hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5016                     hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5017                     hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5018                     hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5019         snd_iprintf(buffer,
5020                     "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5021                     hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5022                     hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5023         snd_iprintf(buffer,
5024                     "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5025                     "status2=0x%x\n",
5026                     hdspm->control_register, hdspm->control2_register,
5027                     status, status2);
5028
5029         snd_iprintf(buffer, "--- Settings ---\n");
5030
5031         x = hdspm_get_latency(hdspm);
5032
5033         snd_iprintf(buffer,
5034                     "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5035                     x, (unsigned long) hdspm->period_bytes);
5036
5037         snd_iprintf(buffer, "Line out: %s\n",
5038                     (hdspm->
5039                      control_register & HDSPM_LineOut) ? "on " : "off");
5040
5041         snd_iprintf(buffer,
5042                     "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5043                     (hdspm->
5044                      control_register & HDSPM_clr_tms) ? "on" : "off",
5045                     (hdspm->
5046                      control_register & HDSPM_Emphasis) ? "on" : "off",
5047                     (hdspm->
5048                      control_register & HDSPM_Dolby) ? "on" : "off");
5049
5050
5051         pref_syncref = hdspm_pref_sync_ref(hdspm);
5052         if (pref_syncref == 0)
5053                 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5054         else
5055                 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5056                                 pref_syncref);
5057
5058         snd_iprintf(buffer, "System Clock Frequency: %d\n",
5059                     hdspm->system_sample_rate);
5060
5061         snd_iprintf(buffer, "Double speed: %s\n",
5062                         hdspm->control_register & HDSPM_DS_DoubleWire?
5063                         "Double wire" : "Single wire");
5064         snd_iprintf(buffer, "Quad speed: %s\n",
5065                         hdspm->control_register & HDSPM_QS_DoubleWire?
5066                         "Double wire" :
5067                         hdspm->control_register & HDSPM_QS_QuadWire?
5068                         "Quad wire" : "Single wire");
5069
5070         snd_iprintf(buffer, "--- Status:\n");
5071
5072         wcLock = status & HDSPM_AES32_wcLock;
5073         wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5074
5075         snd_iprintf(buffer, "Word: %s  Frequency: %d\n",
5076                     (wcLock) ? (wcSync ? "Sync   " : "Lock   ") : "No Lock",
5077                     HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5078
5079         for (x = 0; x < 8; x++) {
5080                 snd_iprintf(buffer, "AES%d: %s  Frequency: %d\n",
5081                             x+1,
5082                             (status2 & (HDSPM_LockAES >> x)) ?
5083                             "Sync   " : "No Lock",
5084                             HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5085         }
5086
5087         switch (hdspm_autosync_ref(hdspm)) {
5088         case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5089                 autosync_ref = "None"; break;
5090         case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5091                 autosync_ref = "Word Clock"; break;
5092         case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5093                 autosync_ref = "AES1"; break;
5094         case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5095                 autosync_ref = "AES2"; break;
5096         case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5097                 autosync_ref = "AES3"; break;
5098         case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5099                 autosync_ref = "AES4"; break;
5100         case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5101                 autosync_ref = "AES5"; break;
5102         case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5103                 autosync_ref = "AES6"; break;
5104         case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5105                 autosync_ref = "AES7"; break;
5106         case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5107                 autosync_ref = "AES8"; break;
5108         default:
5109                 autosync_ref = "---"; break;
5110         }
5111         snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5112
5113         snd_iprintf(buffer, "\n");
5114 }
5115
5116 static void
5117 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5118                          struct snd_info_buffer *buffer)
5119 {
5120         struct hdspm *hdspm = entry->private_data;
5121         unsigned int status1, status2, status3, control, i;
5122         unsigned int lock, sync;
5123
5124         status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5125         status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5126         status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5127
5128         control = hdspm->control_register;
5129
5130         snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5131         snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5132         snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5133
5134
5135         snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5136
5137         snd_iprintf(buffer, "Clock mode      : %s\n",
5138                 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5139         snd_iprintf(buffer, "System frequency: %d Hz\n",
5140                 hdspm_get_system_sample_rate(hdspm));
5141
5142         snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5143
5144         lock = 0x1;
5145         sync = 0x100;
5146
5147         for (i = 0; i < 8; i++) {
5148                 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5149                                 i,
5150                                 (status1 & lock) ? 1 : 0,
5151                                 (status1 & sync) ? 1 : 0,
5152                                 texts_freq[(status2 >> (i * 4)) & 0xF]);
5153
5154                 lock = lock<<1;
5155                 sync = sync<<1;
5156         }
5157
5158         snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5159                         (status1 & 0x1000000) ? 1 : 0,
5160                         (status1 & 0x2000000) ? 1 : 0,
5161                         texts_freq[(status1 >> 16) & 0xF]);
5162
5163         snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5164                         (status1 & 0x4000000) ? 1 : 0,
5165                         (status1 & 0x8000000) ? 1 : 0,
5166                         texts_freq[(status1 >> 20) & 0xF]);
5167
5168         snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5169                         (status3 & 0x400) ? 1 : 0,
5170                         (status3 & 0x800) ? 1 : 0,
5171                         texts_freq[(status2 >> 12) & 0xF]);
5172
5173 }
5174
5175 #ifdef CONFIG_SND_DEBUG
5176 static void
5177 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5178                           struct snd_info_buffer *buffer)
5179 {
5180         struct hdspm *hdspm = entry->private_data;
5181
5182         int j,i;
5183
5184         for (i = 0; i < 256 /* 1024*64 */; i += j) {
5185                 snd_iprintf(buffer, "0x%08X: ", i);
5186                 for (j = 0; j < 16; j += 4)
5187                         snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5188                 snd_iprintf(buffer, "\n");
5189         }
5190 }
5191 #endif
5192
5193
5194 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5195                           struct snd_info_buffer *buffer)
5196 {
5197         struct hdspm *hdspm = entry->private_data;
5198         int i;
5199
5200         snd_iprintf(buffer, "# generated by hdspm\n");
5201
5202         for (i = 0; i < hdspm->max_channels_in; i++) {
5203                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5204         }
5205 }
5206
5207 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5208                           struct snd_info_buffer *buffer)
5209 {
5210         struct hdspm *hdspm = entry->private_data;
5211         int i;
5212
5213         snd_iprintf(buffer, "# generated by hdspm\n");
5214
5215         for (i = 0; i < hdspm->max_channels_out; i++) {
5216                 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5217         }
5218 }
5219
5220
5221 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5222 {
5223         struct snd_info_entry *entry;
5224
5225         if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5226                 switch (hdspm->io_type) {
5227                 case AES32:
5228                         snd_info_set_text_ops(entry, hdspm,
5229                                         snd_hdspm_proc_read_aes32);
5230                         break;
5231                 case MADI:
5232                         snd_info_set_text_ops(entry, hdspm,
5233                                         snd_hdspm_proc_read_madi);
5234                         break;
5235                 case MADIface:
5236                         /* snd_info_set_text_ops(entry, hdspm,
5237                          snd_hdspm_proc_read_madiface); */
5238                         break;
5239                 case RayDAT:
5240                         snd_info_set_text_ops(entry, hdspm,
5241                                         snd_hdspm_proc_read_raydat);
5242                         break;
5243                 case AIO:
5244                         break;
5245                 }
5246         }
5247
5248         if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5249                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5250         }
5251
5252         if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5253                 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5254         }
5255
5256 #ifdef CONFIG_SND_DEBUG
5257         /* debug file to read all hdspm registers */
5258         if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5259                 snd_info_set_text_ops(entry, hdspm,
5260                                 snd_hdspm_proc_read_debug);
5261 #endif
5262 }
5263
5264 /*------------------------------------------------------------
5265    hdspm intitialize
5266  ------------------------------------------------------------*/
5267
5268 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5269 {
5270         /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5271            hold it (e.g. during module initialization).
5272            */
5273
5274         /* set defaults:       */
5275
5276         hdspm->settings_register = 0;
5277
5278         switch (hdspm->io_type) {
5279         case MADI:
5280         case MADIface:
5281                 hdspm->control_register =
5282                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5283                 break;
5284
5285         case RayDAT:
5286         case AIO:
5287                 hdspm->settings_register = 0x1 + 0x1000;
5288                 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5289                  * line_out */
5290                 hdspm->control_register =
5291                         0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5292                 break;
5293
5294         case AES32:
5295                 hdspm->control_register =
5296                         HDSPM_ClockModeMaster | /* Master Clock Mode on */
5297                         hdspm_encode_latency(7) | /* latency max=8192samples */
5298                         HDSPM_SyncRef0 |        /* AES1 is syncclock */
5299                         HDSPM_LineOut | /* Analog output in */
5300                         HDSPM_Professional;  /* Professional mode */
5301                 break;
5302         }
5303
5304         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5305
5306         if (AES32 == hdspm->io_type) {
5307                 /* No control2 register for AES32 */
5308 #ifdef SNDRV_BIG_ENDIAN
5309                 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5310 #else
5311                 hdspm->control2_register = 0;
5312 #endif
5313
5314                 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5315         }
5316         hdspm_compute_period_size(hdspm);
5317
5318         /* silence everything */
5319
5320         all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5321
5322         if (hdspm_is_raydat_or_aio(hdspm))
5323                 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5324
5325         /* set a default rate so that the channel map is set up. */
5326         hdspm_set_rate(hdspm, 48000, 1);
5327
5328         return 0;
5329 }
5330
5331
5332 /*------------------------------------------------------------
5333    interrupt
5334  ------------------------------------------------------------*/
5335
5336 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5337 {
5338         struct hdspm *hdspm = (struct hdspm *) dev_id;
5339         unsigned int status;
5340         int i, audio, midi, schedule = 0;
5341         /* cycles_t now; */
5342
5343         status = hdspm_read(hdspm, HDSPM_statusRegister);
5344
5345         audio = status & HDSPM_audioIRQPending;
5346         midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5347                         HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5348
5349         /* now = get_cycles(); */
5350         /**
5351          *   LAT_2..LAT_0 period  counter (win)  counter (mac)
5352          *          6       4096   ~256053425     ~514672358
5353          *          5       2048   ~128024983     ~257373821
5354          *          4       1024    ~64023706     ~128718089
5355          *          3        512    ~32005945      ~64385999
5356          *          2        256    ~16003039      ~32260176
5357          *          1        128     ~7998738      ~16194507
5358          *          0         64     ~3998231       ~8191558
5359          **/
5360         /*
5361            snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5362            now-hdspm->last_interrupt, status & 0xFFC0);
5363            hdspm->last_interrupt = now;
5364         */
5365
5366         if (!audio && !midi)
5367                 return IRQ_NONE;
5368
5369         hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5370         hdspm->irq_count++;
5371
5372
5373         if (audio) {
5374                 if (hdspm->capture_substream)
5375                         snd_pcm_period_elapsed(hdspm->capture_substream);
5376
5377                 if (hdspm->playback_substream)
5378                         snd_pcm_period_elapsed(hdspm->playback_substream);
5379         }
5380
5381         if (midi) {
5382                 i = 0;
5383                 while (i < hdspm->midiPorts) {
5384                         if ((hdspm_read(hdspm,
5385                                 hdspm->midi[i].statusIn) & 0xff) &&
5386                                         (status & hdspm->midi[i].irq)) {
5387                                 /* we disable interrupts for this input until
5388                                  * processing is done
5389                                  */
5390                                 hdspm->control_register &= ~hdspm->midi[i].ie;
5391                                 hdspm_write(hdspm, HDSPM_controlRegister,
5392                                                 hdspm->control_register);
5393                                 hdspm->midi[i].pending = 1;
5394                                 schedule = 1;
5395                         }
5396
5397                         i++;
5398                 }
5399
5400                 if (schedule)
5401                         tasklet_hi_schedule(&hdspm->midi_tasklet);
5402         }
5403
5404         return IRQ_HANDLED;
5405 }
5406
5407 /*------------------------------------------------------------
5408    pcm interface
5409   ------------------------------------------------------------*/
5410
5411
5412 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5413                                               *substream)
5414 {
5415         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5416         return hdspm_hw_pointer(hdspm);
5417 }
5418
5419
5420 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5421 {
5422         struct snd_pcm_runtime *runtime = substream->runtime;
5423         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5424         struct snd_pcm_substream *other;
5425
5426         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5427                 other = hdspm->capture_substream;
5428         else
5429                 other = hdspm->playback_substream;
5430
5431         if (hdspm->running)
5432                 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5433         else
5434                 runtime->status->hw_ptr = 0;
5435         if (other) {
5436                 struct snd_pcm_substream *s;
5437                 struct snd_pcm_runtime *oruntime = other->runtime;
5438                 snd_pcm_group_for_each_entry(s, substream) {
5439                         if (s == other) {
5440                                 oruntime->status->hw_ptr =
5441                                         runtime->status->hw_ptr;
5442                                 break;
5443                         }
5444                 }
5445         }
5446         return 0;
5447 }
5448
5449 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5450                                struct snd_pcm_hw_params *params)
5451 {
5452         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5453         int err;
5454         int i;
5455         pid_t this_pid;
5456         pid_t other_pid;
5457
5458         spin_lock_irq(&hdspm->lock);
5459
5460         if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5461                 this_pid = hdspm->playback_pid;
5462                 other_pid = hdspm->capture_pid;
5463         } else {
5464                 this_pid = hdspm->capture_pid;
5465                 other_pid = hdspm->playback_pid;
5466         }
5467
5468         if (other_pid > 0 && this_pid != other_pid) {
5469
5470                 /* The other stream is open, and not by the same
5471                    task as this one. Make sure that the parameters
5472                    that matter are the same.
5473                    */
5474
5475                 if (params_rate(params) != hdspm->system_sample_rate) {
5476                         spin_unlock_irq(&hdspm->lock);
5477                         _snd_pcm_hw_param_setempty(params,
5478                                         SNDRV_PCM_HW_PARAM_RATE);
5479                         return -EBUSY;
5480                 }
5481
5482                 if (params_period_size(params) != hdspm->period_bytes / 4) {
5483                         spin_unlock_irq(&hdspm->lock);
5484                         _snd_pcm_hw_param_setempty(params,
5485                                         SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5486                         return -EBUSY;
5487                 }
5488
5489         }
5490         /* We're fine. */
5491         spin_unlock_irq(&hdspm->lock);
5492
5493         /* how to make sure that the rate matches an externally-set one ?   */
5494
5495         spin_lock_irq(&hdspm->lock);
5496         err = hdspm_set_rate(hdspm, params_rate(params), 0);
5497         if (err < 0) {
5498                 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err);
5499                 spin_unlock_irq(&hdspm->lock);
5500                 _snd_pcm_hw_param_setempty(params,
5501                                 SNDRV_PCM_HW_PARAM_RATE);
5502                 return err;
5503         }
5504         spin_unlock_irq(&hdspm->lock);
5505
5506         err = hdspm_set_interrupt_interval(hdspm,
5507                         params_period_size(params));
5508         if (err < 0) {
5509                 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err);
5510                 _snd_pcm_hw_param_setempty(params,
5511                                 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5512                 return err;
5513         }
5514
5515         /* Memory allocation, takashi's method, dont know if we should
5516          * spinlock
5517          */
5518         /* malloc all buffer even if not enabled to get sure */
5519         /* Update for MADI rev 204: we need to allocate for all channels,
5520          * otherwise it doesn't work at 96kHz */
5521
5522         err =
5523                 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5524         if (err < 0) {
5525                 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err);
5526                 return err;
5527         }
5528
5529         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5530
5531                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5532                                 params_channels(params));
5533
5534                 for (i = 0; i < params_channels(params); ++i)
5535                         snd_hdspm_enable_out(hdspm, i, 1);
5536
5537                 hdspm->playback_buffer =
5538                         (unsigned char *) substream->runtime->dma_area;
5539                 snd_printdd("Allocated sample buffer for playback at %p\n",
5540                                 hdspm->playback_buffer);
5541         } else {
5542                 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5543                                 params_channels(params));
5544
5545                 for (i = 0; i < params_channels(params); ++i)
5546                         snd_hdspm_enable_in(hdspm, i, 1);
5547
5548                 hdspm->capture_buffer =
5549                         (unsigned char *) substream->runtime->dma_area;
5550                 snd_printdd("Allocated sample buffer for capture at %p\n",
5551                                 hdspm->capture_buffer);
5552         }
5553
5554         /*
5555            snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5556            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5557            "playback" : "capture",
5558            snd_pcm_sgbuf_get_addr(substream, 0));
5559            */
5560         /*
5561            snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5562            substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5563            "playback" : "capture",
5564            params_rate(params), params_channels(params),
5565            params_buffer_size(params));
5566            */
5567
5568
5569         /*  For AES cards, the float format bit is the same as the
5570          *  preferred sync reference. Since we don't want to break
5571          *  sync settings, we have to skip the remaining part of this
5572          *  function.
5573          */
5574         if (hdspm->io_type == AES32) {
5575                 return 0;
5576         }
5577
5578
5579         /* Switch to native float format if requested */
5580         if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5581                 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5582                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n");
5583
5584                 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5585         } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5586                 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5587                         snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n");
5588
5589                 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5590         }
5591         hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5592
5593         return 0;
5594 }
5595
5596 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5597 {
5598         int i;
5599         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5600
5601         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5602
5603                 /* params_channels(params) should be enough,
5604                    but to get sure in case of error */
5605                 for (i = 0; i < hdspm->max_channels_out; ++i)
5606                         snd_hdspm_enable_out(hdspm, i, 0);
5607
5608                 hdspm->playback_buffer = NULL;
5609         } else {
5610                 for (i = 0; i < hdspm->max_channels_in; ++i)
5611                         snd_hdspm_enable_in(hdspm, i, 0);
5612
5613                 hdspm->capture_buffer = NULL;
5614
5615         }
5616
5617         snd_pcm_lib_free_pages(substream);
5618
5619         return 0;
5620 }
5621
5622
5623 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5624                 struct snd_pcm_channel_info *info)
5625 {
5626         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5627
5628         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5629                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) {
5630                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel);
5631                         return -EINVAL;
5632                 }
5633
5634                 if (hdspm->channel_map_out[info->channel] < 0) {
5635                         snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel);
5636                         return -EINVAL;
5637                 }
5638
5639                 info->offset = hdspm->channel_map_out[info->channel] *
5640                         HDSPM_CHANNEL_BUFFER_BYTES;
5641         } else {
5642                 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) {
5643                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel);
5644                         return -EINVAL;
5645                 }
5646
5647                 if (hdspm->channel_map_in[info->channel] < 0) {
5648                         snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel);
5649                         return -EINVAL;
5650                 }
5651
5652                 info->offset = hdspm->channel_map_in[info->channel] *
5653                         HDSPM_CHANNEL_BUFFER_BYTES;
5654         }
5655
5656         info->first = 0;
5657         info->step = 32;
5658         return 0;
5659 }
5660
5661
5662 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5663                 unsigned int cmd, void *arg)
5664 {
5665         switch (cmd) {
5666         case SNDRV_PCM_IOCTL1_RESET:
5667                 return snd_hdspm_reset(substream);
5668
5669         case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5670                 {
5671                         struct snd_pcm_channel_info *info = arg;
5672                         return snd_hdspm_channel_info(substream, info);
5673                 }
5674         default:
5675                 break;
5676         }
5677
5678         return snd_pcm_lib_ioctl(substream, cmd, arg);
5679 }
5680
5681 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5682 {
5683         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5684         struct snd_pcm_substream *other;
5685         int running;
5686
5687         spin_lock(&hdspm->lock);
5688         running = hdspm->running;
5689         switch (cmd) {
5690         case SNDRV_PCM_TRIGGER_START:
5691                 running |= 1 << substream->stream;
5692                 break;
5693         case SNDRV_PCM_TRIGGER_STOP:
5694                 running &= ~(1 << substream->stream);
5695                 break;
5696         default:
5697                 snd_BUG();
5698                 spin_unlock(&hdspm->lock);
5699                 return -EINVAL;
5700         }
5701         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5702                 other = hdspm->capture_substream;
5703         else
5704                 other = hdspm->playback_substream;
5705
5706         if (other) {
5707                 struct snd_pcm_substream *s;
5708                 snd_pcm_group_for_each_entry(s, substream) {
5709                         if (s == other) {
5710                                 snd_pcm_trigger_done(s, substream);
5711                                 if (cmd == SNDRV_PCM_TRIGGER_START)
5712                                         running |= 1 << s->stream;
5713                                 else
5714                                         running &= ~(1 << s->stream);
5715                                 goto _ok;
5716                         }
5717                 }
5718                 if (cmd == SNDRV_PCM_TRIGGER_START) {
5719                         if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5720                                         && substream->stream ==
5721                                         SNDRV_PCM_STREAM_CAPTURE)
5722                                 hdspm_silence_playback(hdspm);
5723                 } else {
5724                         if (running &&
5725                                 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5726                                 hdspm_silence_playback(hdspm);
5727                 }
5728         } else {
5729                 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5730                         hdspm_silence_playback(hdspm);
5731         }
5732 _ok:
5733         snd_pcm_trigger_done(substream, substream);
5734         if (!hdspm->running && running)
5735                 hdspm_start_audio(hdspm);
5736         else if (hdspm->running && !running)
5737                 hdspm_stop_audio(hdspm);
5738         hdspm->running = running;
5739         spin_unlock(&hdspm->lock);
5740
5741         return 0;
5742 }
5743
5744 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5745 {
5746         return 0;
5747 }
5748
5749 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5750         .info = (SNDRV_PCM_INFO_MMAP |
5751                  SNDRV_PCM_INFO_MMAP_VALID |
5752                  SNDRV_PCM_INFO_NONINTERLEAVED |
5753                  SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5754         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5755         .rates = (SNDRV_PCM_RATE_32000 |
5756                   SNDRV_PCM_RATE_44100 |
5757                   SNDRV_PCM_RATE_48000 |
5758                   SNDRV_PCM_RATE_64000 |
5759                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5760                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5761         .rate_min = 32000,
5762         .rate_max = 192000,
5763         .channels_min = 1,
5764         .channels_max = HDSPM_MAX_CHANNELS,
5765         .buffer_bytes_max =
5766             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5767         .period_bytes_min = (32 * 4),
5768         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5769         .periods_min = 2,
5770         .periods_max = 512,
5771         .fifo_size = 0
5772 };
5773
5774 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5775         .info = (SNDRV_PCM_INFO_MMAP |
5776                  SNDRV_PCM_INFO_MMAP_VALID |
5777                  SNDRV_PCM_INFO_NONINTERLEAVED |
5778                  SNDRV_PCM_INFO_SYNC_START),
5779         .formats = SNDRV_PCM_FMTBIT_S32_LE,
5780         .rates = (SNDRV_PCM_RATE_32000 |
5781                   SNDRV_PCM_RATE_44100 |
5782                   SNDRV_PCM_RATE_48000 |
5783                   SNDRV_PCM_RATE_64000 |
5784                   SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5785                   SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5786         .rate_min = 32000,
5787         .rate_max = 192000,
5788         .channels_min = 1,
5789         .channels_max = HDSPM_MAX_CHANNELS,
5790         .buffer_bytes_max =
5791             HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5792         .period_bytes_min = (32 * 4),
5793         .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5794         .periods_min = 2,
5795         .periods_max = 512,
5796         .fifo_size = 0
5797 };
5798
5799 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5800                                            struct snd_pcm_hw_rule *rule)
5801 {
5802         struct hdspm *hdspm = rule->private;
5803         struct snd_interval *c =
5804             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5805         struct snd_interval *r =
5806             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5807
5808         if (r->min > 96000 && r->max <= 192000) {
5809                 struct snd_interval t = {
5810                         .min = hdspm->qs_in_channels,
5811                         .max = hdspm->qs_in_channels,
5812                         .integer = 1,
5813                 };
5814                 return snd_interval_refine(c, &t);
5815         } else if (r->min > 48000 && r->max <= 96000) {
5816                 struct snd_interval t = {
5817                         .min = hdspm->ds_in_channels,
5818                         .max = hdspm->ds_in_channels,
5819                         .integer = 1,
5820                 };
5821                 return snd_interval_refine(c, &t);
5822         } else if (r->max < 64000) {
5823                 struct snd_interval t = {
5824                         .min = hdspm->ss_in_channels,
5825                         .max = hdspm->ss_in_channels,
5826                         .integer = 1,
5827                 };
5828                 return snd_interval_refine(c, &t);
5829         }
5830
5831         return 0;
5832 }
5833
5834 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5835                                            struct snd_pcm_hw_rule * rule)
5836 {
5837         struct hdspm *hdspm = rule->private;
5838         struct snd_interval *c =
5839             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5840         struct snd_interval *r =
5841             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5842
5843         if (r->min > 96000 && r->max <= 192000) {
5844                 struct snd_interval t = {
5845                         .min = hdspm->qs_out_channels,
5846                         .max = hdspm->qs_out_channels,
5847                         .integer = 1,
5848                 };
5849                 return snd_interval_refine(c, &t);
5850         } else if (r->min > 48000 && r->max <= 96000) {
5851                 struct snd_interval t = {
5852                         .min = hdspm->ds_out_channels,
5853                         .max = hdspm->ds_out_channels,
5854                         .integer = 1,
5855                 };
5856                 return snd_interval_refine(c, &t);
5857         } else if (r->max < 64000) {
5858                 struct snd_interval t = {
5859                         .min = hdspm->ss_out_channels,
5860                         .max = hdspm->ss_out_channels,
5861                         .integer = 1,
5862                 };
5863                 return snd_interval_refine(c, &t);
5864         } else {
5865         }
5866         return 0;
5867 }
5868
5869 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5870                                            struct snd_pcm_hw_rule * rule)
5871 {
5872         struct hdspm *hdspm = rule->private;
5873         struct snd_interval *c =
5874             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5875         struct snd_interval *r =
5876             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5877
5878         if (c->min >= hdspm->ss_in_channels) {
5879                 struct snd_interval t = {
5880                         .min = 32000,
5881                         .max = 48000,
5882                         .integer = 1,
5883                 };
5884                 return snd_interval_refine(r, &t);
5885         } else if (c->max <= hdspm->qs_in_channels) {
5886                 struct snd_interval t = {
5887                         .min = 128000,
5888                         .max = 192000,
5889                         .integer = 1,
5890                 };
5891                 return snd_interval_refine(r, &t);
5892         } else if (c->max <= hdspm->ds_in_channels) {
5893                 struct snd_interval t = {
5894                         .min = 64000,
5895                         .max = 96000,
5896                         .integer = 1,
5897                 };
5898                 return snd_interval_refine(r, &t);
5899         }
5900
5901         return 0;
5902 }
5903 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5904                                            struct snd_pcm_hw_rule *rule)
5905 {
5906         struct hdspm *hdspm = rule->private;
5907         struct snd_interval *c =
5908             hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5909         struct snd_interval *r =
5910             hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5911
5912         if (c->min >= hdspm->ss_out_channels) {
5913                 struct snd_interval t = {
5914                         .min = 32000,
5915                         .max = 48000,
5916                         .integer = 1,
5917                 };
5918                 return snd_interval_refine(r, &t);
5919         } else if (c->max <= hdspm->qs_out_channels) {
5920                 struct snd_interval t = {
5921                         .min = 128000,
5922                         .max = 192000,
5923                         .integer = 1,
5924                 };
5925                 return snd_interval_refine(r, &t);
5926         } else if (c->max <= hdspm->ds_out_channels) {
5927                 struct snd_interval t = {
5928                         .min = 64000,
5929                         .max = 96000,
5930                         .integer = 1,
5931                 };
5932                 return snd_interval_refine(r, &t);
5933         }
5934
5935         return 0;
5936 }
5937
5938 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
5939                                       struct snd_pcm_hw_rule *rule)
5940 {
5941         unsigned int list[3];
5942         struct hdspm *hdspm = rule->private;
5943         struct snd_interval *c = hw_param_interval(params,
5944                         SNDRV_PCM_HW_PARAM_CHANNELS);
5945
5946         list[0] = hdspm->qs_in_channels;
5947         list[1] = hdspm->ds_in_channels;
5948         list[2] = hdspm->ss_in_channels;
5949         return snd_interval_list(c, 3, list, 0);
5950 }
5951
5952 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
5953                                       struct snd_pcm_hw_rule *rule)
5954 {
5955         unsigned int list[3];
5956         struct hdspm *hdspm = rule->private;
5957         struct snd_interval *c = hw_param_interval(params,
5958                         SNDRV_PCM_HW_PARAM_CHANNELS);
5959
5960         list[0] = hdspm->qs_out_channels;
5961         list[1] = hdspm->ds_out_channels;
5962         list[2] = hdspm->ss_out_channels;
5963         return snd_interval_list(c, 3, list, 0);
5964 }
5965
5966
5967 static unsigned int hdspm_aes32_sample_rates[] = {
5968         32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5969 };
5970
5971 static struct snd_pcm_hw_constraint_list
5972 hdspm_hw_constraints_aes32_sample_rates = {
5973         .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
5974         .list = hdspm_aes32_sample_rates,
5975         .mask = 0
5976 };
5977
5978 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream)
5979 {
5980         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5981         struct snd_pcm_runtime *runtime = substream->runtime;
5982
5983         spin_lock_irq(&hdspm->lock);
5984
5985         snd_pcm_set_sync(substream);
5986
5987
5988         runtime->hw = snd_hdspm_playback_subinfo;
5989
5990         if (hdspm->capture_substream == NULL)
5991                 hdspm_stop_audio(hdspm);
5992
5993         hdspm->playback_pid = current->pid;
5994         hdspm->playback_substream = substream;
5995
5996         spin_unlock_irq(&hdspm->lock);
5997
5998         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
5999         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6000
6001         switch (hdspm->io_type) {
6002         case AIO:
6003         case RayDAT:
6004                 snd_pcm_hw_constraint_minmax(runtime,
6005                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6006                                              32, 4096);
6007                 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6008                 snd_pcm_hw_constraint_minmax(runtime,
6009                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6010                                              16384, 16384);
6011                 break;
6012
6013         default:
6014                 snd_pcm_hw_constraint_minmax(runtime,
6015                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6016                                              64, 8192);
6017                 break;
6018         }
6019
6020         if (AES32 == hdspm->io_type) {
6021                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6022                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6023                                 &hdspm_hw_constraints_aes32_sample_rates);
6024         } else {
6025                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6026                                 snd_hdspm_hw_rule_rate_out_channels, hdspm,
6027                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6028         }
6029
6030         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6031                         snd_hdspm_hw_rule_out_channels, hdspm,
6032                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6033
6034         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6035                         snd_hdspm_hw_rule_out_channels_rate, hdspm,
6036                         SNDRV_PCM_HW_PARAM_RATE, -1);
6037
6038         return 0;
6039 }
6040
6041 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream)
6042 {
6043         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6044
6045         spin_lock_irq(&hdspm->lock);
6046
6047         hdspm->playback_pid = -1;
6048         hdspm->playback_substream = NULL;
6049
6050         spin_unlock_irq(&hdspm->lock);
6051
6052         return 0;
6053 }
6054
6055
6056 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream)
6057 {
6058         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6059         struct snd_pcm_runtime *runtime = substream->runtime;
6060
6061         spin_lock_irq(&hdspm->lock);
6062         snd_pcm_set_sync(substream);
6063         runtime->hw = snd_hdspm_capture_subinfo;
6064
6065         if (hdspm->playback_substream == NULL)
6066                 hdspm_stop_audio(hdspm);
6067
6068         hdspm->capture_pid = current->pid;
6069         hdspm->capture_substream = substream;
6070
6071         spin_unlock_irq(&hdspm->lock);
6072
6073         snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6074         snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6075
6076         switch (hdspm->io_type) {
6077         case AIO:
6078         case RayDAT:
6079                 snd_pcm_hw_constraint_minmax(runtime,
6080                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6081                                              32, 4096);
6082                 snd_pcm_hw_constraint_minmax(runtime,
6083                                              SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6084                                              16384, 16384);
6085                 break;
6086
6087         default:
6088                 snd_pcm_hw_constraint_minmax(runtime,
6089                                              SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6090                                              64, 8192);
6091                 break;
6092         }
6093
6094         if (AES32 == hdspm->io_type) {
6095                 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6096                 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6097                                 &hdspm_hw_constraints_aes32_sample_rates);
6098         } else {
6099                 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6100                                 snd_hdspm_hw_rule_rate_in_channels, hdspm,
6101                                 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6102         }
6103
6104         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6105                         snd_hdspm_hw_rule_in_channels, hdspm,
6106                         SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6107
6108         snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6109                         snd_hdspm_hw_rule_in_channels_rate, hdspm,
6110                         SNDRV_PCM_HW_PARAM_RATE, -1);
6111
6112         return 0;
6113 }
6114
6115 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream)
6116 {
6117         struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6118
6119         spin_lock_irq(&hdspm->lock);
6120
6121         hdspm->capture_pid = -1;
6122         hdspm->capture_substream = NULL;
6123
6124         spin_unlock_irq(&hdspm->lock);
6125         return 0;
6126 }
6127
6128 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6129 {
6130         /* we have nothing to initialize but the call is required */
6131         return 0;
6132 }
6133
6134 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6135 {
6136         u32 val = readl(src);
6137         return copy_to_user(dest, &val, 4);
6138 }
6139
6140 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6141                 unsigned int cmd, unsigned long arg)
6142 {
6143         void __user *argp = (void __user *)arg;
6144         struct hdspm *hdspm = hw->private_data;
6145         struct hdspm_mixer_ioctl mixer;
6146         struct hdspm_config info;
6147         struct hdspm_status status;
6148         struct hdspm_version hdspm_version;
6149         struct hdspm_peak_rms *levels;
6150         struct hdspm_ltc ltc;
6151         unsigned int statusregister;
6152         long unsigned int s;
6153         int i = 0;
6154
6155         switch (cmd) {
6156
6157         case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6158                 levels = &hdspm->peak_rms;
6159                 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6160                         levels->input_peaks[i] =
6161                                 readl(hdspm->iobase +
6162                                                 HDSPM_MADI_INPUT_PEAK + i*4);
6163                         levels->playback_peaks[i] =
6164                                 readl(hdspm->iobase +
6165                                                 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6166                         levels->output_peaks[i] =
6167                                 readl(hdspm->iobase +
6168                                                 HDSPM_MADI_OUTPUT_PEAK + i*4);
6169
6170                         levels->input_rms[i] =
6171                                 ((uint64_t) readl(hdspm->iobase +
6172                                         HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6173                                 (uint64_t) readl(hdspm->iobase +
6174                                                 HDSPM_MADI_INPUT_RMS_L + i*4);
6175                         levels->playback_rms[i] =
6176                                 ((uint64_t)readl(hdspm->iobase +
6177                                         HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6178                                 (uint64_t)readl(hdspm->iobase +
6179                                         HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6180                         levels->output_rms[i] =
6181                                 ((uint64_t)readl(hdspm->iobase +
6182                                         HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6183                                 (uint64_t)readl(hdspm->iobase +
6184                                                 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6185                 }
6186
6187                 if (hdspm->system_sample_rate > 96000) {
6188                         levels->speed = qs;
6189                 } else if (hdspm->system_sample_rate > 48000) {
6190                         levels->speed = ds;
6191                 } else {
6192                         levels->speed = ss;
6193                 }
6194                 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6195
6196                 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms));
6197                 if (0 != s) {
6198                         /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
6199                          [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6200                          */
6201                         return -EFAULT;
6202                 }
6203                 break;
6204
6205         case SNDRV_HDSPM_IOCTL_GET_LTC:
6206                 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6207                 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6208                 if (i & HDSPM_TCO1_LTC_Input_valid) {
6209                         switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6210                                 HDSPM_TCO1_LTC_Format_MSB)) {
6211                         case 0:
6212                                 ltc.format = fps_24;
6213                                 break;
6214                         case HDSPM_TCO1_LTC_Format_LSB:
6215                                 ltc.format = fps_25;
6216                                 break;
6217                         case HDSPM_TCO1_LTC_Format_MSB:
6218                                 ltc.format = fps_2997;
6219                                 break;
6220                         default:
6221                                 ltc.format = 30;
6222                                 break;
6223                         }
6224                         if (i & HDSPM_TCO1_set_drop_frame_flag) {
6225                                 ltc.frame = drop_frame;
6226                         } else {
6227                                 ltc.frame = full_frame;
6228                         }
6229                 } else {
6230                         ltc.format = format_invalid;
6231                         ltc.frame = frame_invalid;
6232                 }
6233                 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6234                         ltc.input_format = ntsc;
6235                 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6236                         ltc.input_format = pal;
6237                 } else {
6238                         ltc.input_format = no_video;
6239                 }
6240
6241                 s = copy_to_user(argp, &ltc, sizeof(struct hdspm_ltc));
6242                 if (0 != s) {
6243                         /*
6244                          snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6245                         return -EFAULT;
6246                 }
6247
6248                 break;
6249
6250         case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6251
6252                 memset(&info, 0, sizeof(info));
6253                 spin_lock_irq(&hdspm->lock);
6254                 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6255                 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6256
6257                 info.system_sample_rate = hdspm->system_sample_rate;
6258                 info.autosync_sample_rate =
6259                         hdspm_external_sample_rate(hdspm);
6260                 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6261                 info.clock_source = hdspm_clock_source(hdspm);
6262                 info.autosync_ref = hdspm_autosync_ref(hdspm);
6263                 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6264                 info.passthru = 0;
6265                 spin_unlock_irq(&hdspm->lock);
6266                 if (copy_to_user(argp, &info, sizeof(info)))
6267                         return -EFAULT;
6268                 break;
6269
6270         case SNDRV_HDSPM_IOCTL_GET_STATUS:
6271                 memset(&status, 0, sizeof(status));
6272
6273                 status.card_type = hdspm->io_type;
6274
6275                 status.autosync_source = hdspm_autosync_ref(hdspm);
6276
6277                 status.card_clock = 110069313433624ULL;
6278                 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6279
6280                 switch (hdspm->io_type) {
6281                 case MADI:
6282                 case MADIface:
6283                         status.card_specific.madi.sync_wc =
6284                                 hdspm_wc_sync_check(hdspm);
6285                         status.card_specific.madi.sync_madi =
6286                                 hdspm_madi_sync_check(hdspm);
6287                         status.card_specific.madi.sync_tco =
6288                                 hdspm_tco_sync_check(hdspm);
6289                         status.card_specific.madi.sync_in =
6290                                 hdspm_sync_in_sync_check(hdspm);
6291
6292                         statusregister =
6293                                 hdspm_read(hdspm, HDSPM_statusRegister);
6294                         status.card_specific.madi.madi_input =
6295                                 (statusregister & HDSPM_AB_int) ? 1 : 0;
6296                         status.card_specific.madi.channel_format =
6297                                 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6298                         /* TODO: Mac driver sets it when f_s>48kHz */
6299                         status.card_specific.madi.frame_format = 0;
6300
6301                 default:
6302                         break;
6303                 }
6304
6305                 if (copy_to_user(argp, &status, sizeof(status)))
6306                         return -EFAULT;
6307
6308
6309                 break;
6310
6311         case SNDRV_HDSPM_IOCTL_GET_VERSION:
6312                 memset(&hdspm_version, 0, sizeof(hdspm_version));
6313
6314                 hdspm_version.card_type = hdspm->io_type;
6315                 strncpy(hdspm_version.cardname, hdspm->card_name,
6316                                 sizeof(hdspm_version.cardname));
6317                 hdspm_version.serial = hdspm->serial;
6318                 hdspm_version.firmware_rev = hdspm->firmware_rev;
6319                 hdspm_version.addons = 0;
6320                 if (hdspm->tco)
6321                         hdspm_version.addons |= HDSPM_ADDON_TCO;
6322
6323                 if (copy_to_user(argp, &hdspm_version,
6324                                         sizeof(hdspm_version)))
6325                         return -EFAULT;
6326                 break;
6327
6328         case SNDRV_HDSPM_IOCTL_GET_MIXER:
6329                 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6330                         return -EFAULT;
6331                 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6332                                         sizeof(struct hdspm_mixer)))
6333                         return -EFAULT;
6334                 break;
6335
6336         default:
6337                 return -EINVAL;
6338         }
6339         return 0;
6340 }
6341
6342 static struct snd_pcm_ops snd_hdspm_playback_ops = {
6343         .open = snd_hdspm_playback_open,
6344         .close = snd_hdspm_playback_release,
6345         .ioctl = snd_hdspm_ioctl,
6346         .hw_params = snd_hdspm_hw_params,
6347         .hw_free = snd_hdspm_hw_free,
6348         .prepare = snd_hdspm_prepare,
6349         .trigger = snd_hdspm_trigger,
6350         .pointer = snd_hdspm_hw_pointer,
6351         .page = snd_pcm_sgbuf_ops_page,
6352 };
6353
6354 static struct snd_pcm_ops snd_hdspm_capture_ops = {
6355         .open = snd_hdspm_capture_open,
6356         .close = snd_hdspm_capture_release,
6357         .ioctl = snd_hdspm_ioctl,
6358         .hw_params = snd_hdspm_hw_params,
6359         .hw_free = snd_hdspm_hw_free,
6360         .prepare = snd_hdspm_prepare,
6361         .trigger = snd_hdspm_trigger,
6362         .pointer = snd_hdspm_hw_pointer,
6363         .page = snd_pcm_sgbuf_ops_page,
6364 };
6365
6366 static int snd_hdspm_create_hwdep(struct snd_card *card,
6367                                   struct hdspm *hdspm)
6368 {
6369         struct snd_hwdep *hw;
6370         int err;
6371
6372         err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6373         if (err < 0)
6374                 return err;
6375
6376         hdspm->hwdep = hw;
6377         hw->private_data = hdspm;
6378         strcpy(hw->name, "HDSPM hwdep interface");
6379
6380         hw->ops.open = snd_hdspm_hwdep_dummy_op;
6381         hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6382         hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6383         hw->ops.release = snd_hdspm_hwdep_dummy_op;
6384
6385         return 0;
6386 }
6387
6388
6389 /*------------------------------------------------------------
6390    memory interface
6391  ------------------------------------------------------------*/
6392 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6393 {
6394         int err;
6395         struct snd_pcm *pcm;
6396         size_t wanted;
6397
6398         pcm = hdspm->pcm;
6399
6400         wanted = HDSPM_DMA_AREA_BYTES;
6401
6402         err =
6403              snd_pcm_lib_preallocate_pages_for_all(pcm,
6404                                                    SNDRV_DMA_TYPE_DEV_SG,
6405                                                    snd_dma_pci_data(hdspm->pci),
6406                                                    wanted,
6407                                                    wanted);
6408         if (err < 0) {
6409                 snd_printdd("Could not preallocate %zd Bytes\n", wanted);
6410
6411                 return err;
6412         } else
6413                 snd_printdd(" Preallocated %zd Bytes\n", wanted);
6414
6415         return 0;
6416 }
6417
6418
6419 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6420                             struct snd_pcm_substream *substream,
6421                              unsigned int reg, int channels)
6422 {
6423         int i;
6424
6425         /* continuous memory segment */
6426         for (i = 0; i < (channels * 16); i++)
6427                 hdspm_write(hdspm, reg + 4 * i,
6428                                 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6429 }
6430
6431
6432 /* ------------- ALSA Devices ---------------------------- */
6433 static int snd_hdspm_create_pcm(struct snd_card *card,
6434                                 struct hdspm *hdspm)
6435 {
6436         struct snd_pcm *pcm;
6437         int err;
6438
6439         err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6440         if (err < 0)
6441                 return err;
6442
6443         hdspm->pcm = pcm;
6444         pcm->private_data = hdspm;
6445         strcpy(pcm->name, hdspm->card_name);
6446
6447         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6448                         &snd_hdspm_playback_ops);
6449         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6450                         &snd_hdspm_capture_ops);
6451
6452         pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6453
6454         err = snd_hdspm_preallocate_memory(hdspm);
6455         if (err < 0)
6456                 return err;
6457
6458         return 0;
6459 }
6460
6461 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6462 {
6463         int i;
6464
6465         for (i = 0; i < hdspm->midiPorts; i++)
6466                 snd_hdspm_flush_midi_input(hdspm, i);
6467 }
6468
6469 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6470                                          struct hdspm *hdspm)
6471 {
6472         int err, i;
6473
6474         snd_printdd("Create card...\n");
6475         err = snd_hdspm_create_pcm(card, hdspm);
6476         if (err < 0)
6477                 return err;
6478
6479         i = 0;
6480         while (i < hdspm->midiPorts) {
6481                 err = snd_hdspm_create_midi(card, hdspm, i);
6482                 if (err < 0) {
6483                         return err;
6484                 }
6485                 i++;
6486         }
6487
6488         err = snd_hdspm_create_controls(card, hdspm);
6489         if (err < 0)
6490                 return err;
6491
6492         err = snd_hdspm_create_hwdep(card, hdspm);
6493         if (err < 0)
6494                 return err;
6495
6496         snd_printdd("proc init...\n");
6497         snd_hdspm_proc_init(hdspm);
6498
6499         hdspm->system_sample_rate = -1;
6500         hdspm->last_external_sample_rate = -1;
6501         hdspm->last_internal_sample_rate = -1;
6502         hdspm->playback_pid = -1;
6503         hdspm->capture_pid = -1;
6504         hdspm->capture_substream = NULL;
6505         hdspm->playback_substream = NULL;
6506
6507         snd_printdd("Set defaults...\n");
6508         err = snd_hdspm_set_defaults(hdspm);
6509         if (err < 0)
6510                 return err;
6511
6512         snd_printdd("Update mixer controls...\n");
6513         hdspm_update_simple_mixer_controls(hdspm);
6514
6515         snd_printdd("Initializeing complete ???\n");
6516
6517         err = snd_card_register(card);
6518         if (err < 0) {
6519                 snd_printk(KERN_ERR "HDSPM: error registering card\n");
6520                 return err;
6521         }
6522
6523         snd_printdd("... yes now\n");
6524
6525         return 0;
6526 }
6527
6528 static int snd_hdspm_create(struct snd_card *card,
6529                             struct hdspm *hdspm)
6530 {
6531
6532         struct pci_dev *pci = hdspm->pci;
6533         int err;
6534         unsigned long io_extent;
6535
6536         hdspm->irq = -1;
6537         hdspm->card = card;
6538
6539         spin_lock_init(&hdspm->lock);
6540
6541         pci_read_config_word(hdspm->pci,
6542                         PCI_CLASS_REVISION, &hdspm->firmware_rev);
6543
6544         strcpy(card->mixername, "Xilinx FPGA");
6545         strcpy(card->driver, "HDSPM");
6546
6547         switch (hdspm->firmware_rev) {
6548         case HDSPM_RAYDAT_REV:
6549                 hdspm->io_type = RayDAT;
6550                 hdspm->card_name = "RME RayDAT";
6551                 hdspm->midiPorts = 2;
6552                 break;
6553         case HDSPM_AIO_REV:
6554                 hdspm->io_type = AIO;
6555                 hdspm->card_name = "RME AIO";
6556                 hdspm->midiPorts = 1;
6557                 break;
6558         case HDSPM_MADIFACE_REV:
6559                 hdspm->io_type = MADIface;
6560                 hdspm->card_name = "RME MADIface";
6561                 hdspm->midiPorts = 1;
6562                 break;
6563         default:
6564                 if ((hdspm->firmware_rev == 0xf0) ||
6565                         ((hdspm->firmware_rev >= 0xe6) &&
6566                                         (hdspm->firmware_rev <= 0xea))) {
6567                         hdspm->io_type = AES32;
6568                         hdspm->card_name = "RME AES32";
6569                         hdspm->midiPorts = 2;
6570                 } else if ((hdspm->firmware_rev == 0xd2) ||
6571                         ((hdspm->firmware_rev >= 0xc8)  &&
6572                                 (hdspm->firmware_rev <= 0xcf))) {
6573                         hdspm->io_type = MADI;
6574                         hdspm->card_name = "RME MADI";
6575                         hdspm->midiPorts = 3;
6576                 } else {
6577                         snd_printk(KERN_ERR
6578                                 "HDSPM: unknown firmware revision %x\n",
6579                                 hdspm->firmware_rev);
6580                         return -ENODEV;
6581                 }
6582         }
6583
6584         err = pci_enable_device(pci);
6585         if (err < 0)
6586                 return err;
6587
6588         pci_set_master(hdspm->pci);
6589
6590         err = pci_request_regions(pci, "hdspm");
6591         if (err < 0)
6592                 return err;
6593
6594         hdspm->port = pci_resource_start(pci, 0);
6595         io_extent = pci_resource_len(pci, 0);
6596
6597         snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6598                         hdspm->port, hdspm->port + io_extent - 1);
6599
6600         hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6601         if (!hdspm->iobase) {
6602                 snd_printk(KERN_ERR "HDSPM: "
6603                                 "unable to remap region 0x%lx-0x%lx\n",
6604                                 hdspm->port, hdspm->port + io_extent - 1);
6605                 return -EBUSY;
6606         }
6607         snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6608                         (unsigned long)hdspm->iobase, hdspm->port,
6609                         hdspm->port + io_extent - 1);
6610
6611         if (request_irq(pci->irq, snd_hdspm_interrupt,
6612                         IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6613                 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq);
6614                 return -EBUSY;
6615         }
6616
6617         snd_printdd("use IRQ %d\n", pci->irq);
6618
6619         hdspm->irq = pci->irq;
6620
6621         snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6622                         sizeof(struct hdspm_mixer));
6623         hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL);
6624         if (!hdspm->mixer) {
6625                 snd_printk(KERN_ERR "HDSPM: "
6626                                 "unable to kmalloc Mixer memory of %d Bytes\n",
6627                                 (int)sizeof(struct hdspm_mixer));
6628                 return -ENOMEM;
6629         }
6630
6631         hdspm->port_names_in = NULL;
6632         hdspm->port_names_out = NULL;
6633
6634         switch (hdspm->io_type) {
6635         case AES32:
6636                 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6637                 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6638                 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6639
6640                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6641                         channel_map_aes32;
6642                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6643                         channel_map_aes32;
6644                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6645                         channel_map_aes32;
6646                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6647                         texts_ports_aes32;
6648                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6649                         texts_ports_aes32;
6650                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6651                         texts_ports_aes32;
6652
6653                 hdspm->max_channels_out = hdspm->max_channels_in =
6654                         AES32_CHANNELS;
6655                 hdspm->port_names_in = hdspm->port_names_out =
6656                         texts_ports_aes32;
6657                 hdspm->channel_map_in = hdspm->channel_map_out =
6658                         channel_map_aes32;
6659
6660                 break;
6661
6662         case MADI:
6663         case MADIface:
6664                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6665                         MADI_SS_CHANNELS;
6666                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6667                         MADI_DS_CHANNELS;
6668                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6669                         MADI_QS_CHANNELS;
6670
6671                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6672                         channel_map_unity_ss;
6673                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6674                         channel_map_unity_ss;
6675                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6676                         channel_map_unity_ss;
6677
6678                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6679                         texts_ports_madi;
6680                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6681                         texts_ports_madi;
6682                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6683                         texts_ports_madi;
6684                 break;
6685
6686         case AIO:
6687                 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6688                 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6689                 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6690                 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6691                 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6692                 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6693
6694                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6695                         snd_printk(KERN_INFO "HDSPM: AEB input board found\n");
6696                         hdspm->ss_in_channels += 4;
6697                         hdspm->ds_in_channels += 4;
6698                         hdspm->qs_in_channels += 4;
6699                 }
6700
6701                 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6702                         snd_printk(KERN_INFO "HDSPM: AEB output board found\n");
6703                         hdspm->ss_out_channels += 4;
6704                         hdspm->ds_out_channels += 4;
6705                         hdspm->qs_out_channels += 4;
6706                 }
6707
6708                 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6709                 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6710                 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6711
6712                 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6713                 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6714                 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6715
6716                 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6717                 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6718                 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6719                 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6720                 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6721                 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6722
6723                 break;
6724
6725         case RayDAT:
6726                 hdspm->ss_in_channels = hdspm->ss_out_channels =
6727                         RAYDAT_SS_CHANNELS;
6728                 hdspm->ds_in_channels = hdspm->ds_out_channels =
6729                         RAYDAT_DS_CHANNELS;
6730                 hdspm->qs_in_channels = hdspm->qs_out_channels =
6731                         RAYDAT_QS_CHANNELS;
6732
6733                 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6734                 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6735
6736                 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6737                         channel_map_raydat_ss;
6738                 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6739                         channel_map_raydat_ds;
6740                 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6741                         channel_map_raydat_qs;
6742                 hdspm->channel_map_in = hdspm->channel_map_out =
6743                         channel_map_raydat_ss;
6744
6745                 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6746                         texts_ports_raydat_ss;
6747                 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6748                         texts_ports_raydat_ds;
6749                 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6750                         texts_ports_raydat_qs;
6751
6752
6753                 break;
6754
6755         }
6756
6757         /* TCO detection */
6758         switch (hdspm->io_type) {
6759         case AIO:
6760         case RayDAT:
6761                 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6762                                 HDSPM_s2_tco_detect) {
6763                         hdspm->midiPorts++;
6764                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6765                                         GFP_KERNEL);
6766                         if (NULL != hdspm->tco) {
6767                                 hdspm_tco_write(hdspm);
6768                         }
6769                         snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n");
6770                 } else {
6771                         hdspm->tco = NULL;
6772                 }
6773                 break;
6774
6775         case MADI:
6776                 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6777                         hdspm->midiPorts++;
6778                         hdspm->tco = kzalloc(sizeof(struct hdspm_tco),
6779                                         GFP_KERNEL);
6780                         if (NULL != hdspm->tco) {
6781                                 hdspm_tco_write(hdspm);
6782                         }
6783                         snd_printk(KERN_INFO "HDSPM: MADI/AES TCO module found\n");
6784                 } else {
6785                         hdspm->tco = NULL;
6786                 }
6787                 break;
6788
6789         default:
6790                 hdspm->tco = NULL;
6791         }
6792
6793         /* texts */
6794         switch (hdspm->io_type) {
6795         case AES32:
6796                 if (hdspm->tco) {
6797                         hdspm->texts_autosync = texts_autosync_aes_tco;
6798                         hdspm->texts_autosync_items =
6799                                 ARRAY_SIZE(texts_autosync_aes_tco);
6800                 } else {
6801                         hdspm->texts_autosync = texts_autosync_aes;
6802                         hdspm->texts_autosync_items =
6803                                 ARRAY_SIZE(texts_autosync_aes);
6804                 }
6805                 break;
6806
6807         case MADI:
6808                 if (hdspm->tco) {
6809                         hdspm->texts_autosync = texts_autosync_madi_tco;
6810                         hdspm->texts_autosync_items = 4;
6811                 } else {
6812                         hdspm->texts_autosync = texts_autosync_madi;
6813                         hdspm->texts_autosync_items = 3;
6814                 }
6815                 break;
6816
6817         case MADIface:
6818
6819                 break;
6820
6821         case RayDAT:
6822                 if (hdspm->tco) {
6823                         hdspm->texts_autosync = texts_autosync_raydat_tco;
6824                         hdspm->texts_autosync_items = 9;
6825                 } else {
6826                         hdspm->texts_autosync = texts_autosync_raydat;
6827                         hdspm->texts_autosync_items = 8;
6828                 }
6829                 break;
6830
6831         case AIO:
6832                 if (hdspm->tco) {
6833                         hdspm->texts_autosync = texts_autosync_aio_tco;
6834                         hdspm->texts_autosync_items = 6;
6835                 } else {
6836                         hdspm->texts_autosync = texts_autosync_aio;
6837                         hdspm->texts_autosync_items = 5;
6838                 }
6839                 break;
6840
6841         }
6842
6843         tasklet_init(&hdspm->midi_tasklet,
6844                         hdspm_midi_tasklet, (unsigned long) hdspm);
6845
6846
6847         if (hdspm->io_type != MADIface) {
6848                 hdspm->serial = (hdspm_read(hdspm,
6849                                 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6850                 /* id contains either a user-provided value or the default
6851                  * NULL. If it's the default, we're safe to
6852                  * fill card->id with the serial number.
6853                  *
6854                  * If the serial number is 0xFFFFFF, then we're dealing with
6855                  * an old PCI revision that comes without a sane number. In
6856                  * this case, we don't set card->id to avoid collisions
6857                  * when running with multiple cards.
6858                  */
6859                 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6860                         sprintf(card->id, "HDSPMx%06x", hdspm->serial);
6861                         snd_card_set_id(card, card->id);
6862                 }
6863         }
6864
6865         snd_printdd("create alsa devices.\n");
6866         err = snd_hdspm_create_alsa_devices(card, hdspm);
6867         if (err < 0)
6868                 return err;
6869
6870         snd_hdspm_initialize_midi_flush(hdspm);
6871
6872         return 0;
6873 }
6874
6875
6876 static int snd_hdspm_free(struct hdspm * hdspm)
6877 {
6878
6879         if (hdspm->port) {
6880
6881                 /* stop th audio, and cancel all interrupts */
6882                 hdspm->control_register &=
6883                     ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6884                       HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6885                       HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6886                 hdspm_write(hdspm, HDSPM_controlRegister,
6887                             hdspm->control_register);
6888         }
6889
6890         if (hdspm->irq >= 0)
6891                 free_irq(hdspm->irq, (void *) hdspm);
6892
6893         kfree(hdspm->mixer);
6894
6895         if (hdspm->iobase)
6896                 iounmap(hdspm->iobase);
6897
6898         if (hdspm->port)
6899                 pci_release_regions(hdspm->pci);
6900
6901         pci_disable_device(hdspm->pci);
6902         return 0;
6903 }
6904
6905
6906 static void snd_hdspm_card_free(struct snd_card *card)
6907 {
6908         struct hdspm *hdspm = card->private_data;
6909
6910         if (hdspm)
6911                 snd_hdspm_free(hdspm);
6912 }
6913
6914
6915 static int snd_hdspm_probe(struct pci_dev *pci,
6916                            const struct pci_device_id *pci_id)
6917 {
6918         static int dev;
6919         struct hdspm *hdspm;
6920         struct snd_card *card;
6921         int err;
6922
6923         if (dev >= SNDRV_CARDS)
6924                 return -ENODEV;
6925         if (!enable[dev]) {
6926                 dev++;
6927                 return -ENOENT;
6928         }
6929
6930         err = snd_card_create(index[dev], id[dev],
6931                         THIS_MODULE, sizeof(struct hdspm), &card);
6932         if (err < 0)
6933                 return err;
6934
6935         hdspm = card->private_data;
6936         card->private_free = snd_hdspm_card_free;
6937         hdspm->dev = dev;
6938         hdspm->pci = pci;
6939
6940         snd_card_set_dev(card, &pci->dev);
6941
6942         err = snd_hdspm_create(card, hdspm);
6943         if (err < 0) {
6944                 snd_card_free(card);
6945                 return err;
6946         }
6947
6948         if (hdspm->io_type != MADIface) {
6949                 sprintf(card->shortname, "%s_%x",
6950                         hdspm->card_name,
6951                         hdspm->serial);
6952                 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d",
6953                         hdspm->card_name,
6954                         hdspm->serial,
6955                         hdspm->port, hdspm->irq);
6956         } else {
6957                 sprintf(card->shortname, "%s", hdspm->card_name);
6958                 sprintf(card->longname, "%s at 0x%lx, irq %d",
6959                                 hdspm->card_name, hdspm->port, hdspm->irq);
6960         }
6961
6962         err = snd_card_register(card);
6963         if (err < 0) {
6964                 snd_card_free(card);
6965                 return err;
6966         }
6967
6968         pci_set_drvdata(pci, card);
6969
6970         dev++;
6971         return 0;
6972 }
6973
6974 static void snd_hdspm_remove(struct pci_dev *pci)
6975 {
6976         snd_card_free(pci_get_drvdata(pci));
6977 }
6978
6979 static struct pci_driver hdspm_driver = {
6980         .name = KBUILD_MODNAME,
6981         .id_table = snd_hdspm_ids,
6982         .probe = snd_hdspm_probe,
6983         .remove = snd_hdspm_remove,
6984 };
6985
6986 module_pci_driver(hdspm_driver);