sound/soc/codecs/arizona.c

   1 /*
   2  * arizona.c - Wolfson Arizona class device shared support
   3  *
   4  * Copyright 2012 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/gcd.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <sound/pcm.h>
  18 #include <sound/pcm_params.h>
  19 #include <sound/tlv.h>
  20
  21 #include <linux/mfd/arizona/core.h>
  22 #include <linux/mfd/arizona/gpio.h>
  23 #include <linux/mfd/arizona/registers.h>
  24
  25 #include "arizona.h"
  26
  27 #define ARIZONA_AIF_BCLK_CTRL                   0x00
  28 #define ARIZONA_AIF_TX_PIN_CTRL                 0x01
  29 #define ARIZONA_AIF_RX_PIN_CTRL                 0x02
  30 #define ARIZONA_AIF_RATE_CTRL                   0x03
  31 #define ARIZONA_AIF_FORMAT                      0x04
  32 #define ARIZONA_AIF_TX_BCLK_RATE                0x05
  33 #define ARIZONA_AIF_RX_BCLK_RATE                0x06
  34 #define ARIZONA_AIF_FRAME_CTRL_1                0x07
  35 #define ARIZONA_AIF_FRAME_CTRL_2                0x08
  36 #define ARIZONA_AIF_FRAME_CTRL_3                0x09
  37 #define ARIZONA_AIF_FRAME_CTRL_4                0x0A
  38 #define ARIZONA_AIF_FRAME_CTRL_5                0x0B
  39 #define ARIZONA_AIF_FRAME_CTRL_6                0x0C
  40 #define ARIZONA_AIF_FRAME_CTRL_7                0x0D
  41 #define ARIZONA_AIF_FRAME_CTRL_8                0x0E
  42 #define ARIZONA_AIF_FRAME_CTRL_9                0x0F
  43 #define ARIZONA_AIF_FRAME_CTRL_10               0x10
  44 #define ARIZONA_AIF_FRAME_CTRL_11               0x11
  45 #define ARIZONA_AIF_FRAME_CTRL_12               0x12
  46 #define ARIZONA_AIF_FRAME_CTRL_13               0x13
  47 #define ARIZONA_AIF_FRAME_CTRL_14               0x14
  48 #define ARIZONA_AIF_FRAME_CTRL_15               0x15
  49 #define ARIZONA_AIF_FRAME_CTRL_16               0x16
  50 #define ARIZONA_AIF_FRAME_CTRL_17               0x17
  51 #define ARIZONA_AIF_FRAME_CTRL_18               0x18
  52 #define ARIZONA_AIF_TX_ENABLES                  0x19
  53 #define ARIZONA_AIF_RX_ENABLES                  0x1A
  54 #define ARIZONA_AIF_FORCE_WRITE                 0x1B
  55
  56 #define ARIZONA_FLL_VCO_CORNER 141900000
  57 #define ARIZONA_FLL_MAX_FREF   13500000
  58 #define ARIZONA_FLL_MIN_FVCO   90000000
  59 #define ARIZONA_FLL_MAX_FRATIO 16
  60 #define ARIZONA_FLL_MAX_REFDIV 8
  61 #define ARIZONA_FLL_MIN_OUTDIV 2
  62 #define ARIZONA_FLL_MAX_OUTDIV 7
  63
  64 #define arizona_fll_err(_fll, fmt, ...) \
  65         dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  66 #define arizona_fll_warn(_fll, fmt, ...) \
  67         dev_warn(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  68 #define arizona_fll_dbg(_fll, fmt, ...) \
  69         dev_dbg(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
  70
  71 #define arizona_aif_err(_dai, fmt, ...) \
  72         dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  73 #define arizona_aif_warn(_dai, fmt, ...) \
  74         dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  75 #define arizona_aif_dbg(_dai, fmt, ...) \
  76         dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
  77
  78 static int arizona_spk_ev(struct snd_soc_dapm_widget *w,
  79                           struct snd_kcontrol *kcontrol,
  80                           int event)
  81 {
  82         struct snd_soc_codec *codec = w->codec;
  83         struct arizona *arizona = dev_get_drvdata(codec->dev->parent);
  84         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
  85         bool manual_ena = false;
  86         int val;
  87
  88         switch (arizona->type) {
  89         case WM5102:
  90                 switch (arizona->rev) {
  91                 case 0:
  92                         break;
  93                 default:
  94                         manual_ena = true;
  95                         break;
  96                 }
  97         default:
  98                 break;
  99         }
 100
 101         switch (event) {
 102         case SND_SOC_DAPM_PRE_PMU:
 103                 if (!priv->spk_ena && manual_ena) {
 104                         regmap_write_async(arizona->regmap, 0x4f5, 0x25a);
 105                         priv->spk_ena_pending = true;
 106                 }
 107                 break;
 108         case SND_SOC_DAPM_POST_PMU:
 109                 val = snd_soc_read(codec, ARIZONA_INTERRUPT_RAW_STATUS_3);
 110                 if (val & ARIZONA_SPK_OVERHEAT_STS) {
 111                         dev_crit(arizona->dev,
 112                                  "Speaker not enabled due to temperature\n");
 113                         return -EBUSY;
 114                 }
 115
 116                 regmap_update_bits_async(arizona->regmap,
 117                                          ARIZONA_OUTPUT_ENABLES_1,
 118                                          1 << w->shift, 1 << w->shift);
 119
 120                 if (priv->spk_ena_pending) {
 121                         msleep(75);
 122                         regmap_write_async(arizona->regmap, 0x4f5, 0xda);
 123                         priv->spk_ena_pending = false;
 124                         priv->spk_ena++;
 125                 }
 126                 break;
 127         case SND_SOC_DAPM_PRE_PMD:
 128                 if (manual_ena) {
 129                         priv->spk_ena--;
 130                         if (!priv->spk_ena)
 131                                 regmap_write_async(arizona->regmap,
 132                                                    0x4f5, 0x25a);
 133                 }
 134
 135                 regmap_update_bits_async(arizona->regmap,
 136                                          ARIZONA_OUTPUT_ENABLES_1,
 137                                          1 << w->shift, 0);
 138                 break;
 139         case SND_SOC_DAPM_POST_PMD:
 140                 if (manual_ena) {
 141                         if (!priv->spk_ena)
 142                                 regmap_write_async(arizona->regmap,
 143                                                    0x4f5, 0x0da);
 144                 }
 145                 break;
 146         }
 147
 148         return 0;
 149 }
 150
 151 static irqreturn_t arizona_thermal_warn(int irq, void *data)
 152 {
 153         struct arizona *arizona = data;
 154         unsigned int val;
 155         int ret;
 156
 157         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 158                           &val);
 159         if (ret != 0) {
 160                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 161                         ret);
 162         } else if (val & ARIZONA_SPK_OVERHEAT_WARN_STS) {
 163                 dev_crit(arizona->dev, "Thermal warning\n");
 164         }
 165
 166         return IRQ_HANDLED;
 167 }
 168
 169 static irqreturn_t arizona_thermal_shutdown(int irq, void *data)
 170 {
 171         struct arizona *arizona = data;
 172         unsigned int val;
 173         int ret;
 174
 175         ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_3,
 176                           &val);
 177         if (ret != 0) {
 178                 dev_err(arizona->dev, "Failed to read thermal status: %d\n",
 179                         ret);
 180         } else if (val & ARIZONA_SPK_OVERHEAT_STS) {
 181                 dev_crit(arizona->dev, "Thermal shutdown\n");
 182                 ret = regmap_update_bits(arizona->regmap,
 183                                          ARIZONA_OUTPUT_ENABLES_1,
 184                                          ARIZONA_OUT4L_ENA |
 185                                          ARIZONA_OUT4R_ENA, 0);
 186                 if (ret != 0)
 187                         dev_crit(arizona->dev,
 188                                  "Failed to disable speaker outputs: %d\n",
 189                                  ret);
 190         }
 191
 192         return IRQ_HANDLED;
 193 }
 194
 195 static const struct snd_soc_dapm_widget arizona_spkl =
 196         SND_SOC_DAPM_PGA_E("OUT4L", SND_SOC_NOPM,
 197                            ARIZONA_OUT4L_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 198                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 199
 200 static const struct snd_soc_dapm_widget arizona_spkr =
 201         SND_SOC_DAPM_PGA_E("OUT4R", SND_SOC_NOPM,
 202                            ARIZONA_OUT4R_ENA_SHIFT, 0, NULL, 0, arizona_spk_ev,
 203                            SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU);
 204
 205 int arizona_init_spk(struct snd_soc_codec *codec)
 206 {
 207         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 208         struct arizona *arizona = priv->arizona;
 209         int ret;
 210
 211         ret = snd_soc_dapm_new_controls(&codec->dapm, &arizona_spkl, 1);
 212         if (ret != 0)
 213                 return ret;
 214
 215         switch (arizona->type) {
 216         case WM8997:
 217                 break;
 218         default:
 219                 ret = snd_soc_dapm_new_controls(&codec->dapm,
 220                                                 &arizona_spkr, 1);
 221                 if (ret != 0)
 222                         return ret;
 223                 break;
 224         }
 225
 226         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT_WARN,
 227                                   "Thermal warning", arizona_thermal_warn,
 228                                   arizona);
 229         if (ret != 0)
 230                 dev_err(arizona->dev,
 231                         "Failed to get thermal warning IRQ: %d\n",
 232                         ret);
 233
 234         ret = arizona_request_irq(arizona, ARIZONA_IRQ_SPK_OVERHEAT,
 235                                   "Thermal shutdown", arizona_thermal_shutdown,
 236                                   arizona);
 237         if (ret != 0)
 238                 dev_err(arizona->dev,
 239                         "Failed to get thermal shutdown IRQ: %d\n",
 240                         ret);
 241
 242         return 0;
 243 }
 244 EXPORT_SYMBOL_GPL(arizona_init_spk);
 245
 246 static const struct snd_soc_dapm_route arizona_mono_routes[] = {
 247         { "OUT1R", NULL, "OUT1L" },
 248         { "OUT2R", NULL, "OUT2L" },
 249         { "OUT3R", NULL, "OUT3L" },
 250         { "OUT4R", NULL, "OUT4L" },
 251         { "OUT5R", NULL, "OUT5L" },
 252         { "OUT6R", NULL, "OUT6L" },
 253 };
 254
 255 int arizona_init_mono(struct snd_soc_codec *codec)
 256 {
 257         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 258         struct arizona *arizona = priv->arizona;
 259         int i;
 260
 261         for (i = 0; i < ARIZONA_MAX_OUTPUT; ++i) {
 262                 if (arizona->pdata.out_mono[i])
 263                         snd_soc_dapm_add_routes(&codec->dapm,
 264                                                 &arizona_mono_routes[i], 1);
 265         }
 266
 267         return 0;
 268 }
 269 EXPORT_SYMBOL_GPL(arizona_init_mono);
 270
 271 int arizona_init_gpio(struct snd_soc_codec *codec)
 272 {
 273         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 274         struct arizona *arizona = priv->arizona;
 275         int i;
 276
 277         switch (arizona->type) {
 278         case WM5110:
 279                 snd_soc_dapm_disable_pin(&codec->dapm, "DRC2 Signal Activity");
 280                 break;
 281         default:
 282                 break;
 283         }
 284
 285         snd_soc_dapm_disable_pin(&codec->dapm, "DRC1 Signal Activity");
 286
 287         for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
 288                 switch (arizona->pdata.gpio_defaults[i] & ARIZONA_GPN_FN_MASK) {
 289                 case ARIZONA_GP_FN_DRC1_SIGNAL_DETECT:
 290                         snd_soc_dapm_enable_pin(&codec->dapm,
 291                                                 "DRC1 Signal Activity");
 292                         break;
 293                 case ARIZONA_GP_FN_DRC2_SIGNAL_DETECT:
 294                         snd_soc_dapm_enable_pin(&codec->dapm,
 295                                                 "DRC2 Signal Activity");
 296                         break;
 297                 default:
 298                         break;
 299                 }
 300         }
 301
 302         return 0;
 303 }
 304 EXPORT_SYMBOL_GPL(arizona_init_gpio);
 305
 306 const char *arizona_mixer_texts[ARIZONA_NUM_MIXER_INPUTS] = {
 307         "None",
 308         "Tone Generator 1",
 309         "Tone Generator 2",
 310         "Haptics",
 311         "AEC",
 312         "Mic Mute Mixer",
 313         "Noise Generator",
 314         "IN1L",
 315         "IN1R",
 316         "IN2L",
 317         "IN2R",
 318         "IN3L",
 319         "IN3R",
 320         "IN4L",
 321         "IN4R",
 322         "AIF1RX1",
 323         "AIF1RX2",
 324         "AIF1RX3",
 325         "AIF1RX4",
 326         "AIF1RX5",
 327         "AIF1RX6",
 328         "AIF1RX7",
 329         "AIF1RX8",
 330         "AIF2RX1",
 331         "AIF2RX2",
 332         "AIF2RX3",
 333         "AIF2RX4",
 334         "AIF2RX5",
 335         "AIF2RX6",
 336         "AIF3RX1",
 337         "AIF3RX2",
 338         "SLIMRX1",
 339         "SLIMRX2",
 340         "SLIMRX3",
 341         "SLIMRX4",
 342         "SLIMRX5",
 343         "SLIMRX6",
 344         "SLIMRX7",
 345         "SLIMRX8",
 346         "EQ1",
 347         "EQ2",
 348         "EQ3",
 349         "EQ4",
 350         "DRC1L",
 351         "DRC1R",
 352         "DRC2L",
 353         "DRC2R",
 354         "LHPF1",
 355         "LHPF2",
 356         "LHPF3",
 357         "LHPF4",
 358         "DSP1.1",
 359         "DSP1.2",
 360         "DSP1.3",
 361         "DSP1.4",
 362         "DSP1.5",
 363         "DSP1.6",
 364         "DSP2.1",
 365         "DSP2.2",
 366         "DSP2.3",
 367         "DSP2.4",
 368         "DSP2.5",
 369         "DSP2.6",
 370         "DSP3.1",
 371         "DSP3.2",
 372         "DSP3.3",
 373         "DSP3.4",
 374         "DSP3.5",
 375         "DSP3.6",
 376         "DSP4.1",
 377         "DSP4.2",
 378         "DSP4.3",
 379         "DSP4.4",
 380         "DSP4.5",
 381         "DSP4.6",
 382         "ASRC1L",
 383         "ASRC1R",
 384         "ASRC2L",
 385         "ASRC2R",
 386         "ISRC1INT1",
 387         "ISRC1INT2",
 388         "ISRC1INT3",
 389         "ISRC1INT4",
 390         "ISRC1DEC1",
 391         "ISRC1DEC2",
 392         "ISRC1DEC3",
 393         "ISRC1DEC4",
 394         "ISRC2INT1",
 395         "ISRC2INT2",
 396         "ISRC2INT3",
 397         "ISRC2INT4",
 398         "ISRC2DEC1",
 399         "ISRC2DEC2",
 400         "ISRC2DEC3",
 401         "ISRC2DEC4",
 402         "ISRC3INT1",
 403         "ISRC3INT2",
 404         "ISRC3INT3",
 405         "ISRC3INT4",
 406         "ISRC3DEC1",
 407         "ISRC3DEC2",
 408         "ISRC3DEC3",
 409         "ISRC3DEC4",
 410 };
 411 EXPORT_SYMBOL_GPL(arizona_mixer_texts);
 412
 413 int arizona_mixer_values[ARIZONA_NUM_MIXER_INPUTS] = {
 414         0x00,  /* None */
 415         0x04,  /* Tone */
 416         0x05,
 417         0x06,  /* Haptics */
 418         0x08,  /* AEC */
 419         0x0c,  /* Noise mixer */
 420         0x0d,  /* Comfort noise */
 421         0x10,  /* IN1L */
 422         0x11,
 423         0x12,
 424         0x13,
 425         0x14,
 426         0x15,
 427         0x16,
 428         0x17,
 429         0x20,  /* AIF1RX1 */
 430         0x21,
 431         0x22,
 432         0x23,
 433         0x24,
 434         0x25,
 435         0x26,
 436         0x27,
 437         0x28,  /* AIF2RX1 */
 438         0x29,
 439         0x2a,
 440         0x2b,
 441         0x2c,
 442         0x2d,
 443         0x30,  /* AIF3RX1 */
 444         0x31,
 445         0x38,  /* SLIMRX1 */
 446         0x39,
 447         0x3a,
 448         0x3b,
 449         0x3c,
 450         0x3d,
 451         0x3e,
 452         0x3f,
 453         0x50,  /* EQ1 */
 454         0x51,
 455         0x52,
 456         0x53,
 457         0x58,  /* DRC1L */
 458         0x59,
 459         0x5a,
 460         0x5b,
 461         0x60,  /* LHPF1 */
 462         0x61,
 463         0x62,
 464         0x63,
 465         0x68,  /* DSP1.1 */
 466         0x69,
 467         0x6a,
 468         0x6b,
 469         0x6c,
 470         0x6d,
 471         0x70,  /* DSP2.1 */
 472         0x71,
 473         0x72,
 474         0x73,
 475         0x74,
 476         0x75,
 477         0x78,  /* DSP3.1 */
 478         0x79,
 479         0x7a,
 480         0x7b,
 481         0x7c,
 482         0x7d,
 483         0x80,  /* DSP4.1 */
 484         0x81,
 485         0x82,
 486         0x83,
 487         0x84,
 488         0x85,
 489         0x90,  /* ASRC1L */
 490         0x91,
 491         0x92,
 492         0x93,
 493         0xa0,  /* ISRC1INT1 */
 494         0xa1,
 495         0xa2,
 496         0xa3,
 497         0xa4,  /* ISRC1DEC1 */
 498         0xa5,
 499         0xa6,
 500         0xa7,
 501         0xa8,  /* ISRC2DEC1 */
 502         0xa9,
 503         0xaa,
 504         0xab,
 505         0xac,  /* ISRC2INT1 */
 506         0xad,
 507         0xae,
 508         0xaf,
 509         0xb0,  /* ISRC3DEC1 */
 510         0xb1,
 511         0xb2,
 512         0xb3,
 513         0xb4,  /* ISRC3INT1 */
 514         0xb5,
 515         0xb6,
 516         0xb7,
 517 };
 518 EXPORT_SYMBOL_GPL(arizona_mixer_values);
 519
 520 const DECLARE_TLV_DB_SCALE(arizona_mixer_tlv, -3200, 100, 0);
 521 EXPORT_SYMBOL_GPL(arizona_mixer_tlv);
 522
 523 const char *arizona_rate_text[ARIZONA_RATE_ENUM_SIZE] = {
 524         "SYNCCLK rate", "8kHz", "16kHz", "ASYNCCLK rate",
 525 };
 526 EXPORT_SYMBOL_GPL(arizona_rate_text);
 527
 528 const int arizona_rate_val[ARIZONA_RATE_ENUM_SIZE] = {
 529         0, 1, 2, 8,
 530 };
 531 EXPORT_SYMBOL_GPL(arizona_rate_val);
 532
 533
 534 const struct soc_enum arizona_isrc_fsh[] = {
 535         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_1,
 536                               ARIZONA_ISRC1_FSH_SHIFT, 0xf,
 537                               ARIZONA_RATE_ENUM_SIZE,
 538                               arizona_rate_text, arizona_rate_val),
 539         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_1,
 540                               ARIZONA_ISRC2_FSH_SHIFT, 0xf,
 541                               ARIZONA_RATE_ENUM_SIZE,
 542                               arizona_rate_text, arizona_rate_val),
 543         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_1,
 544                               ARIZONA_ISRC3_FSH_SHIFT, 0xf,
 545                               ARIZONA_RATE_ENUM_SIZE,
 546                               arizona_rate_text, arizona_rate_val),
 547 };
 548 EXPORT_SYMBOL_GPL(arizona_isrc_fsh);
 549
 550 const struct soc_enum arizona_isrc_fsl[] = {
 551         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_1_CTRL_2,
 552                               ARIZONA_ISRC1_FSL_SHIFT, 0xf,
 553                               ARIZONA_RATE_ENUM_SIZE,
 554                               arizona_rate_text, arizona_rate_val),
 555         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_2_CTRL_2,
 556                               ARIZONA_ISRC2_FSL_SHIFT, 0xf,
 557                               ARIZONA_RATE_ENUM_SIZE,
 558                               arizona_rate_text, arizona_rate_val),
 559         SOC_VALUE_ENUM_SINGLE(ARIZONA_ISRC_3_CTRL_2,
 560                               ARIZONA_ISRC3_FSL_SHIFT, 0xf,
 561                               ARIZONA_RATE_ENUM_SIZE,
 562                               arizona_rate_text, arizona_rate_val),
 563 };
 564 EXPORT_SYMBOL_GPL(arizona_isrc_fsl);
 565
 566 const struct soc_enum arizona_asrc_rate1 =
 567         SOC_VALUE_ENUM_SINGLE(ARIZONA_ASRC_RATE1,
 568                               ARIZONA_ASRC_RATE1_SHIFT, 0xf,
 569                               ARIZONA_RATE_ENUM_SIZE - 1,
 570                               arizona_rate_text, arizona_rate_val);
 571 EXPORT_SYMBOL_GPL(arizona_asrc_rate1);
 572
 573 static const char *arizona_vol_ramp_text[] = {
 574         "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB",
 575         "15ms/6dB", "30ms/6dB",
 576 };
 577
 578 SOC_ENUM_SINGLE_DECL(arizona_in_vd_ramp,
 579                      ARIZONA_INPUT_VOLUME_RAMP,
 580                      ARIZONA_IN_VD_RAMP_SHIFT,
 581                      arizona_vol_ramp_text);
 582 EXPORT_SYMBOL_GPL(arizona_in_vd_ramp);
 583
 584 SOC_ENUM_SINGLE_DECL(arizona_in_vi_ramp,
 585                      ARIZONA_INPUT_VOLUME_RAMP,
 586                      ARIZONA_IN_VI_RAMP_SHIFT,
 587                      arizona_vol_ramp_text);
 588 EXPORT_SYMBOL_GPL(arizona_in_vi_ramp);
 589
 590 SOC_ENUM_SINGLE_DECL(arizona_out_vd_ramp,
 591                      ARIZONA_OUTPUT_VOLUME_RAMP,
 592                      ARIZONA_OUT_VD_RAMP_SHIFT,
 593                      arizona_vol_ramp_text);
 594 EXPORT_SYMBOL_GPL(arizona_out_vd_ramp);
 595
 596 SOC_ENUM_SINGLE_DECL(arizona_out_vi_ramp,
 597                      ARIZONA_OUTPUT_VOLUME_RAMP,
 598                      ARIZONA_OUT_VI_RAMP_SHIFT,
 599                      arizona_vol_ramp_text);
 600 EXPORT_SYMBOL_GPL(arizona_out_vi_ramp);
 601
 602 static const char *arizona_lhpf_mode_text[] = {
 603         "Low-pass", "High-pass"
 604 };
 605
 606 SOC_ENUM_SINGLE_DECL(arizona_lhpf1_mode,
 607                      ARIZONA_HPLPF1_1,
 608                      ARIZONA_LHPF1_MODE_SHIFT,
 609                      arizona_lhpf_mode_text);
 610 EXPORT_SYMBOL_GPL(arizona_lhpf1_mode);
 611
 612 SOC_ENUM_SINGLE_DECL(arizona_lhpf2_mode,
 613                      ARIZONA_HPLPF2_1,
 614                      ARIZONA_LHPF2_MODE_SHIFT,
 615                      arizona_lhpf_mode_text);
 616 EXPORT_SYMBOL_GPL(arizona_lhpf2_mode);
 617
 618 SOC_ENUM_SINGLE_DECL(arizona_lhpf3_mode,
 619                      ARIZONA_HPLPF3_1,
 620                      ARIZONA_LHPF3_MODE_SHIFT,
 621                      arizona_lhpf_mode_text);
 622 EXPORT_SYMBOL_GPL(arizona_lhpf3_mode);
 623
 624 SOC_ENUM_SINGLE_DECL(arizona_lhpf4_mode,
 625                      ARIZONA_HPLPF4_1,
 626                      ARIZONA_LHPF4_MODE_SHIFT,
 627                      arizona_lhpf_mode_text);
 628 EXPORT_SYMBOL_GPL(arizona_lhpf4_mode);
 629
 630 static const char *arizona_ng_hold_text[] = {
 631         "30ms", "120ms", "250ms", "500ms",
 632 };
 633
 634 SOC_ENUM_SINGLE_DECL(arizona_ng_hold,
 635                      ARIZONA_NOISE_GATE_CONTROL,
 636                      ARIZONA_NGATE_HOLD_SHIFT,
 637                      arizona_ng_hold_text);
 638 EXPORT_SYMBOL_GPL(arizona_ng_hold);
 639
 640 static const char * const arizona_in_hpf_cut_text[] = {
 641         "2.5Hz", "5Hz", "10Hz", "20Hz", "40Hz"
 642 };
 643
 644 SOC_ENUM_SINGLE_DECL(arizona_in_hpf_cut_enum,
 645                      ARIZONA_HPF_CONTROL,
 646                      ARIZONA_IN_HPF_CUT_SHIFT,
 647                      arizona_in_hpf_cut_text);
 648 EXPORT_SYMBOL_GPL(arizona_in_hpf_cut_enum);
 649
 650 static const char * const arizona_in_dmic_osr_text[] = {
 651         "1.536MHz", "3.072MHz", "6.144MHz",
 652 };
 653
 654 const struct soc_enum arizona_in_dmic_osr[] = {
 655         SOC_ENUM_SINGLE(ARIZONA_IN1L_CONTROL, ARIZONA_IN1_OSR_SHIFT,
 656                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 657                         arizona_in_dmic_osr_text),
 658         SOC_ENUM_SINGLE(ARIZONA_IN2L_CONTROL, ARIZONA_IN2_OSR_SHIFT,
 659                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 660                         arizona_in_dmic_osr_text),
 661         SOC_ENUM_SINGLE(ARIZONA_IN3L_CONTROL, ARIZONA_IN3_OSR_SHIFT,
 662                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 663                         arizona_in_dmic_osr_text),
 664         SOC_ENUM_SINGLE(ARIZONA_IN4L_CONTROL, ARIZONA_IN4_OSR_SHIFT,
 665                         ARRAY_SIZE(arizona_in_dmic_osr_text),
 666                         arizona_in_dmic_osr_text),
 667 };
 668 EXPORT_SYMBOL_GPL(arizona_in_dmic_osr);
 669
 670 static void arizona_in_set_vu(struct snd_soc_codec *codec, int ena)
 671 {
 672         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 673         unsigned int val;
 674         int i;
 675
 676         if (ena)
 677                 val = ARIZONA_IN_VU;
 678         else
 679                 val = 0;
 680
 681         for (i = 0; i < priv->num_inputs; i++)
 682                 snd_soc_update_bits(codec,
 683                                     ARIZONA_ADC_DIGITAL_VOLUME_1L + (i * 4),
 684                                     ARIZONA_IN_VU, val);
 685 }
 686
 687 int arizona_in_ev(struct snd_soc_dapm_widget *w, struct snd_kcontrol *kcontrol,
 688                   int event)
 689 {
 690         struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
 691         unsigned int reg;
 692
 693         if (w->shift % 2)
 694                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
 695         else
 696                 reg = ARIZONA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
 697
 698         switch (event) {
 699         case SND_SOC_DAPM_PRE_PMU:
 700                 priv->in_pending++;
 701                 break;
 702         case SND_SOC_DAPM_POST_PMU:
 703                 snd_soc_update_bits(w->codec, reg, ARIZONA_IN1L_MUTE, 0);
 704
 705                 /* If this is the last input pending then allow VU */
 706                 priv->in_pending--;
 707                 if (priv->in_pending == 0) {
 708                         msleep(1);
 709                         arizona_in_set_vu(w->codec, 1);
 710                 }
 711                 break;
 712         case SND_SOC_DAPM_PRE_PMD:
 713                 snd_soc_update_bits(w->codec, reg,
 714                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU,
 715                                     ARIZONA_IN1L_MUTE | ARIZONA_IN_VU);
 716                 break;
 717         case SND_SOC_DAPM_POST_PMD:
 718                 /* Disable volume updates if no inputs are enabled */
 719                 reg = snd_soc_read(w->codec, ARIZONA_INPUT_ENABLES);
 720                 if (reg == 0)
 721                         arizona_in_set_vu(w->codec, 0);
 722         }
 723
 724         return 0;
 725 }
 726 EXPORT_SYMBOL_GPL(arizona_in_ev);
 727
 728 int arizona_out_ev(struct snd_soc_dapm_widget *w,
 729                    struct snd_kcontrol *kcontrol,
 730                    int event)
 731 {
 732         switch (event) {
 733         case SND_SOC_DAPM_POST_PMU:
 734                 switch (w->shift) {
 735                 case ARIZONA_OUT1L_ENA_SHIFT:
 736                 case ARIZONA_OUT1R_ENA_SHIFT:
 737                 case ARIZONA_OUT2L_ENA_SHIFT:
 738                 case ARIZONA_OUT2R_ENA_SHIFT:
 739                 case ARIZONA_OUT3L_ENA_SHIFT:
 740                 case ARIZONA_OUT3R_ENA_SHIFT:
 741                         msleep(17);
 742                         break;
 743
 744                 default:
 745                         break;
 746                 }
 747                 break;
 748         }
 749
 750         return 0;
 751 }
 752 EXPORT_SYMBOL_GPL(arizona_out_ev);
 753
 754 int arizona_hp_ev(struct snd_soc_dapm_widget *w,
 755                    struct snd_kcontrol *kcontrol,
 756                    int event)
 757 {
 758         struct arizona_priv *priv = snd_soc_codec_get_drvdata(w->codec);
 759         struct arizona *arizona = priv->arizona;
 760         unsigned int mask = 1 << w->shift;
 761         unsigned int val;
 762
 763         switch (event) {
 764         case SND_SOC_DAPM_POST_PMU:
 765                 val = mask;
 766                 break;
 767         case SND_SOC_DAPM_PRE_PMD:
 768                 val = 0;
 769                 break;
 770         default:
 771                 return -EINVAL;
 772         }
 773
 774         /* Store the desired state for the HP outputs */
 775         priv->arizona->hp_ena &= ~mask;
 776         priv->arizona->hp_ena |= val;
 777
 778         /* Force off if HPDET magic is active */
 779         if (priv->arizona->hpdet_magic)
 780                 val = 0;
 781
 782         regmap_update_bits_async(arizona->regmap, ARIZONA_OUTPUT_ENABLES_1,
 783                                  mask, val);
 784
 785         return arizona_out_ev(w, kcontrol, event);
 786 }
 787 EXPORT_SYMBOL_GPL(arizona_hp_ev);
 788
 789 static unsigned int arizona_sysclk_48k_rates[] = {
 790         6144000,
 791         12288000,
 792         24576000,
 793         49152000,
 794         73728000,
 795         98304000,
 796         147456000,
 797 };
 798
 799 static unsigned int arizona_sysclk_44k1_rates[] = {
 800         5644800,
 801         11289600,
 802         22579200,
 803         45158400,
 804         67737600,
 805         90316800,
 806         135475200,
 807 };
 808
 809 static int arizona_set_opclk(struct snd_soc_codec *codec, unsigned int clk,
 810                              unsigned int freq)
 811 {
 812         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 813         unsigned int reg;
 814         unsigned int *rates;
 815         int ref, div, refclk;
 816
 817         switch (clk) {
 818         case ARIZONA_CLK_OPCLK:
 819                 reg = ARIZONA_OUTPUT_SYSTEM_CLOCK;
 820                 refclk = priv->sysclk;
 821                 break;
 822         case ARIZONA_CLK_ASYNC_OPCLK:
 823                 reg = ARIZONA_OUTPUT_ASYNC_CLOCK;
 824                 refclk = priv->asyncclk;
 825                 break;
 826         default:
 827                 return -EINVAL;
 828         }
 829
 830         if (refclk % 8000)
 831                 rates = arizona_sysclk_44k1_rates;
 832         else
 833                 rates = arizona_sysclk_48k_rates;
 834
 835         for (ref = 0; ref < ARRAY_SIZE(arizona_sysclk_48k_rates) &&
 836                      rates[ref] <= refclk; ref++) {
 837                 div = 1;
 838                 while (rates[ref] / div >= freq && div < 32) {
 839                         if (rates[ref] / div == freq) {
 840                                 dev_dbg(codec->dev, "Configured %dHz OPCLK\n",
 841                                         freq);
 842                                 snd_soc_update_bits(codec, reg,
 843                                                     ARIZONA_OPCLK_DIV_MASK |
 844                                                     ARIZONA_OPCLK_SEL_MASK,
 845                                                     (div <<
 846                                                      ARIZONA_OPCLK_DIV_SHIFT) |
 847                                                     ref);
 848                                 return 0;
 849                         }
 850                         div++;
 851                 }
 852         }
 853
 854         dev_err(codec->dev, "Unable to generate %dHz OPCLK\n", freq);
 855         return -EINVAL;
 856 }
 857
 858 int arizona_set_sysclk(struct snd_soc_codec *codec, int clk_id,
 859                        int source, unsigned int freq, int dir)
 860 {
 861         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 862         struct arizona *arizona = priv->arizona;
 863         char *name;
 864         unsigned int reg;
 865         unsigned int mask = ARIZONA_SYSCLK_FREQ_MASK | ARIZONA_SYSCLK_SRC_MASK;
 866         unsigned int val = source << ARIZONA_SYSCLK_SRC_SHIFT;
 867         unsigned int *clk;
 868
 869         switch (clk_id) {
 870         case ARIZONA_CLK_SYSCLK:
 871                 name = "SYSCLK";
 872                 reg = ARIZONA_SYSTEM_CLOCK_1;
 873                 clk = &priv->sysclk;
 874                 mask |= ARIZONA_SYSCLK_FRAC;
 875                 break;
 876         case ARIZONA_CLK_ASYNCCLK:
 877                 name = "ASYNCCLK";
 878                 reg = ARIZONA_ASYNC_CLOCK_1;
 879                 clk = &priv->asyncclk;
 880                 break;
 881         case ARIZONA_CLK_OPCLK:
 882         case ARIZONA_CLK_ASYNC_OPCLK:
 883                 return arizona_set_opclk(codec, clk_id, freq);
 884         default:
 885                 return -EINVAL;
 886         }
 887
 888         switch (freq) {
 889         case  5644800:
 890         case  6144000:
 891                 break;
 892         case 11289600:
 893         case 12288000:
 894                 val |= ARIZONA_CLK_12MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 895                 break;
 896         case 22579200:
 897         case 24576000:
 898                 val |= ARIZONA_CLK_24MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 899                 break;
 900         case 45158400:
 901         case 49152000:
 902                 val |= ARIZONA_CLK_49MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 903                 break;
 904         case 67737600:
 905         case 73728000:
 906                 val |= ARIZONA_CLK_73MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 907                 break;
 908         case 90316800:
 909         case 98304000:
 910                 val |= ARIZONA_CLK_98MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 911                 break;
 912         case 135475200:
 913         case 147456000:
 914                 val |= ARIZONA_CLK_147MHZ << ARIZONA_SYSCLK_FREQ_SHIFT;
 915                 break;
 916         case 0:
 917                 dev_dbg(arizona->dev, "%s cleared\n", name);
 918                 *clk = freq;
 919                 return 0;
 920         default:
 921                 return -EINVAL;
 922         }
 923
 924         *clk = freq;
 925
 926         if (freq % 6144000)
 927                 val |= ARIZONA_SYSCLK_FRAC;
 928
 929         dev_dbg(arizona->dev, "%s set to %uHz", name, freq);
 930
 931         return regmap_update_bits(arizona->regmap, reg, mask, val);
 932 }
 933 EXPORT_SYMBOL_GPL(arizona_set_sysclk);
 934
 935 static int arizona_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 936 {
 937         struct snd_soc_codec *codec = dai->codec;
 938         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
 939         struct arizona *arizona = priv->arizona;
 940         int lrclk, bclk, mode, base;
 941
 942         base = dai->driver->base;
 943
 944         lrclk = 0;
 945         bclk = 0;
 946
 947         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 948         case SND_SOC_DAIFMT_DSP_A:
 949                 mode = 0;
 950                 break;
 951         case SND_SOC_DAIFMT_I2S:
 952                 mode = 2;
 953                 break;
 954         default:
 955                 arizona_aif_err(dai, "Unsupported DAI format %d\n",
 956                                 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 957                 return -EINVAL;
 958         }
 959
 960         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 961         case SND_SOC_DAIFMT_CBS_CFS:
 962                 break;
 963         case SND_SOC_DAIFMT_CBS_CFM:
 964                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
 965                 break;
 966         case SND_SOC_DAIFMT_CBM_CFS:
 967                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
 968                 break;
 969         case SND_SOC_DAIFMT_CBM_CFM:
 970                 bclk |= ARIZONA_AIF1_BCLK_MSTR;
 971                 lrclk |= ARIZONA_AIF1TX_LRCLK_MSTR;
 972                 break;
 973         default:
 974                 arizona_aif_err(dai, "Unsupported master mode %d\n",
 975                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 976                 return -EINVAL;
 977         }
 978
 979         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 980         case SND_SOC_DAIFMT_NB_NF:
 981                 break;
 982         case SND_SOC_DAIFMT_IB_IF:
 983                 bclk |= ARIZONA_AIF1_BCLK_INV;
 984                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
 985                 break;
 986         case SND_SOC_DAIFMT_IB_NF:
 987                 bclk |= ARIZONA_AIF1_BCLK_INV;
 988                 break;
 989         case SND_SOC_DAIFMT_NB_IF:
 990                 lrclk |= ARIZONA_AIF1TX_LRCLK_INV;
 991                 break;
 992         default:
 993                 return -EINVAL;
 994         }
 995
 996         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_BCLK_CTRL,
 997                                  ARIZONA_AIF1_BCLK_INV |
 998                                  ARIZONA_AIF1_BCLK_MSTR,
 999                                  bclk);
1000         regmap_update_bits_async(arizona->regmap, base + ARIZONA_AIF_TX_PIN_CTRL,
1001                                  ARIZONA_AIF1TX_LRCLK_INV |
1002                                  ARIZONA_AIF1TX_LRCLK_MSTR, lrclk);
1003         regmap_update_bits_async(arizona->regmap,
1004                                  base + ARIZONA_AIF_RX_PIN_CTRL,
1005                                  ARIZONA_AIF1RX_LRCLK_INV |
1006                                  ARIZONA_AIF1RX_LRCLK_MSTR, lrclk);
1007         regmap_update_bits(arizona->regmap, base + ARIZONA_AIF_FORMAT,
1008                            ARIZONA_AIF1_FMT_MASK, mode);
1009
1010         return 0;
1011 }
1012
1013 static const int arizona_48k_bclk_rates[] = {
1014         -1,
1015         48000,
1016         64000,
1017         96000,
1018         128000,
1019         192000,
1020         256000,
1021         384000,
1022         512000,
1023         768000,
1024         1024000,
1025         1536000,
1026         2048000,
1027         3072000,
1028         4096000,
1029         6144000,
1030         8192000,
1031         12288000,
1032         24576000,
1033 };
1034
1035 static const unsigned int arizona_48k_rates[] = {
1036         12000,
1037         24000,
1038         48000,
1039         96000,
1040         192000,
1041         384000,
1042         768000,
1043         4000,
1044         8000,
1045         16000,
1046         32000,
1047         64000,
1048         128000,
1049         256000,
1050         512000,
1051 };
1052
1053 static const struct snd_pcm_hw_constraint_list arizona_48k_constraint = {
1054         .count  = ARRAY_SIZE(arizona_48k_rates),
1055         .list   = arizona_48k_rates,
1056 };
1057
1058 static const int arizona_44k1_bclk_rates[] = {
1059         -1,
1060         44100,
1061         58800,
1062         88200,
1063         117600,
1064         177640,
1065         235200,
1066         352800,
1067         470400,
1068         705600,
1069         940800,
1070         1411200,
1071         1881600,
1072         2822400,
1073         3763200,
1074         5644800,
1075         7526400,
1076         11289600,
1077         22579200,
1078 };
1079
1080 static const unsigned int arizona_44k1_rates[] = {
1081         11025,
1082         22050,
1083         44100,
1084         88200,
1085         176400,
1086         352800,
1087         705600,
1088 };
1089
1090 static const struct snd_pcm_hw_constraint_list arizona_44k1_constraint = {
1091         .count  = ARRAY_SIZE(arizona_44k1_rates),
1092         .list   = arizona_44k1_rates,
1093 };
1094
1095 static int arizona_sr_vals[] = {
1096         0,
1097         12000,
1098         24000,
1099         48000,
1100         96000,
1101         192000,
1102         384000,
1103         768000,
1104         0,
1105         11025,
1106         22050,
1107         44100,
1108         88200,
1109         176400,
1110         352800,
1111         705600,
1112         4000,
1113         8000,
1114         16000,
1115         32000,
1116         64000,
1117         128000,
1118         256000,
1119         512000,
1120 };
1121
1122 static int arizona_startup(struct snd_pcm_substream *substream,
1123                            struct snd_soc_dai *dai)
1124 {
1125         struct snd_soc_codec *codec = dai->codec;
1126         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1127         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1128         const struct snd_pcm_hw_constraint_list *constraint;
1129         unsigned int base_rate;
1130
1131         switch (dai_priv->clk) {
1132         case ARIZONA_CLK_SYSCLK:
1133                 base_rate = priv->sysclk;
1134                 break;
1135         case ARIZONA_CLK_ASYNCCLK:
1136                 base_rate = priv->asyncclk;
1137                 break;
1138         default:
1139                 return 0;
1140         }
1141
1142         if (base_rate == 0)
1143                 return 0;
1144
1145         if (base_rate % 8000)
1146                 constraint = &arizona_44k1_constraint;
1147         else
1148                 constraint = &arizona_48k_constraint;
1149
1150         return snd_pcm_hw_constraint_list(substream->runtime, 0,
1151                                           SNDRV_PCM_HW_PARAM_RATE,
1152                                           constraint);
1153 }
1154
1155 static void arizona_wm5102_set_dac_comp(struct snd_soc_codec *codec,
1156                                         unsigned int rate)
1157 {
1158         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1159         struct arizona *arizona = priv->arizona;
1160         struct reg_default dac_comp[] = {
1161                 { 0x80, 0x3 },
1162                 { ARIZONA_DAC_COMP_1, 0 },
1163                 { ARIZONA_DAC_COMP_2, 0 },
1164                 { 0x80, 0x0 },
1165         };
1166
1167         mutex_lock(&codec->mutex);
1168
1169         dac_comp[1].def = arizona->dac_comp_coeff;
1170         if (rate >= 176400)
1171                 dac_comp[2].def = arizona->dac_comp_enabled;
1172
1173         mutex_unlock(&codec->mutex);
1174
1175         regmap_multi_reg_write(arizona->regmap,
1176                                dac_comp,
1177                                ARRAY_SIZE(dac_comp));
1178 }
1179
1180 static int arizona_hw_params_rate(struct snd_pcm_substream *substream,
1181                                   struct snd_pcm_hw_params *params,
1182                                   struct snd_soc_dai *dai)
1183 {
1184         struct snd_soc_codec *codec = dai->codec;
1185         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1186         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1187         int base = dai->driver->base;
1188         int i, sr_val;
1189
1190         /*
1191          * We will need to be more flexible than this in future,
1192          * currently we use a single sample rate for SYSCLK.
1193          */
1194         for (i = 0; i < ARRAY_SIZE(arizona_sr_vals); i++)
1195                 if (arizona_sr_vals[i] == params_rate(params))
1196                         break;
1197         if (i == ARRAY_SIZE(arizona_sr_vals)) {
1198                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1199                                 params_rate(params));
1200                 return -EINVAL;
1201         }
1202         sr_val = i;
1203
1204         switch (dai_priv->clk) {
1205         case ARIZONA_CLK_SYSCLK:
1206                 switch (priv->arizona->type) {
1207                 case WM5102:
1208                         arizona_wm5102_set_dac_comp(codec,
1209                                                     params_rate(params));
1210                         break;
1211                 default:
1212                         break;
1213                 }
1214
1215                 snd_soc_update_bits(codec, ARIZONA_SAMPLE_RATE_1,
1216                                     ARIZONA_SAMPLE_RATE_1_MASK, sr_val);
1217                 if (base)
1218                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1219                                             ARIZONA_AIF1_RATE_MASK, 0);
1220                 break;
1221         case ARIZONA_CLK_ASYNCCLK:
1222                 snd_soc_update_bits(codec, ARIZONA_ASYNC_SAMPLE_RATE_1,
1223                                     ARIZONA_ASYNC_SAMPLE_RATE_MASK, sr_val);
1224                 if (base)
1225                         snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1226                                             ARIZONA_AIF1_RATE_MASK,
1227                                             8 << ARIZONA_AIF1_RATE_SHIFT);
1228                 break;
1229         default:
1230                 arizona_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
1231                 return -EINVAL;
1232         }
1233
1234         return 0;
1235 }
1236
1237 static bool arizona_aif_cfg_changed(struct snd_soc_codec *codec,
1238                                     int base, int bclk, int lrclk, int frame)
1239 {
1240         int val;
1241
1242         val = snd_soc_read(codec, base + ARIZONA_AIF_BCLK_CTRL);
1243         if (bclk != (val & ARIZONA_AIF1_BCLK_FREQ_MASK))
1244                 return true;
1245
1246         val = snd_soc_read(codec, base + ARIZONA_AIF_TX_BCLK_RATE);
1247         if (lrclk != (val & ARIZONA_AIF1TX_BCPF_MASK))
1248                 return true;
1249
1250         val = snd_soc_read(codec, base + ARIZONA_AIF_FRAME_CTRL_1);
1251         if (frame != (val & (ARIZONA_AIF1TX_WL_MASK |
1252                              ARIZONA_AIF1TX_SLOT_LEN_MASK)))
1253                 return true;
1254
1255         return false;
1256 }
1257
1258 static int arizona_hw_params(struct snd_pcm_substream *substream,
1259                              struct snd_pcm_hw_params *params,
1260                              struct snd_soc_dai *dai)
1261 {
1262         struct snd_soc_codec *codec = dai->codec;
1263         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1264         struct arizona *arizona = priv->arizona;
1265         int base = dai->driver->base;
1266         const int *rates;
1267         int i, ret, val;
1268         int channels = params_channels(params);
1269         int chan_limit = arizona->pdata.max_channels_clocked[dai->id - 1];
1270         int tdm_width = arizona->tdm_width[dai->id - 1];
1271         int tdm_slots = arizona->tdm_slots[dai->id - 1];
1272         int bclk, lrclk, wl, frame, bclk_target;
1273         bool reconfig;
1274         unsigned int aif_tx_state, aif_rx_state;
1275
1276         if (params_rate(params) % 8000)
1277                 rates = &arizona_44k1_bclk_rates[0];
1278         else
1279                 rates = &arizona_48k_bclk_rates[0];
1280
1281         if (tdm_slots) {
1282                 arizona_aif_dbg(dai, "Configuring for %d %d bit TDM slots\n",
1283                                 tdm_slots, tdm_width);
1284                 bclk_target = tdm_slots * tdm_width * params_rate(params);
1285                 channels = tdm_slots;
1286         } else {
1287                 bclk_target = snd_soc_params_to_bclk(params);
1288         }
1289
1290         if (chan_limit && chan_limit < channels) {
1291                 arizona_aif_dbg(dai, "Limiting to %d channels\n", chan_limit);
1292                 bclk_target /= channels;
1293                 bclk_target *= chan_limit;
1294         }
1295
1296         /* Force multiple of 2 channels for I2S mode */
1297         val = snd_soc_read(codec, base + ARIZONA_AIF_FORMAT);
1298         if ((channels & 1) && (val & ARIZONA_AIF1_FMT_MASK)) {
1299                 arizona_aif_dbg(dai, "Forcing stereo mode\n");
1300                 bclk_target /= channels;
1301                 bclk_target *= channels + 1;
1302         }
1303
1304         for (i = 0; i < ARRAY_SIZE(arizona_44k1_bclk_rates); i++) {
1305                 if (rates[i] >= bclk_target &&
1306                     rates[i] % params_rate(params) == 0) {
1307                         bclk = i;
1308                         break;
1309                 }
1310         }
1311         if (i == ARRAY_SIZE(arizona_44k1_bclk_rates)) {
1312                 arizona_aif_err(dai, "Unsupported sample rate %dHz\n",
1313                                 params_rate(params));
1314                 return -EINVAL;
1315         }
1316
1317         lrclk = rates[bclk] / params_rate(params);
1318
1319         arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n",
1320                         rates[bclk], rates[bclk] / lrclk);
1321
1322         wl = snd_pcm_format_width(params_format(params));
1323         frame = wl << ARIZONA_AIF1TX_WL_SHIFT | wl;
1324
1325         reconfig = arizona_aif_cfg_changed(codec, base, bclk, lrclk, frame);
1326
1327         if (reconfig) {
1328                 /* Save AIF TX/RX state */
1329                 aif_tx_state = snd_soc_read(codec,
1330                                             base + ARIZONA_AIF_TX_ENABLES);
1331                 aif_rx_state = snd_soc_read(codec,
1332                                             base + ARIZONA_AIF_RX_ENABLES);
1333                 /* Disable AIF TX/RX before reconfiguring it */
1334                 regmap_update_bits_async(arizona->regmap,
1335                                     base + ARIZONA_AIF_TX_ENABLES, 0xff, 0x0);
1336                 regmap_update_bits(arizona->regmap,
1337                                     base + ARIZONA_AIF_RX_ENABLES, 0xff, 0x0);
1338         }
1339
1340         ret = arizona_hw_params_rate(substream, params, dai);
1341         if (ret != 0)
1342                 goto restore_aif;
1343
1344         if (reconfig) {
1345                 regmap_update_bits_async(arizona->regmap,
1346                                          base + ARIZONA_AIF_BCLK_CTRL,
1347                                          ARIZONA_AIF1_BCLK_FREQ_MASK, bclk);
1348                 regmap_update_bits_async(arizona->regmap,
1349                                          base + ARIZONA_AIF_TX_BCLK_RATE,
1350                                          ARIZONA_AIF1TX_BCPF_MASK, lrclk);
1351                 regmap_update_bits_async(arizona->regmap,
1352                                          base + ARIZONA_AIF_RX_BCLK_RATE,
1353                                          ARIZONA_AIF1RX_BCPF_MASK, lrclk);
1354                 regmap_update_bits_async(arizona->regmap,
1355                                          base + ARIZONA_AIF_FRAME_CTRL_1,
1356                                          ARIZONA_AIF1TX_WL_MASK |
1357                                          ARIZONA_AIF1TX_SLOT_LEN_MASK, frame);
1358                 regmap_update_bits(arizona->regmap,
1359                                    base + ARIZONA_AIF_FRAME_CTRL_2,
1360                                    ARIZONA_AIF1RX_WL_MASK |
1361                                    ARIZONA_AIF1RX_SLOT_LEN_MASK, frame);
1362         }
1363
1364 restore_aif:
1365         if (reconfig) {
1366                 /* Restore AIF TX/RX state */
1367                 regmap_update_bits_async(arizona->regmap,
1368                                          base + ARIZONA_AIF_TX_ENABLES,
1369                                          0xff, aif_tx_state);
1370                 regmap_update_bits(arizona->regmap,
1371                                    base + ARIZONA_AIF_RX_ENABLES,
1372                                    0xff, aif_rx_state);
1373         }
1374         return ret;
1375 }
1376
1377 static const char *arizona_dai_clk_str(int clk_id)
1378 {
1379         switch (clk_id) {
1380         case ARIZONA_CLK_SYSCLK:
1381                 return "SYSCLK";
1382         case ARIZONA_CLK_ASYNCCLK:
1383                 return "ASYNCCLK";
1384         default:
1385                 return "Unknown clock";
1386         }
1387 }
1388
1389 static int arizona_dai_set_sysclk(struct snd_soc_dai *dai,
1390                                   int clk_id, unsigned int freq, int dir)
1391 {
1392         struct snd_soc_codec *codec = dai->codec;
1393         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1394         struct arizona_dai_priv *dai_priv = &priv->dai[dai->id - 1];
1395         struct snd_soc_dapm_route routes[2];
1396
1397         switch (clk_id) {
1398         case ARIZONA_CLK_SYSCLK:
1399         case ARIZONA_CLK_ASYNCCLK:
1400                 break;
1401         default:
1402                 return -EINVAL;
1403         }
1404
1405         if (clk_id == dai_priv->clk)
1406                 return 0;
1407
1408         if (dai->active) {
1409                 dev_err(codec->dev, "Can't change clock on active DAI %d\n",
1410                         dai->id);
1411                 return -EBUSY;
1412         }
1413
1414         dev_dbg(codec->dev, "Setting AIF%d to %s\n", dai->id + 1,
1415                 arizona_dai_clk_str(clk_id));
1416
1417         memset(&routes, 0, sizeof(routes));
1418         routes[0].sink = dai->driver->capture.stream_name;
1419         routes[1].sink = dai->driver->playback.stream_name;
1420
1421         routes[0].source = arizona_dai_clk_str(dai_priv->clk);
1422         routes[1].source = arizona_dai_clk_str(dai_priv->clk);
1423         snd_soc_dapm_del_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1424
1425         routes[0].source = arizona_dai_clk_str(clk_id);
1426         routes[1].source = arizona_dai_clk_str(clk_id);
1427         snd_soc_dapm_add_routes(&codec->dapm, routes, ARRAY_SIZE(routes));
1428
1429         dai_priv->clk = clk_id;
1430
1431         return snd_soc_dapm_sync(&codec->dapm);
1432 }
1433
1434 static int arizona_set_tristate(struct snd_soc_dai *dai, int tristate)
1435 {
1436         struct snd_soc_codec *codec = dai->codec;
1437         int base = dai->driver->base;
1438         unsigned int reg;
1439
1440         if (tristate)
1441                 reg = ARIZONA_AIF1_TRI;
1442         else
1443                 reg = 0;
1444
1445         return snd_soc_update_bits(codec, base + ARIZONA_AIF_RATE_CTRL,
1446                                    ARIZONA_AIF1_TRI, reg);
1447 }
1448
1449 static void arizona_set_channels_to_mask(struct snd_soc_dai *dai,
1450                                          unsigned int base,
1451                                          int channels, unsigned int mask)
1452 {
1453         struct snd_soc_codec *codec = dai->codec;
1454         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1455         struct arizona *arizona = priv->arizona;
1456         int slot, i;
1457
1458         for (i = 0; i < channels; ++i) {
1459                 slot = ffs(mask) - 1;
1460                 if (slot < 0)
1461                         return;
1462
1463                 regmap_write(arizona->regmap, base + i, slot);
1464
1465                 mask &= ~(1 << slot);
1466         }
1467
1468         if (mask)
1469                 arizona_aif_warn(dai, "Too many channels in TDM mask\n");
1470 }
1471
1472 static int arizona_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1473                                 unsigned int rx_mask, int slots, int slot_width)
1474 {
1475         struct snd_soc_codec *codec = dai->codec;
1476         struct arizona_priv *priv = snd_soc_codec_get_drvdata(codec);
1477         struct arizona *arizona = priv->arizona;
1478         int base = dai->driver->base;
1479         int rx_max_chan = dai->driver->playback.channels_max;
1480         int tx_max_chan = dai->driver->capture.channels_max;
1481
1482         /* Only support TDM for the physical AIFs */
1483         if (dai->id > ARIZONA_MAX_AIF)
1484                 return -ENOTSUPP;
1485
1486         if (slots == 0) {
1487                 tx_mask = (1 << tx_max_chan) - 1;
1488                 rx_mask = (1 << rx_max_chan) - 1;
1489         }
1490
1491         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_3,
1492                                      tx_max_chan, tx_mask);
1493         arizona_set_channels_to_mask(dai, base + ARIZONA_AIF_FRAME_CTRL_11,
1494                                      rx_max_chan, rx_mask);
1495
1496         arizona->tdm_width[dai->id - 1] = slot_width;
1497         arizona->tdm_slots[dai->id - 1] = slots;
1498
1499         return 0;
1500 }
1501
1502 const struct snd_soc_dai_ops arizona_dai_ops = {
1503         .startup = arizona_startup,
1504         .set_fmt = arizona_set_fmt,
1505         .set_tdm_slot = arizona_set_tdm_slot,
1506         .hw_params = arizona_hw_params,
1507         .set_sysclk = arizona_dai_set_sysclk,
1508         .set_tristate = arizona_set_tristate,
1509 };
1510 EXPORT_SYMBOL_GPL(arizona_dai_ops);
1511
1512 const struct snd_soc_dai_ops arizona_simple_dai_ops = {
1513         .startup = arizona_startup,
1514         .hw_params = arizona_hw_params_rate,
1515         .set_sysclk = arizona_dai_set_sysclk,
1516 };
1517 EXPORT_SYMBOL_GPL(arizona_simple_dai_ops);
1518
1519 int arizona_init_dai(struct arizona_priv *priv, int id)
1520 {
1521         struct arizona_dai_priv *dai_priv = &priv->dai[id];
1522
1523         dai_priv->clk = ARIZONA_CLK_SYSCLK;
1524
1525         return 0;
1526 }
1527 EXPORT_SYMBOL_GPL(arizona_init_dai);
1528
1529 static irqreturn_t arizona_fll_clock_ok(int irq, void *data)
1530 {
1531         struct arizona_fll *fll = data;
1532
1533         arizona_fll_dbg(fll, "clock OK\n");
1534
1535         complete(&fll->ok);
1536
1537         return IRQ_HANDLED;
1538 }
1539
1540 static struct {
1541         unsigned int min;
1542         unsigned int max;
1543         u16 fratio;
1544         int ratio;
1545 } fll_fratios[] = {
1546         {       0,    64000, 4, 16 },
1547         {   64000,   128000, 3,  8 },
1548         {  128000,   256000, 2,  4 },
1549         {  256000,  1000000, 1,  2 },
1550         { 1000000, 13500000, 0,  1 },
1551 };
1552
1553 static struct {
1554         unsigned int min;
1555         unsigned int max;
1556         u16 gain;
1557 } fll_gains[] = {
1558         {       0,   256000, 0 },
1559         {  256000,  1000000, 2 },
1560         { 1000000, 13500000, 4 },
1561 };
1562
1563 struct arizona_fll_cfg {
1564         int n;
1565         int theta;
1566         int lambda;
1567         int refdiv;
1568         int outdiv;
1569         int fratio;
1570         int gain;
1571 };
1572
1573 static int arizona_validate_fll(struct arizona_fll *fll,
1574                                 unsigned int Fref,
1575                                 unsigned int Fout)
1576 {
1577         unsigned int Fvco_min;
1578
1579         if (fll->fout && Fout != fll->fout) {
1580                 arizona_fll_err(fll,
1581                                 "Can't change output on active FLL\n");
1582                 return -EINVAL;
1583         }
1584
1585         if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
1586                 arizona_fll_err(fll,
1587                                 "Can't scale %dMHz in to <=13.5MHz\n",
1588                                 Fref);
1589                 return -EINVAL;
1590         }
1591
1592         Fvco_min = ARIZONA_FLL_MIN_FVCO * fll->vco_mult;
1593         if (Fout * ARIZONA_FLL_MAX_OUTDIV < Fvco_min) {
1594                 arizona_fll_err(fll, "No FLL_OUTDIV for Fout=%uHz\n",
1595                                 Fout);
1596                 return -EINVAL;
1597         }
1598
1599         return 0;
1600 }
1601
1602 static int arizona_find_fratio(unsigned int Fref, int *fratio)
1603 {
1604         int i;
1605
1606         /* Find an appropriate FLL_FRATIO */
1607         for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1608                 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1609                         if (fratio)
1610                                 *fratio = fll_fratios[i].fratio;
1611                         return fll_fratios[i].ratio;
1612                 }
1613         }
1614
1615         return -EINVAL;
1616 }
1617
1618 static int arizona_calc_fratio(struct arizona_fll *fll,
1619                                struct arizona_fll_cfg *cfg,
1620                                unsigned int target,
1621                                unsigned int Fref, bool sync)
1622 {
1623         int init_ratio, ratio;
1624         int refdiv, div;
1625
1626         /* Fref must be <=13.5MHz, find initial refdiv */
1627         div = 1;
1628         cfg->refdiv = 0;
1629         while (Fref > ARIZONA_FLL_MAX_FREF) {
1630                 div *= 2;
1631                 Fref /= 2;
1632                 cfg->refdiv++;
1633
1634                 if (div > ARIZONA_FLL_MAX_REFDIV)
1635                         return -EINVAL;
1636         }
1637
1638         /* Find an appropriate FLL_FRATIO */
1639         init_ratio = arizona_find_fratio(Fref, &cfg->fratio);
1640         if (init_ratio < 0) {
1641                 arizona_fll_err(fll, "Unable to find FRATIO for Fref=%uHz\n",
1642                                 Fref);
1643                 return init_ratio;
1644         }
1645
1646         switch (fll->arizona->type) {
1647         case WM5110:
1648                 if (fll->arizona->rev < 3 || sync)
1649                         return init_ratio;
1650                 break;
1651         default:
1652                 return init_ratio;
1653         }
1654
1655         cfg->fratio = init_ratio - 1;
1656
1657         /* Adjust FRATIO/refdiv to avoid integer mode if possible */
1658         refdiv = cfg->refdiv;
1659
1660         while (div <= ARIZONA_FLL_MAX_REFDIV) {
1661                 for (ratio = init_ratio; ratio <= ARIZONA_FLL_MAX_FRATIO;
1662                      ratio++) {
1663                         if ((ARIZONA_FLL_VCO_CORNER / 2) /
1664                             (fll->vco_mult * ratio) < Fref)
1665                                 break;
1666
1667                         if (target % (ratio * Fref)) {
1668                                 cfg->refdiv = refdiv;
1669                                 cfg->fratio = ratio - 1;
1670                                 return ratio;
1671                         }
1672                 }
1673
1674                 for (ratio = init_ratio - 1; ratio > 0; ratio--) {
1675                         if (target % (ratio * Fref)) {
1676                                 cfg->refdiv = refdiv;
1677                                 cfg->fratio = ratio - 1;
1678                                 return ratio;
1679                         }
1680                 }
1681
1682                 div *= 2;
1683                 Fref /= 2;
1684                 refdiv++;
1685                 init_ratio = arizona_find_fratio(Fref, NULL);
1686         }
1687
1688         arizona_fll_warn(fll, "Falling back to integer mode operation\n");
1689         return cfg->fratio + 1;
1690 }
1691
1692 static int arizona_calc_fll(struct arizona_fll *fll,
1693                             struct arizona_fll_cfg *cfg,
1694                             unsigned int Fref, bool sync)
1695 {
1696         unsigned int target, div, gcd_fll;
1697         int i, ratio;
1698
1699         arizona_fll_dbg(fll, "Fref=%u Fout=%u\n", Fref, fll->fout);
1700
1701         /* Fvco should be over the targt; don't check the upper bound */
1702         div = ARIZONA_FLL_MIN_OUTDIV;
1703         while (fll->fout * div < ARIZONA_FLL_MIN_FVCO * fll->vco_mult) {
1704                 div++;
1705                 if (div > ARIZONA_FLL_MAX_OUTDIV)
1706                         return -EINVAL;
1707         }
1708         target = fll->fout * div / fll->vco_mult;
1709         cfg->outdiv = div;
1710
1711         arizona_fll_dbg(fll, "Fvco=%dHz\n", target);
1712
1713         /* Find an appropriate FLL_FRATIO and refdiv */
1714         ratio = arizona_calc_fratio(fll, cfg, target, Fref, sync);
1715         if (ratio < 0)
1716                 return ratio;
1717
1718         /* Apply the division for our remaining calculations */
1719         Fref = Fref / (1 << cfg->refdiv);
1720
1721         cfg->n = target / (ratio * Fref);
1722
1723         if (target % (ratio * Fref)) {
1724                 gcd_fll = gcd(target, ratio * Fref);
1725                 arizona_fll_dbg(fll, "GCD=%u\n", gcd_fll);
1726
1727                 cfg->theta = (target - (cfg->n * ratio * Fref))
1728                         / gcd_fll;
1729                 cfg->lambda = (ratio * Fref) / gcd_fll;
1730         } else {
1731                 cfg->theta = 0;
1732                 cfg->lambda = 0;
1733         }
1734
1735         /* Round down to 16bit range with cost of accuracy lost.
1736          * Denominator must be bigger than numerator so we only
1737          * take care of it.
1738          */
1739         while (cfg->lambda >= (1 << 16)) {
1740                 cfg->theta >>= 1;
1741                 cfg->lambda >>= 1;
1742         }
1743
1744         for (i = 0; i < ARRAY_SIZE(fll_gains); i++) {
1745                 if (fll_gains[i].min <= Fref && Fref <= fll_gains[i].max) {
1746                         cfg->gain = fll_gains[i].gain;
1747                         break;
1748                 }
1749         }
1750         if (i == ARRAY_SIZE(fll_gains)) {
1751                 arizona_fll_err(fll, "Unable to find gain for Fref=%uHz\n",
1752                                 Fref);
1753                 return -EINVAL;
1754         }
1755
1756         arizona_fll_dbg(fll, "N=%x THETA=%x LAMBDA=%x\n",
1757                         cfg->n, cfg->theta, cfg->lambda);
1758         arizona_fll_dbg(fll, "FRATIO=%x(%d) OUTDIV=%x REFCLK_DIV=%x\n",
1759                         cfg->fratio, cfg->fratio, cfg->outdiv, cfg->refdiv);
1760         arizona_fll_dbg(fll, "GAIN=%d\n", cfg->gain);
1761
1762         return 0;
1763
1764 }
1765
1766 static void arizona_apply_fll(struct arizona *arizona, unsigned int base,
1767                               struct arizona_fll_cfg *cfg, int source,
1768                               bool sync)
1769 {
1770         regmap_update_bits_async(arizona->regmap, base + 3,
1771                                  ARIZONA_FLL1_THETA_MASK, cfg->theta);
1772         regmap_update_bits_async(arizona->regmap, base + 4,
1773                                  ARIZONA_FLL1_LAMBDA_MASK, cfg->lambda);
1774         regmap_update_bits_async(arizona->regmap, base + 5,
1775                                  ARIZONA_FLL1_FRATIO_MASK,
1776                                  cfg->fratio << ARIZONA_FLL1_FRATIO_SHIFT);
1777         regmap_update_bits_async(arizona->regmap, base + 6,
1778                                  ARIZONA_FLL1_CLK_REF_DIV_MASK |
1779                                  ARIZONA_FLL1_CLK_REF_SRC_MASK,
1780                                  cfg->refdiv << ARIZONA_FLL1_CLK_REF_DIV_SHIFT |
1781                                  source << ARIZONA_FLL1_CLK_REF_SRC_SHIFT);
1782
1783         if (sync) {
1784                 regmap_update_bits(arizona->regmap, base + 0x7,
1785                                    ARIZONA_FLL1_GAIN_MASK,
1786                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1787         } else {
1788                 regmap_update_bits(arizona->regmap, base + 0x5,
1789                                    ARIZONA_FLL1_OUTDIV_MASK,
1790                                    cfg->outdiv << ARIZONA_FLL1_OUTDIV_SHIFT);
1791                 regmap_update_bits(arizona->regmap, base + 0x9,
1792                                    ARIZONA_FLL1_GAIN_MASK,
1793                                    cfg->gain << ARIZONA_FLL1_GAIN_SHIFT);
1794         }
1795
1796         regmap_update_bits_async(arizona->regmap, base + 2,
1797                                  ARIZONA_FLL1_CTRL_UPD | ARIZONA_FLL1_N_MASK,
1798                                  ARIZONA_FLL1_CTRL_UPD | cfg->n);
1799 }
1800
1801 static int arizona_is_enabled_fll(struct arizona_fll *fll)
1802 {
1803         struct arizona *arizona = fll->arizona;
1804         unsigned int reg;
1805         int ret;
1806
1807         ret = regmap_read(arizona->regmap, fll->base + 1, &reg);
1808         if (ret != 0) {
1809                 arizona_fll_err(fll, "Failed to read current state: %d\n",
1810                                 ret);
1811                 return ret;
1812         }
1813
1814         return reg & ARIZONA_FLL1_ENA;
1815 }
1816
1817 static int arizona_enable_fll(struct arizona_fll *fll)
1818 {
1819         struct arizona *arizona = fll->arizona;
1820         int ret;
1821         bool use_sync = false;
1822         int already_enabled = arizona_is_enabled_fll(fll);
1823         struct arizona_fll_cfg cfg;
1824
1825         if (already_enabled < 0)
1826                 return already_enabled;
1827
1828         if (already_enabled) {
1829                 /* Facilitate smooth refclk across the transition */
1830                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x7,
1831                                          ARIZONA_FLL1_GAIN_MASK, 0);
1832                 regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
1833                                          ARIZONA_FLL1_FREERUN,
1834                                          ARIZONA_FLL1_FREERUN);
1835         }
1836
1837         /*
1838          * If we have both REFCLK and SYNCCLK then enable both,
1839          * otherwise apply the SYNCCLK settings to REFCLK.
1840          */
1841         if (fll->ref_src >= 0 && fll->ref_freq &&
1842             fll->ref_src != fll->sync_src) {
1843                 arizona_calc_fll(fll, &cfg, fll->ref_freq, false);
1844
1845                 arizona_apply_fll(arizona, fll->base, &cfg, fll->ref_src,
1846                                   false);
1847                 if (fll->sync_src >= 0) {
1848                         arizona_calc_fll(fll, &cfg, fll->sync_freq, true);
1849
1850                         arizona_apply_fll(arizona, fll->base + 0x10, &cfg,
1851                                           fll->sync_src, true);
1852                         use_sync = true;
1853                 }
1854         } else if (fll->sync_src >= 0) {
1855                 arizona_calc_fll(fll, &cfg, fll->sync_freq, false);
1856
1857                 arizona_apply_fll(arizona, fll->base, &cfg,
1858                                   fll->sync_src, false);
1859
1860                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1861                                          ARIZONA_FLL1_SYNC_ENA, 0);
1862         } else {
1863                 arizona_fll_err(fll, "No clocks provided\n");
1864                 return -EINVAL;
1865         }
1866
1867         /*
1868          * Increase the bandwidth if we're not using a low frequency
1869          * sync source.
1870          */
1871         if (use_sync && fll->sync_freq > 100000)
1872                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1873                                          ARIZONA_FLL1_SYNC_BW, 0);
1874         else
1875                 regmap_update_bits_async(arizona->regmap, fll->base + 0x17,
1876                                          ARIZONA_FLL1_SYNC_BW,
1877                                          ARIZONA_FLL1_SYNC_BW);
1878
1879         if (!already_enabled)
1880                 pm_runtime_get(arizona->dev);
1881
1882         /* Clear any pending completions */
1883         try_wait_for_completion(&fll->ok);
1884
1885         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1886                                  ARIZONA_FLL1_ENA, ARIZONA_FLL1_ENA);
1887         if (use_sync)
1888                 regmap_update_bits_async(arizona->regmap, fll->base + 0x11,
1889                                          ARIZONA_FLL1_SYNC_ENA,
1890                                          ARIZONA_FLL1_SYNC_ENA);
1891
1892         if (already_enabled)
1893                 regmap_update_bits_async(arizona->regmap, fll->base + 1,
1894                                          ARIZONA_FLL1_FREERUN, 0);
1895
1896         ret = wait_for_completion_timeout(&fll->ok,
1897                                           msecs_to_jiffies(250));
1898         if (ret == 0)
1899                 arizona_fll_warn(fll, "Timed out waiting for lock\n");
1900
1901         return 0;
1902 }
1903
1904 static void arizona_disable_fll(struct arizona_fll *fll)
1905 {
1906         struct arizona *arizona = fll->arizona;
1907         bool change;
1908
1909         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1910                                  ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN);
1911         regmap_update_bits_check(arizona->regmap, fll->base + 1,
1912                                  ARIZONA_FLL1_ENA, 0, &change);
1913         regmap_update_bits(arizona->regmap, fll->base + 0x11,
1914                            ARIZONA_FLL1_SYNC_ENA, 0);
1915         regmap_update_bits_async(arizona->regmap, fll->base + 1,
1916                                  ARIZONA_FLL1_FREERUN, 0);
1917
1918         if (change)
1919                 pm_runtime_put_autosuspend(arizona->dev);
1920 }
1921
1922 int arizona_set_fll_refclk(struct arizona_fll *fll, int source,
1923                            unsigned int Fref, unsigned int Fout)
1924 {
1925         int ret = 0;
1926
1927         if (fll->ref_src == source && fll->ref_freq == Fref)
1928                 return 0;
1929
1930         if (fll->fout && Fref > 0) {
1931                 ret = arizona_validate_fll(fll, Fref, fll->fout);
1932                 if (ret != 0)
1933                         return ret;
1934         }
1935
1936         fll->ref_src = source;
1937         fll->ref_freq = Fref;
1938
1939         if (fll->fout && Fref > 0) {
1940                 ret = arizona_enable_fll(fll);
1941         }
1942
1943         return ret;
1944 }
1945 EXPORT_SYMBOL_GPL(arizona_set_fll_refclk);
1946
1947 int arizona_set_fll(struct arizona_fll *fll, int source,
1948                     unsigned int Fref, unsigned int Fout)
1949 {
1950         int ret = 0;
1951
1952         if (fll->sync_src == source &&
1953             fll->sync_freq == Fref && fll->fout == Fout)
1954                 return 0;
1955
1956         if (Fout) {
1957                 if (fll->ref_src >= 0) {
1958                         ret = arizona_validate_fll(fll, fll->ref_freq, Fout);
1959                         if (ret != 0)
1960                                 return ret;
1961                 }
1962
1963                 ret = arizona_validate_fll(fll, Fref, Fout);
1964                 if (ret != 0)
1965                         return ret;
1966         }
1967
1968         fll->sync_src = source;
1969         fll->sync_freq = Fref;
1970         fll->fout = Fout;
1971
1972         if (Fout)
1973                 ret = arizona_enable_fll(fll);
1974         else
1975                 arizona_disable_fll(fll);
1976
1977         return ret;
1978 }
1979 EXPORT_SYMBOL_GPL(arizona_set_fll);
1980
1981 int arizona_init_fll(struct arizona *arizona, int id, int base, int lock_irq,
1982                      int ok_irq, struct arizona_fll *fll)
1983 {
1984         int ret;
1985         unsigned int val;
1986
1987         init_completion(&fll->ok);
1988
1989         fll->id = id;
1990         fll->base = base;
1991         fll->arizona = arizona;
1992         fll->sync_src = ARIZONA_FLL_SRC_NONE;
1993
1994         /* Configure default refclk to 32kHz if we have one */
1995         regmap_read(arizona->regmap, ARIZONA_CLOCK_32K_1, &val);
1996         switch (val & ARIZONA_CLK_32K_SRC_MASK) {
1997         case ARIZONA_CLK_SRC_MCLK1:
1998         case ARIZONA_CLK_SRC_MCLK2:
1999                 fll->ref_src = val & ARIZONA_CLK_32K_SRC_MASK;
2000                 break;
2001         default:
2002                 fll->ref_src = ARIZONA_FLL_SRC_NONE;
2003         }
2004         fll->ref_freq = 32768;
2005
2006         snprintf(fll->lock_name, sizeof(fll->lock_name), "FLL%d lock", id);
2007         snprintf(fll->clock_ok_name, sizeof(fll->clock_ok_name),
2008                  "FLL%d clock OK", id);
2009
2010         ret = arizona_request_irq(arizona, ok_irq, fll->clock_ok_name,
2011                                   arizona_fll_clock_ok, fll);
2012         if (ret != 0) {
2013                 dev_err(arizona->dev, "Failed to get FLL%d clock OK IRQ: %d\n",
2014                         id, ret);
2015         }
2016
2017         regmap_update_bits(arizona->regmap, fll->base + 1,
2018                            ARIZONA_FLL1_FREERUN, 0);
2019
2020         return 0;
2021 }
2022 EXPORT_SYMBOL_GPL(arizona_init_fll);
2023
2024 /**
2025  * arizona_set_output_mode - Set the mode of the specified output
2026  *
2027  * @codec: Device to configure
2028  * @output: Output number
2029  * @diff: True to set the output to differential mode
2030  *
2031  * Some systems use external analogue switches to connect more
2032  * analogue devices to the CODEC than are supported by the device.  In
2033  * some systems this requires changing the switched output from single
2034  * ended to differential mode dynamically at runtime, an operation
2035  * supported using this function.
2036  *
2037  * Most systems have a single static configuration and should use
2038  * platform data instead.
2039  */
2040 int arizona_set_output_mode(struct snd_soc_codec *codec, int output, bool diff)
2041 {
2042         unsigned int reg, val;
2043
2044         if (output < 1 || output > 6)
2045                 return -EINVAL;
2046
2047         reg = ARIZONA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
2048
2049         if (diff)
2050                 val = ARIZONA_OUT1_MONO;
2051         else
2052                 val = 0;
2053
2054         return snd_soc_update_bits(codec, reg, ARIZONA_OUT1_MONO, val);
2055 }
2056 EXPORT_SYMBOL_GPL(arizona_set_output_mode);
2057
2058 MODULE_DESCRIPTION("ASoC Wolfson Arizona class device support");
2059 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2060 MODULE_LICENSE("GPL");