2 * ALSA SoC Texas Instruments TLV320DAC33 codec driver
4 * Author: Peter Ujfalusi <peter.ujfalusi@nokia.com>
6 * Copyright: (C) 2009 Nokia Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
29 #include <linux/i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/interrupt.h>
32 #include <linux/gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/slab.h>
35 #include <sound/core.h>
36 #include <sound/pcm.h>
37 #include <sound/pcm_params.h>
38 #include <sound/soc.h>
39 #include <sound/soc-dapm.h>
40 #include <sound/initval.h>
41 #include <sound/tlv.h>
43 #include <sound/tlv320dac33-plat.h>
44 #include "tlv320dac33.h"
46 #define DAC33_BUFFER_SIZE_BYTES 24576 /* bytes, 12288 16 bit words,
48 #define DAC33_BUFFER_SIZE_SAMPLES 6144
50 #define NSAMPLE_MAX 5700
53 #define MODE7_UTHR (DAC33_BUFFER_SIZE_SAMPLES - 10)
55 #define BURST_BASEFREQ_HZ 49152000
57 #define SAMPLES_TO_US(rate, samples) \
58 (1000000000 / ((rate * 1000) / samples))
60 #define US_TO_SAMPLES(rate, us) \
61 (rate / (1000000 / us))
63 #define UTHR_FROM_PERIOD_SIZE(samples, playrate, burstrate) \
64 ((samples * 5000) / ((burstrate * 5000) / (burstrate - playrate)))
66 static void dac33_calculate_times(struct snd_pcm_substream *substream);
67 static int dac33_prepare_chip(struct snd_pcm_substream *substream);
76 enum dac33_fifo_modes {
77 DAC33_FIFO_BYPASS = 0,
83 #define DAC33_NUM_SUPPLIES 3
84 static const char *dac33_supply_names[DAC33_NUM_SUPPLIES] = {
90 struct tlv320dac33_priv {
92 struct workqueue_struct *dac33_wq;
93 struct work_struct work;
94 struct snd_soc_codec *codec;
95 struct regulator_bulk_data supplies[DAC33_NUM_SUPPLIES];
96 struct snd_pcm_substream *substream;
102 unsigned int alarm_threshold; /* set to be half of LATENCY_TIME_MS */
103 unsigned int nsample_min; /* nsample should not be lower than
105 unsigned int nsample_max; /* nsample should not be higher than
107 enum dac33_fifo_modes fifo_mode;/* FIFO mode selection */
108 unsigned int nsample; /* burst read amount from host */
109 int mode1_latency; /* latency caused by the i2c writes in
111 int auto_fifo_config; /* Configure the FIFO based on the
113 u8 burst_bclkdiv; /* BCLK divider value in burst mode */
114 unsigned int burst_rate; /* Interface speed in Burst modes */
116 int keep_bclk; /* Keep the BCLK continuously running
119 unsigned long long t_stamp1; /* Time stamp for FIFO modes to */
120 unsigned long long t_stamp2; /* calculate the FIFO caused delay */
122 unsigned int mode1_us_burst; /* Time to burst read n number of
124 unsigned int mode7_us_to_lthr; /* Time to reach lthr from uthr */
128 enum dac33_state state;
129 enum snd_soc_control_type control_type;
133 static const u8 dac33_reg[DAC33_CACHEREGNUM] = {
134 0x00, 0x00, 0x00, 0x00, /* 0x00 - 0x03 */
135 0x00, 0x00, 0x00, 0x00, /* 0x04 - 0x07 */
136 0x00, 0x00, 0x00, 0x00, /* 0x08 - 0x0b */
137 0x00, 0x00, 0x00, 0x00, /* 0x0c - 0x0f */
138 0x00, 0x00, 0x00, 0x00, /* 0x10 - 0x13 */
139 0x00, 0x00, 0x00, 0x00, /* 0x14 - 0x17 */
140 0x00, 0x00, 0x00, 0x00, /* 0x18 - 0x1b */
141 0x00, 0x00, 0x00, 0x00, /* 0x1c - 0x1f */
142 0x00, 0x00, 0x00, 0x00, /* 0x20 - 0x23 */
143 0x00, 0x00, 0x00, 0x00, /* 0x24 - 0x27 */
144 0x00, 0x00, 0x00, 0x00, /* 0x28 - 0x2b */
145 0x00, 0x00, 0x00, 0x80, /* 0x2c - 0x2f */
146 0x80, 0x00, 0x00, 0x00, /* 0x30 - 0x33 */
147 0x00, 0x00, 0x00, 0x00, /* 0x34 - 0x37 */
148 0x00, 0x00, /* 0x38 - 0x39 */
149 /* Registers 0x3a - 0x3f are reserved */
150 0x00, 0x00, /* 0x3a - 0x3b */
151 0x00, 0x00, 0x00, 0x00, /* 0x3c - 0x3f */
153 0x00, 0x00, 0x00, 0x00, /* 0x40 - 0x43 */
154 0x00, 0x80, /* 0x44 - 0x45 */
155 /* Registers 0x46 - 0x47 are reserved */
156 0x80, 0x80, /* 0x46 - 0x47 */
158 0x80, 0x00, 0x00, /* 0x48 - 0x4a */
159 /* Registers 0x4b - 0x7c are reserved */
161 0x00, 0x00, 0x00, 0x00, /* 0x4c - 0x4f */
162 0x00, 0x00, 0x00, 0x00, /* 0x50 - 0x53 */
163 0x00, 0x00, 0x00, 0x00, /* 0x54 - 0x57 */
164 0x00, 0x00, 0x00, 0x00, /* 0x58 - 0x5b */
165 0x00, 0x00, 0x00, 0x00, /* 0x5c - 0x5f */
166 0x00, 0x00, 0x00, 0x00, /* 0x60 - 0x63 */
167 0x00, 0x00, 0x00, 0x00, /* 0x64 - 0x67 */
168 0x00, 0x00, 0x00, 0x00, /* 0x68 - 0x6b */
169 0x00, 0x00, 0x00, 0x00, /* 0x6c - 0x6f */
170 0x00, 0x00, 0x00, 0x00, /* 0x70 - 0x73 */
171 0x00, 0x00, 0x00, 0x00, /* 0x74 - 0x77 */
172 0x00, 0x00, 0x00, 0x00, /* 0x78 - 0x7b */
175 0xda, 0x33, 0x03, /* 0x7d - 0x7f */
178 /* Register read and write */
179 static inline unsigned int dac33_read_reg_cache(struct snd_soc_codec *codec,
182 u8 *cache = codec->reg_cache;
183 if (reg >= DAC33_CACHEREGNUM)
189 static inline void dac33_write_reg_cache(struct snd_soc_codec *codec,
192 u8 *cache = codec->reg_cache;
193 if (reg >= DAC33_CACHEREGNUM)
199 static int dac33_read(struct snd_soc_codec *codec, unsigned int reg,
202 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
207 /* If powered off, return the cached value */
208 if (dac33->chip_power) {
209 val = i2c_smbus_read_byte_data(codec->control_data, value[0]);
211 dev_err(codec->dev, "Read failed (%d)\n", val);
212 value[0] = dac33_read_reg_cache(codec, reg);
215 dac33_write_reg_cache(codec, reg, val);
218 value[0] = dac33_read_reg_cache(codec, reg);
224 static int dac33_write(struct snd_soc_codec *codec, unsigned int reg,
227 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
233 * D15..D8 dac33 register offset
234 * D7...D0 register data
236 data[0] = reg & 0xff;
237 data[1] = value & 0xff;
239 dac33_write_reg_cache(codec, data[0], data[1]);
240 if (dac33->chip_power) {
241 ret = codec->hw_write(codec->control_data, data, 2);
243 dev_err(codec->dev, "Write failed (%d)\n", ret);
251 static int dac33_write_locked(struct snd_soc_codec *codec, unsigned int reg,
254 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
257 mutex_lock(&dac33->mutex);
258 ret = dac33_write(codec, reg, value);
259 mutex_unlock(&dac33->mutex);
264 #define DAC33_I2C_ADDR_AUTOINC 0x80
265 static int dac33_write16(struct snd_soc_codec *codec, unsigned int reg,
268 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
274 * D23..D16 dac33 register offset
275 * D15..D8 register data MSB
276 * D7...D0 register data LSB
278 data[0] = reg & 0xff;
279 data[1] = (value >> 8) & 0xff;
280 data[2] = value & 0xff;
282 dac33_write_reg_cache(codec, data[0], data[1]);
283 dac33_write_reg_cache(codec, data[0] + 1, data[2]);
285 if (dac33->chip_power) {
286 /* We need to set autoincrement mode for 16 bit writes */
287 data[0] |= DAC33_I2C_ADDR_AUTOINC;
288 ret = codec->hw_write(codec->control_data, data, 3);
290 dev_err(codec->dev, "Write failed (%d)\n", ret);
298 static void dac33_init_chip(struct snd_soc_codec *codec)
300 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
302 if (unlikely(!dac33->chip_power))
305 /* 44-46: DAC Control Registers */
306 /* A : DAC sample rate Fsref/1.5 */
307 dac33_write(codec, DAC33_DAC_CTRL_A, DAC33_DACRATE(0));
308 /* B : DAC src=normal, not muted */
309 dac33_write(codec, DAC33_DAC_CTRL_B, DAC33_DACSRCR_RIGHT |
312 dac33_write(codec, DAC33_DAC_CTRL_C, 0x00);
314 /* 73 : volume soft stepping control,
315 clock source = internal osc (?) */
316 dac33_write(codec, DAC33_ANA_VOL_SOFT_STEP_CTRL, DAC33_VOLCLKEN);
318 dac33_write(codec, DAC33_PWR_CTRL, DAC33_PDNALLB);
320 /* Restore only selected registers (gains mostly) */
321 dac33_write(codec, DAC33_LDAC_DIG_VOL_CTRL,
322 dac33_read_reg_cache(codec, DAC33_LDAC_DIG_VOL_CTRL));
323 dac33_write(codec, DAC33_RDAC_DIG_VOL_CTRL,
324 dac33_read_reg_cache(codec, DAC33_RDAC_DIG_VOL_CTRL));
326 dac33_write(codec, DAC33_LINEL_TO_LLO_VOL,
327 dac33_read_reg_cache(codec, DAC33_LINEL_TO_LLO_VOL));
328 dac33_write(codec, DAC33_LINER_TO_RLO_VOL,
329 dac33_read_reg_cache(codec, DAC33_LINER_TO_RLO_VOL));
332 static inline void dac33_read_id(struct snd_soc_codec *codec)
336 dac33_read(codec, DAC33_DEVICE_ID_MSB, ®);
337 dac33_read(codec, DAC33_DEVICE_ID_LSB, ®);
338 dac33_read(codec, DAC33_DEVICE_REV_ID, ®);
341 static inline void dac33_soft_power(struct snd_soc_codec *codec, int power)
345 reg = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
347 reg |= DAC33_PDNALLB;
349 reg &= ~(DAC33_PDNALLB | DAC33_OSCPDNB |
350 DAC33_DACRPDNB | DAC33_DACLPDNB);
351 dac33_write(codec, DAC33_PWR_CTRL, reg);
354 static int dac33_hard_power(struct snd_soc_codec *codec, int power)
356 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
359 mutex_lock(&dac33->mutex);
362 if (unlikely(power == dac33->chip_power)) {
363 dev_dbg(codec->dev, "Trying to set the same power state: %s\n",
364 power ? "ON" : "OFF");
369 ret = regulator_bulk_enable(ARRAY_SIZE(dac33->supplies),
373 "Failed to enable supplies: %d\n", ret);
377 if (dac33->power_gpio >= 0)
378 gpio_set_value(dac33->power_gpio, 1);
380 dac33->chip_power = 1;
382 dac33_soft_power(codec, 0);
383 if (dac33->power_gpio >= 0)
384 gpio_set_value(dac33->power_gpio, 0);
386 ret = regulator_bulk_disable(ARRAY_SIZE(dac33->supplies),
390 "Failed to disable supplies: %d\n", ret);
394 dac33->chip_power = 0;
398 mutex_unlock(&dac33->mutex);
402 static int playback_event(struct snd_soc_dapm_widget *w,
403 struct snd_kcontrol *kcontrol, int event)
405 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(w->codec);
408 case SND_SOC_DAPM_PRE_PMU:
409 if (likely(dac33->substream)) {
410 dac33_calculate_times(dac33->substream);
411 dac33_prepare_chip(dac33->substream);
418 static int dac33_get_nsample(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
421 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
422 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
424 ucontrol->value.integer.value[0] = dac33->nsample;
429 static int dac33_set_nsample(struct snd_kcontrol *kcontrol,
430 struct snd_ctl_elem_value *ucontrol)
432 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
433 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
436 if (dac33->nsample == ucontrol->value.integer.value[0])
439 if (ucontrol->value.integer.value[0] < dac33->nsample_min ||
440 ucontrol->value.integer.value[0] > dac33->nsample_max) {
443 dac33->nsample = ucontrol->value.integer.value[0];
444 /* Re calculate the burst time */
445 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
452 static int dac33_get_uthr(struct snd_kcontrol *kcontrol,
453 struct snd_ctl_elem_value *ucontrol)
455 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
456 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
458 ucontrol->value.integer.value[0] = dac33->uthr;
463 static int dac33_set_uthr(struct snd_kcontrol *kcontrol,
464 struct snd_ctl_elem_value *ucontrol)
466 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
467 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
470 if (dac33->substream)
473 if (dac33->uthr == ucontrol->value.integer.value[0])
476 if (ucontrol->value.integer.value[0] < (MODE7_LTHR + 10) ||
477 ucontrol->value.integer.value[0] > MODE7_UTHR)
480 dac33->uthr = ucontrol->value.integer.value[0];
485 static int dac33_get_fifo_mode(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
488 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
489 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
491 ucontrol->value.integer.value[0] = dac33->fifo_mode;
496 static int dac33_set_fifo_mode(struct snd_kcontrol *kcontrol,
497 struct snd_ctl_elem_value *ucontrol)
499 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
500 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
503 if (dac33->fifo_mode == ucontrol->value.integer.value[0])
505 /* Do not allow changes while stream is running*/
509 if (ucontrol->value.integer.value[0] < 0 ||
510 ucontrol->value.integer.value[0] >= DAC33_FIFO_LAST_MODE)
513 dac33->fifo_mode = ucontrol->value.integer.value[0];
518 /* Codec operation modes */
519 static const char *dac33_fifo_mode_texts[] = {
520 "Bypass", "Mode 1", "Mode 7"
523 static const struct soc_enum dac33_fifo_mode_enum =
524 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dac33_fifo_mode_texts),
525 dac33_fifo_mode_texts);
527 /* L/R Line Output Gain */
528 static const char *lr_lineout_gain_texts[] = {
529 "Line -12dB DAC 0dB", "Line -6dB DAC 6dB",
530 "Line 0dB DAC 12dB", "Line 6dB DAC 18dB",
533 static const struct soc_enum l_lineout_gain_enum =
534 SOC_ENUM_SINGLE(DAC33_LDAC_PWR_CTRL, 0,
535 ARRAY_SIZE(lr_lineout_gain_texts),
536 lr_lineout_gain_texts);
538 static const struct soc_enum r_lineout_gain_enum =
539 SOC_ENUM_SINGLE(DAC33_RDAC_PWR_CTRL, 0,
540 ARRAY_SIZE(lr_lineout_gain_texts),
541 lr_lineout_gain_texts);
544 * DACL/R digital volume control:
545 * from 0 dB to -63.5 in 0.5 dB steps
546 * Need to be inverted later on:
550 static DECLARE_TLV_DB_SCALE(dac_digivol_tlv, -6350, 50, 0);
552 static const struct snd_kcontrol_new dac33_snd_controls[] = {
553 SOC_DOUBLE_R_TLV("DAC Digital Playback Volume",
554 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL,
555 0, 0x7f, 1, dac_digivol_tlv),
556 SOC_DOUBLE_R("DAC Digital Playback Switch",
557 DAC33_LDAC_DIG_VOL_CTRL, DAC33_RDAC_DIG_VOL_CTRL, 7, 1, 1),
558 SOC_DOUBLE_R("Line to Line Out Volume",
559 DAC33_LINEL_TO_LLO_VOL, DAC33_LINER_TO_RLO_VOL, 0, 127, 1),
560 SOC_ENUM("Left Line Output Gain", l_lineout_gain_enum),
561 SOC_ENUM("Right Line Output Gain", r_lineout_gain_enum),
564 static const struct snd_kcontrol_new dac33_mode_snd_controls[] = {
565 SOC_ENUM_EXT("FIFO Mode", dac33_fifo_mode_enum,
566 dac33_get_fifo_mode, dac33_set_fifo_mode),
569 static const struct snd_kcontrol_new dac33_fifo_snd_controls[] = {
570 SOC_SINGLE_EXT("nSample", 0, 0, 5900, 0,
571 dac33_get_nsample, dac33_set_nsample),
572 SOC_SINGLE_EXT("UTHR", 0, 0, MODE7_UTHR, 0,
573 dac33_get_uthr, dac33_set_uthr),
577 static const struct snd_kcontrol_new dac33_dapm_abypassl_control =
578 SOC_DAPM_SINGLE("Switch", DAC33_LINEL_TO_LLO_VOL, 7, 1, 1);
580 static const struct snd_kcontrol_new dac33_dapm_abypassr_control =
581 SOC_DAPM_SINGLE("Switch", DAC33_LINER_TO_RLO_VOL, 7, 1, 1);
583 static const struct snd_soc_dapm_widget dac33_dapm_widgets[] = {
584 SND_SOC_DAPM_OUTPUT("LEFT_LO"),
585 SND_SOC_DAPM_OUTPUT("RIGHT_LO"),
587 SND_SOC_DAPM_INPUT("LINEL"),
588 SND_SOC_DAPM_INPUT("LINER"),
590 SND_SOC_DAPM_DAC("DACL", "Left Playback", DAC33_LDAC_PWR_CTRL, 2, 0),
591 SND_SOC_DAPM_DAC("DACR", "Right Playback", DAC33_RDAC_PWR_CTRL, 2, 0),
594 SND_SOC_DAPM_SWITCH("Analog Left Bypass", SND_SOC_NOPM, 0, 0,
595 &dac33_dapm_abypassl_control),
596 SND_SOC_DAPM_SWITCH("Analog Right Bypass", SND_SOC_NOPM, 0, 0,
597 &dac33_dapm_abypassr_control),
599 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Left Amp Power",
600 DAC33_OUT_AMP_PWR_CTRL, 6, 3, 3, 0),
601 SND_SOC_DAPM_REG(snd_soc_dapm_mixer, "Output Right Amp Power",
602 DAC33_OUT_AMP_PWR_CTRL, 4, 3, 3, 0),
604 SND_SOC_DAPM_PRE("Prepare Playback", playback_event),
607 static const struct snd_soc_dapm_route audio_map[] = {
609 {"Analog Left Bypass", "Switch", "LINEL"},
610 {"Analog Right Bypass", "Switch", "LINER"},
612 {"Output Left Amp Power", NULL, "DACL"},
613 {"Output Right Amp Power", NULL, "DACR"},
615 {"Output Left Amp Power", NULL, "Analog Left Bypass"},
616 {"Output Right Amp Power", NULL, "Analog Right Bypass"},
619 {"LEFT_LO", NULL, "Output Left Amp Power"},
620 {"RIGHT_LO", NULL, "Output Right Amp Power"},
623 static int dac33_add_widgets(struct snd_soc_codec *codec)
625 snd_soc_dapm_new_controls(codec, dac33_dapm_widgets,
626 ARRAY_SIZE(dac33_dapm_widgets));
628 /* set up audio path interconnects */
629 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
634 static int dac33_set_bias_level(struct snd_soc_codec *codec,
635 enum snd_soc_bias_level level)
640 case SND_SOC_BIAS_ON:
641 dac33_soft_power(codec, 1);
643 case SND_SOC_BIAS_PREPARE:
645 case SND_SOC_BIAS_STANDBY:
646 if (codec->bias_level == SND_SOC_BIAS_OFF) {
647 /* Coming from OFF, switch on the codec */
648 ret = dac33_hard_power(codec, 1);
652 dac33_init_chip(codec);
655 case SND_SOC_BIAS_OFF:
656 /* Do not power off, when the codec is already off */
657 if (codec->bias_level == SND_SOC_BIAS_OFF)
659 ret = dac33_hard_power(codec, 0);
664 codec->bias_level = level;
669 static inline void dac33_prefill_handler(struct tlv320dac33_priv *dac33)
671 struct snd_soc_codec *codec = dac33->codec;
673 switch (dac33->fifo_mode) {
674 case DAC33_FIFO_MODE1:
675 dac33_write16(codec, DAC33_NSAMPLE_MSB,
676 DAC33_THRREG(dac33->nsample));
678 /* Take the timestamps */
679 spin_lock_irq(&dac33->lock);
680 dac33->t_stamp2 = ktime_to_us(ktime_get());
681 dac33->t_stamp1 = dac33->t_stamp2;
682 spin_unlock_irq(&dac33->lock);
684 dac33_write16(codec, DAC33_PREFILL_MSB,
685 DAC33_THRREG(dac33->alarm_threshold));
686 /* Enable Alarm Threshold IRQ with a delay */
687 udelay(SAMPLES_TO_US(dac33->burst_rate,
688 dac33->alarm_threshold));
689 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MAT);
691 case DAC33_FIFO_MODE7:
692 /* Take the timestamp */
693 spin_lock_irq(&dac33->lock);
694 dac33->t_stamp1 = ktime_to_us(ktime_get());
695 /* Move back the timestamp with drain time */
696 dac33->t_stamp1 -= dac33->mode7_us_to_lthr;
697 spin_unlock_irq(&dac33->lock);
699 dac33_write16(codec, DAC33_PREFILL_MSB,
700 DAC33_THRREG(MODE7_LTHR));
702 /* Enable Upper Threshold IRQ */
703 dac33_write(codec, DAC33_FIFO_IRQ_MASK, DAC33_MUT);
706 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
712 static inline void dac33_playback_handler(struct tlv320dac33_priv *dac33)
714 struct snd_soc_codec *codec = dac33->codec;
716 switch (dac33->fifo_mode) {
717 case DAC33_FIFO_MODE1:
718 /* Take the timestamp */
719 spin_lock_irq(&dac33->lock);
720 dac33->t_stamp2 = ktime_to_us(ktime_get());
721 spin_unlock_irq(&dac33->lock);
723 dac33_write16(codec, DAC33_NSAMPLE_MSB,
724 DAC33_THRREG(dac33->nsample));
726 case DAC33_FIFO_MODE7:
727 /* At the moment we are not using interrupts in mode7 */
730 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
736 static void dac33_work(struct work_struct *work)
738 struct snd_soc_codec *codec;
739 struct tlv320dac33_priv *dac33;
742 dac33 = container_of(work, struct tlv320dac33_priv, work);
743 codec = dac33->codec;
745 mutex_lock(&dac33->mutex);
746 switch (dac33->state) {
748 dac33->state = DAC33_PLAYBACK;
749 dac33_prefill_handler(dac33);
752 dac33_playback_handler(dac33);
757 dac33->state = DAC33_IDLE;
758 /* Mask all interrupts from dac33 */
759 dac33_write(codec, DAC33_FIFO_IRQ_MASK, 0);
762 reg = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
763 reg |= DAC33_FIFOFLUSH;
764 dac33_write(codec, DAC33_FIFO_CTRL_A, reg);
767 mutex_unlock(&dac33->mutex);
770 static irqreturn_t dac33_interrupt_handler(int irq, void *dev)
772 struct snd_soc_codec *codec = dev;
773 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
775 spin_lock(&dac33->lock);
776 dac33->t_stamp1 = ktime_to_us(ktime_get());
777 spin_unlock(&dac33->lock);
779 /* Do not schedule the workqueue in Mode7 */
780 if (dac33->fifo_mode != DAC33_FIFO_MODE7)
781 queue_work(dac33->dac33_wq, &dac33->work);
786 static void dac33_oscwait(struct snd_soc_codec *codec)
793 dac33_read(codec, DAC33_INT_OSC_STATUS, ®);
794 } while (((reg & 0x03) != DAC33_OSCSTATUS_NORMAL) && timeout--);
795 if ((reg & 0x03) != DAC33_OSCSTATUS_NORMAL)
797 "internal oscillator calibration failed\n");
800 static int dac33_startup(struct snd_pcm_substream *substream,
801 struct snd_soc_dai *dai)
803 struct snd_soc_pcm_runtime *rtd = substream->private_data;
804 struct snd_soc_codec *codec = rtd->codec;
805 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
807 /* Stream started, save the substream pointer */
808 dac33->substream = substream;
813 static void dac33_shutdown(struct snd_pcm_substream *substream,
814 struct snd_soc_dai *dai)
816 struct snd_soc_pcm_runtime *rtd = substream->private_data;
817 struct snd_soc_codec *codec = rtd->codec;
818 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
820 dac33->substream = NULL;
822 /* Reset the nSample restrictions */
823 dac33->nsample_min = 0;
824 dac33->nsample_max = NSAMPLE_MAX;
827 static int dac33_hw_params(struct snd_pcm_substream *substream,
828 struct snd_pcm_hw_params *params,
829 struct snd_soc_dai *dai)
831 struct snd_soc_pcm_runtime *rtd = substream->private_data;
832 struct snd_soc_codec *codec = rtd->codec;
834 /* Check parameters for validity */
835 switch (params_rate(params)) {
840 dev_err(codec->dev, "unsupported rate %d\n",
841 params_rate(params));
845 switch (params_format(params)) {
846 case SNDRV_PCM_FORMAT_S16_LE:
849 dev_err(codec->dev, "unsupported format %d\n",
850 params_format(params));
857 #define CALC_OSCSET(rate, refclk) ( \
858 ((((rate * 10000) / refclk) * 4096) + 7000) / 10000)
859 #define CALC_RATIOSET(rate, refclk) ( \
860 ((((refclk * 100000) / rate) * 16384) + 50000) / 100000)
863 * tlv320dac33 is strict on the sequence of the register writes, if the register
864 * writes happens in different order, than dac33 might end up in unknown state.
865 * Use the known, working sequence of register writes to initialize the dac33.
867 static int dac33_prepare_chip(struct snd_pcm_substream *substream)
869 struct snd_soc_pcm_runtime *rtd = substream->private_data;
870 struct snd_soc_codec *codec = rtd->codec;
871 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
872 unsigned int oscset, ratioset, pwr_ctrl, reg_tmp;
873 u8 aictrl_a, aictrl_b, fifoctrl_a;
875 switch (substream->runtime->rate) {
878 oscset = CALC_OSCSET(substream->runtime->rate, dac33->refclk);
879 ratioset = CALC_RATIOSET(substream->runtime->rate,
883 dev_err(codec->dev, "unsupported rate %d\n",
884 substream->runtime->rate);
889 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
890 aictrl_a &= ~(DAC33_NCYCL_MASK | DAC33_WLEN_MASK);
891 /* Read FIFO control A, and clear FIFO flush bit */
892 fifoctrl_a = dac33_read_reg_cache(codec, DAC33_FIFO_CTRL_A);
893 fifoctrl_a &= ~DAC33_FIFOFLUSH;
895 fifoctrl_a &= ~DAC33_WIDTH;
896 switch (substream->runtime->format) {
897 case SNDRV_PCM_FORMAT_S16_LE:
898 aictrl_a |= (DAC33_NCYCL_16 | DAC33_WLEN_16);
899 fifoctrl_a |= DAC33_WIDTH;
902 dev_err(codec->dev, "unsupported format %d\n",
903 substream->runtime->format);
907 mutex_lock(&dac33->mutex);
909 if (!dac33->chip_power) {
911 * Chip is not powered yet.
912 * Do the init in the dac33_set_bias_level later.
914 mutex_unlock(&dac33->mutex);
918 dac33_soft_power(codec, 0);
919 dac33_soft_power(codec, 1);
921 reg_tmp = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
922 dac33_write(codec, DAC33_INT_OSC_CTRL, reg_tmp);
924 /* Write registers 0x08 and 0x09 (MSB, LSB) */
925 dac33_write16(codec, DAC33_INT_OSC_FREQ_RAT_A, oscset);
927 /* calib time: 128 is a nice number ;) */
928 dac33_write(codec, DAC33_CALIB_TIME, 128);
930 /* adjustment treshold & step */
931 dac33_write(codec, DAC33_INT_OSC_CTRL_B, DAC33_ADJTHRSHLD(2) |
934 /* div=4 / gain=1 / div */
935 dac33_write(codec, DAC33_INT_OSC_CTRL_C, DAC33_REFDIV(4));
937 pwr_ctrl = dac33_read_reg_cache(codec, DAC33_PWR_CTRL);
938 pwr_ctrl |= DAC33_OSCPDNB | DAC33_DACRPDNB | DAC33_DACLPDNB;
939 dac33_write(codec, DAC33_PWR_CTRL, pwr_ctrl);
941 dac33_oscwait(codec);
943 if (dac33->fifo_mode) {
944 /* Generic for all FIFO modes */
945 /* 50-51 : ASRC Control registers */
946 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCLKDIV(1));
947 dac33_write(codec, DAC33_ASRC_CTRL_B, 1); /* ??? */
949 /* Write registers 0x34 and 0x35 (MSB, LSB) */
950 dac33_write16(codec, DAC33_SRC_REF_CLK_RATIO_A, ratioset);
952 /* Set interrupts to high active */
953 dac33_write(codec, DAC33_INTP_CTRL_A, DAC33_INTPM_AHIGH);
955 /* FIFO bypass mode */
956 /* 50-51 : ASRC Control registers */
957 dac33_write(codec, DAC33_ASRC_CTRL_A, DAC33_SRCBYP);
958 dac33_write(codec, DAC33_ASRC_CTRL_B, 0); /* ??? */
961 /* Interrupt behaviour configuration */
962 switch (dac33->fifo_mode) {
963 case DAC33_FIFO_MODE1:
964 dac33_write(codec, DAC33_FIFO_IRQ_MODE_B,
965 DAC33_ATM(DAC33_FIFO_IRQ_MODE_LEVEL));
967 case DAC33_FIFO_MODE7:
968 dac33_write(codec, DAC33_FIFO_IRQ_MODE_A,
969 DAC33_UTM(DAC33_FIFO_IRQ_MODE_LEVEL));
972 /* in FIFO bypass mode, the interrupts are not used */
976 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
978 switch (dac33->fifo_mode) {
979 case DAC33_FIFO_MODE1:
982 * Disable the FIFO bypass (Enable the use of FIFO)
983 * Select nSample mode
984 * BCLK is only running when data is needed by DAC33
986 fifoctrl_a &= ~DAC33_FBYPAS;
987 fifoctrl_a &= ~DAC33_FAUTO;
988 if (dac33->keep_bclk)
989 aictrl_b |= DAC33_BCLKON;
991 aictrl_b &= ~DAC33_BCLKON;
993 case DAC33_FIFO_MODE7:
996 * Disable the FIFO bypass (Enable the use of FIFO)
997 * Select Threshold mode
998 * BCLK is only running when data is needed by DAC33
1000 fifoctrl_a &= ~DAC33_FBYPAS;
1001 fifoctrl_a |= DAC33_FAUTO;
1002 if (dac33->keep_bclk)
1003 aictrl_b |= DAC33_BCLKON;
1005 aictrl_b &= ~DAC33_BCLKON;
1009 * For FIFO bypass mode:
1010 * Enable the FIFO bypass (Disable the FIFO use)
1011 * Set the BCLK as continous
1013 fifoctrl_a |= DAC33_FBYPAS;
1014 aictrl_b |= DAC33_BCLKON;
1018 dac33_write(codec, DAC33_FIFO_CTRL_A, fifoctrl_a);
1019 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1020 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1031 if (dac33->fifo_mode)
1032 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C,
1033 dac33->burst_bclkdiv);
1035 dac33_write(codec, DAC33_SER_AUDIOIF_CTRL_C, 32);
1037 switch (dac33->fifo_mode) {
1038 case DAC33_FIFO_MODE1:
1039 dac33_write16(codec, DAC33_ATHR_MSB,
1040 DAC33_THRREG(dac33->alarm_threshold));
1042 case DAC33_FIFO_MODE7:
1044 * Configure the threshold levels, and leave 10 sample space
1045 * at the bottom, and also at the top of the FIFO
1047 dac33_write16(codec, DAC33_UTHR_MSB, DAC33_THRREG(dac33->uthr));
1048 dac33_write16(codec, DAC33_LTHR_MSB, DAC33_THRREG(MODE7_LTHR));
1054 mutex_unlock(&dac33->mutex);
1059 static void dac33_calculate_times(struct snd_pcm_substream *substream)
1061 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1062 struct snd_soc_codec *codec = rtd->codec;
1063 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1064 unsigned int period_size = substream->runtime->period_size;
1065 unsigned int rate = substream->runtime->rate;
1066 unsigned int nsample_limit;
1068 /* In bypass mode we don't need to calculate */
1069 if (!dac33->fifo_mode)
1072 switch (dac33->fifo_mode) {
1073 case DAC33_FIFO_MODE1:
1074 /* Number of samples under i2c latency */
1075 dac33->alarm_threshold = US_TO_SAMPLES(rate,
1076 dac33->mode1_latency);
1077 if (dac33->auto_fifo_config) {
1078 if (period_size <= dac33->alarm_threshold)
1080 * Configure nSamaple to number of periods,
1081 * which covers the latency requironment.
1083 dac33->nsample = period_size *
1084 ((dac33->alarm_threshold / period_size) +
1085 (dac33->alarm_threshold % period_size ?
1088 dac33->nsample = period_size;
1090 /* nSample time shall not be shorter than i2c latency */
1091 dac33->nsample_min = dac33->alarm_threshold;
1093 * nSample should not be bigger than alsa buffer minus
1094 * size of one period to avoid overruns
1096 dac33->nsample_max = substream->runtime->buffer_size -
1098 nsample_limit = DAC33_BUFFER_SIZE_SAMPLES -
1099 dac33->alarm_threshold;
1100 if (dac33->nsample_max > nsample_limit)
1101 dac33->nsample_max = nsample_limit;
1103 /* Correct the nSample if it is outside of the ranges */
1104 if (dac33->nsample < dac33->nsample_min)
1105 dac33->nsample = dac33->nsample_min;
1106 if (dac33->nsample > dac33->nsample_max)
1107 dac33->nsample = dac33->nsample_max;
1110 dac33->mode1_us_burst = SAMPLES_TO_US(dac33->burst_rate,
1112 dac33->t_stamp1 = 0;
1113 dac33->t_stamp2 = 0;
1115 case DAC33_FIFO_MODE7:
1116 if (dac33->auto_fifo_config) {
1117 dac33->uthr = UTHR_FROM_PERIOD_SIZE(
1120 dac33->burst_rate) + 9;
1121 if (dac33->uthr > MODE7_UTHR)
1122 dac33->uthr = MODE7_UTHR;
1123 if (dac33->uthr < (MODE7_LTHR + 10))
1124 dac33->uthr = (MODE7_LTHR + 10);
1126 dac33->mode7_us_to_lthr =
1127 SAMPLES_TO_US(substream->runtime->rate,
1128 dac33->uthr - MODE7_LTHR + 1);
1129 dac33->t_stamp1 = 0;
1137 static int dac33_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
1138 struct snd_soc_dai *dai)
1140 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1141 struct snd_soc_codec *codec = rtd->codec;
1142 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1146 case SNDRV_PCM_TRIGGER_START:
1147 case SNDRV_PCM_TRIGGER_RESUME:
1148 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1149 if (dac33->fifo_mode) {
1150 dac33->state = DAC33_PREFILL;
1151 queue_work(dac33->dac33_wq, &dac33->work);
1154 case SNDRV_PCM_TRIGGER_STOP:
1155 case SNDRV_PCM_TRIGGER_SUSPEND:
1156 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1157 if (dac33->fifo_mode) {
1158 dac33->state = DAC33_FLUSH;
1159 queue_work(dac33->dac33_wq, &dac33->work);
1169 static snd_pcm_sframes_t dac33_dai_delay(
1170 struct snd_pcm_substream *substream,
1171 struct snd_soc_dai *dai)
1173 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1174 struct snd_soc_codec *codec = rtd->codec;
1175 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1176 unsigned long long t0, t1, t_now;
1177 unsigned int time_delta, uthr;
1178 int samples_out, samples_in, samples;
1179 snd_pcm_sframes_t delay = 0;
1181 switch (dac33->fifo_mode) {
1182 case DAC33_FIFO_BYPASS:
1184 case DAC33_FIFO_MODE1:
1185 spin_lock(&dac33->lock);
1186 t0 = dac33->t_stamp1;
1187 t1 = dac33->t_stamp2;
1188 spin_unlock(&dac33->lock);
1189 t_now = ktime_to_us(ktime_get());
1191 /* We have not started to fill the FIFO yet, delay is 0 */
1198 * After Alarm threshold, and before nSample write
1200 time_delta = t_now - t0;
1201 samples_out = time_delta ? US_TO_SAMPLES(
1202 substream->runtime->rate,
1205 if (likely(dac33->alarm_threshold > samples_out))
1206 delay = dac33->alarm_threshold - samples_out;
1209 } else if ((t_now - t1) <= dac33->mode1_us_burst) {
1212 * After nSample write (during burst operation)
1214 time_delta = t_now - t0;
1215 samples_out = time_delta ? US_TO_SAMPLES(
1216 substream->runtime->rate,
1219 time_delta = t_now - t1;
1220 samples_in = time_delta ? US_TO_SAMPLES(
1224 samples = dac33->alarm_threshold;
1225 samples += (samples_in - samples_out);
1227 if (likely(samples > 0))
1234 * After burst operation, before next alarm threshold
1236 time_delta = t_now - t0;
1237 samples_out = time_delta ? US_TO_SAMPLES(
1238 substream->runtime->rate,
1241 samples_in = dac33->nsample;
1242 samples = dac33->alarm_threshold;
1243 samples += (samples_in - samples_out);
1245 if (likely(samples > 0))
1246 delay = samples > DAC33_BUFFER_SIZE_SAMPLES ?
1247 DAC33_BUFFER_SIZE_SAMPLES : samples;
1252 case DAC33_FIFO_MODE7:
1253 spin_lock(&dac33->lock);
1254 t0 = dac33->t_stamp1;
1256 spin_unlock(&dac33->lock);
1257 t_now = ktime_to_us(ktime_get());
1259 /* We have not started to fill the FIFO yet, delay is 0 */
1265 * Either the timestamps are messed or equal. Report
1272 time_delta = t_now - t0;
1273 if (time_delta <= dac33->mode7_us_to_lthr) {
1276 * After burst (draining phase)
1278 samples_out = US_TO_SAMPLES(
1279 substream->runtime->rate,
1282 if (likely(uthr > samples_out))
1283 delay = uthr - samples_out;
1289 * During burst operation
1291 time_delta = time_delta - dac33->mode7_us_to_lthr;
1293 samples_out = US_TO_SAMPLES(
1294 substream->runtime->rate,
1296 samples_in = US_TO_SAMPLES(
1299 delay = MODE7_LTHR + samples_in - samples_out;
1301 if (unlikely(delay > uthr))
1306 dev_warn(codec->dev, "Unhandled FIFO mode: %d\n",
1314 static int dac33_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1315 int clk_id, unsigned int freq, int dir)
1317 struct snd_soc_codec *codec = codec_dai->codec;
1318 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1319 u8 ioc_reg, asrcb_reg;
1321 ioc_reg = dac33_read_reg_cache(codec, DAC33_INT_OSC_CTRL);
1322 asrcb_reg = dac33_read_reg_cache(codec, DAC33_ASRC_CTRL_B);
1324 case TLV320DAC33_MCLK:
1325 ioc_reg |= DAC33_REFSEL;
1326 asrcb_reg |= DAC33_SRCREFSEL;
1328 case TLV320DAC33_SLEEPCLK:
1329 ioc_reg &= ~DAC33_REFSEL;
1330 asrcb_reg &= ~DAC33_SRCREFSEL;
1333 dev_err(codec->dev, "Invalid clock ID (%d)\n", clk_id);
1336 dac33->refclk = freq;
1338 dac33_write_reg_cache(codec, DAC33_INT_OSC_CTRL, ioc_reg);
1339 dac33_write_reg_cache(codec, DAC33_ASRC_CTRL_B, asrcb_reg);
1344 static int dac33_set_dai_fmt(struct snd_soc_dai *codec_dai,
1347 struct snd_soc_codec *codec = codec_dai->codec;
1348 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1349 u8 aictrl_a, aictrl_b;
1351 aictrl_a = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A);
1352 aictrl_b = dac33_read_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B);
1353 /* set master/slave audio interface */
1354 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1355 case SND_SOC_DAIFMT_CBM_CFM:
1357 aictrl_a |= (DAC33_MSBCLK | DAC33_MSWCLK);
1359 case SND_SOC_DAIFMT_CBS_CFS:
1361 if (dac33->fifo_mode) {
1362 dev_err(codec->dev, "FIFO mode requires master mode\n");
1365 aictrl_a &= ~(DAC33_MSBCLK | DAC33_MSWCLK);
1371 aictrl_a &= ~DAC33_AFMT_MASK;
1372 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1373 case SND_SOC_DAIFMT_I2S:
1374 aictrl_a |= DAC33_AFMT_I2S;
1376 case SND_SOC_DAIFMT_DSP_A:
1377 aictrl_a |= DAC33_AFMT_DSP;
1378 aictrl_b &= ~DAC33_DATA_DELAY_MASK;
1379 aictrl_b |= DAC33_DATA_DELAY(0);
1381 case SND_SOC_DAIFMT_RIGHT_J:
1382 aictrl_a |= DAC33_AFMT_RIGHT_J;
1384 case SND_SOC_DAIFMT_LEFT_J:
1385 aictrl_a |= DAC33_AFMT_LEFT_J;
1388 dev_err(codec->dev, "Unsupported format (%u)\n",
1389 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1393 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_A, aictrl_a);
1394 dac33_write_reg_cache(codec, DAC33_SER_AUDIOIF_CTRL_B, aictrl_b);
1399 static int dac33_soc_probe(struct snd_soc_codec *codec)
1401 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1404 codec->control_data = dac33->control_data;
1405 codec->hw_write = (hw_write_t) i2c_master_send;
1406 codec->idle_bias_off = 1;
1407 dac33->codec = codec;
1409 /* Read the tlv320dac33 ID registers */
1410 ret = dac33_hard_power(codec, 1);
1412 dev_err(codec->dev, "Failed to power up codec: %d\n", ret);
1415 dac33_read_id(codec);
1416 dac33_hard_power(codec, 0);
1418 /* Check if the IRQ number is valid and request it */
1419 if (dac33->irq >= 0) {
1420 ret = request_irq(dac33->irq, dac33_interrupt_handler,
1421 IRQF_TRIGGER_RISING | IRQF_DISABLED,
1422 codec->name, codec);
1424 dev_err(codec->dev, "Could not request IRQ%d (%d)\n",
1428 if (dac33->irq != -1) {
1429 /* Setup work queue */
1431 create_singlethread_workqueue("tlv320dac33");
1432 if (dac33->dac33_wq == NULL) {
1433 free_irq(dac33->irq, codec);
1437 INIT_WORK(&dac33->work, dac33_work);
1441 snd_soc_add_controls(codec, dac33_snd_controls,
1442 ARRAY_SIZE(dac33_snd_controls));
1443 /* Only add the FIFO controls, if we have valid IRQ number */
1444 if (dac33->irq >= 0) {
1445 snd_soc_add_controls(codec, dac33_mode_snd_controls,
1446 ARRAY_SIZE(dac33_mode_snd_controls));
1447 /* FIFO usage controls only, if autoio config is not selected */
1448 if (!dac33->auto_fifo_config)
1449 snd_soc_add_controls(codec, dac33_fifo_snd_controls,
1450 ARRAY_SIZE(dac33_fifo_snd_controls));
1452 dac33_add_widgets(codec);
1458 static int dac33_soc_remove(struct snd_soc_codec *codec)
1460 struct tlv320dac33_priv *dac33 = snd_soc_codec_get_drvdata(codec);
1462 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1464 if (dac33->irq >= 0) {
1465 free_irq(dac33->irq, dac33->codec);
1466 destroy_workqueue(dac33->dac33_wq);
1471 static int dac33_soc_suspend(struct snd_soc_codec *codec, pm_message_t state)
1473 dac33_set_bias_level(codec, SND_SOC_BIAS_OFF);
1478 static int dac33_soc_resume(struct snd_soc_codec *codec)
1480 dac33_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1485 static struct snd_soc_codec_driver soc_codec_dev_tlv320dac33 = {
1486 .read = dac33_read_reg_cache,
1487 .write = dac33_write_locked,
1488 .set_bias_level = dac33_set_bias_level,
1489 .reg_cache_size = ARRAY_SIZE(dac33_reg),
1490 .reg_word_size = sizeof(u8),
1491 .reg_cache_default = dac33_reg,
1492 .probe = dac33_soc_probe,
1493 .remove = dac33_soc_remove,
1494 .suspend = dac33_soc_suspend,
1495 .resume = dac33_soc_resume,
1498 #define DAC33_RATES (SNDRV_PCM_RATE_44100 | \
1499 SNDRV_PCM_RATE_48000)
1500 #define DAC33_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1502 static struct snd_soc_dai_ops dac33_dai_ops = {
1503 .startup = dac33_startup,
1504 .shutdown = dac33_shutdown,
1505 .hw_params = dac33_hw_params,
1506 .trigger = dac33_pcm_trigger,
1507 .delay = dac33_dai_delay,
1508 .set_sysclk = dac33_set_dai_sysclk,
1509 .set_fmt = dac33_set_dai_fmt,
1512 static struct snd_soc_dai_driver dac33_dai = {
1513 .name = "tlv320dac33-hifi",
1515 .stream_name = "Playback",
1518 .rates = DAC33_RATES,
1519 .formats = DAC33_FORMATS,},
1520 .ops = &dac33_dai_ops,
1523 static int __devinit dac33_i2c_probe(struct i2c_client *client,
1524 const struct i2c_device_id *id)
1526 struct tlv320dac33_platform_data *pdata;
1527 struct tlv320dac33_priv *dac33;
1530 if (client->dev.platform_data == NULL) {
1531 dev_err(&client->dev, "Platform data not set\n");
1534 pdata = client->dev.platform_data;
1536 dac33 = kzalloc(sizeof(struct tlv320dac33_priv), GFP_KERNEL);
1540 dac33->control_data = client;
1541 mutex_init(&dac33->mutex);
1542 spin_lock_init(&dac33->lock);
1544 i2c_set_clientdata(client, dac33);
1546 dac33->power_gpio = pdata->power_gpio;
1547 dac33->burst_bclkdiv = pdata->burst_bclkdiv;
1548 /* Pre calculate the burst rate */
1549 dac33->burst_rate = BURST_BASEFREQ_HZ / dac33->burst_bclkdiv / 32;
1550 dac33->keep_bclk = pdata->keep_bclk;
1551 dac33->auto_fifo_config = pdata->auto_fifo_config;
1552 dac33->mode1_latency = pdata->mode1_latency;
1553 if (!dac33->mode1_latency)
1554 dac33->mode1_latency = 10000; /* 10ms */
1555 dac33->irq = client->irq;
1556 dac33->nsample = NSAMPLE_MAX;
1557 dac33->nsample_max = NSAMPLE_MAX;
1558 dac33->uthr = MODE7_UTHR;
1559 /* Disable FIFO use by default */
1560 dac33->fifo_mode = DAC33_FIFO_BYPASS;
1562 /* Check if the reset GPIO number is valid and request it */
1563 if (dac33->power_gpio >= 0) {
1564 ret = gpio_request(dac33->power_gpio, "tlv320dac33 reset");
1566 dev_err(&client->dev,
1567 "Failed to request reset GPIO (%d)\n",
1571 gpio_direction_output(dac33->power_gpio, 0);
1574 for (i = 0; i < ARRAY_SIZE(dac33->supplies); i++)
1575 dac33->supplies[i].supply = dac33_supply_names[i];
1577 ret = regulator_bulk_get(&client->dev, ARRAY_SIZE(dac33->supplies),
1581 dev_err(&client->dev, "Failed to request supplies: %d\n", ret);
1585 ret = snd_soc_register_codec(&client->dev,
1586 &soc_codec_dev_tlv320dac33, &dac33_dai, 1);
1592 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1594 if (dac33->power_gpio >= 0)
1595 gpio_free(dac33->power_gpio);
1601 static int __devexit dac33_i2c_remove(struct i2c_client *client)
1603 struct tlv320dac33_priv *dac33 = i2c_get_clientdata(client);
1605 if (unlikely(dac33->chip_power))
1606 dac33_hard_power(dac33->codec, 0);
1608 if (dac33->power_gpio >= 0)
1609 gpio_free(dac33->power_gpio);
1611 regulator_bulk_free(ARRAY_SIZE(dac33->supplies), dac33->supplies);
1613 snd_soc_unregister_codec(&client->dev);
1619 static const struct i2c_device_id tlv320dac33_i2c_id[] = {
1621 .name = "tlv320dac33",
1627 static struct i2c_driver tlv320dac33_i2c_driver = {
1629 .name = "tlv320dac33-codec",
1630 .owner = THIS_MODULE,
1632 .probe = dac33_i2c_probe,
1633 .remove = __devexit_p(dac33_i2c_remove),
1634 .id_table = tlv320dac33_i2c_id,
1637 static int __init dac33_module_init(void)
1640 r = i2c_add_driver(&tlv320dac33_i2c_driver);
1642 printk(KERN_ERR "DAC33: driver registration failed\n");
1647 module_init(dac33_module_init);
1649 static void __exit dac33_module_exit(void)
1651 i2c_del_driver(&tlv320dac33_i2c_driver);
1653 module_exit(dac33_module_exit);
1656 MODULE_DESCRIPTION("ASoC TLV320DAC33 codec driver");
1657 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@nokia.com>");
1658 MODULE_LICENSE("GPL");