2 * wm8900.c -- WM8900 ALSA Soc Audio driver
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 * - FLL source configuration, currently only MCLK is supported.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/delay.h>
25 #include <linux/i2c.h>
26 #include <linux/regmap.h>
27 #include <linux/spi/spi.h>
28 #include <linux/slab.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/pcm_params.h>
32 #include <sound/soc.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
38 /* WM8900 register space */
39 #define WM8900_REG_RESET 0x0
40 #define WM8900_REG_ID 0x0
41 #define WM8900_REG_POWER1 0x1
42 #define WM8900_REG_POWER2 0x2
43 #define WM8900_REG_POWER3 0x3
44 #define WM8900_REG_AUDIO1 0x4
45 #define WM8900_REG_AUDIO2 0x5
46 #define WM8900_REG_CLOCKING1 0x6
47 #define WM8900_REG_CLOCKING2 0x7
48 #define WM8900_REG_AUDIO3 0x8
49 #define WM8900_REG_AUDIO4 0x9
50 #define WM8900_REG_DACCTRL 0xa
51 #define WM8900_REG_LDAC_DV 0xb
52 #define WM8900_REG_RDAC_DV 0xc
53 #define WM8900_REG_SIDETONE 0xd
54 #define WM8900_REG_ADCCTRL 0xe
55 #define WM8900_REG_LADC_DV 0xf
56 #define WM8900_REG_RADC_DV 0x10
57 #define WM8900_REG_GPIO 0x12
58 #define WM8900_REG_INCTL 0x15
59 #define WM8900_REG_LINVOL 0x16
60 #define WM8900_REG_RINVOL 0x17
61 #define WM8900_REG_INBOOSTMIX1 0x18
62 #define WM8900_REG_INBOOSTMIX2 0x19
63 #define WM8900_REG_ADCPATH 0x1a
64 #define WM8900_REG_AUXBOOST 0x1b
65 #define WM8900_REG_ADDCTL 0x1e
66 #define WM8900_REG_FLLCTL1 0x24
67 #define WM8900_REG_FLLCTL2 0x25
68 #define WM8900_REG_FLLCTL3 0x26
69 #define WM8900_REG_FLLCTL4 0x27
70 #define WM8900_REG_FLLCTL5 0x28
71 #define WM8900_REG_FLLCTL6 0x29
72 #define WM8900_REG_LOUTMIXCTL1 0x2c
73 #define WM8900_REG_ROUTMIXCTL1 0x2d
74 #define WM8900_REG_BYPASS1 0x2e
75 #define WM8900_REG_BYPASS2 0x2f
76 #define WM8900_REG_AUXOUT_CTL 0x30
77 #define WM8900_REG_LOUT1CTL 0x33
78 #define WM8900_REG_ROUT1CTL 0x34
79 #define WM8900_REG_LOUT2CTL 0x35
80 #define WM8900_REG_ROUT2CTL 0x36
81 #define WM8900_REG_HPCTL1 0x3a
82 #define WM8900_REG_OUTBIASCTL 0x73
84 #define WM8900_MAXREG 0x80
86 #define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87 #define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88 #define WM8900_REG_ADDCTL_VMID_DIS 0x20
89 #define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90 #define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91 #define WM8900_REG_ADDCTL_TEMP_SD 0x02
93 #define WM8900_REG_GPIO_TEMP_ENA 0x2
95 #define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96 #define WM8900_REG_POWER1_BIAS_ENA 0x0008
97 #define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98 #define WM8900_REG_POWER1_FLL_ENA 0x0040
100 #define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101 #define WM8900_REG_POWER2_ADCL_ENA 0x0002
102 #define WM8900_REG_POWER2_ADCR_ENA 0x0001
104 #define WM8900_REG_POWER3_DACL_ENA 0x0002
105 #define WM8900_REG_POWER3_DACR_ENA 0x0001
107 #define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108 #define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109 #define WM8900_REG_AUDIO1_BCLK_INV 0x0100
111 #define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112 #define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113 #define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
114 #define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
116 #define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117 #define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
119 #define WM8900_REG_DACCTRL_MUTE 0x004
120 #define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
121 #define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
123 #define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
125 #define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
127 #define WM8900_REG_FLLCTL1_OSC_ENA 0x100
129 #define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
131 #define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132 #define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133 #define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
134 #define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
135 #define WM8900_REG_HPCTL1_HP_SHORT 0x08
136 #define WM8900_REG_HPCTL1_HP_SHORT2 0x04
138 #define WM8900_LRC_MASK 0x03ff
141 struct regmap *regmap;
143 u32 fll_in; /* FLL input frequency */
144 u32 fll_out; /* FLL output frequency */
148 * wm8900 register cache. We can't read the entire register space and we
149 * have slow control buses so we cache the registers.
151 static const struct reg_default wm8900_reg_defaults[] = {
209 static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
219 static void wm8900_reset(struct snd_soc_codec *codec)
221 snd_soc_write(codec, WM8900_REG_RESET, 0);
224 static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
225 struct snd_kcontrol *kcontrol, int event)
227 struct snd_soc_codec *codec = w->codec;
228 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
231 case SND_SOC_DAPM_PRE_PMU:
232 /* Clamp headphone outputs */
233 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
234 WM8900_REG_HPCTL1_HP_CLAMP_OP;
235 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
238 case SND_SOC_DAPM_POST_PMU:
239 /* Enable the input stage */
240 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
241 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
242 WM8900_REG_HPCTL1_HP_SHORT2 |
243 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
248 /* Enable the output stage */
249 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
250 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
251 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
253 /* Remove the shorts */
254 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
255 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
256 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
257 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
260 case SND_SOC_DAPM_PRE_PMD:
261 /* Short the output */
262 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
263 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
265 /* Disable the output stage */
266 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
267 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
269 /* Clamp the outputs and power down input */
270 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
271 WM8900_REG_HPCTL1_HP_CLAMP_OP;
272 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
273 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
276 case SND_SOC_DAPM_POST_PMD:
277 /* Disable everything */
278 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
288 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
290 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
292 static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
296 static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
298 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
300 static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
302 static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
304 static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
306 static const struct soc_enum mic_bias_level =
307 SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
309 static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
311 static const struct soc_enum dac_mute_rate =
312 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
314 static const char *dac_deemphasis_txt[] = {
315 "Disabled", "32kHz", "44.1kHz", "48kHz"
318 static const struct soc_enum dac_deemphasis =
319 SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
321 static const char *adc_hpf_cut_txt[] = {
322 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
325 static const struct soc_enum adc_hpf_cut =
326 SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
328 static const char *lr_txt[] = {
332 static const struct soc_enum aifl_src =
333 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
335 static const struct soc_enum aifr_src =
336 SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
338 static const struct soc_enum dacl_src =
339 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
341 static const struct soc_enum dacr_src =
342 SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
344 static const char *sidetone_txt[] = {
345 "Disabled", "Left ADC", "Right ADC"
348 static const struct soc_enum dacl_sidetone =
349 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
351 static const struct soc_enum dacr_sidetone =
352 SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
354 static const struct snd_kcontrol_new wm8900_snd_controls[] = {
355 SOC_ENUM("Mic Bias Level", mic_bias_level),
357 SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
359 SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
360 SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
362 SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
364 SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
365 SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
367 SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
368 SOC_ENUM("DAC Mute Rate", dac_mute_rate),
369 SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
370 SOC_ENUM("DAC Deemphasis", dac_deemphasis),
371 SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
374 SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
375 SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
376 SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
377 SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
379 SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
381 SOC_ENUM("Left Digital Audio Source", aifl_src),
382 SOC_ENUM("Right Digital Audio Source", aifr_src),
384 SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
386 SOC_ENUM("Left DAC Source", dacl_src),
387 SOC_ENUM("Right DAC Source", dacr_src),
388 SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
389 SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
390 SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
392 SOC_DOUBLE_R_TLV("Digital Playback Volume",
393 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
395 SOC_DOUBLE_R_TLV("Digital Capture Volume",
396 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
398 SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
400 SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
402 SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
404 SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
407 SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
409 SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
411 SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
413 SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
416 SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
418 SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
420 SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
422 SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
424 SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
426 SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
429 SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
430 0, 63, 0, out_pga_tlv),
431 SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
433 SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
436 SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
437 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
438 0, 63, 0, out_pga_tlv),
439 SOC_DOUBLE_R("LINEOUT2 Switch",
440 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
441 SOC_DOUBLE_R("LINEOUT2 ZC Switch",
442 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
443 SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
448 static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
449 SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
451 static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
452 SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
454 static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
455 SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
456 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
457 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
458 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
459 SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
462 static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
463 SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
464 SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
465 SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
466 SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
467 SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
470 static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
471 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
472 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
473 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
474 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
477 static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
478 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
479 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
480 SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
481 SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
484 static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
485 SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
486 SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
487 SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
490 static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
491 SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
492 SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
493 SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
496 static const char *wm8900_lp_mux[] = { "Disabled", "Enabled" };
498 static const struct soc_enum wm8900_lineout2_lp_mux =
499 SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm8900_lp_mux);
501 static const struct snd_kcontrol_new wm8900_lineout2_lp =
502 SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
504 static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
506 /* Externally visible pins */
507 SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
508 SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
509 SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
510 SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
511 SND_SOC_DAPM_OUTPUT("HP_L"),
512 SND_SOC_DAPM_OUTPUT("HP_R"),
514 SND_SOC_DAPM_INPUT("RINPUT1"),
515 SND_SOC_DAPM_INPUT("LINPUT1"),
516 SND_SOC_DAPM_INPUT("RINPUT2"),
517 SND_SOC_DAPM_INPUT("LINPUT2"),
518 SND_SOC_DAPM_INPUT("RINPUT3"),
519 SND_SOC_DAPM_INPUT("LINPUT3"),
520 SND_SOC_DAPM_INPUT("AUX"),
522 SND_SOC_DAPM_VMID("VMID"),
525 SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
526 wm8900_linpga_controls,
527 ARRAY_SIZE(wm8900_linpga_controls)),
528 SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
529 wm8900_rinpga_controls,
530 ARRAY_SIZE(wm8900_rinpga_controls)),
532 SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
533 wm8900_linmix_controls,
534 ARRAY_SIZE(wm8900_linmix_controls)),
535 SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
536 wm8900_rinmix_controls,
537 ARRAY_SIZE(wm8900_rinmix_controls)),
539 SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
541 SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
542 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
545 SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
546 SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
548 SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
550 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
551 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
553 SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
554 SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
556 SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
557 SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
558 SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
560 SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
561 wm8900_loutmix_controls,
562 ARRAY_SIZE(wm8900_loutmix_controls)),
563 SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
564 wm8900_routmix_controls,
565 ARRAY_SIZE(wm8900_routmix_controls)),
568 /* Target, Path, Source */
569 static const struct snd_soc_dapm_route wm8900_dapm_routes[] = {
571 {"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
572 {"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
573 {"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
575 {"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
576 {"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
577 {"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
579 {"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
580 {"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
581 {"Left Input Mixer", "AUX Switch", "AUX"},
582 {"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
584 {"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
585 {"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
586 {"Right Input Mixer", "AUX Switch", "AUX"},
587 {"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
589 {"ADCL", NULL, "Left Input Mixer"},
590 {"ADCR", NULL, "Right Input Mixer"},
593 {"LINEOUT1L", NULL, "LINEOUT1L PGA"},
594 {"LINEOUT1L PGA", NULL, "Left Output Mixer"},
595 {"LINEOUT1R", NULL, "LINEOUT1R PGA"},
596 {"LINEOUT1R PGA", NULL, "Right Output Mixer"},
598 {"LINEOUT2L PGA", NULL, "Left Output Mixer"},
599 {"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
600 {"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
601 {"LINEOUT2L", NULL, "LINEOUT2 LP"},
603 {"LINEOUT2R PGA", NULL, "Right Output Mixer"},
604 {"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
605 {"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
606 {"LINEOUT2R", NULL, "LINEOUT2 LP"},
608 {"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
609 {"Left Output Mixer", "AUX Bypass Switch", "AUX"},
610 {"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
611 {"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
612 {"Left Output Mixer", "DACL Switch", "DACL"},
614 {"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
615 {"Right Output Mixer", "AUX Bypass Switch", "AUX"},
616 {"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
617 {"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
618 {"Right Output Mixer", "DACR Switch", "DACR"},
620 /* Note that the headphone output stage needs to be connected
621 * externally to LINEOUT2 via DC blocking capacitors. Other
622 * configurations are not supported.
624 * Note also that left and right headphone paths are treated as a
627 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
628 {"Headphone Amplifier", NULL, "LINEOUT2 LP"},
629 {"HP_L", NULL, "Headphone Amplifier"},
630 {"HP_R", NULL, "Headphone Amplifier"},
633 static int wm8900_hw_params(struct snd_pcm_substream *substream,
634 struct snd_pcm_hw_params *params,
635 struct snd_soc_dai *dai)
637 struct snd_soc_codec *codec = dai->codec;
640 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
642 switch (params_format(params)) {
643 case SNDRV_PCM_FORMAT_S16_LE:
645 case SNDRV_PCM_FORMAT_S20_3LE:
648 case SNDRV_PCM_FORMAT_S24_LE:
651 case SNDRV_PCM_FORMAT_S32_LE:
658 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
660 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
661 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
663 if (params_rate(params) <= 24000)
664 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
666 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
668 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
678 u16 fll_slow_lock_ref;
683 /* The size in bits of the FLL divide multiplied by 10
684 * to allow rounding later */
685 #define FIXED_FLL_SIZE ((1 << 16) * 10)
687 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
691 unsigned int K, Ndiv, Nmod, target;
697 /* The FLL must run at 90-100MHz which is then scaled down to
698 * the output value by FLLCLK_DIV. */
701 while (target < 90000000) {
706 if (target > 100000000)
707 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
708 " Fout=%u\n", target, Fref, Fout);
710 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
711 "Fref=%u, Fout=%u, target=%u\n",
712 div, Fref, Fout, target);
716 fll_div->fllclk_div = div >> 2;
719 fll_div->fll_slow_lock_ref = 1;
721 fll_div->fll_slow_lock_ref = 0;
723 Ndiv = target / Fref;
726 fll_div->fll_ratio = 8;
728 fll_div->fll_ratio = 1;
730 fll_div->n = Ndiv / fll_div->fll_ratio;
731 Nmod = (target / fll_div->fll_ratio) % Fref;
733 /* Calculate fractional part - scale up so we can round. */
734 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
738 K = Kpart & 0xFFFFFFFF;
743 /* Move down to proper range now rounding is done */
746 if (WARN_ON(target != Fout * (fll_div->fllclk_div << 2)) ||
747 WARN_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n))
753 static int wm8900_set_fll(struct snd_soc_codec *codec,
754 int fll_id, unsigned int freq_in, unsigned int freq_out)
756 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
757 struct _fll_div fll_div;
759 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
762 /* The digital side should be disabled during any change. */
763 snd_soc_update_bits(codec, WM8900_REG_POWER1,
764 WM8900_REG_POWER1_FLL_ENA, 0);
766 /* Disable the FLL? */
767 if (!freq_in || !freq_out) {
768 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
769 WM8900_REG_CLOCKING1_MCLK_SRC, 0);
770 snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
771 WM8900_REG_FLLCTL1_OSC_ENA, 0);
772 wm8900->fll_in = freq_in;
773 wm8900->fll_out = freq_out;
778 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
781 wm8900->fll_in = freq_in;
782 wm8900->fll_out = freq_out;
784 /* The osclilator *MUST* be enabled before we enable the
785 * digital circuit. */
786 snd_soc_write(codec, WM8900_REG_FLLCTL1,
787 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
789 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
790 snd_soc_write(codec, WM8900_REG_FLLCTL5,
791 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
794 snd_soc_write(codec, WM8900_REG_FLLCTL2,
795 (fll_div.k >> 8) | 0x100);
796 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
798 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
800 if (fll_div.fll_slow_lock_ref)
801 snd_soc_write(codec, WM8900_REG_FLLCTL6,
802 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
804 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
806 snd_soc_update_bits(codec, WM8900_REG_POWER1,
807 WM8900_REG_POWER1_FLL_ENA,
808 WM8900_REG_POWER1_FLL_ENA);
811 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
812 WM8900_REG_CLOCKING1_MCLK_SRC,
813 WM8900_REG_CLOCKING1_MCLK_SRC);
817 static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
818 int source, unsigned int freq_in, unsigned int freq_out)
820 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
823 static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
826 struct snd_soc_codec *codec = codec_dai->codec;
829 case WM8900_BCLK_DIV:
830 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
831 WM8900_REG_CLOCKING1_BCLK_MASK, div);
833 case WM8900_OPCLK_DIV:
834 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
835 WM8900_REG_CLOCKING1_OPCLK_MASK, div);
837 case WM8900_DAC_LRCLK:
838 snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
839 WM8900_LRC_MASK, div);
841 case WM8900_ADC_LRCLK:
842 snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
843 WM8900_LRC_MASK, div);
845 case WM8900_DAC_CLKDIV:
846 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
847 WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
849 case WM8900_ADC_CLKDIV:
850 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
851 WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
853 case WM8900_LRCLK_MODE:
854 snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
855 WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
865 static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
868 struct snd_soc_codec *codec = codec_dai->codec;
869 unsigned int clocking1, aif1, aif3, aif4;
871 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
872 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
873 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
874 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
876 /* set master/slave audio interface */
877 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
878 case SND_SOC_DAIFMT_CBS_CFS:
879 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
880 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
881 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
883 case SND_SOC_DAIFMT_CBS_CFM:
884 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
885 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
886 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
888 case SND_SOC_DAIFMT_CBM_CFM:
889 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
890 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
891 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
893 case SND_SOC_DAIFMT_CBM_CFS:
894 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
895 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
896 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
902 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
903 case SND_SOC_DAIFMT_DSP_A:
904 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
905 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
907 case SND_SOC_DAIFMT_DSP_B:
908 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
909 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
911 case SND_SOC_DAIFMT_I2S:
912 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
915 case SND_SOC_DAIFMT_RIGHT_J:
916 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
918 case SND_SOC_DAIFMT_LEFT_J:
919 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
926 /* Clock inversion */
927 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
928 case SND_SOC_DAIFMT_DSP_A:
929 case SND_SOC_DAIFMT_DSP_B:
930 /* frame inversion not valid for DSP modes */
931 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
932 case SND_SOC_DAIFMT_NB_NF:
933 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
935 case SND_SOC_DAIFMT_IB_NF:
936 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
942 case SND_SOC_DAIFMT_I2S:
943 case SND_SOC_DAIFMT_RIGHT_J:
944 case SND_SOC_DAIFMT_LEFT_J:
945 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
946 case SND_SOC_DAIFMT_NB_NF:
947 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
948 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
950 case SND_SOC_DAIFMT_IB_IF:
951 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
952 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
954 case SND_SOC_DAIFMT_IB_NF:
955 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
956 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
958 case SND_SOC_DAIFMT_NB_IF:
959 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
960 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
970 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
971 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
972 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
973 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
978 static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
980 struct snd_soc_codec *codec = codec_dai->codec;
983 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
986 reg |= WM8900_REG_DACCTRL_MUTE;
988 reg &= ~WM8900_REG_DACCTRL_MUTE;
990 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
995 #define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
996 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
997 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
999 #define WM8900_PCM_FORMATS \
1000 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1001 SNDRV_PCM_FORMAT_S24_LE)
1003 static const struct snd_soc_dai_ops wm8900_dai_ops = {
1004 .hw_params = wm8900_hw_params,
1005 .set_clkdiv = wm8900_set_dai_clkdiv,
1006 .set_pll = wm8900_set_dai_pll,
1007 .set_fmt = wm8900_set_dai_fmt,
1008 .digital_mute = wm8900_digital_mute,
1011 static struct snd_soc_dai_driver wm8900_dai = {
1012 .name = "wm8900-hifi",
1014 .stream_name = "HiFi Playback",
1017 .rates = WM8900_RATES,
1018 .formats = WM8900_PCM_FORMATS,
1021 .stream_name = "HiFi Capture",
1024 .rates = WM8900_RATES,
1025 .formats = WM8900_PCM_FORMATS,
1027 .ops = &wm8900_dai_ops,
1030 static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1031 enum snd_soc_bias_level level)
1036 case SND_SOC_BIAS_ON:
1037 /* Enable thermal shutdown */
1038 snd_soc_update_bits(codec, WM8900_REG_GPIO,
1039 WM8900_REG_GPIO_TEMP_ENA,
1040 WM8900_REG_GPIO_TEMP_ENA);
1041 snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
1042 WM8900_REG_ADDCTL_TEMP_SD,
1043 WM8900_REG_ADDCTL_TEMP_SD);
1046 case SND_SOC_BIAS_PREPARE:
1049 case SND_SOC_BIAS_STANDBY:
1050 /* Charge capacitors if initial power up */
1051 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1052 /* STARTUP_BIAS_ENA on */
1053 snd_soc_write(codec, WM8900_REG_POWER1,
1054 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1056 /* Startup bias mode */
1057 snd_soc_write(codec, WM8900_REG_ADDCTL,
1058 WM8900_REG_ADDCTL_BIAS_SRC |
1059 WM8900_REG_ADDCTL_VMID_SOFTST);
1062 snd_soc_write(codec, WM8900_REG_POWER1,
1063 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1065 /* Allow capacitors to charge */
1066 schedule_timeout_interruptible(msecs_to_jiffies(400));
1069 snd_soc_write(codec, WM8900_REG_POWER1,
1070 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1071 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1073 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1075 snd_soc_write(codec, WM8900_REG_POWER1,
1076 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1079 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1080 snd_soc_write(codec, WM8900_REG_POWER1,
1081 (reg & WM8900_REG_POWER1_FLL_ENA) |
1082 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1083 snd_soc_write(codec, WM8900_REG_POWER2,
1084 WM8900_REG_POWER2_SYSCLK_ENA);
1085 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1088 case SND_SOC_BIAS_OFF:
1089 /* Startup bias enable */
1090 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1091 snd_soc_write(codec, WM8900_REG_POWER1,
1092 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1093 snd_soc_write(codec, WM8900_REG_ADDCTL,
1094 WM8900_REG_ADDCTL_BIAS_SRC |
1095 WM8900_REG_ADDCTL_VMID_SOFTST);
1097 /* Discharge caps */
1098 snd_soc_write(codec, WM8900_REG_POWER1,
1099 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1100 schedule_timeout_interruptible(msecs_to_jiffies(500));
1103 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
1106 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1107 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1108 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1109 snd_soc_write(codec, WM8900_REG_POWER3, 0);
1111 /* Need to let things settle before stopping the clock
1112 * to ensure that restart works, see "Stopping the
1113 * master clock" in the datasheet. */
1114 schedule_timeout_interruptible(msecs_to_jiffies(1));
1115 snd_soc_write(codec, WM8900_REG_POWER2,
1116 WM8900_REG_POWER2_SYSCLK_ENA);
1119 codec->dapm.bias_level = level;
1123 static int wm8900_suspend(struct snd_soc_codec *codec)
1125 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1126 int fll_out = wm8900->fll_out;
1127 int fll_in = wm8900->fll_in;
1130 /* Stop the FLL in an orderly fashion */
1131 ret = wm8900_set_fll(codec, 0, 0, 0);
1133 dev_err(codec->dev, "Failed to stop FLL\n");
1137 wm8900->fll_out = fll_out;
1138 wm8900->fll_in = fll_in;
1140 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1145 static int wm8900_resume(struct snd_soc_codec *codec)
1147 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1150 wm8900_reset(codec);
1152 ret = regcache_sync(wm8900->regmap);
1154 dev_err(codec->dev, "Failed to restore cache: %d\n", ret);
1158 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1160 /* Restart the FLL? */
1161 if (wm8900->fll_out) {
1162 int fll_out = wm8900->fll_out;
1163 int fll_in = wm8900->fll_in;
1166 wm8900->fll_out = 0;
1168 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1170 dev_err(codec->dev, "Failed to restart FLL\n");
1178 static int wm8900_probe(struct snd_soc_codec *codec)
1182 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1184 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1188 reg = snd_soc_read(codec, WM8900_REG_ID);
1189 if (reg != 0x8900) {
1190 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1194 wm8900_reset(codec);
1196 /* Turn the chip on */
1197 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1199 /* Latch the volume update bits */
1200 snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
1201 snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
1202 snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1203 snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1204 snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1205 snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1206 snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
1207 snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
1208 snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
1209 snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
1211 /* Set the DAC and mixer output bias */
1212 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1217 /* power down chip */
1218 static int wm8900_remove(struct snd_soc_codec *codec)
1220 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1224 static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1225 .probe = wm8900_probe,
1226 .remove = wm8900_remove,
1227 .suspend = wm8900_suspend,
1228 .resume = wm8900_resume,
1229 .set_bias_level = wm8900_set_bias_level,
1231 .controls = wm8900_snd_controls,
1232 .num_controls = ARRAY_SIZE(wm8900_snd_controls),
1233 .dapm_widgets = wm8900_dapm_widgets,
1234 .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
1235 .dapm_routes = wm8900_dapm_routes,
1236 .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
1239 static const struct regmap_config wm8900_regmap = {
1242 .max_register = WM8900_MAXREG,
1244 .reg_defaults = wm8900_reg_defaults,
1245 .num_reg_defaults = ARRAY_SIZE(wm8900_reg_defaults),
1246 .cache_type = REGCACHE_RBTREE,
1248 .volatile_reg = wm8900_volatile_register,
1251 #if defined(CONFIG_SPI_MASTER)
1252 static int wm8900_spi_probe(struct spi_device *spi)
1254 struct wm8900_priv *wm8900;
1257 wm8900 = devm_kzalloc(&spi->dev, sizeof(struct wm8900_priv),
1262 wm8900->regmap = devm_regmap_init_spi(spi, &wm8900_regmap);
1263 if (IS_ERR(wm8900->regmap))
1264 return PTR_ERR(wm8900->regmap);
1266 spi_set_drvdata(spi, wm8900);
1268 ret = snd_soc_register_codec(&spi->dev,
1269 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1274 static int wm8900_spi_remove(struct spi_device *spi)
1276 snd_soc_unregister_codec(&spi->dev);
1280 static struct spi_driver wm8900_spi_driver = {
1283 .owner = THIS_MODULE,
1285 .probe = wm8900_spi_probe,
1286 .remove = wm8900_spi_remove,
1288 #endif /* CONFIG_SPI_MASTER */
1290 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1291 static int wm8900_i2c_probe(struct i2c_client *i2c,
1292 const struct i2c_device_id *id)
1294 struct wm8900_priv *wm8900;
1297 wm8900 = devm_kzalloc(&i2c->dev, sizeof(struct wm8900_priv),
1302 wm8900->regmap = devm_regmap_init_i2c(i2c, &wm8900_regmap);
1303 if (IS_ERR(wm8900->regmap))
1304 return PTR_ERR(wm8900->regmap);
1306 i2c_set_clientdata(i2c, wm8900);
1308 ret = snd_soc_register_codec(&i2c->dev,
1309 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1314 static int wm8900_i2c_remove(struct i2c_client *client)
1316 snd_soc_unregister_codec(&client->dev);
1320 static const struct i2c_device_id wm8900_i2c_id[] = {
1324 MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
1326 static struct i2c_driver wm8900_i2c_driver = {
1329 .owner = THIS_MODULE,
1331 .probe = wm8900_i2c_probe,
1332 .remove = wm8900_i2c_remove,
1333 .id_table = wm8900_i2c_id,
1337 static int __init wm8900_modinit(void)
1340 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1341 ret = i2c_add_driver(&wm8900_i2c_driver);
1343 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1347 #if defined(CONFIG_SPI_MASTER)
1348 ret = spi_register_driver(&wm8900_spi_driver);
1350 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1356 module_init(wm8900_modinit);
1358 static void __exit wm8900_exit(void)
1360 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1361 i2c_del_driver(&wm8900_i2c_driver);
1363 #if defined(CONFIG_SPI_MASTER)
1364 spi_unregister_driver(&wm8900_spi_driver);
1367 module_exit(wm8900_exit);
1369 MODULE_DESCRIPTION("ASoC WM8900 driver");
1370 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1371 MODULE_LICENSE("GPL");