2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * The SSI has a limitation in that the samples must be in the same byte
71 * order as the host CPU. This is because when multiple bytes are written
72 * to the STX register, the bytes and bits must be written in the same
73 * order. The STX is a shift register, so all the bits need to be aligned
74 * (bit-endianness must match byte-endianness). Processors typically write
75 * the bits within a byte in the same order that the bytes of a word are
76 * written in. So if the host CPU is big-endian, then only big-endian
77 * samples will be written to STX properly.
80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
103 struct fsl_ssi_reg_val {
110 struct fsl_ssi_rxtx_reg_val {
111 struct fsl_ssi_reg_val rx;
112 struct fsl_ssi_reg_val tx;
115 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
118 case CCSR_SSI_SACCEN:
119 case CCSR_SSI_SACCDIS:
126 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
136 case CCSR_SSI_SACADD:
137 case CCSR_SSI_SACDAT:
139 case CCSR_SSI_SACCST:
146 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
152 case CCSR_SSI_SACADD:
153 case CCSR_SSI_SACDAT:
161 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
166 case CCSR_SSI_SACCST:
173 static const struct regmap_config fsl_ssi_regconfig = {
174 .max_register = CCSR_SSI_SACCDIS,
178 .val_format_endian = REGMAP_ENDIAN_NATIVE,
179 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
180 .readable_reg = fsl_ssi_readable_reg,
181 .volatile_reg = fsl_ssi_volatile_reg,
182 .precious_reg = fsl_ssi_precious_reg,
183 .writeable_reg = fsl_ssi_writeable_reg,
184 .cache_type = REGCACHE_RBTREE,
187 struct fsl_ssi_soc_data {
189 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
195 * fsl_ssi_private: per-SSI private data
197 * @reg: Pointer to the regmap registers
198 * @irq: IRQ of this SSI
199 * @cpu_dai_drv: CPU DAI driver for this device
201 * @dai_fmt: DAI configuration this device is currently used with
202 * @i2s_mode: i2s and network mode configuration of the device. Is used to
203 * switch between normal and i2s/network mode
204 * mode depending on the number of channels
205 * @use_dma: DMA is used or FIQ with stream filter
206 * @use_dual_fifo: DMA with support for both FIFOs used
207 * @fifo_deph: Depth of the SSI FIFOs
208 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
211 * @baudclk: SSI baud clock for master mode
212 * @baudclk_streams: Active streams that are using baudclk
213 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
215 * @dma_params_tx: DMA transmit parameters
216 * @dma_params_rx: DMA receive parameters
217 * @ssi_phys: physical address of the SSI registers
219 * @fiq_params: FIQ stream filtering parameters
221 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
223 * @dbg_stats: Debugging statistics
225 * @soc: SoC specific data
227 struct fsl_ssi_private {
230 struct snd_soc_dai_driver cpu_dai_drv;
232 unsigned int dai_fmt;
236 bool has_ipg_clk_name;
237 unsigned int fifo_depth;
238 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
242 unsigned int baudclk_streams;
243 unsigned int bitclk_freq;
245 /* regcache for volatile regs */
250 struct snd_dmaengine_dai_dma_data dma_params_tx;
251 struct snd_dmaengine_dai_dma_data dma_params_rx;
254 /* params for non-dma FIQ stream filtered mode */
255 struct imx_pcm_fiq_params fiq_params;
257 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
258 * should be replaced with simple-sound-card. */
259 struct platform_device *pdev;
261 struct fsl_ssi_dbg dbg_stats;
263 const struct fsl_ssi_soc_data *soc;
268 * imx51 and later SoCs have a slightly different IP that allows the
269 * SSI configuration while the SSI unit is running.
271 * More important, it is necessary on those SoCs to configure the
272 * sperate TX/RX DMA bits just before starting the stream
273 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
274 * sends any DMA requests to the SDMA unit, otherwise it is not defined
275 * how the SDMA unit handles the DMA request.
277 * SDMA units are present on devices starting at imx35 but the imx35
278 * reference manual states that the DMA bits should not be changed
279 * while the SSI unit is running (SSIEN). So we support the necessary
280 * online configuration of fsl-ssi starting at imx51.
283 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
285 .offline_config = true,
286 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
287 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
288 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
291 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
294 .offline_config = true,
295 .sisr_write_mask = 0,
298 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
300 .offline_config = true,
301 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
302 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
303 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
306 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
308 .offline_config = false,
309 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
310 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
313 static const struct of_device_id fsl_ssi_ids[] = {
314 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
315 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
316 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
317 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
320 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
322 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
324 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
328 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
330 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
331 SND_SOC_DAIFMT_CBS_CFS;
334 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
336 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
337 SND_SOC_DAIFMT_CBM_CFS;
340 * fsl_ssi_isr: SSI interrupt handler
342 * Although it's possible to use the interrupt handler to send and receive
343 * data to/from the SSI, we use the DMA instead. Programming is more
344 * complicated, but the performance is much better.
346 * This interrupt handler is used only to gather statistics.
348 * @irq: IRQ of the SSI device
349 * @dev_id: pointer to the ssi_private structure for this SSI device
351 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
353 struct fsl_ssi_private *ssi_private = dev_id;
354 struct regmap *regs = ssi_private->regs;
358 /* We got an interrupt, so read the status register to see what we
359 were interrupted for. We mask it with the Interrupt Enable register
360 so that we only check for events that we're interested in.
362 regmap_read(regs, CCSR_SSI_SISR, &sisr);
364 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
365 /* Clear the bits that we set */
367 regmap_write(regs, CCSR_SSI_SISR, sisr2);
369 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
375 * Enable/Disable all rx/tx config flags at once.
377 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
380 struct regmap *regs = ssi_private->regs;
381 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
384 regmap_update_bits(regs, CCSR_SSI_SIER,
385 vals->rx.sier | vals->tx.sier,
386 vals->rx.sier | vals->tx.sier);
387 regmap_update_bits(regs, CCSR_SSI_SRCR,
388 vals->rx.srcr | vals->tx.srcr,
389 vals->rx.srcr | vals->tx.srcr);
390 regmap_update_bits(regs, CCSR_SSI_STCR,
391 vals->rx.stcr | vals->tx.stcr,
392 vals->rx.stcr | vals->tx.stcr);
394 regmap_update_bits(regs, CCSR_SSI_SRCR,
395 vals->rx.srcr | vals->tx.srcr, 0);
396 regmap_update_bits(regs, CCSR_SSI_STCR,
397 vals->rx.stcr | vals->tx.stcr, 0);
398 regmap_update_bits(regs, CCSR_SSI_SIER,
399 vals->rx.sier | vals->tx.sier, 0);
404 * Calculate the bits that have to be disabled for the current stream that is
405 * getting disabled. This keeps the bits enabled that are necessary for the
406 * second stream to work if 'stream_active' is true.
408 * Detailed calculation:
409 * These are the values that need to be active after disabling. For non-active
410 * second stream, this is 0:
411 * vals_stream * !!stream_active
413 * The following computes the overall differences between the setup for the
414 * to-disable stream and the active stream, a simple XOR:
415 * vals_disable ^ (vals_stream * !!(stream_active))
417 * The full expression adds a mask on all values we care about
419 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
421 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
424 * Enable/Disable a ssi configuration. You have to pass either
425 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
427 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
428 struct fsl_ssi_reg_val *vals)
430 struct regmap *regs = ssi_private->regs;
431 struct fsl_ssi_reg_val *avals;
432 int nr_active_streams;
436 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
438 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
439 !!(scr_val & CCSR_SSI_SCR_RE);
441 if (nr_active_streams - 1 > 0)
446 /* Find the other direction values rx or tx which we do not want to
448 if (&ssi_private->rxtx_reg_val.rx == vals)
449 avals = &ssi_private->rxtx_reg_val.tx;
451 avals = &ssi_private->rxtx_reg_val.rx;
453 /* If vals should be disabled, start with disabling the unit */
455 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
457 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
461 * We are running on a SoC which does not support online SSI
462 * reconfiguration, so we have to enable all necessary flags at once
463 * even if we do not use them later (capture and playback configuration)
465 if (ssi_private->soc->offline_config) {
466 if ((enable && !nr_active_streams) ||
467 (!enable && !keep_active))
468 fsl_ssi_rxtx_config(ssi_private, enable);
474 * Configure single direction units while the SSI unit is running
475 * (online configuration)
478 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
479 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
480 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
487 * Disabling the necessary flags for one of rx/tx while the
488 * other stream is active is a little bit more difficult. We
489 * have to disable only those flags that differ between both
490 * streams (rx XOR tx) and that are set in the stream that is
491 * disabled now. Otherwise we could alter flags of the other
495 /* These assignments are simply vals without bits set in avals*/
496 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
498 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
500 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
503 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
504 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
505 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
509 /* Enabling of subunits is done after configuration */
511 if (ssi_private->use_dma && (vals->scr & CCSR_SSI_SCR_TE)) {
513 * Be sure the Tx FIFO is filled when TE is set.
514 * Otherwise, there are some chances to start the
515 * playback with some void samples inserted first,
516 * generating a channel slip.
518 * First, SSIEN must be set, to let the FIFO be filled.
521 * - Limit this fix to the DMA case until FIQ cases can
523 * - Limit the length of the busy loop to not lock the
524 * system too long, even if 1-2 loops are sufficient
529 regmap_update_bits(regs, CCSR_SSI_SCR,
530 CCSR_SSI_SCR_SSIEN, CCSR_SSI_SCR_SSIEN);
531 for (i = 0; i < max_loop; i++) {
533 regmap_read(regs, CCSR_SSI_SFCSR, &sfcsr);
534 if (CCSR_SSI_SFCSR_TFCNT0(sfcsr))
538 dev_err(ssi_private->dev,
539 "Timeout waiting TX FIFO filling\n");
542 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
547 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
549 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
552 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
554 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
558 * Setup rx/tx register values used to enable/disable the streams. These will
559 * be used later in fsl_ssi_config to setup the streams without the need to
560 * check for all different SSI modes.
562 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
564 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
566 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
567 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
569 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
570 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
573 if (!fsl_ssi_is_ac97(ssi_private)) {
574 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
575 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
576 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
577 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
580 if (ssi_private->use_dma) {
581 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
582 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
584 reg->rx.sier |= CCSR_SSI_SIER_RIE;
585 reg->tx.sier |= CCSR_SSI_SIER_TIE;
588 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
589 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
592 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
594 struct regmap *regs = ssi_private->regs;
597 * Setup the clock control register
599 regmap_write(regs, CCSR_SSI_STCCR,
600 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
601 regmap_write(regs, CCSR_SSI_SRCCR,
602 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
605 * Enable AC97 mode and startup the SSI
607 regmap_write(regs, CCSR_SSI_SACNT,
608 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
610 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
611 if (!ssi_private->soc->imx21regs) {
612 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
613 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
617 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
618 * codec before a stream is started.
620 regmap_update_bits(regs, CCSR_SSI_SCR,
621 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
622 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
624 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
628 * fsl_ssi_startup: create a new substream
630 * This is the first function called when a stream is opened.
632 * If this is the first stream open, then grab the IRQ and program most of
635 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
636 struct snd_soc_dai *dai)
638 struct snd_soc_pcm_runtime *rtd = substream->private_data;
639 struct fsl_ssi_private *ssi_private =
640 snd_soc_dai_get_drvdata(rtd->cpu_dai);
643 ret = clk_prepare_enable(ssi_private->clk);
647 /* When using dual fifo mode, it is safer to ensure an even period
648 * size. If appearing to an odd number while DMA always starts its
649 * task from fifo0, fifo1 would be neglected at the end of each
650 * period. But SSI would still access fifo1 with an invalid data.
652 if (ssi_private->use_dual_fifo)
653 snd_pcm_hw_constraint_step(substream->runtime, 0,
654 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
660 * fsl_ssi_shutdown: shutdown the SSI
663 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
664 struct snd_soc_dai *dai)
666 struct snd_soc_pcm_runtime *rtd = substream->private_data;
667 struct fsl_ssi_private *ssi_private =
668 snd_soc_dai_get_drvdata(rtd->cpu_dai);
670 clk_disable_unprepare(ssi_private->clk);
675 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
677 * Note: This function can be only called when using SSI as DAI master
679 * Quick instruction for parameters:
680 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
681 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
683 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
684 struct snd_soc_dai *cpu_dai,
685 struct snd_pcm_hw_params *hw_params)
687 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
688 struct regmap *regs = ssi_private->regs;
689 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
690 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
691 unsigned long clkrate, baudrate, tmprate;
692 u64 sub, savesub = 100000;
694 bool baudclk_is_used;
696 /* Prefer the explicitly set bitclock frequency */
697 if (ssi_private->bitclk_freq)
698 freq = ssi_private->bitclk_freq;
700 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
702 /* Don't apply it to any non-baudclk circumstance */
703 if (IS_ERR(ssi_private->baudclk))
707 * Hardware limitation: The bclk rate must be
708 * never greater than 1/5 IPG clock rate
710 if (freq * 5 > clk_get_rate(ssi_private->clk)) {
711 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
715 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
717 /* It should be already enough to divide clock by setting pm alone */
721 factor = (div2 + 1) * (7 * psr + 1) * 2;
723 for (i = 0; i < 255; i++) {
724 tmprate = freq * factor * (i + 1);
727 clkrate = clk_get_rate(ssi_private->baudclk);
729 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
732 afreq = clkrate / (i + 1);
736 else if (freq / afreq == 1)
738 else if (afreq / freq == 1)
743 /* Calculate the fraction */
747 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
758 /* No proper pm found if it is still remaining the initial value */
760 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
764 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
765 (psr ? CCSR_SSI_SxCCR_PSR : 0);
766 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
769 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
770 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
772 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
774 if (!baudclk_is_used) {
775 ret = clk_set_rate(ssi_private->baudclk, baudrate);
777 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
785 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
786 int clk_id, unsigned int freq, int dir)
788 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
790 ssi_private->bitclk_freq = freq;
796 * fsl_ssi_hw_params - program the sample size
798 * Most of the SSI registers have been programmed in the startup function,
799 * but the word length must be programmed here. Unfortunately, programming
800 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
801 * cause a problem with supporting simultaneous playback and capture. If
802 * the SSI is already playing a stream, then that stream may be temporarily
803 * stopped when you start capture.
805 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
808 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
809 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
811 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
812 struct regmap *regs = ssi_private->regs;
813 unsigned int channels = params_channels(hw_params);
814 unsigned int sample_size = params_width(hw_params);
815 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
820 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
821 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
824 * If we're in synchronous mode, and the SSI is already enabled,
825 * then STCCR is already set properly.
827 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
830 if (fsl_ssi_is_i2s_master(ssi_private)) {
831 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
835 /* Do not enable the clock if it is already enabled */
836 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
837 ret = clk_prepare_enable(ssi_private->baudclk);
841 ssi_private->baudclk_streams |= BIT(substream->stream);
845 if (!fsl_ssi_is_ac97(ssi_private)) {
848 * Switch to normal net mode in order to have a frame sync
849 * signal every 32 bits instead of 16 bits
851 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
852 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
855 i2smode = ssi_private->i2s_mode;
857 regmap_update_bits(regs, CCSR_SSI_SCR,
858 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
859 channels == 1 ? 0 : i2smode);
863 * FIXME: The documentation says that SxCCR[WL] should not be
864 * modified while the SSI is enabled. The only time this can
865 * happen is if we're trying to do simultaneous playback and
866 * capture in asynchronous mode. Unfortunately, I have been enable
867 * to get that to work at all on the P1022DS. Therefore, we don't
868 * bother to disable/enable the SSI when setting SxCCR[WL], because
869 * the SSI will stop anyway. Maybe one day, this will get fixed.
872 /* In synchronous mode, the SSI uses STCCR for capture */
873 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
874 ssi_private->cpu_dai_drv.symmetric_rates)
875 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
878 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
884 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
885 struct snd_soc_dai *cpu_dai)
887 struct snd_soc_pcm_runtime *rtd = substream->private_data;
888 struct fsl_ssi_private *ssi_private =
889 snd_soc_dai_get_drvdata(rtd->cpu_dai);
891 if (fsl_ssi_is_i2s_master(ssi_private) &&
892 ssi_private->baudclk_streams & BIT(substream->stream)) {
893 clk_disable_unprepare(ssi_private->baudclk);
894 ssi_private->baudclk_streams &= ~BIT(substream->stream);
900 static int _fsl_ssi_set_dai_fmt(struct device *dev,
901 struct fsl_ssi_private *ssi_private,
904 struct regmap *regs = ssi_private->regs;
905 u32 strcr = 0, stcr, srcr, scr, mask;
908 ssi_private->dai_fmt = fmt;
910 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
911 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
915 fsl_ssi_setup_reg_vals(ssi_private);
917 regmap_read(regs, CCSR_SSI_SCR, &scr);
918 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
919 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
921 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
922 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
924 regmap_read(regs, CCSR_SSI_STCR, &stcr);
925 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
929 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
930 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
931 case SND_SOC_DAIFMT_I2S:
932 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
933 case SND_SOC_DAIFMT_CBM_CFS:
934 case SND_SOC_DAIFMT_CBS_CFS:
935 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
936 regmap_update_bits(regs, CCSR_SSI_STCCR,
937 CCSR_SSI_SxCCR_DC_MASK,
938 CCSR_SSI_SxCCR_DC(2));
939 regmap_update_bits(regs, CCSR_SSI_SRCCR,
940 CCSR_SSI_SxCCR_DC_MASK,
941 CCSR_SSI_SxCCR_DC(2));
943 case SND_SOC_DAIFMT_CBM_CFM:
944 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
950 /* Data on rising edge of bclk, frame low, 1clk before data */
951 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
952 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
954 case SND_SOC_DAIFMT_LEFT_J:
955 /* Data on rising edge of bclk, frame high */
956 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
958 case SND_SOC_DAIFMT_DSP_A:
959 /* Data on rising edge of bclk, frame high, 1clk before data */
960 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
961 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
963 case SND_SOC_DAIFMT_DSP_B:
964 /* Data on rising edge of bclk, frame high */
965 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
966 CCSR_SSI_STCR_TXBIT0;
968 case SND_SOC_DAIFMT_AC97:
969 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
974 scr |= ssi_private->i2s_mode;
976 /* DAI clock inversion */
977 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
978 case SND_SOC_DAIFMT_NB_NF:
979 /* Nothing to do for both normal cases */
981 case SND_SOC_DAIFMT_IB_NF:
982 /* Invert bit clock */
983 strcr ^= CCSR_SSI_STCR_TSCKP;
985 case SND_SOC_DAIFMT_NB_IF:
986 /* Invert frame clock */
987 strcr ^= CCSR_SSI_STCR_TFSI;
989 case SND_SOC_DAIFMT_IB_IF:
990 /* Invert both clocks */
991 strcr ^= CCSR_SSI_STCR_TSCKP;
992 strcr ^= CCSR_SSI_STCR_TFSI;
998 /* DAI clock master masks */
999 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1000 case SND_SOC_DAIFMT_CBS_CFS:
1001 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
1002 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
1004 case SND_SOC_DAIFMT_CBM_CFM:
1005 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1007 case SND_SOC_DAIFMT_CBM_CFS:
1008 strcr &= ~CCSR_SSI_STCR_TXDIR;
1009 strcr |= CCSR_SSI_STCR_TFDIR;
1010 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
1013 if (!fsl_ssi_is_ac97(ssi_private))
1020 if (ssi_private->cpu_dai_drv.symmetric_rates
1021 || fsl_ssi_is_ac97(ssi_private)) {
1022 /* Need to clear RXDIR when using SYNC or AC97 mode */
1023 srcr &= ~CCSR_SSI_SRCR_RXDIR;
1024 scr |= CCSR_SSI_SCR_SYN;
1027 regmap_write(regs, CCSR_SSI_STCR, stcr);
1028 regmap_write(regs, CCSR_SSI_SRCR, srcr);
1029 regmap_write(regs, CCSR_SSI_SCR, scr);
1032 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
1033 * use FIFO 1. We program the transmit water to signal a DMA transfer
1034 * if there are only two (or fewer) elements left in the FIFO. Two
1035 * elements equals one frame (left channel, right channel). This value,
1036 * however, depends on the depth of the transmit buffer.
1038 * We set the watermark on the same level as the DMA burstsize. For
1039 * fiq it is probably better to use the biggest possible watermark
1042 if (ssi_private->use_dma)
1043 wm = ssi_private->fifo_depth - 2;
1045 wm = ssi_private->fifo_depth;
1047 regmap_write(regs, CCSR_SSI_SFCSR,
1048 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1049 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1051 if (ssi_private->use_dual_fifo) {
1052 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1053 CCSR_SSI_SRCR_RFEN1);
1054 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1055 CCSR_SSI_STCR_TFEN1);
1056 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1057 CCSR_SSI_SCR_TCH_EN);
1060 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1061 fsl_ssi_setup_ac97(ssi_private);
1068 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1070 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1072 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1074 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1078 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1080 * Note: This function can be only called when using SSI as DAI master
1082 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1083 u32 rx_mask, int slots, int slot_width)
1085 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1086 struct regmap *regs = ssi_private->regs;
1089 /* The slot number should be >= 2 if using Network mode or I2S mode */
1090 regmap_read(regs, CCSR_SSI_SCR, &val);
1091 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1092 if (val && slots < 2) {
1093 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1097 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1098 CCSR_SSI_SxCCR_DC(slots));
1099 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1100 CCSR_SSI_SxCCR_DC(slots));
1102 /* The register SxMSKs needs SSI to provide essential clock due to
1103 * hardware design. So we here temporarily enable SSI to set them.
1105 regmap_read(regs, CCSR_SSI_SCR, &val);
1106 val &= CCSR_SSI_SCR_SSIEN;
1107 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1108 CCSR_SSI_SCR_SSIEN);
1110 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1111 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1113 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1119 * fsl_ssi_trigger: start and stop the DMA transfer.
1121 * This function is called by ALSA to start, stop, pause, and resume the DMA
1124 * The DMA channel is in external master start and pause mode, which
1125 * means the SSI completely controls the flow of data.
1127 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1128 struct snd_soc_dai *dai)
1130 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1131 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1132 struct regmap *regs = ssi_private->regs;
1135 case SNDRV_PCM_TRIGGER_START:
1136 case SNDRV_PCM_TRIGGER_RESUME:
1137 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1138 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1139 fsl_ssi_tx_config(ssi_private, true);
1141 fsl_ssi_rx_config(ssi_private, true);
1144 case SNDRV_PCM_TRIGGER_STOP:
1145 case SNDRV_PCM_TRIGGER_SUSPEND:
1146 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1147 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1148 fsl_ssi_tx_config(ssi_private, false);
1150 fsl_ssi_rx_config(ssi_private, false);
1157 if (fsl_ssi_is_ac97(ssi_private)) {
1158 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1159 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1161 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1167 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1169 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1171 if (ssi_private->soc->imx && ssi_private->use_dma) {
1172 dai->playback_dma_data = &ssi_private->dma_params_tx;
1173 dai->capture_dma_data = &ssi_private->dma_params_rx;
1179 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1180 .startup = fsl_ssi_startup,
1181 .shutdown = fsl_ssi_shutdown,
1182 .hw_params = fsl_ssi_hw_params,
1183 .hw_free = fsl_ssi_hw_free,
1184 .set_fmt = fsl_ssi_set_dai_fmt,
1185 .set_sysclk = fsl_ssi_set_dai_sysclk,
1186 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1187 .trigger = fsl_ssi_trigger,
1190 /* Template for the CPU dai driver structure */
1191 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1192 .probe = fsl_ssi_dai_probe,
1194 .stream_name = "CPU-Playback",
1197 .rates = FSLSSI_I2S_RATES,
1198 .formats = FSLSSI_I2S_FORMATS,
1201 .stream_name = "CPU-Capture",
1204 .rates = FSLSSI_I2S_RATES,
1205 .formats = FSLSSI_I2S_FORMATS,
1207 .ops = &fsl_ssi_dai_ops,
1210 static const struct snd_soc_component_driver fsl_ssi_component = {
1214 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1215 .bus_control = true,
1216 .probe = fsl_ssi_dai_probe,
1218 .stream_name = "AC97 Playback",
1221 .rates = SNDRV_PCM_RATE_8000_48000,
1222 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1225 .stream_name = "AC97 Capture",
1228 .rates = SNDRV_PCM_RATE_48000,
1229 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1231 .ops = &fsl_ssi_dai_ops,
1235 static struct fsl_ssi_private *fsl_ac97_data;
1237 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1240 struct regmap *regs = fsl_ac97_data->regs;
1248 ret = clk_prepare_enable(fsl_ac97_data->clk);
1250 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1256 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1259 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1261 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1265 clk_disable_unprepare(fsl_ac97_data->clk);
1268 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1271 struct regmap *regs = fsl_ac97_data->regs;
1273 unsigned short val = -1;
1278 ret = clk_prepare_enable(fsl_ac97_data->clk);
1280 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1285 lreg = (reg & 0x7f) << 12;
1286 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1287 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1292 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1293 val = (reg_val >> 4) & 0xffff;
1295 clk_disable_unprepare(fsl_ac97_data->clk);
1300 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1301 .read = fsl_ssi_ac97_read,
1302 .write = fsl_ssi_ac97_write,
1306 * Make every character in a string lower-case
1308 static void make_lowercase(char *s)
1314 if ((c >= 'A') && (c <= 'Z'))
1315 *p = c + ('a' - 'A');
1320 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1321 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1323 struct device_node *np = pdev->dev.of_node;
1327 if (ssi_private->has_ipg_clk_name)
1328 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1330 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1331 if (IS_ERR(ssi_private->clk)) {
1332 ret = PTR_ERR(ssi_private->clk);
1333 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1337 if (!ssi_private->has_ipg_clk_name) {
1338 ret = clk_prepare_enable(ssi_private->clk);
1340 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1345 /* For those SLAVE implementations, we ignore non-baudclk cases
1346 * and, instead, abandon MASTER mode that needs baud clock.
1348 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1349 if (IS_ERR(ssi_private->baudclk))
1350 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1351 PTR_ERR(ssi_private->baudclk));
1354 * We have burstsize be "fifo_depth - 2" to match the SSI
1355 * watermark setting in fsl_ssi_startup().
1357 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1358 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1359 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1360 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1362 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1363 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1364 ssi_private->use_dual_fifo = true;
1365 /* When using dual fifo mode, we need to keep watermark
1366 * as even numbers due to dma script limitation.
1368 ssi_private->dma_params_tx.maxburst &= ~0x1;
1369 ssi_private->dma_params_rx.maxburst &= ~0x1;
1372 if (!ssi_private->use_dma) {
1375 * Some boards use an incompatible codec. To get it
1376 * working, we are using imx-fiq-pcm-audio, that
1377 * can handle those codecs. DMA is not possible in this
1381 ssi_private->fiq_params.irq = ssi_private->irq;
1382 ssi_private->fiq_params.base = iomem;
1383 ssi_private->fiq_params.dma_params_rx =
1384 &ssi_private->dma_params_rx;
1385 ssi_private->fiq_params.dma_params_tx =
1386 &ssi_private->dma_params_tx;
1388 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1392 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1401 if (!ssi_private->has_ipg_clk_name)
1402 clk_disable_unprepare(ssi_private->clk);
1406 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1407 struct fsl_ssi_private *ssi_private)
1409 if (!ssi_private->use_dma)
1410 imx_pcm_fiq_exit(pdev);
1411 if (!ssi_private->has_ipg_clk_name)
1412 clk_disable_unprepare(ssi_private->clk);
1415 static int fsl_ssi_probe(struct platform_device *pdev)
1417 struct fsl_ssi_private *ssi_private;
1419 struct device_node *np = pdev->dev.of_node;
1420 const struct of_device_id *of_id;
1421 const char *p, *sprop;
1422 const uint32_t *iprop;
1423 struct resource *res;
1424 void __iomem *iomem;
1426 struct regmap_config regconfig = fsl_ssi_regconfig;
1428 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1429 if (!of_id || !of_id->data)
1432 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1435 dev_err(&pdev->dev, "could not allocate DAI object\n");
1439 ssi_private->soc = of_id->data;
1440 ssi_private->dev = &pdev->dev;
1442 sprop = of_get_property(np, "fsl,mode", NULL);
1444 if (!strcmp(sprop, "ac97-slave"))
1445 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1448 ssi_private->use_dma = !of_property_read_bool(np,
1449 "fsl,fiq-stream-filter");
1451 if (fsl_ssi_is_ac97(ssi_private)) {
1452 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1453 sizeof(fsl_ssi_ac97_dai));
1455 fsl_ac97_data = ssi_private;
1457 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1459 dev_err(&pdev->dev, "could not set AC'97 ops\n");
1463 /* Initialize this copy of the CPU DAI driver structure */
1464 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1465 sizeof(fsl_ssi_dai_template));
1467 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1469 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1470 iomem = devm_ioremap_resource(&pdev->dev, res);
1472 return PTR_ERR(iomem);
1473 ssi_private->ssi_phys = res->start;
1475 if (ssi_private->soc->imx21regs) {
1477 * According to datasheet imx21-class SSI
1478 * don't have SACC{ST,EN,DIS} regs.
1480 regconfig.max_register = CCSR_SSI_SRMSK;
1481 regconfig.num_reg_defaults_raw =
1482 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1485 ret = of_property_match_string(np, "clock-names", "ipg");
1487 ssi_private->has_ipg_clk_name = false;
1488 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1491 ssi_private->has_ipg_clk_name = true;
1492 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1493 "ipg", iomem, ®config);
1495 if (IS_ERR(ssi_private->regs)) {
1496 dev_err(&pdev->dev, "Failed to init register map\n");
1497 return PTR_ERR(ssi_private->regs);
1500 ssi_private->irq = platform_get_irq(pdev, 0);
1501 if (ssi_private->irq < 0) {
1502 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1503 return ssi_private->irq;
1506 /* Are the RX and the TX clocks locked? */
1507 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1508 if (!fsl_ssi_is_ac97(ssi_private))
1509 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1511 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1512 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1515 /* Determine the FIFO depth. */
1516 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1518 ssi_private->fifo_depth = be32_to_cpup(iprop);
1520 /* Older 8610 DTs didn't have the fifo-depth property */
1521 ssi_private->fifo_depth = 8;
1523 dev_set_drvdata(&pdev->dev, ssi_private);
1525 if (ssi_private->soc->imx) {
1526 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1531 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1532 &ssi_private->cpu_dai_drv, 1);
1534 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1535 goto error_asoc_register;
1538 if (ssi_private->use_dma) {
1539 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1540 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1543 dev_err(&pdev->dev, "could not claim irq %u\n",
1545 goto error_asoc_register;
1549 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1551 goto error_asoc_register;
1554 * If codec-handle property is missing from SSI node, we assume
1555 * that the machine driver uses new binding which does not require
1556 * SSI driver to trigger machine driver's probe.
1558 if (!of_get_property(np, "codec-handle", NULL))
1561 /* Trigger the machine driver's probe function. The platform driver
1562 * name of the machine driver is taken from /compatible property of the
1563 * device tree. We also pass the address of the CPU DAI driver
1566 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1567 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1568 p = strrchr(sprop, ',');
1571 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1572 make_lowercase(name);
1575 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1576 if (IS_ERR(ssi_private->pdev)) {
1577 ret = PTR_ERR(ssi_private->pdev);
1578 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1579 goto error_sound_card;
1583 if (ssi_private->dai_fmt)
1584 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1585 ssi_private->dai_fmt);
1587 if (fsl_ssi_is_ac97(ssi_private)) {
1590 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1592 dev_err(&pdev->dev, "cannot get SSI index property\n");
1593 goto error_sound_card;
1597 platform_device_register_data(NULL,
1598 "ac97-codec", ssi_idx, NULL, 0);
1599 if (IS_ERR(ssi_private->pdev)) {
1600 ret = PTR_ERR(ssi_private->pdev);
1602 "failed to register AC97 codec platform: %d\n",
1604 goto error_sound_card;
1611 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1613 error_asoc_register:
1614 if (ssi_private->soc->imx)
1615 fsl_ssi_imx_clean(pdev, ssi_private);
1620 static int fsl_ssi_remove(struct platform_device *pdev)
1622 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1624 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1626 if (ssi_private->pdev)
1627 platform_device_unregister(ssi_private->pdev);
1629 if (ssi_private->soc->imx)
1630 fsl_ssi_imx_clean(pdev, ssi_private);
1632 if (fsl_ssi_is_ac97(ssi_private))
1633 snd_soc_set_ac97_ops(NULL);
1638 #ifdef CONFIG_PM_SLEEP
1639 static int fsl_ssi_suspend(struct device *dev)
1641 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1642 struct regmap *regs = ssi_private->regs;
1644 regmap_read(regs, CCSR_SSI_SFCSR,
1645 &ssi_private->regcache_sfcsr);
1646 regmap_read(regs, CCSR_SSI_SACNT,
1647 &ssi_private->regcache_sacnt);
1649 regcache_cache_only(regs, true);
1650 regcache_mark_dirty(regs);
1655 static int fsl_ssi_resume(struct device *dev)
1657 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1658 struct regmap *regs = ssi_private->regs;
1660 regcache_cache_only(regs, false);
1662 regmap_update_bits(regs, CCSR_SSI_SFCSR,
1663 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1664 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1665 ssi_private->regcache_sfcsr);
1666 regmap_write(regs, CCSR_SSI_SACNT,
1667 ssi_private->regcache_sacnt);
1669 return regcache_sync(regs);
1671 #endif /* CONFIG_PM_SLEEP */
1673 static const struct dev_pm_ops fsl_ssi_pm = {
1674 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1677 static struct platform_driver fsl_ssi_driver = {
1679 .name = "fsl-ssi-dai",
1680 .of_match_table = fsl_ssi_ids,
1683 .probe = fsl_ssi_probe,
1684 .remove = fsl_ssi_remove,
1687 module_platform_driver(fsl_ssi_driver);
1689 MODULE_ALIAS("platform:fsl-ssi-dai");
1690 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1691 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1692 MODULE_LICENSE("GPL v2");