2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
43 #include <linux/of_address.h>
44 #include <linux/of_irq.h>
45 #include <linux/of_platform.h>
47 #include <sound/core.h>
48 #include <sound/pcm.h>
49 #include <sound/pcm_params.h>
50 #include <sound/initval.h>
51 #include <sound/soc.h>
52 #include <sound/dmaengine_pcm.h>
58 * FSLSSI_I2S_RATES: sample rates supported by the I2S
60 * This driver currently only supports the SSI running in I2S slave mode,
61 * which means the codec determines the sample rate. Therefore, we tell
62 * ALSA that we support all rates and let the codec driver decide what rates
63 * are really supported.
65 #define FSLSSI_I2S_RATES SNDRV_PCM_RATE_CONTINUOUS
68 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
70 * The SSI has a limitation in that the samples must be in the same byte
71 * order as the host CPU. This is because when multiple bytes are written
72 * to the STX register, the bytes and bits must be written in the same
73 * order. The STX is a shift register, so all the bits need to be aligned
74 * (bit-endianness must match byte-endianness). Processors typically write
75 * the bits within a byte in the same order that the bytes of a word are
76 * written in. So if the host CPU is big-endian, then only big-endian
77 * samples will be written to STX properly.
80 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
81 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
82 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
84 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
85 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
86 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
89 #define FSLSSI_SIER_DBG_RX_FLAGS (CCSR_SSI_SIER_RFF0_EN | \
90 CCSR_SSI_SIER_RLS_EN | CCSR_SSI_SIER_RFS_EN | \
91 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_RFRC_EN)
92 #define FSLSSI_SIER_DBG_TX_FLAGS (CCSR_SSI_SIER_TFE0_EN | \
93 CCSR_SSI_SIER_TLS_EN | CCSR_SSI_SIER_TFS_EN | \
94 CCSR_SSI_SIER_TUE0_EN | CCSR_SSI_SIER_TFRC_EN)
103 struct fsl_ssi_reg_val {
110 struct fsl_ssi_rxtx_reg_val {
111 struct fsl_ssi_reg_val rx;
112 struct fsl_ssi_reg_val tx;
115 static bool fsl_ssi_readable_reg(struct device *dev, unsigned int reg)
118 case CCSR_SSI_SACCEN:
119 case CCSR_SSI_SACCDIS:
126 static bool fsl_ssi_volatile_reg(struct device *dev, unsigned int reg)
136 case CCSR_SSI_SACADD:
137 case CCSR_SSI_SACDAT:
139 case CCSR_SSI_SACCST:
146 static bool fsl_ssi_precious_reg(struct device *dev, unsigned int reg)
152 case CCSR_SSI_SACADD:
153 case CCSR_SSI_SACDAT:
161 static bool fsl_ssi_writeable_reg(struct device *dev, unsigned int reg)
166 case CCSR_SSI_SACCST:
173 static const struct regmap_config fsl_ssi_regconfig = {
174 .max_register = CCSR_SSI_SACCDIS,
178 .val_format_endian = REGMAP_ENDIAN_NATIVE,
179 .num_reg_defaults_raw = CCSR_SSI_SACCDIS / sizeof(uint32_t) + 1,
180 .readable_reg = fsl_ssi_readable_reg,
181 .volatile_reg = fsl_ssi_volatile_reg,
182 .precious_reg = fsl_ssi_precious_reg,
183 .writeable_reg = fsl_ssi_writeable_reg,
184 .cache_type = REGCACHE_RBTREE,
187 struct fsl_ssi_soc_data {
189 bool imx21regs; /* imx21-class SSI - no SACC{ST,EN,DIS} regs */
195 * fsl_ssi_private: per-SSI private data
197 * @reg: Pointer to the regmap registers
198 * @irq: IRQ of this SSI
199 * @cpu_dai_drv: CPU DAI driver for this device
201 * @dai_fmt: DAI configuration this device is currently used with
202 * @i2s_mode: i2s and network mode configuration of the device. Is used to
203 * switch between normal and i2s/network mode
204 * mode depending on the number of channels
205 * @use_dma: DMA is used or FIQ with stream filter
206 * @use_dual_fifo: DMA with support for both FIFOs used
207 * @fifo_deph: Depth of the SSI FIFOs
208 * @rxtx_reg_val: Specific register settings for receive/transmit configuration
211 * @baudclk: SSI baud clock for master mode
212 * @baudclk_streams: Active streams that are using baudclk
213 * @bitclk_freq: bitclock frequency set by .set_dai_sysclk
215 * @dma_params_tx: DMA transmit parameters
216 * @dma_params_rx: DMA receive parameters
217 * @ssi_phys: physical address of the SSI registers
219 * @fiq_params: FIQ stream filtering parameters
221 * @pdev: Pointer to pdev used for deprecated fsl-ssi sound card
223 * @dbg_stats: Debugging statistics
225 * @soc: SoC specific data
227 struct fsl_ssi_private {
230 struct snd_soc_dai_driver cpu_dai_drv;
232 unsigned int dai_fmt;
236 bool has_ipg_clk_name;
237 unsigned int fifo_depth;
238 struct fsl_ssi_rxtx_reg_val rxtx_reg_val;
242 unsigned int baudclk_streams;
243 unsigned int bitclk_freq;
245 /* regcache for volatile regs */
250 struct snd_dmaengine_dai_dma_data dma_params_tx;
251 struct snd_dmaengine_dai_dma_data dma_params_rx;
254 /* params for non-dma FIQ stream filtered mode */
255 struct imx_pcm_fiq_params fiq_params;
257 /* Used when using fsl-ssi as sound-card. This is only used by ppc and
258 * should be replaced with simple-sound-card. */
259 struct platform_device *pdev;
261 struct fsl_ssi_dbg dbg_stats;
263 const struct fsl_ssi_soc_data *soc;
268 * imx51 and later SoCs have a slightly different IP that allows the
269 * SSI configuration while the SSI unit is running.
271 * More important, it is necessary on those SoCs to configure the
272 * sperate TX/RX DMA bits just before starting the stream
273 * (fsl_ssi_trigger). The SDMA unit has to be configured before fsl_ssi
274 * sends any DMA requests to the SDMA unit, otherwise it is not defined
275 * how the SDMA unit handles the DMA request.
277 * SDMA units are present on devices starting at imx35 but the imx35
278 * reference manual states that the DMA bits should not be changed
279 * while the SSI unit is running (SSIEN). So we support the necessary
280 * online configuration of fsl-ssi starting at imx51.
283 static struct fsl_ssi_soc_data fsl_ssi_mpc8610 = {
285 .offline_config = true,
286 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
287 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
288 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
291 static struct fsl_ssi_soc_data fsl_ssi_imx21 = {
294 .offline_config = true,
295 .sisr_write_mask = 0,
298 static struct fsl_ssi_soc_data fsl_ssi_imx35 = {
300 .offline_config = true,
301 .sisr_write_mask = CCSR_SSI_SISR_RFRC | CCSR_SSI_SISR_TFRC |
302 CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
303 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
306 static struct fsl_ssi_soc_data fsl_ssi_imx51 = {
308 .offline_config = false,
309 .sisr_write_mask = CCSR_SSI_SISR_ROE0 | CCSR_SSI_SISR_ROE1 |
310 CCSR_SSI_SISR_TUE0 | CCSR_SSI_SISR_TUE1,
313 static const struct of_device_id fsl_ssi_ids[] = {
314 { .compatible = "fsl,mpc8610-ssi", .data = &fsl_ssi_mpc8610 },
315 { .compatible = "fsl,imx51-ssi", .data = &fsl_ssi_imx51 },
316 { .compatible = "fsl,imx35-ssi", .data = &fsl_ssi_imx35 },
317 { .compatible = "fsl,imx21-ssi", .data = &fsl_ssi_imx21 },
320 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
322 static bool fsl_ssi_is_ac97(struct fsl_ssi_private *ssi_private)
324 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
328 static bool fsl_ssi_is_i2s_master(struct fsl_ssi_private *ssi_private)
330 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
331 SND_SOC_DAIFMT_CBS_CFS;
334 static bool fsl_ssi_is_i2s_cbm_cfs(struct fsl_ssi_private *ssi_private)
336 return (ssi_private->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) ==
337 SND_SOC_DAIFMT_CBM_CFS;
340 * fsl_ssi_isr: SSI interrupt handler
342 * Although it's possible to use the interrupt handler to send and receive
343 * data to/from the SSI, we use the DMA instead. Programming is more
344 * complicated, but the performance is much better.
346 * This interrupt handler is used only to gather statistics.
348 * @irq: IRQ of the SSI device
349 * @dev_id: pointer to the ssi_private structure for this SSI device
351 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
353 struct fsl_ssi_private *ssi_private = dev_id;
354 struct regmap *regs = ssi_private->regs;
358 /* We got an interrupt, so read the status register to see what we
359 were interrupted for. We mask it with the Interrupt Enable register
360 so that we only check for events that we're interested in.
362 regmap_read(regs, CCSR_SSI_SISR, &sisr);
364 sisr2 = sisr & ssi_private->soc->sisr_write_mask;
365 /* Clear the bits that we set */
367 regmap_write(regs, CCSR_SSI_SISR, sisr2);
369 fsl_ssi_dbg_isr(&ssi_private->dbg_stats, sisr);
375 * Enable/Disable all rx/tx config flags at once.
377 static void fsl_ssi_rxtx_config(struct fsl_ssi_private *ssi_private,
380 struct regmap *regs = ssi_private->regs;
381 struct fsl_ssi_rxtx_reg_val *vals = &ssi_private->rxtx_reg_val;
384 regmap_update_bits(regs, CCSR_SSI_SIER,
385 vals->rx.sier | vals->tx.sier,
386 vals->rx.sier | vals->tx.sier);
387 regmap_update_bits(regs, CCSR_SSI_SRCR,
388 vals->rx.srcr | vals->tx.srcr,
389 vals->rx.srcr | vals->tx.srcr);
390 regmap_update_bits(regs, CCSR_SSI_STCR,
391 vals->rx.stcr | vals->tx.stcr,
392 vals->rx.stcr | vals->tx.stcr);
394 regmap_update_bits(regs, CCSR_SSI_SRCR,
395 vals->rx.srcr | vals->tx.srcr, 0);
396 regmap_update_bits(regs, CCSR_SSI_STCR,
397 vals->rx.stcr | vals->tx.stcr, 0);
398 regmap_update_bits(regs, CCSR_SSI_SIER,
399 vals->rx.sier | vals->tx.sier, 0);
404 * Calculate the bits that have to be disabled for the current stream that is
405 * getting disabled. This keeps the bits enabled that are necessary for the
406 * second stream to work if 'stream_active' is true.
408 * Detailed calculation:
409 * These are the values that need to be active after disabling. For non-active
410 * second stream, this is 0:
411 * vals_stream * !!stream_active
413 * The following computes the overall differences between the setup for the
414 * to-disable stream and the active stream, a simple XOR:
415 * vals_disable ^ (vals_stream * !!(stream_active))
417 * The full expression adds a mask on all values we care about
419 #define fsl_ssi_disable_val(vals_disable, vals_stream, stream_active) \
421 ((vals_disable) ^ ((vals_stream) * (u32)!!(stream_active))))
424 * Enable/Disable a ssi configuration. You have to pass either
425 * ssi_private->rxtx_reg_val.rx or tx as vals parameter.
427 static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
428 struct fsl_ssi_reg_val *vals)
430 struct regmap *regs = ssi_private->regs;
431 struct fsl_ssi_reg_val *avals;
432 int nr_active_streams;
436 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
438 nr_active_streams = !!(scr_val & CCSR_SSI_SCR_TE) +
439 !!(scr_val & CCSR_SSI_SCR_RE);
441 if (nr_active_streams - 1 > 0)
446 /* Find the other direction values rx or tx which we do not want to
448 if (&ssi_private->rxtx_reg_val.rx == vals)
449 avals = &ssi_private->rxtx_reg_val.tx;
451 avals = &ssi_private->rxtx_reg_val.rx;
453 /* If vals should be disabled, start with disabling the unit */
455 u32 scr = fsl_ssi_disable_val(vals->scr, avals->scr,
457 regmap_update_bits(regs, CCSR_SSI_SCR, scr, 0);
461 * We are running on a SoC which does not support online SSI
462 * reconfiguration, so we have to enable all necessary flags at once
463 * even if we do not use them later (capture and playback configuration)
465 if (ssi_private->soc->offline_config) {
466 if ((enable && !nr_active_streams) ||
467 (!enable && !keep_active))
468 fsl_ssi_rxtx_config(ssi_private, enable);
474 * Configure single direction units while the SSI unit is running
475 * (online configuration)
478 regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
479 regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
480 regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
487 * Disabling the necessary flags for one of rx/tx while the
488 * other stream is active is a little bit more difficult. We
489 * have to disable only those flags that differ between both
490 * streams (rx XOR tx) and that are set in the stream that is
491 * disabled now. Otherwise we could alter flags of the other
495 /* These assignments are simply vals without bits set in avals*/
496 sier = fsl_ssi_disable_val(vals->sier, avals->sier,
498 srcr = fsl_ssi_disable_val(vals->srcr, avals->srcr,
500 stcr = fsl_ssi_disable_val(vals->stcr, avals->stcr,
503 regmap_update_bits(regs, CCSR_SSI_SRCR, srcr, 0);
504 regmap_update_bits(regs, CCSR_SSI_STCR, stcr, 0);
505 regmap_update_bits(regs, CCSR_SSI_SIER, sier, 0);
509 /* Enabling of subunits is done after configuration */
511 regmap_update_bits(regs, CCSR_SSI_SCR, vals->scr, vals->scr);
515 static void fsl_ssi_rx_config(struct fsl_ssi_private *ssi_private, bool enable)
517 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.rx);
520 static void fsl_ssi_tx_config(struct fsl_ssi_private *ssi_private, bool enable)
522 fsl_ssi_config(ssi_private, enable, &ssi_private->rxtx_reg_val.tx);
526 * Setup rx/tx register values used to enable/disable the streams. These will
527 * be used later in fsl_ssi_config to setup the streams without the need to
528 * check for all different SSI modes.
530 static void fsl_ssi_setup_reg_vals(struct fsl_ssi_private *ssi_private)
532 struct fsl_ssi_rxtx_reg_val *reg = &ssi_private->rxtx_reg_val;
534 reg->rx.sier = CCSR_SSI_SIER_RFF0_EN;
535 reg->rx.srcr = CCSR_SSI_SRCR_RFEN0;
537 reg->tx.sier = CCSR_SSI_SIER_TFE0_EN;
538 reg->tx.stcr = CCSR_SSI_STCR_TFEN0;
541 if (!fsl_ssi_is_ac97(ssi_private)) {
542 reg->rx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE;
543 reg->rx.sier |= CCSR_SSI_SIER_RFF0_EN;
544 reg->tx.scr = CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE;
545 reg->tx.sier |= CCSR_SSI_SIER_TFE0_EN;
548 if (ssi_private->use_dma) {
549 reg->rx.sier |= CCSR_SSI_SIER_RDMAE;
550 reg->tx.sier |= CCSR_SSI_SIER_TDMAE;
552 reg->rx.sier |= CCSR_SSI_SIER_RIE;
553 reg->tx.sier |= CCSR_SSI_SIER_TIE;
556 reg->rx.sier |= FSLSSI_SIER_DBG_RX_FLAGS;
557 reg->tx.sier |= FSLSSI_SIER_DBG_TX_FLAGS;
560 static void fsl_ssi_setup_ac97(struct fsl_ssi_private *ssi_private)
562 struct regmap *regs = ssi_private->regs;
565 * Setup the clock control register
567 regmap_write(regs, CCSR_SSI_STCCR,
568 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
569 regmap_write(regs, CCSR_SSI_SRCCR,
570 CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13));
573 * Enable AC97 mode and startup the SSI
575 regmap_write(regs, CCSR_SSI_SACNT,
576 CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV);
578 /* no SACC{ST,EN,DIS} regs on imx21-class SSI */
579 if (!ssi_private->soc->imx21regs) {
580 regmap_write(regs, CCSR_SSI_SACCDIS, 0xff);
581 regmap_write(regs, CCSR_SSI_SACCEN, 0x300);
585 * Enable SSI, Transmit and Receive. AC97 has to communicate with the
586 * codec before a stream is started.
588 regmap_update_bits(regs, CCSR_SSI_SCR,
589 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE,
590 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
592 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_WAIT(3));
596 * fsl_ssi_startup: create a new substream
598 * This is the first function called when a stream is opened.
600 * If this is the first stream open, then grab the IRQ and program most of
603 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
604 struct snd_soc_dai *dai)
606 struct snd_soc_pcm_runtime *rtd = substream->private_data;
607 struct fsl_ssi_private *ssi_private =
608 snd_soc_dai_get_drvdata(rtd->cpu_dai);
611 ret = clk_prepare_enable(ssi_private->clk);
615 /* When using dual fifo mode, it is safer to ensure an even period
616 * size. If appearing to an odd number while DMA always starts its
617 * task from fifo0, fifo1 would be neglected at the end of each
618 * period. But SSI would still access fifo1 with an invalid data.
620 if (ssi_private->use_dual_fifo)
621 snd_pcm_hw_constraint_step(substream->runtime, 0,
622 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
628 * fsl_ssi_shutdown: shutdown the SSI
631 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
632 struct snd_soc_dai *dai)
634 struct snd_soc_pcm_runtime *rtd = substream->private_data;
635 struct fsl_ssi_private *ssi_private =
636 snd_soc_dai_get_drvdata(rtd->cpu_dai);
638 clk_disable_unprepare(ssi_private->clk);
643 * fsl_ssi_set_bclk - configure Digital Audio Interface bit clock
645 * Note: This function can be only called when using SSI as DAI master
647 * Quick instruction for parameters:
648 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
649 * dir: SND_SOC_CLOCK_OUT -> TxBCLK, SND_SOC_CLOCK_IN -> RxBCLK.
651 static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
652 struct snd_soc_dai *cpu_dai,
653 struct snd_pcm_hw_params *hw_params)
655 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
656 struct regmap *regs = ssi_private->regs;
657 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates, ret;
658 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i;
659 unsigned long clkrate, baudrate, tmprate;
660 u64 sub, savesub = 100000;
662 bool baudclk_is_used;
664 /* Prefer the explicitly set bitclock frequency */
665 if (ssi_private->bitclk_freq)
666 freq = ssi_private->bitclk_freq;
668 freq = params_channels(hw_params) * 32 * params_rate(hw_params);
670 /* Don't apply it to any non-baudclk circumstance */
671 if (IS_ERR(ssi_private->baudclk))
675 * Hardware limitation: The bclk rate must be
676 * never greater than 1/5 IPG clock rate
678 if (freq * 5 > clk_get_rate(ssi_private->clk)) {
679 dev_err(cpu_dai->dev, "bitclk > ipgclk/5\n");
683 baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream));
685 /* It should be already enough to divide clock by setting pm alone */
689 factor = (div2 + 1) * (7 * psr + 1) * 2;
691 for (i = 0; i < 255; i++) {
692 tmprate = freq * factor * (i + 1);
695 clkrate = clk_get_rate(ssi_private->baudclk);
697 clkrate = clk_round_rate(ssi_private->baudclk, tmprate);
700 afreq = clkrate / (i + 1);
704 else if (freq / afreq == 1)
706 else if (afreq / freq == 1)
711 /* Calculate the fraction */
715 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) {
726 /* No proper pm found if it is still remaining the initial value */
728 dev_err(cpu_dai->dev, "failed to handle the required sysclk\n");
732 stccr = CCSR_SSI_SxCCR_PM(pm + 1) | (div2 ? CCSR_SSI_SxCCR_DIV2 : 0) |
733 (psr ? CCSR_SSI_SxCCR_PSR : 0);
734 mask = CCSR_SSI_SxCCR_PM_MASK | CCSR_SSI_SxCCR_DIV2 |
737 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK || synchronous)
738 regmap_update_bits(regs, CCSR_SSI_STCCR, mask, stccr);
740 regmap_update_bits(regs, CCSR_SSI_SRCCR, mask, stccr);
742 if (!baudclk_is_used) {
743 ret = clk_set_rate(ssi_private->baudclk, baudrate);
745 dev_err(cpu_dai->dev, "failed to set baudclk rate\n");
753 static int fsl_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
754 int clk_id, unsigned int freq, int dir)
756 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
758 ssi_private->bitclk_freq = freq;
764 * fsl_ssi_hw_params - program the sample size
766 * Most of the SSI registers have been programmed in the startup function,
767 * but the word length must be programmed here. Unfortunately, programming
768 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
769 * cause a problem with supporting simultaneous playback and capture. If
770 * the SSI is already playing a stream, then that stream may be temporarily
771 * stopped when you start capture.
773 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
776 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
777 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
779 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
780 struct regmap *regs = ssi_private->regs;
781 unsigned int channels = params_channels(hw_params);
782 unsigned int sample_size = params_width(hw_params);
783 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
788 regmap_read(regs, CCSR_SSI_SCR, &scr_val);
789 enabled = scr_val & CCSR_SSI_SCR_SSIEN;
792 * If we're in synchronous mode, and the SSI is already enabled,
793 * then STCCR is already set properly.
795 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
798 if (fsl_ssi_is_i2s_master(ssi_private)) {
799 ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params);
803 /* Do not enable the clock if it is already enabled */
804 if (!(ssi_private->baudclk_streams & BIT(substream->stream))) {
805 ret = clk_prepare_enable(ssi_private->baudclk);
809 ssi_private->baudclk_streams |= BIT(substream->stream);
813 if (!fsl_ssi_is_ac97(ssi_private)) {
816 * Switch to normal net mode in order to have a frame sync
817 * signal every 32 bits instead of 16 bits
819 if (fsl_ssi_is_i2s_cbm_cfs(ssi_private) && sample_size == 16)
820 i2smode = CCSR_SSI_SCR_I2S_MODE_NORMAL |
823 i2smode = ssi_private->i2s_mode;
825 regmap_update_bits(regs, CCSR_SSI_SCR,
826 CCSR_SSI_SCR_NET | CCSR_SSI_SCR_I2S_MODE_MASK,
827 channels == 1 ? 0 : i2smode);
831 * FIXME: The documentation says that SxCCR[WL] should not be
832 * modified while the SSI is enabled. The only time this can
833 * happen is if we're trying to do simultaneous playback and
834 * capture in asynchronous mode. Unfortunately, I have been enable
835 * to get that to work at all on the P1022DS. Therefore, we don't
836 * bother to disable/enable the SSI when setting SxCCR[WL], because
837 * the SSI will stop anyway. Maybe one day, this will get fixed.
840 /* In synchronous mode, the SSI uses STCCR for capture */
841 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
842 ssi_private->cpu_dai_drv.symmetric_rates)
843 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_WL_MASK,
846 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_WL_MASK,
852 static int fsl_ssi_hw_free(struct snd_pcm_substream *substream,
853 struct snd_soc_dai *cpu_dai)
855 struct snd_soc_pcm_runtime *rtd = substream->private_data;
856 struct fsl_ssi_private *ssi_private =
857 snd_soc_dai_get_drvdata(rtd->cpu_dai);
859 if (fsl_ssi_is_i2s_master(ssi_private) &&
860 ssi_private->baudclk_streams & BIT(substream->stream)) {
861 clk_disable_unprepare(ssi_private->baudclk);
862 ssi_private->baudclk_streams &= ~BIT(substream->stream);
868 static int _fsl_ssi_set_dai_fmt(struct device *dev,
869 struct fsl_ssi_private *ssi_private,
872 struct regmap *regs = ssi_private->regs;
873 u32 strcr = 0, stcr, srcr, scr, mask;
876 ssi_private->dai_fmt = fmt;
878 if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) {
879 dev_err(dev, "baudclk is missing which is necessary for master mode\n");
883 fsl_ssi_setup_reg_vals(ssi_private);
885 regmap_read(regs, CCSR_SSI_SCR, &scr);
886 scr &= ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK);
887 scr |= CCSR_SSI_SCR_SYNC_TX_FS;
889 mask = CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR |
890 CCSR_SSI_STCR_TSCKP | CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TFSL |
892 regmap_read(regs, CCSR_SSI_STCR, &stcr);
893 regmap_read(regs, CCSR_SSI_SRCR, &srcr);
897 ssi_private->i2s_mode = CCSR_SSI_SCR_NET;
898 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
899 case SND_SOC_DAIFMT_I2S:
900 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
901 case SND_SOC_DAIFMT_CBM_CFS:
902 case SND_SOC_DAIFMT_CBS_CFS:
903 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_MASTER;
904 regmap_update_bits(regs, CCSR_SSI_STCCR,
905 CCSR_SSI_SxCCR_DC_MASK,
906 CCSR_SSI_SxCCR_DC(2));
907 regmap_update_bits(regs, CCSR_SSI_SRCCR,
908 CCSR_SSI_SxCCR_DC_MASK,
909 CCSR_SSI_SxCCR_DC(2));
911 case SND_SOC_DAIFMT_CBM_CFM:
912 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_SLAVE;
918 /* Data on rising edge of bclk, frame low, 1clk before data */
919 strcr |= CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TSCKP |
920 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
922 case SND_SOC_DAIFMT_LEFT_J:
923 /* Data on rising edge of bclk, frame high */
924 strcr |= CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TSCKP;
926 case SND_SOC_DAIFMT_DSP_A:
927 /* Data on rising edge of bclk, frame high, 1clk before data */
928 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
929 CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TEFS;
931 case SND_SOC_DAIFMT_DSP_B:
932 /* Data on rising edge of bclk, frame high */
933 strcr |= CCSR_SSI_STCR_TFSL | CCSR_SSI_STCR_TSCKP |
934 CCSR_SSI_STCR_TXBIT0;
936 case SND_SOC_DAIFMT_AC97:
937 ssi_private->i2s_mode |= CCSR_SSI_SCR_I2S_MODE_NORMAL;
942 scr |= ssi_private->i2s_mode;
944 /* DAI clock inversion */
945 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
946 case SND_SOC_DAIFMT_NB_NF:
947 /* Nothing to do for both normal cases */
949 case SND_SOC_DAIFMT_IB_NF:
950 /* Invert bit clock */
951 strcr ^= CCSR_SSI_STCR_TSCKP;
953 case SND_SOC_DAIFMT_NB_IF:
954 /* Invert frame clock */
955 strcr ^= CCSR_SSI_STCR_TFSI;
957 case SND_SOC_DAIFMT_IB_IF:
958 /* Invert both clocks */
959 strcr ^= CCSR_SSI_STCR_TSCKP;
960 strcr ^= CCSR_SSI_STCR_TFSI;
966 /* DAI clock master masks */
967 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
968 case SND_SOC_DAIFMT_CBS_CFS:
969 strcr |= CCSR_SSI_STCR_TFDIR | CCSR_SSI_STCR_TXDIR;
970 scr |= CCSR_SSI_SCR_SYS_CLK_EN;
972 case SND_SOC_DAIFMT_CBM_CFM:
973 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
975 case SND_SOC_DAIFMT_CBM_CFS:
976 strcr &= ~CCSR_SSI_STCR_TXDIR;
977 strcr |= CCSR_SSI_STCR_TFDIR;
978 scr &= ~CCSR_SSI_SCR_SYS_CLK_EN;
981 if (!fsl_ssi_is_ac97(ssi_private))
988 if (ssi_private->cpu_dai_drv.symmetric_rates
989 || fsl_ssi_is_ac97(ssi_private)) {
990 /* Need to clear RXDIR when using SYNC or AC97 mode */
991 srcr &= ~CCSR_SSI_SRCR_RXDIR;
992 scr |= CCSR_SSI_SCR_SYN;
995 regmap_write(regs, CCSR_SSI_STCR, stcr);
996 regmap_write(regs, CCSR_SSI_SRCR, srcr);
997 regmap_write(regs, CCSR_SSI_SCR, scr);
1000 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
1001 * use FIFO 1. We program the transmit water to signal a DMA transfer
1002 * if there are only two (or fewer) elements left in the FIFO. Two
1003 * elements equals one frame (left channel, right channel). This value,
1004 * however, depends on the depth of the transmit buffer.
1006 * We set the watermark on the same level as the DMA burstsize. For
1007 * fiq it is probably better to use the biggest possible watermark
1010 if (ssi_private->use_dma)
1011 wm = ssi_private->fifo_depth - 2;
1013 wm = ssi_private->fifo_depth;
1015 regmap_write(regs, CCSR_SSI_SFCSR,
1016 CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
1017 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm));
1019 if (ssi_private->use_dual_fifo) {
1020 regmap_update_bits(regs, CCSR_SSI_SRCR, CCSR_SSI_SRCR_RFEN1,
1021 CCSR_SSI_SRCR_RFEN1);
1022 regmap_update_bits(regs, CCSR_SSI_STCR, CCSR_SSI_STCR_TFEN1,
1023 CCSR_SSI_STCR_TFEN1);
1024 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_TCH_EN,
1025 CCSR_SSI_SCR_TCH_EN);
1028 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_AC97)
1029 fsl_ssi_setup_ac97(ssi_private);
1036 * fsl_ssi_set_dai_fmt - configure Digital Audio Interface Format.
1038 static int fsl_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
1040 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1042 return _fsl_ssi_set_dai_fmt(cpu_dai->dev, ssi_private, fmt);
1046 * fsl_ssi_set_dai_tdm_slot - set TDM slot number
1048 * Note: This function can be only called when using SSI as DAI master
1050 static int fsl_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
1051 u32 rx_mask, int slots, int slot_width)
1053 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
1054 struct regmap *regs = ssi_private->regs;
1057 /* The slot number should be >= 2 if using Network mode or I2S mode */
1058 regmap_read(regs, CCSR_SSI_SCR, &val);
1059 val &= CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_NET;
1060 if (val && slots < 2) {
1061 dev_err(cpu_dai->dev, "slot number should be >= 2 in I2S or NET\n");
1065 regmap_update_bits(regs, CCSR_SSI_STCCR, CCSR_SSI_SxCCR_DC_MASK,
1066 CCSR_SSI_SxCCR_DC(slots));
1067 regmap_update_bits(regs, CCSR_SSI_SRCCR, CCSR_SSI_SxCCR_DC_MASK,
1068 CCSR_SSI_SxCCR_DC(slots));
1070 /* The register SxMSKs needs SSI to provide essential clock due to
1071 * hardware design. So we here temporarily enable SSI to set them.
1073 regmap_read(regs, CCSR_SSI_SCR, &val);
1074 val &= CCSR_SSI_SCR_SSIEN;
1075 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN,
1076 CCSR_SSI_SCR_SSIEN);
1078 regmap_write(regs, CCSR_SSI_STMSK, ~tx_mask);
1079 regmap_write(regs, CCSR_SSI_SRMSK, ~rx_mask);
1081 regmap_update_bits(regs, CCSR_SSI_SCR, CCSR_SSI_SCR_SSIEN, val);
1087 * fsl_ssi_trigger: start and stop the DMA transfer.
1089 * This function is called by ALSA to start, stop, pause, and resume the DMA
1092 * The DMA channel is in external master start and pause mode, which
1093 * means the SSI completely controls the flow of data.
1095 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
1096 struct snd_soc_dai *dai)
1098 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1099 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
1100 struct regmap *regs = ssi_private->regs;
1103 case SNDRV_PCM_TRIGGER_START:
1104 case SNDRV_PCM_TRIGGER_RESUME:
1105 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1107 fsl_ssi_tx_config(ssi_private, true);
1109 fsl_ssi_rx_config(ssi_private, true);
1112 case SNDRV_PCM_TRIGGER_STOP:
1113 case SNDRV_PCM_TRIGGER_SUSPEND:
1114 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1115 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1116 fsl_ssi_tx_config(ssi_private, false);
1118 fsl_ssi_rx_config(ssi_private, false);
1125 if (fsl_ssi_is_ac97(ssi_private)) {
1126 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1127 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_TX_CLR);
1129 regmap_write(regs, CCSR_SSI_SOR, CCSR_SSI_SOR_RX_CLR);
1135 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
1137 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
1139 if (ssi_private->soc->imx && ssi_private->use_dma) {
1140 dai->playback_dma_data = &ssi_private->dma_params_tx;
1141 dai->capture_dma_data = &ssi_private->dma_params_rx;
1147 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
1148 .startup = fsl_ssi_startup,
1149 .shutdown = fsl_ssi_shutdown,
1150 .hw_params = fsl_ssi_hw_params,
1151 .hw_free = fsl_ssi_hw_free,
1152 .set_fmt = fsl_ssi_set_dai_fmt,
1153 .set_sysclk = fsl_ssi_set_dai_sysclk,
1154 .set_tdm_slot = fsl_ssi_set_dai_tdm_slot,
1155 .trigger = fsl_ssi_trigger,
1158 /* Template for the CPU dai driver structure */
1159 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
1160 .probe = fsl_ssi_dai_probe,
1162 .stream_name = "CPU-Playback",
1165 .rates = FSLSSI_I2S_RATES,
1166 .formats = FSLSSI_I2S_FORMATS,
1169 .stream_name = "CPU-Capture",
1172 .rates = FSLSSI_I2S_RATES,
1173 .formats = FSLSSI_I2S_FORMATS,
1175 .ops = &fsl_ssi_dai_ops,
1178 static const struct snd_soc_component_driver fsl_ssi_component = {
1182 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
1183 .bus_control = true,
1184 .probe = fsl_ssi_dai_probe,
1186 .stream_name = "AC97 Playback",
1189 .rates = SNDRV_PCM_RATE_8000_48000,
1190 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1193 .stream_name = "AC97 Capture",
1196 .rates = SNDRV_PCM_RATE_48000,
1197 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1199 .ops = &fsl_ssi_dai_ops,
1203 static struct fsl_ssi_private *fsl_ac97_data;
1205 static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
1208 struct regmap *regs = fsl_ac97_data->regs;
1216 ret = clk_prepare_enable(fsl_ac97_data->clk);
1218 pr_err("ac97 write clk_prepare_enable failed: %d\n",
1224 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1227 regmap_write(regs, CCSR_SSI_SACDAT, lval);
1229 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1233 clk_disable_unprepare(fsl_ac97_data->clk);
1236 static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
1239 struct regmap *regs = fsl_ac97_data->regs;
1241 unsigned short val = -1;
1246 ret = clk_prepare_enable(fsl_ac97_data->clk);
1248 pr_err("ac97 read clk_prepare_enable failed: %d\n",
1253 lreg = (reg & 0x7f) << 12;
1254 regmap_write(regs, CCSR_SSI_SACADD, lreg);
1255 regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK,
1260 regmap_read(regs, CCSR_SSI_SACDAT, ®_val);
1261 val = (reg_val >> 4) & 0xffff;
1263 clk_disable_unprepare(fsl_ac97_data->clk);
1268 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
1269 .read = fsl_ssi_ac97_read,
1270 .write = fsl_ssi_ac97_write,
1274 * Make every character in a string lower-case
1276 static void make_lowercase(char *s)
1282 if ((c >= 'A') && (c <= 'Z'))
1283 *p = c + ('a' - 'A');
1288 static int fsl_ssi_imx_probe(struct platform_device *pdev,
1289 struct fsl_ssi_private *ssi_private, void __iomem *iomem)
1291 struct device_node *np = pdev->dev.of_node;
1295 if (ssi_private->has_ipg_clk_name)
1296 ssi_private->clk = devm_clk_get(&pdev->dev, "ipg");
1298 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
1299 if (IS_ERR(ssi_private->clk)) {
1300 ret = PTR_ERR(ssi_private->clk);
1301 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
1305 if (!ssi_private->has_ipg_clk_name) {
1306 ret = clk_prepare_enable(ssi_private->clk);
1308 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1313 /* For those SLAVE implementations, we ignore non-baudclk cases
1314 * and, instead, abandon MASTER mode that needs baud clock.
1316 ssi_private->baudclk = devm_clk_get(&pdev->dev, "baud");
1317 if (IS_ERR(ssi_private->baudclk))
1318 dev_dbg(&pdev->dev, "could not get baud clock: %ld\n",
1319 PTR_ERR(ssi_private->baudclk));
1322 * We have burstsize be "fifo_depth - 2" to match the SSI
1323 * watermark setting in fsl_ssi_startup().
1325 ssi_private->dma_params_tx.maxburst = ssi_private->fifo_depth - 2;
1326 ssi_private->dma_params_rx.maxburst = ssi_private->fifo_depth - 2;
1327 ssi_private->dma_params_tx.addr = ssi_private->ssi_phys + CCSR_SSI_STX0;
1328 ssi_private->dma_params_rx.addr = ssi_private->ssi_phys + CCSR_SSI_SRX0;
1330 ret = of_property_read_u32_array(np, "dmas", dmas, 4);
1331 if (ssi_private->use_dma && !ret && dmas[2] == IMX_DMATYPE_SSI_DUAL) {
1332 ssi_private->use_dual_fifo = true;
1333 /* When using dual fifo mode, we need to keep watermark
1334 * as even numbers due to dma script limitation.
1336 ssi_private->dma_params_tx.maxburst &= ~0x1;
1337 ssi_private->dma_params_rx.maxburst &= ~0x1;
1340 if (!ssi_private->use_dma) {
1343 * Some boards use an incompatible codec. To get it
1344 * working, we are using imx-fiq-pcm-audio, that
1345 * can handle those codecs. DMA is not possible in this
1349 ssi_private->fiq_params.irq = ssi_private->irq;
1350 ssi_private->fiq_params.base = iomem;
1351 ssi_private->fiq_params.dma_params_rx =
1352 &ssi_private->dma_params_rx;
1353 ssi_private->fiq_params.dma_params_tx =
1354 &ssi_private->dma_params_tx;
1356 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1360 ret = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
1369 if (!ssi_private->has_ipg_clk_name)
1370 clk_disable_unprepare(ssi_private->clk);
1374 static void fsl_ssi_imx_clean(struct platform_device *pdev,
1375 struct fsl_ssi_private *ssi_private)
1377 if (!ssi_private->use_dma)
1378 imx_pcm_fiq_exit(pdev);
1379 if (!ssi_private->has_ipg_clk_name)
1380 clk_disable_unprepare(ssi_private->clk);
1383 static int fsl_ssi_probe(struct platform_device *pdev)
1385 struct fsl_ssi_private *ssi_private;
1387 struct device_node *np = pdev->dev.of_node;
1388 const struct of_device_id *of_id;
1389 const char *p, *sprop;
1390 const uint32_t *iprop;
1391 struct resource *res;
1392 void __iomem *iomem;
1394 struct regmap_config regconfig = fsl_ssi_regconfig;
1396 of_id = of_match_device(fsl_ssi_ids, &pdev->dev);
1397 if (!of_id || !of_id->data)
1400 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private),
1403 dev_err(&pdev->dev, "could not allocate DAI object\n");
1407 ssi_private->soc = of_id->data;
1408 ssi_private->dev = &pdev->dev;
1410 sprop = of_get_property(np, "fsl,mode", NULL);
1412 if (!strcmp(sprop, "ac97-slave"))
1413 ssi_private->dai_fmt = SND_SOC_DAIFMT_AC97;
1416 ssi_private->use_dma = !of_property_read_bool(np,
1417 "fsl,fiq-stream-filter");
1419 if (fsl_ssi_is_ac97(ssi_private)) {
1420 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
1421 sizeof(fsl_ssi_ac97_dai));
1423 fsl_ac97_data = ssi_private;
1425 ret = snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
1427 dev_err(&pdev->dev, "could not set AC'97 ops\n");
1431 /* Initialize this copy of the CPU DAI driver structure */
1432 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
1433 sizeof(fsl_ssi_dai_template));
1435 ssi_private->cpu_dai_drv.name = dev_name(&pdev->dev);
1437 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1438 iomem = devm_ioremap_resource(&pdev->dev, res);
1440 return PTR_ERR(iomem);
1441 ssi_private->ssi_phys = res->start;
1443 if (ssi_private->soc->imx21regs) {
1445 * According to datasheet imx21-class SSI
1446 * don't have SACC{ST,EN,DIS} regs.
1448 regconfig.max_register = CCSR_SSI_SRMSK;
1449 regconfig.num_reg_defaults_raw =
1450 CCSR_SSI_SRMSK / sizeof(uint32_t) + 1;
1453 ret = of_property_match_string(np, "clock-names", "ipg");
1455 ssi_private->has_ipg_clk_name = false;
1456 ssi_private->regs = devm_regmap_init_mmio(&pdev->dev, iomem,
1459 ssi_private->has_ipg_clk_name = true;
1460 ssi_private->regs = devm_regmap_init_mmio_clk(&pdev->dev,
1461 "ipg", iomem, ®config);
1463 if (IS_ERR(ssi_private->regs)) {
1464 dev_err(&pdev->dev, "Failed to init register map\n");
1465 return PTR_ERR(ssi_private->regs);
1468 ssi_private->irq = platform_get_irq(pdev, 0);
1469 if (ssi_private->irq < 0) {
1470 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
1471 return ssi_private->irq;
1474 /* Are the RX and the TX clocks locked? */
1475 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL)) {
1476 if (!fsl_ssi_is_ac97(ssi_private))
1477 ssi_private->cpu_dai_drv.symmetric_rates = 1;
1479 ssi_private->cpu_dai_drv.symmetric_channels = 1;
1480 ssi_private->cpu_dai_drv.symmetric_samplebits = 1;
1483 /* Determine the FIFO depth. */
1484 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
1486 ssi_private->fifo_depth = be32_to_cpup(iprop);
1488 /* Older 8610 DTs didn't have the fifo-depth property */
1489 ssi_private->fifo_depth = 8;
1491 dev_set_drvdata(&pdev->dev, ssi_private);
1493 if (ssi_private->soc->imx) {
1494 ret = fsl_ssi_imx_probe(pdev, ssi_private, iomem);
1499 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1500 &ssi_private->cpu_dai_drv, 1);
1502 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1503 goto error_asoc_register;
1506 if (ssi_private->use_dma) {
1507 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
1508 fsl_ssi_isr, 0, dev_name(&pdev->dev),
1511 dev_err(&pdev->dev, "could not claim irq %u\n",
1513 goto error_asoc_register;
1517 ret = fsl_ssi_debugfs_create(&ssi_private->dbg_stats, &pdev->dev);
1519 goto error_asoc_register;
1522 * If codec-handle property is missing from SSI node, we assume
1523 * that the machine driver uses new binding which does not require
1524 * SSI driver to trigger machine driver's probe.
1526 if (!of_get_property(np, "codec-handle", NULL))
1529 /* Trigger the machine driver's probe function. The platform driver
1530 * name of the machine driver is taken from /compatible property of the
1531 * device tree. We also pass the address of the CPU DAI driver
1534 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1535 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1536 p = strrchr(sprop, ',');
1539 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1540 make_lowercase(name);
1543 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1544 if (IS_ERR(ssi_private->pdev)) {
1545 ret = PTR_ERR(ssi_private->pdev);
1546 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1547 goto error_sound_card;
1551 if (ssi_private->dai_fmt)
1552 _fsl_ssi_set_dai_fmt(&pdev->dev, ssi_private,
1553 ssi_private->dai_fmt);
1555 if (fsl_ssi_is_ac97(ssi_private)) {
1558 ret = of_property_read_u32(np, "cell-index", &ssi_idx);
1560 dev_err(&pdev->dev, "cannot get SSI index property\n");
1561 goto error_sound_card;
1565 platform_device_register_data(NULL,
1566 "ac97-codec", ssi_idx, NULL, 0);
1567 if (IS_ERR(ssi_private->pdev)) {
1568 ret = PTR_ERR(ssi_private->pdev);
1570 "failed to register AC97 codec platform: %d\n",
1572 goto error_sound_card;
1579 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1581 error_asoc_register:
1582 if (ssi_private->soc->imx)
1583 fsl_ssi_imx_clean(pdev, ssi_private);
1588 static int fsl_ssi_remove(struct platform_device *pdev)
1590 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1592 fsl_ssi_debugfs_remove(&ssi_private->dbg_stats);
1594 if (ssi_private->pdev)
1595 platform_device_unregister(ssi_private->pdev);
1597 if (ssi_private->soc->imx)
1598 fsl_ssi_imx_clean(pdev, ssi_private);
1600 if (fsl_ssi_is_ac97(ssi_private))
1601 snd_soc_set_ac97_ops(NULL);
1606 #ifdef CONFIG_PM_SLEEP
1607 static int fsl_ssi_suspend(struct device *dev)
1609 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1610 struct regmap *regs = ssi_private->regs;
1612 regmap_read(regs, CCSR_SSI_SFCSR,
1613 &ssi_private->regcache_sfcsr);
1614 regmap_read(regs, CCSR_SSI_SACNT,
1615 &ssi_private->regcache_sacnt);
1617 regcache_cache_only(regs, true);
1618 regcache_mark_dirty(regs);
1623 static int fsl_ssi_resume(struct device *dev)
1625 struct fsl_ssi_private *ssi_private = dev_get_drvdata(dev);
1626 struct regmap *regs = ssi_private->regs;
1628 regcache_cache_only(regs, false);
1630 regmap_update_bits(regs, CCSR_SSI_SFCSR,
1631 CCSR_SSI_SFCSR_RFWM1_MASK | CCSR_SSI_SFCSR_TFWM1_MASK |
1632 CCSR_SSI_SFCSR_RFWM0_MASK | CCSR_SSI_SFCSR_TFWM0_MASK,
1633 ssi_private->regcache_sfcsr);
1634 regmap_write(regs, CCSR_SSI_SACNT,
1635 ssi_private->regcache_sacnt);
1637 return regcache_sync(regs);
1639 #endif /* CONFIG_PM_SLEEP */
1641 static const struct dev_pm_ops fsl_ssi_pm = {
1642 SET_SYSTEM_SLEEP_PM_OPS(fsl_ssi_suspend, fsl_ssi_resume)
1645 static struct platform_driver fsl_ssi_driver = {
1647 .name = "fsl-ssi-dai",
1648 .of_match_table = fsl_ssi_ids,
1651 .probe = fsl_ssi_probe,
1652 .remove = fsl_ssi_remove,
1655 module_platform_driver(fsl_ssi_driver);
1657 MODULE_ALIAS("platform:fsl-ssi-dai");
1658 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1659 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1660 MODULE_LICENSE("GPL v2");