2 * Intel SST Haswell/Broadwell IPC Support
4 * Copyright (C) 2013, Intel Corporation. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License version
8 * 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __SST_HASWELL_IPC_H
18 #define __SST_HASWELL_IPC_H
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/platform_device.h>
23 #include <sound/asound.h>
25 #define SST_HSW_NO_CHANNELS 4
26 #define SST_HSW_MAX_DX_REGIONS 14
27 #define SST_HSW_DX_CONTEXT_SIZE (640 * 1024)
28 #define SST_HSW_CHANNELS_ALL 0xffffffff
30 #define SST_HSW_FW_LOG_CONFIG_DWORDS 12
31 #define SST_HSW_GLOBAL_LOG 15
34 * Upfront defined maximum message size that is
35 * expected by the in/out communication pipes in FW.
37 #define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400
38 #define SST_HSW_MAX_INFO_SIZE 64
39 #define SST_HSW_BUILD_HASH_LENGTH 40
42 struct sst_hsw_stream;
43 struct sst_hsw_log_stream;
46 struct sst_module_runtime;
47 extern struct sst_ops haswell_ops;
49 /* Stream Allocate Path ID */
50 enum sst_hsw_stream_path_id {
51 SST_HSW_STREAM_PATH_SSP0_OUT = 0,
52 SST_HSW_STREAM_PATH_SSP0_IN = 1,
53 SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
56 /* Stream Allocate Stream Type */
57 enum sst_hsw_stream_type {
58 SST_HSW_STREAM_TYPE_RENDER = 0,
59 SST_HSW_STREAM_TYPE_SYSTEM = 1,
60 SST_HSW_STREAM_TYPE_CAPTURE = 2,
61 SST_HSW_STREAM_TYPE_LOOPBACK = 3,
62 SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
65 /* Stream Allocate Stream Format */
66 enum sst_hsw_stream_format {
67 SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
68 SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
69 SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
70 SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
74 enum sst_hsw_device_id {
75 SST_HSW_DEVICE_SSP_0 = 0,
76 SST_HSW_DEVICE_SSP_1 = 1,
79 /* Device Master Clock Frequency */
80 enum sst_hsw_device_mclk {
81 SST_HSW_DEVICE_MCLK_OFF = 0,
82 SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1,
83 SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
84 SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
87 /* Device Clock Master */
88 enum sst_hsw_device_mode {
89 SST_HSW_DEVICE_CLOCK_SLAVE = 0,
90 SST_HSW_DEVICE_CLOCK_MASTER = 1,
91 SST_HSW_DEVICE_TDM_CLOCK_MASTER = 2,
95 enum sst_hsw_dx_state {
96 SST_HSW_DX_STATE_D0 = 0,
97 SST_HSW_DX_STATE_D1 = 1,
98 SST_HSW_DX_STATE_D3 = 3,
99 SST_HSW_DX_STATE_MAX = 3,
102 /* Audio stream stage IDs */
103 enum sst_hsw_fx_stage_id {
104 SST_HSW_STAGE_ID_WAVES = 0,
105 SST_HSW_STAGE_ID_DTS = 1,
106 SST_HSW_STAGE_ID_DOLBY = 2,
107 SST_HSW_STAGE_ID_BOOST = 3,
108 SST_HSW_STAGE_ID_MAX_FX_ID
112 enum sst_hsw_dx_type {
113 SST_HSW_DX_TYPE_FW_IMAGE = 0,
114 SST_HSW_DX_TYPE_MEMORY_DUMP = 1
117 /* Volume Curve Type*/
118 enum sst_hsw_volume_curve {
119 SST_HSW_VOLUME_CURVE_NONE = 0,
120 SST_HSW_VOLUME_CURVE_FADE = 1
123 /* Sample ordering */
124 enum sst_hsw_interleaving {
125 SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
126 SST_HSW_INTERLEAVING_PER_SAMPLE = 1,
129 /* Channel indices */
130 enum sst_hsw_channel_index {
131 SST_HSW_CHANNEL_LEFT = 0,
132 SST_HSW_CHANNEL_CENTER = 1,
133 SST_HSW_CHANNEL_RIGHT = 2,
134 SST_HSW_CHANNEL_LEFT_SURROUND = 3,
135 SST_HSW_CHANNEL_CENTER_SURROUND = 3,
136 SST_HSW_CHANNEL_RIGHT_SURROUND = 4,
137 SST_HSW_CHANNEL_LFE = 7,
138 SST_HSW_CHANNEL_INVALID = 0xF,
141 /* List of supported channel maps. */
142 enum sst_hsw_channel_config {
143 SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */
144 SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */
145 SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
146 SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
147 SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
148 SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */
149 SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
150 SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
151 SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
152 SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
153 SST_HSW_CHANNEL_CONFIG_INVALID,
156 /* List of supported bit depths. */
157 enum sst_hsw_bitdepth {
158 SST_HSW_DEPTH_8BIT = 8,
159 SST_HSW_DEPTH_16BIT = 16,
160 SST_HSW_DEPTH_24BIT = 24, /* Default. */
161 SST_HSW_DEPTH_32BIT = 32,
162 SST_HSW_DEPTH_INVALID = 33,
165 enum sst_hsw_module_id {
166 SST_HSW_MODULE_BASE_FW = 0x0,
167 SST_HSW_MODULE_MP3 = 0x1,
168 SST_HSW_MODULE_AAC_5_1 = 0x2,
169 SST_HSW_MODULE_AAC_2_0 = 0x3,
170 SST_HSW_MODULE_SRC = 0x4,
171 SST_HSW_MODULE_WAVES = 0x5,
172 SST_HSW_MODULE_DOLBY = 0x6,
173 SST_HSW_MODULE_BOOST = 0x7,
174 SST_HSW_MODULE_LPAL = 0x8,
175 SST_HSW_MODULE_DTS = 0x9,
176 SST_HSW_MODULE_PCM_CAPTURE = 0xA,
177 SST_HSW_MODULE_PCM_SYSTEM = 0xB,
178 SST_HSW_MODULE_PCM_REFERENCE = 0xC,
179 SST_HSW_MODULE_PCM = 0xD,
180 SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
181 SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
182 SST_HSW_MAX_MODULE_ID,
185 enum sst_hsw_performance_action {
186 SST_HSW_PERF_START = 0,
187 SST_HSW_PERF_STOP = 1,
190 /* SST firmware module info */
191 struct sst_hsw_module_info {
192 u8 name[SST_HSW_MAX_INFO_SIZE];
193 u8 version[SST_HSW_MAX_INFO_SIZE];
194 } __attribute__((packed));
196 /* Module entry point */
197 struct sst_hsw_module_entry {
198 enum sst_hsw_module_id module_id;
200 } __attribute__((packed));
202 /* Module map - alignement matches DSP */
203 struct sst_hsw_module_map {
204 u8 module_entries_count;
205 struct sst_hsw_module_entry module_entries[1];
206 } __attribute__((packed));
208 struct sst_hsw_memory_info {
211 } __attribute__((packed));
213 struct sst_hsw_fx_enable {
214 struct sst_hsw_module_map module_map;
215 struct sst_hsw_memory_info persistent_mem;
216 } __attribute__((packed));
218 struct sst_hsw_get_fx_param {
221 } __attribute__((packed));
223 struct sst_hsw_perf_action {
225 } __attribute__((packed));
227 struct sst_hsw_perf_data {
231 } __attribute__((packed));
234 struct sst_hsw_ipc_fw_version {
239 u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
240 u32 fw_log_providers_hash;
241 } __attribute__((packed));
243 /* Stream ring info */
244 struct sst_hsw_ipc_stream_ring {
250 } __attribute__((packed));
252 /* Debug Dump Log Enable Request */
253 struct sst_hsw_ipc_debug_log_enable_req {
254 struct sst_hsw_ipc_stream_ring ringinfo;
255 u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
256 } __attribute__((packed));
258 /* Debug Dump Log Reply */
259 struct sst_hsw_ipc_debug_log_reply {
260 u32 log_buffer_begining;
262 } __attribute__((packed));
264 /* Stream glitch position */
265 struct sst_hsw_ipc_stream_glitch_position {
269 } __attribute__((packed));
271 /* Stream get position */
272 struct sst_hsw_ipc_stream_get_position {
275 } __attribute__((packed));
277 /* Stream set position */
278 struct sst_hsw_ipc_stream_set_position {
281 } __attribute__((packed));
283 /* Stream Free Request */
284 struct sst_hsw_ipc_stream_free_req {
287 } __attribute__((packed));
289 /* Set Volume Request */
290 struct sst_hsw_ipc_volume_req {
295 } __attribute__((packed));
297 /* Device Configuration Request */
298 struct sst_hsw_ipc_device_config_req {
305 } __attribute__((packed));
307 /* Audio Data formats */
308 struct sst_hsw_audio_data_format_ipc {
317 } __attribute__((packed));
319 /* Stream Allocate Request */
320 struct sst_hsw_ipc_stream_alloc_req {
325 struct sst_hsw_audio_data_format_ipc format;
326 struct sst_hsw_ipc_stream_ring ringinfo;
327 struct sst_hsw_module_map map;
328 struct sst_hsw_memory_info persistent_mem;
329 struct sst_hsw_memory_info scratch_mem;
330 u32 number_of_notifications;
331 } __attribute__((packed));
333 /* Stream Allocate Reply */
334 struct sst_hsw_ipc_stream_alloc_reply {
336 u32 mixer_hw_id; // returns rate ????
337 u32 read_position_register_address;
338 u32 presentation_position_register_address;
339 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
340 u32 volume_register_address[SST_HSW_NO_CHANNELS];
341 } __attribute__((packed));
343 /* Get Mixer Stream Info */
344 struct sst_hsw_ipc_stream_info_reply {
346 u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
347 u32 volume_register_address[SST_HSW_NO_CHANNELS];
348 } __attribute__((packed));
350 /* DX State Request */
351 struct sst_hsw_ipc_dx_req {
354 } __attribute__((packed));
356 /* DX State Reply Memory Info Item */
357 struct sst_hsw_ipc_dx_memory_item {
361 } __attribute__((packed));
364 struct sst_hsw_ipc_dx_reply {
366 struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
367 } __attribute__((packed));
369 struct sst_hsw_ipc_fw_version;
371 /* SST Init & Free */
372 struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
374 void sst_hsw_free(struct sst_hsw *hsw);
375 int sst_hsw_fw_get_version(struct sst_hsw *hsw,
376 struct sst_hsw_ipc_fw_version *version);
377 u32 create_channel_map(enum sst_hsw_channel_config config);
379 /* Stream Mixer Controls - */
380 int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
381 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
382 int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
383 struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
385 /* Global Mixer Controls - */
386 int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
388 int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
392 struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
393 u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
396 int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
398 /* Stream Configuration */
399 int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
400 enum sst_hsw_stream_path_id path_id,
401 enum sst_hsw_stream_type stream_type,
402 enum sst_hsw_stream_format format_id);
404 int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
405 u32 ring_pt_address, u32 num_pages,
406 u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
408 int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
410 int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
412 int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
414 int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
415 enum sst_hsw_bitdepth bits);
416 int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
417 struct sst_hsw_stream *stream, int channels);
418 int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
419 struct sst_hsw_stream *stream, u32 map,
420 enum sst_hsw_channel_config config);
421 int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
422 enum sst_hsw_interleaving style);
423 int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
424 struct sst_hsw_stream *stream, struct sst_module_runtime *runtime);
425 int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
426 struct sst_hsw_stream *stream, u32 offset, u32 size);
427 int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
428 struct sst_hsw_stream *stream, u32 offset, u32 size);
429 snd_pcm_uframes_t sst_hsw_stream_get_old_position(struct sst_hsw *hsw,
430 struct sst_hsw_stream *stream);
431 void sst_hsw_stream_set_old_position(struct sst_hsw *hsw,
432 struct sst_hsw_stream *stream, snd_pcm_uframes_t val);
433 bool sst_hsw_stream_get_silence_start(struct sst_hsw *hsw,
434 struct sst_hsw_stream *stream);
435 void sst_hsw_stream_set_silence_start(struct sst_hsw *hsw,
436 struct sst_hsw_stream *stream, bool val);
437 int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
439 /* Stream ALSA trigger operations */
440 int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
442 int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
444 int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
446 /* Stream pointer positions */
447 int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
448 struct sst_hsw_stream *stream, u32 *position);
449 int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
450 struct sst_hsw_stream *stream, u32 *position);
451 u32 sst_hsw_get_dsp_position(struct sst_hsw *hsw,
452 struct sst_hsw_stream *stream);
453 u64 sst_hsw_get_dsp_presentation_position(struct sst_hsw *hsw,
454 struct sst_hsw_stream *stream);
457 int sst_hsw_device_set_config(struct sst_hsw *hsw,
458 enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
459 enum sst_hsw_device_mode mode, u32 clock_divider);
462 int sst_hsw_dx_set_state(struct sst_hsw *hsw,
463 enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
466 int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
467 void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
468 struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
470 /* runtime module management */
471 struct sst_module_runtime *sst_hsw_runtime_module_create(struct sst_hsw *hsw,
472 int mod_id, int offset);
473 void sst_hsw_runtime_module_free(struct sst_module_runtime *runtime);
476 int sst_hsw_dsp_runtime_resume(struct sst_hsw *hsw);
477 int sst_hsw_dsp_runtime_suspend(struct sst_hsw *hsw);
478 int sst_hsw_dsp_load(struct sst_hsw *hsw);
479 int sst_hsw_dsp_runtime_sleep(struct sst_hsw *hsw);