sound/soc/jz4740/jz4740-i2s.c

   1 /*
   2  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
   3  *
   4  *  This program is free software; you can redistribute it and/or modify it
   5  *  under  the terms of the GNU General  Public License as published by the
   6  *  Free Software Foundation;  either version 2 of the License, or (at your
   7  *  option) any later version.
   8  *
   9  *  You should have received a copy of the GNU General Public License along
  10  *  with this program; if not, write to the Free Software Foundation, Inc.,
  11  *  675 Mass Ave, Cambridge, MA 02139, USA.
  12  *
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/clk.h>
  25 #include <linux/delay.h>
  26
  27 #include <linux/dma-mapping.h>
  28
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/soc.h>
  33 #include <sound/initval.h>
  34 #include <sound/dmaengine_pcm.h>
  35
  36 #include "jz4740-i2s.h"
  37
  38 #define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
  39 #define JZ4740_DMA_TYPE_AIC_RECEIVE 25
  40
  41 #define JZ_REG_AIC_CONF         0x00
  42 #define JZ_REG_AIC_CTRL         0x04
  43 #define JZ_REG_AIC_I2S_FMT      0x10
  44 #define JZ_REG_AIC_FIFO_STATUS  0x14
  45 #define JZ_REG_AIC_I2S_STATUS   0x1c
  46 #define JZ_REG_AIC_CLK_DIV      0x30
  47 #define JZ_REG_AIC_FIFO         0x34
  48
  49 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
  50 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf <<  8)
  51 #define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
  52 #define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
  53 #define JZ_AIC_CONF_I2S BIT(4)
  54 #define JZ_AIC_CONF_RESET BIT(3)
  55 #define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
  56 #define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
  57 #define JZ_AIC_CONF_ENABLE BIT(0)
  58
  59 #define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
  60 #define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
  61
  62 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
  63 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
  64 #define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
  65 #define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
  66 #define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
  67 #define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
  68 #define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
  69 #define JZ_AIC_CTRL_FLUSH               BIT(8)
  70 #define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
  71 #define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
  72 #define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
  73 #define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
  74 #define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
  75 #define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
  76 #define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
  77
  78 #define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
  79 #define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET  16
  80
  81 #define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
  82 #define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
  83 #define JZ_AIC_I2S_FMT_MSB BIT(0)
  84
  85 #define JZ_AIC_I2S_STATUS_BUSY BIT(2)
  86
  87 #define JZ_AIC_CLK_DIV_MASK 0xf
  88 #define I2SDIV_DV_SHIFT 8
  89 #define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
  90
  91 struct jz4740_i2s {
  92         struct resource *mem;
  93         void __iomem *base;
  94         dma_addr_t phys_base;
  95
  96         struct clk *clk_aic;
  97         struct clk *clk_i2s;
  98
  99         struct snd_dmaengine_dai_dma_data playback_dma_data;
 100         struct snd_dmaengine_dai_dma_data capture_dma_data;
 101 };
 102
 103 static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
 104         unsigned int reg)
 105 {
 106         return readl(i2s->base + reg);
 107 }
 108
 109 static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
 110         unsigned int reg, uint32_t value)
 111 {
 112         writel(value, i2s->base + reg);
 113 }
 114
 115 static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
 116         struct snd_soc_dai *dai)
 117 {
 118         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 119         uint32_t conf, ctrl;
 120
 121         if (dai->active)
 122                 return 0;
 123
 124         ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 125         ctrl |= JZ_AIC_CTRL_FLUSH;
 126         jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 127
 128         clk_prepare_enable(i2s->clk_i2s);
 129
 130         conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 131         conf |= JZ_AIC_CONF_ENABLE;
 132         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 133
 134         return 0;
 135 }
 136
 137 static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
 138         struct snd_soc_dai *dai)
 139 {
 140         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 141         uint32_t conf;
 142
 143         if (dai->active)
 144                 return;
 145
 146         conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 147         conf &= ~JZ_AIC_CONF_ENABLE;
 148         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 149
 150         clk_disable_unprepare(i2s->clk_i2s);
 151 }
 152
 153 static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 154         struct snd_soc_dai *dai)
 155 {
 156         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 157
 158         uint32_t ctrl;
 159         uint32_t mask;
 160
 161         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 162                 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
 163         else
 164                 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
 165
 166         ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 167
 168         switch (cmd) {
 169         case SNDRV_PCM_TRIGGER_START:
 170         case SNDRV_PCM_TRIGGER_RESUME:
 171         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 172                 ctrl |= mask;
 173                 break;
 174         case SNDRV_PCM_TRIGGER_STOP:
 175         case SNDRV_PCM_TRIGGER_SUSPEND:
 176         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 177                 ctrl &= ~mask;
 178                 break;
 179         default:
 180                 return -EINVAL;
 181         }
 182
 183         jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 184
 185         return 0;
 186 }
 187
 188 static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 189 {
 190         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 191
 192         uint32_t format = 0;
 193         uint32_t conf;
 194
 195         conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 196
 197         conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
 198
 199         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 200         case SND_SOC_DAIFMT_CBS_CFS:
 201                 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
 202                 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
 203                 break;
 204         case SND_SOC_DAIFMT_CBM_CFS:
 205                 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
 206                 break;
 207         case SND_SOC_DAIFMT_CBS_CFM:
 208                 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
 209                 break;
 210         case SND_SOC_DAIFMT_CBM_CFM:
 211                 break;
 212         default:
 213                 return -EINVAL;
 214         }
 215
 216         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 217         case SND_SOC_DAIFMT_MSB:
 218                 format |= JZ_AIC_I2S_FMT_MSB;
 219                 break;
 220         case SND_SOC_DAIFMT_I2S:
 221                 break;
 222         default:
 223                 return -EINVAL;
 224         }
 225
 226         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 227         case SND_SOC_DAIFMT_NB_NF:
 228                 break;
 229         default:
 230                 return -EINVAL;
 231         }
 232
 233         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 234         jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
 235
 236         return 0;
 237 }
 238
 239 static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
 240         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 241 {
 242         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 243         unsigned int sample_size;
 244         uint32_t ctrl, div_reg;
 245         int div;
 246
 247         ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
 248
 249         div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
 250         div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
 251
 252         switch (params_format(params)) {
 253         case SNDRV_PCM_FORMAT_S8:
 254                 sample_size = 0;
 255                 break;
 256         case SNDRV_PCM_FORMAT_S16:
 257                 sample_size = 1;
 258                 break;
 259         default:
 260                 return -EINVAL;
 261         }
 262
 263         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 264                 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
 265                 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
 266                 if (params_channels(params) == 1)
 267                         ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
 268                 else
 269                         ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
 270         } else {
 271                 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
 272                 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
 273         }
 274
 275         div_reg &= ~I2SDIV_DV_MASK;
 276         div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
 277         jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
 278         jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
 279
 280         return 0;
 281 }
 282
 283 static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 284         unsigned int freq, int dir)
 285 {
 286         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 287         struct clk *parent;
 288         int ret = 0;
 289
 290         switch (clk_id) {
 291         case JZ4740_I2S_CLKSRC_EXT:
 292                 parent = clk_get(NULL, "ext");
 293                 clk_set_parent(i2s->clk_i2s, parent);
 294                 break;
 295         case JZ4740_I2S_CLKSRC_PLL:
 296                 parent = clk_get(NULL, "pll half");
 297                 clk_set_parent(i2s->clk_i2s, parent);
 298                 ret = clk_set_rate(i2s->clk_i2s, freq);
 299                 break;
 300         default:
 301                 return -EINVAL;
 302         }
 303         clk_put(parent);
 304
 305         return ret;
 306 }
 307
 308 static int jz4740_i2s_suspend(struct snd_soc_dai *dai)
 309 {
 310         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 311         uint32_t conf;
 312
 313         if (dai->active) {
 314                 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 315                 conf &= ~JZ_AIC_CONF_ENABLE;
 316                 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 317
 318                 clk_disable_unprepare(i2s->clk_i2s);
 319         }
 320
 321         clk_disable_unprepare(i2s->clk_aic);
 322
 323         return 0;
 324 }
 325
 326 static int jz4740_i2s_resume(struct snd_soc_dai *dai)
 327 {
 328         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 329         uint32_t conf;
 330
 331         clk_prepare_enable(i2s->clk_aic);
 332
 333         if (dai->active) {
 334                 clk_prepare_enable(i2s->clk_i2s);
 335
 336                 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
 337                 conf |= JZ_AIC_CONF_ENABLE;
 338                 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 339         }
 340
 341         return 0;
 342 }
 343
 344 static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
 345 {
 346         struct snd_dmaengine_dai_dma_data *dma_data;
 347
 348         /* Playback */
 349         dma_data = &i2s->playback_dma_data;
 350         dma_data->maxburst = 16;
 351         dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
 352         dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
 353
 354         /* Capture */
 355         dma_data = &i2s->capture_dma_data;
 356         dma_data->maxburst = 16;
 357         dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
 358         dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
 359 }
 360
 361 static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
 362 {
 363         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 364         uint32_t conf;
 365
 366         clk_prepare_enable(i2s->clk_aic);
 367
 368         jz4740_i2c_init_pcm_config(i2s);
 369         snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
 370                 &i2s->capture_dma_data);
 371
 372         conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
 373                 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
 374                 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
 375                 JZ_AIC_CONF_I2S |
 376                 JZ_AIC_CONF_INTERNAL_CODEC;
 377
 378         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
 379         jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
 380
 381         return 0;
 382 }
 383
 384 static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
 385 {
 386         struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 387
 388         clk_disable_unprepare(i2s->clk_aic);
 389         return 0;
 390 }
 391
 392 static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
 393         .startup = jz4740_i2s_startup,
 394         .shutdown = jz4740_i2s_shutdown,
 395         .trigger = jz4740_i2s_trigger,
 396         .hw_params = jz4740_i2s_hw_params,
 397         .set_fmt = jz4740_i2s_set_fmt,
 398         .set_sysclk = jz4740_i2s_set_sysclk,
 399 };
 400
 401 #define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
 402                 SNDRV_PCM_FMTBIT_S16_LE)
 403
 404 static struct snd_soc_dai_driver jz4740_i2s_dai = {
 405         .probe = jz4740_i2s_dai_probe,
 406         .remove = jz4740_i2s_dai_remove,
 407         .playback = {
 408                 .channels_min = 1,
 409                 .channels_max = 2,
 410                 .rates = SNDRV_PCM_RATE_8000_48000,
 411                 .formats = JZ4740_I2S_FMTS,
 412         },
 413         .capture = {
 414                 .channels_min = 2,
 415                 .channels_max = 2,
 416                 .rates = SNDRV_PCM_RATE_8000_48000,
 417                 .formats = JZ4740_I2S_FMTS,
 418         },
 419         .symmetric_rates = 1,
 420         .ops = &jz4740_i2s_dai_ops,
 421         .suspend = jz4740_i2s_suspend,
 422         .resume = jz4740_i2s_resume,
 423 };
 424
 425 static const struct snd_soc_component_driver jz4740_i2s_component = {
 426         .name           = "jz4740-i2s",
 427 };
 428
 429 #ifdef CONFIG_OF
 430 static const struct of_device_id jz4740_of_matches[] = {
 431         { .compatible = "ingenic,jz4740-i2s" },
 432         { /* sentinel */ }
 433 };
 434 #endif
 435
 436 static int jz4740_i2s_dev_probe(struct platform_device *pdev)
 437 {
 438         struct jz4740_i2s *i2s;
 439         struct resource *mem;
 440         int ret;
 441
 442         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
 443         if (!i2s)
 444                 return -ENOMEM;
 445
 446         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 447         i2s->base = devm_ioremap_resource(&pdev->dev, mem);
 448         if (IS_ERR(i2s->base))
 449                 return PTR_ERR(i2s->base);
 450
 451         i2s->phys_base = mem->start;
 452
 453         i2s->clk_aic = devm_clk_get(&pdev->dev, "aic");
 454         if (IS_ERR(i2s->clk_aic))
 455                 return PTR_ERR(i2s->clk_aic);
 456
 457         i2s->clk_i2s = devm_clk_get(&pdev->dev, "i2s");
 458         if (IS_ERR(i2s->clk_i2s))
 459                 return PTR_ERR(i2s->clk_i2s);
 460
 461         platform_set_drvdata(pdev, i2s);
 462
 463         ret = devm_snd_soc_register_component(&pdev->dev,
 464                 &jz4740_i2s_component, &jz4740_i2s_dai, 1);
 465         if (ret)
 466                 return ret;
 467
 468         return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
 469                 SND_DMAENGINE_PCM_FLAG_COMPAT);
 470 }
 471
 472 static struct platform_driver jz4740_i2s_driver = {
 473         .probe = jz4740_i2s_dev_probe,
 474         .driver = {
 475                 .name = "jz4740-i2s",
 476                 .of_match_table = of_match_ptr(jz4740_of_matches)
 477         },
 478 };
 479
 480 module_platform_driver(jz4740_i2s_driver);
 481
 482 MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
 483 MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
 484 MODULE_LICENSE("GPL");
 485 MODULE_ALIAS("platform:jz4740-i2s");