sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@nokia.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <sound/core.h>
  29 #include <sound/pcm.h>
  30 #include <sound/pcm_params.h>
  31 #include <sound/initval.h>
  32 #include <sound/soc.h>
  33
  34 #include <mach/control.h>
  35 #include <mach/dma.h>
  36 #include <mach/mcbsp.h>
  37 #include "omap-mcbsp.h"
  38 #include "omap-pcm.h"
  39
  40 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  41
  42 struct omap_mcbsp_data {
  43         unsigned int                    bus_id;
  44         struct omap_mcbsp_reg_cfg       regs;
  45         unsigned int                    fmt;
  46         /*
  47          * Flags indicating is the bus already activated and configured by
  48          * another substream
  49          */
  50         int                             active;
  51         int                             configured;
  52 };
  53
  54 #define to_mcbsp(priv)  container_of((priv), struct omap_mcbsp_data, bus_id)
  55
  56 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
  57
  58 /*
  59  * Stream DMA parameters. DMA request line and port address are set runtime
  60  * since they are different between OMAP1 and later OMAPs
  61  */
  62 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
  63
  64 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
  65 static const int omap1_dma_reqs[][2] = {
  66         { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
  67         { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
  68         { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
  69 };
  70 static const unsigned long omap1_mcbsp_port[][2] = {
  71         { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
  72           OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
  73         { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
  74           OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
  75         { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
  76           OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
  77 };
  78 #else
  79 static const int omap1_dma_reqs[][2] = {};
  80 static const unsigned long omap1_mcbsp_port[][2] = {};
  81 #endif
  82
  83 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  84 static const int omap24xx_dma_reqs[][2] = {
  85         { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
  86         { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
  87 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
  88         { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
  89         { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
  90         { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
  91 #endif
  92 };
  93 #else
  94 static const int omap24xx_dma_reqs[][2] = {};
  95 #endif
  96
  97 #if defined(CONFIG_ARCH_OMAP2420)
  98 static const unsigned long omap2420_mcbsp_port[][2] = {
  99         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
 100           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
 101         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
 102           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
 103 };
 104 #else
 105 static const unsigned long omap2420_mcbsp_port[][2] = {};
 106 #endif
 107
 108 #if defined(CONFIG_ARCH_OMAP2430)
 109 static const unsigned long omap2430_mcbsp_port[][2] = {
 110         { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 111           OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 112         { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 113           OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 114         { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 115           OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 116         { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 117           OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 118         { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 119           OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 120 };
 121 #else
 122 static const unsigned long omap2430_mcbsp_port[][2] = {};
 123 #endif
 124
 125 #if defined(CONFIG_ARCH_OMAP34XX)
 126 static const unsigned long omap34xx_mcbsp_port[][2] = {
 127         { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
 128           OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
 129         { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
 130           OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
 131         { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
 132           OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
 133         { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
 134           OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
 135         { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
 136           OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
 137 };
 138 #else
 139 static const unsigned long omap34xx_mcbsp_port[][2] = {};
 140 #endif
 141
 142 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
 143 {
 144         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 145         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 146         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 147         int samples = snd_pcm_lib_period_bytes(substream) >> 1;
 148
 149         /* Configure McBSP internal buffer usage */
 150         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 151                 omap_mcbsp_set_tx_threshold(mcbsp_data->bus_id, samples - 1);
 152         else
 153                 omap_mcbsp_set_rx_threshold(mcbsp_data->bus_id, samples - 1);
 154 }
 155
 156 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 157                                   struct snd_soc_dai *dai)
 158 {
 159         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 160         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 161         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 162         int bus_id = mcbsp_data->bus_id;
 163         int err = 0;
 164
 165         if (!cpu_dai->active)
 166                 err = omap_mcbsp_request(bus_id);
 167
 168         if (cpu_is_omap343x()) {
 169                 int max_period;
 170
 171                 /*
 172                  * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
 173                  * Set constraint for minimum buffer size to the same than FIFO
 174                  * size in order to avoid underruns in playback startup because
 175                  * HW is keeping the DMA request active until FIFO is filled.
 176                  */
 177                 if (bus_id == 1)
 178                         snd_pcm_hw_constraint_minmax(substream->runtime,
 179                                         SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
 180                                         4096, UINT_MAX);
 181
 182                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 183                         max_period = omap_mcbsp_get_max_tx_threshold(bus_id);
 184                 else
 185                         max_period = omap_mcbsp_get_max_rx_threshold(bus_id);
 186
 187                 max_period++;
 188                 max_period <<= 1;
 189
 190                 snd_pcm_hw_constraint_minmax(substream->runtime,
 191                                                 SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 192                                                 32, max_period);
 193         }
 194
 195         return err;
 196 }
 197
 198 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 199                                     struct snd_soc_dai *dai)
 200 {
 201         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 202         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 203         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 204
 205         if (!cpu_dai->active) {
 206                 omap_mcbsp_free(mcbsp_data->bus_id);
 207                 mcbsp_data->configured = 0;
 208         }
 209 }
 210
 211 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 212                                   struct snd_soc_dai *dai)
 213 {
 214         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 215         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 216         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 217         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 218
 219         switch (cmd) {
 220         case SNDRV_PCM_TRIGGER_START:
 221         case SNDRV_PCM_TRIGGER_RESUME:
 222         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 223                 mcbsp_data->active++;
 224                 omap_mcbsp_start(mcbsp_data->bus_id, play, !play);
 225                 /* Make sure data transfer is frame synchronized */
 226                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 227                         omap_mcbsp_xmit_enable(mcbsp_data->bus_id, 1);
 228                 else
 229                         omap_mcbsp_recv_enable(mcbsp_data->bus_id, 1);
 230                 break;
 231
 232         case SNDRV_PCM_TRIGGER_STOP:
 233         case SNDRV_PCM_TRIGGER_SUSPEND:
 234         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 235                 omap_mcbsp_stop(mcbsp_data->bus_id, play, !play);
 236                 mcbsp_data->active--;
 237                 break;
 238         default:
 239                 err = -EINVAL;
 240         }
 241
 242         return err;
 243 }
 244
 245 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 246                                     struct snd_pcm_hw_params *params,
 247                                     struct snd_soc_dai *dai)
 248 {
 249         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 250         struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
 251         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 252         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 253         int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
 254         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 255         unsigned long port;
 256         unsigned int format;
 257
 258         if (cpu_class_is_omap1()) {
 259                 dma = omap1_dma_reqs[bus_id][substream->stream];
 260                 port = omap1_mcbsp_port[bus_id][substream->stream];
 261         } else if (cpu_is_omap2420()) {
 262                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 263                 port = omap2420_mcbsp_port[bus_id][substream->stream];
 264         } else if (cpu_is_omap2430()) {
 265                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 266                 port = omap2430_mcbsp_port[bus_id][substream->stream];
 267         } else if (cpu_is_omap343x()) {
 268                 dma = omap24xx_dma_reqs[bus_id][substream->stream];
 269                 port = omap34xx_mcbsp_port[bus_id][substream->stream];
 270                 omap_mcbsp_dai_dma_params[id][substream->stream].set_threshold =
 271                                                 omap_mcbsp_set_threshold;
 272                 sync_mode = OMAP_DMA_SYNC_FRAME;
 273         } else {
 274                 return -ENODEV;
 275         }
 276         omap_mcbsp_dai_dma_params[id][substream->stream].name =
 277                 substream->stream ? "Audio Capture" : "Audio Playback";
 278         omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
 279         omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
 280         omap_mcbsp_dai_dma_params[id][substream->stream].sync_mode = sync_mode;
 281         cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
 282
 283         if (mcbsp_data->configured) {
 284                 /* McBSP already configured by another stream */
 285                 return 0;
 286         }
 287
 288         format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 289         wpf = channels = params_channels(params);
 290         switch (channels) {
 291         case 2:
 292                 if (format == SND_SOC_DAIFMT_I2S) {
 293                         /* Use dual-phase frames */
 294                         regs->rcr2      |= RPHASE;
 295                         regs->xcr2      |= XPHASE;
 296                         /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 297                         wpf--;
 298                         regs->rcr2      |= RFRLEN2(wpf - 1);
 299                         regs->xcr2      |= XFRLEN2(wpf - 1);
 300                 }
 301         case 1:
 302         case 4:
 303                 /* Set word per (McBSP) frame for phase1 */
 304                 regs->rcr1      |= RFRLEN1(wpf - 1);
 305                 regs->xcr1      |= XFRLEN1(wpf - 1);
 306                 break;
 307         default:
 308                 /* Unsupported number of channels */
 309                 return -EINVAL;
 310         }
 311
 312         switch (params_format(params)) {
 313         case SNDRV_PCM_FORMAT_S16_LE:
 314                 /* Set word lengths */
 315                 wlen = 16;
 316                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 317                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 318                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 319                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 320                 break;
 321         default:
 322                 /* Unsupported PCM format */
 323                 return -EINVAL;
 324         }
 325
 326         /* Set FS period and length in terms of bit clock periods */
 327         switch (format) {
 328         case SND_SOC_DAIFMT_I2S:
 329                 regs->srgr2     |= FPER(wlen * channels - 1);
 330                 regs->srgr1     |= FWID(wlen - 1);
 331                 break;
 332         case SND_SOC_DAIFMT_DSP_A:
 333         case SND_SOC_DAIFMT_DSP_B:
 334                 regs->srgr2     |= FPER(wlen * channels - 1);
 335                 regs->srgr1     |= FWID(0);
 336                 break;
 337         }
 338
 339         omap_mcbsp_config(bus_id, &mcbsp_data->regs);
 340         mcbsp_data->configured = 1;
 341
 342         return 0;
 343 }
 344
 345 /*
 346  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 347  * cache is initialized here
 348  */
 349 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 350                                       unsigned int fmt)
 351 {
 352         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 353         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 354         unsigned int temp_fmt = fmt;
 355
 356         if (mcbsp_data->configured)
 357                 return 0;
 358
 359         mcbsp_data->fmt = fmt;
 360         memset(regs, 0, sizeof(*regs));
 361         /* Generic McBSP register settings */
 362         regs->spcr2     |= XINTM(3) | FREE;
 363         regs->spcr1     |= RINTM(3);
 364         /* RFIG and XFIG are not defined in 34xx */
 365         if (!cpu_is_omap34xx()) {
 366                 regs->rcr2      |= RFIG;
 367                 regs->xcr2      |= XFIG;
 368         }
 369         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 370                 regs->xccr = DXENDLY(1) | XDMAEN;
 371                 regs->rccr = RFULL_CYCLE | RDMAEN;
 372         }
 373
 374         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 375         case SND_SOC_DAIFMT_I2S:
 376                 /* 1-bit data delay */
 377                 regs->rcr2      |= RDATDLY(1);
 378                 regs->xcr2      |= XDATDLY(1);
 379                 regs->rccr      |= RFULL_CYCLE | RDMAEN | RDISABLE;
 380                 regs->xccr      |= (DXENDLY(1) | XDMAEN | XDISABLE);
 381                 break;
 382         case SND_SOC_DAIFMT_DSP_A:
 383                 /* 1-bit data delay */
 384                 regs->rcr2      |= RDATDLY(1);
 385                 regs->xcr2      |= XDATDLY(1);
 386                 regs->rccr      |= RFULL_CYCLE | RDMAEN | RDISABLE;
 387                 regs->xccr      |= (DXENDLY(1) | XDMAEN | XDISABLE);
 388                 /* Invert FS polarity configuration */
 389                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 390                 break;
 391         case SND_SOC_DAIFMT_DSP_B:
 392                 /* 0-bit data delay */
 393                 regs->rcr2      |= RDATDLY(0);
 394                 regs->xcr2      |= XDATDLY(0);
 395                 /* Invert FS polarity configuration */
 396                 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
 397                 break;
 398         default:
 399                 /* Unsupported data format */
 400                 return -EINVAL;
 401         }
 402
 403         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 404         case SND_SOC_DAIFMT_CBS_CFS:
 405                 /* McBSP master. Set FS and bit clocks as outputs */
 406                 regs->pcr0      |= FSXM | FSRM |
 407                                    CLKXM | CLKRM;
 408                 /* Sample rate generator drives the FS */
 409                 regs->srgr2     |= FSGM;
 410                 break;
 411         case SND_SOC_DAIFMT_CBM_CFM:
 412                 /* McBSP slave */
 413                 break;
 414         default:
 415                 /* Unsupported master/slave configuration */
 416                 return -EINVAL;
 417         }
 418
 419         /* Set bit clock (CLKX/CLKR) and FS polarities */
 420         switch (temp_fmt & SND_SOC_DAIFMT_INV_MASK) {
 421         case SND_SOC_DAIFMT_NB_NF:
 422                 /*
 423                  * Normal BCLK + FS.
 424                  * FS active low. TX data driven on falling edge of bit clock
 425                  * and RX data sampled on rising edge of bit clock.
 426                  */
 427                 regs->pcr0      |= FSXP | FSRP |
 428                                    CLKXP | CLKRP;
 429                 break;
 430         case SND_SOC_DAIFMT_NB_IF:
 431                 regs->pcr0      |= CLKXP | CLKRP;
 432                 break;
 433         case SND_SOC_DAIFMT_IB_NF:
 434                 regs->pcr0      |= FSXP | FSRP;
 435                 break;
 436         case SND_SOC_DAIFMT_IB_IF:
 437                 break;
 438         default:
 439                 return -EINVAL;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 446                                      int div_id, int div)
 447 {
 448         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 449         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 450
 451         if (div_id != OMAP_MCBSP_CLKGDV)
 452                 return -ENODEV;
 453
 454         regs->srgr1     |= CLKGDV(div - 1);
 455
 456         return 0;
 457 }
 458
 459 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
 460                                        int clk_id)
 461 {
 462         int sel_bit;
 463         u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
 464
 465         if (cpu_class_is_omap1()) {
 466                 /* OMAP1's can use only external source clock */
 467                 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
 468                         return -EINVAL;
 469                 else
 470                         return 0;
 471         }
 472
 473         if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
 474                 return -EINVAL;
 475
 476         if (cpu_is_omap343x())
 477                 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
 478
 479         switch (mcbsp_data->bus_id) {
 480         case 0:
 481                 reg = OMAP2_CONTROL_DEVCONF0;
 482                 sel_bit = 2;
 483                 break;
 484         case 1:
 485                 reg = OMAP2_CONTROL_DEVCONF0;
 486                 sel_bit = 6;
 487                 break;
 488         case 2:
 489                 reg = reg_devconf1;
 490                 sel_bit = 0;
 491                 break;
 492         case 3:
 493                 reg = reg_devconf1;
 494                 sel_bit = 2;
 495                 break;
 496         case 4:
 497                 reg = reg_devconf1;
 498                 sel_bit = 4;
 499                 break;
 500         default:
 501                 return -EINVAL;
 502         }
 503
 504         if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
 505                 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
 506         else
 507                 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
 508
 509         return 0;
 510 }
 511
 512 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 513                                          int clk_id, unsigned int freq,
 514                                          int dir)
 515 {
 516         struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
 517         struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
 518         int err = 0;
 519
 520         switch (clk_id) {
 521         case OMAP_MCBSP_SYSCLK_CLK:
 522                 regs->srgr2     |= CLKSM;
 523                 break;
 524         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 525         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 526                 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
 527                 break;
 528
 529         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 530                 regs->srgr2     |= CLKSM;
 531         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 532                 regs->pcr0      |= SCLKME;
 533                 break;
 534         default:
 535                 err = -ENODEV;
 536         }
 537
 538         return err;
 539 }
 540
 541 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
 542         .startup        = omap_mcbsp_dai_startup,
 543         .shutdown       = omap_mcbsp_dai_shutdown,
 544         .trigger        = omap_mcbsp_dai_trigger,
 545         .hw_params      = omap_mcbsp_dai_hw_params,
 546         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 547         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 548         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 549 };
 550
 551 #define OMAP_MCBSP_DAI_BUILDER(link_id)                         \
 552 {                                                               \
 553         .name = "omap-mcbsp-dai-"#link_id,                      \
 554         .id = (link_id),                                        \
 555         .playback = {                                           \
 556                 .channels_min = 1,                              \
 557                 .channels_max = 4,                              \
 558                 .rates = OMAP_MCBSP_RATES,                      \
 559                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 560         },                                                      \
 561         .capture = {                                            \
 562                 .channels_min = 1,                              \
 563                 .channels_max = 4,                              \
 564                 .rates = OMAP_MCBSP_RATES,                      \
 565                 .formats = SNDRV_PCM_FMTBIT_S16_LE,             \
 566         },                                                      \
 567         .ops = &omap_mcbsp_dai_ops,                             \
 568         .private_data = &mcbsp_data[(link_id)].bus_id,          \
 569 }
 570
 571 struct snd_soc_dai omap_mcbsp_dai[] = {
 572         OMAP_MCBSP_DAI_BUILDER(0),
 573         OMAP_MCBSP_DAI_BUILDER(1),
 574 #if NUM_LINKS >= 3
 575         OMAP_MCBSP_DAI_BUILDER(2),
 576 #endif
 577 #if NUM_LINKS == 5
 578         OMAP_MCBSP_DAI_BUILDER(3),
 579         OMAP_MCBSP_DAI_BUILDER(4),
 580 #endif
 581 };
 582
 583 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
 584
 585 static int __init snd_omap_mcbsp_init(void)
 586 {
 587         return snd_soc_register_dais(omap_mcbsp_dai,
 588                                      ARRAY_SIZE(omap_mcbsp_dai));
 589 }
 590 module_init(snd_omap_mcbsp_init);
 591
 592 static void __exit snd_omap_mcbsp_exit(void)
 593 {
 594         snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
 595 }
 596 module_exit(snd_omap_mcbsp_exit);
 597
 598 MODULE_AUTHOR("Jarkko Nikula <jhnikula@gmail.com>");
 599 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 600 MODULE_LICENSE("GPL");