1 /* sound/soc/rockchip/rockchip_i2s.c
3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver
5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6 * Author: Jianqun <jay.xu@rock-chips.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/of_gpio.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
22 #include "rockchip_i2s.h"
24 #define DRV_NAME "rockchip-i2s"
32 struct snd_dmaengine_dai_dma_data capture_dma_data;
33 struct snd_dmaengine_dai_dma_data playback_dma_data;
35 struct regmap *regmap;
40 static int i2s_runtime_suspend(struct device *dev)
42 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
44 clk_disable_unprepare(i2s->mclk);
49 static int i2s_runtime_resume(struct device *dev)
51 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
54 ret = clk_prepare_enable(i2s->mclk);
56 dev_err(i2s->dev, "clock enable failed %d\n", ret);
63 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
65 return snd_soc_dai_get_drvdata(dai);
68 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
74 regmap_update_bits(i2s->regmap, I2S_DMACR,
75 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
77 regmap_update_bits(i2s->regmap, I2S_XFER,
81 regmap_update_bits(i2s->regmap, I2S_DMACR,
82 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
84 regmap_update_bits(i2s->regmap, I2S_XFER,
88 regmap_update_bits(i2s->regmap, I2S_CLR,
92 regmap_read(i2s->regmap, I2S_CLR, &val);
94 /* Should wait for clear operation to finish */
95 while (val & I2S_CLR_TXC) {
96 regmap_read(i2s->regmap, I2S_CLR, &val);
99 dev_warn(i2s->dev, "fail to clear\n");
106 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
108 unsigned int val = 0;
112 regmap_update_bits(i2s->regmap, I2S_DMACR,
113 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
115 regmap_update_bits(i2s->regmap, I2S_XFER,
119 regmap_update_bits(i2s->regmap, I2S_DMACR,
120 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
122 regmap_update_bits(i2s->regmap, I2S_XFER,
126 regmap_update_bits(i2s->regmap, I2S_CLR,
130 regmap_read(i2s->regmap, I2S_CLR, &val);
132 /* Should wait for clear operation to finish */
133 while (val & I2S_CLR_RXC) {
134 regmap_read(i2s->regmap, I2S_CLR, &val);
137 dev_warn(i2s->dev, "fail to clear\n");
144 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
147 struct rk_i2s_dev *i2s = to_info(cpu_dai);
148 unsigned int mask = 0, val = 0;
150 mask = I2S_CKR_MSS_MASK;
151 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
152 case SND_SOC_DAIFMT_CBS_CFS:
153 /* Set source clock in Master mode */
154 val = I2S_CKR_MSS_MASTER;
155 i2s->is_master_mode = true;
157 case SND_SOC_DAIFMT_CBM_CFM:
158 val = I2S_CKR_MSS_SLAVE;
159 i2s->is_master_mode = false;
165 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
167 mask = I2S_TXCR_IBM_MASK;
168 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
169 case SND_SOC_DAIFMT_RIGHT_J:
170 val = I2S_TXCR_IBM_RSJM;
172 case SND_SOC_DAIFMT_LEFT_J:
173 val = I2S_TXCR_IBM_LSJM;
175 case SND_SOC_DAIFMT_I2S:
176 val = I2S_TXCR_IBM_NORMAL;
182 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
184 mask = I2S_RXCR_IBM_MASK;
185 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
186 case SND_SOC_DAIFMT_RIGHT_J:
187 val = I2S_RXCR_IBM_RSJM;
189 case SND_SOC_DAIFMT_LEFT_J:
190 val = I2S_RXCR_IBM_LSJM;
192 case SND_SOC_DAIFMT_I2S:
193 val = I2S_RXCR_IBM_NORMAL;
199 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
204 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
205 struct snd_pcm_hw_params *params,
206 struct snd_soc_dai *dai)
208 struct rk_i2s_dev *i2s = to_info(dai);
209 struct snd_soc_pcm_runtime *rtd = substream->private_data;
210 unsigned int val = 0;
211 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
213 if (i2s->is_master_mode) {
214 mclk_rate = clk_get_rate(i2s->mclk);
215 bclk_rate = 2 * 32 * params_rate(params);
216 if (bclk_rate && mclk_rate % bclk_rate)
219 div_bclk = mclk_rate / bclk_rate;
220 div_lrck = bclk_rate / params_rate(params);
221 regmap_update_bits(i2s->regmap, I2S_CKR,
223 I2S_CKR_MDIV(div_bclk));
225 regmap_update_bits(i2s->regmap, I2S_CKR,
228 I2S_CKR_TSD(div_lrck) |
229 I2S_CKR_RSD(div_lrck));
232 switch (params_format(params)) {
233 case SNDRV_PCM_FORMAT_S8:
234 val |= I2S_TXCR_VDW(8);
236 case SNDRV_PCM_FORMAT_S16_LE:
237 val |= I2S_TXCR_VDW(16);
239 case SNDRV_PCM_FORMAT_S20_3LE:
240 val |= I2S_TXCR_VDW(20);
242 case SNDRV_PCM_FORMAT_S24_LE:
243 val |= I2S_TXCR_VDW(24);
245 case SNDRV_PCM_FORMAT_S32_LE:
246 val |= I2S_TXCR_VDW(32);
252 switch (params_channels(params)) {
266 dev_err(i2s->dev, "invalid channel: %d\n",
267 params_channels(params));
271 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
272 regmap_update_bits(i2s->regmap, I2S_RXCR,
273 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
276 regmap_update_bits(i2s->regmap, I2S_TXCR,
277 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
280 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
282 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
285 val = I2S_CKR_TRCM_TXRX;
286 if (dai->driver->symmetric_rates || rtd->dai_link->symmetric_rates)
287 val = I2S_CKR_TRCM_TXSHARE;
289 regmap_update_bits(i2s->regmap, I2S_CKR,
295 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
296 int cmd, struct snd_soc_dai *dai)
298 struct rk_i2s_dev *i2s = to_info(dai);
302 case SNDRV_PCM_TRIGGER_START:
303 case SNDRV_PCM_TRIGGER_RESUME:
304 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
305 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
306 rockchip_snd_rxctrl(i2s, 1);
308 rockchip_snd_txctrl(i2s, 1);
310 case SNDRV_PCM_TRIGGER_SUSPEND:
311 case SNDRV_PCM_TRIGGER_STOP:
312 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
313 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
314 rockchip_snd_rxctrl(i2s, 0);
316 rockchip_snd_txctrl(i2s, 0);
326 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
327 unsigned int freq, int dir)
329 struct rk_i2s_dev *i2s = to_info(cpu_dai);
332 ret = clk_set_rate(i2s->mclk, freq);
334 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
339 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
341 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
343 dai->capture_dma_data = &i2s->capture_dma_data;
344 dai->playback_dma_data = &i2s->playback_dma_data;
349 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
350 .hw_params = rockchip_i2s_hw_params,
351 .set_sysclk = rockchip_i2s_set_sysclk,
352 .set_fmt = rockchip_i2s_set_fmt,
353 .trigger = rockchip_i2s_trigger,
356 static struct snd_soc_dai_driver rockchip_i2s_dai = {
357 .probe = rockchip_i2s_dai_probe,
359 .stream_name = "Playback",
362 .rates = SNDRV_PCM_RATE_8000_192000,
363 .formats = (SNDRV_PCM_FMTBIT_S8 |
364 SNDRV_PCM_FMTBIT_S16_LE |
365 SNDRV_PCM_FMTBIT_S20_3LE |
366 SNDRV_PCM_FMTBIT_S24_LE |
367 SNDRV_PCM_FMTBIT_S32_LE),
370 .stream_name = "Capture",
373 .rates = SNDRV_PCM_RATE_8000_192000,
374 .formats = (SNDRV_PCM_FMTBIT_S8 |
375 SNDRV_PCM_FMTBIT_S16_LE |
376 SNDRV_PCM_FMTBIT_S20_3LE |
377 SNDRV_PCM_FMTBIT_S24_LE |
378 SNDRV_PCM_FMTBIT_S32_LE),
380 .ops = &rockchip_i2s_dai_ops,
381 .symmetric_rates = 1,
384 static const struct snd_soc_component_driver rockchip_i2s_component = {
388 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
405 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
424 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
435 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
443 static const struct reg_default rockchip_i2s_reg_defaults[] = {
451 static const struct regmap_config rockchip_i2s_regmap_config = {
455 .max_register = I2S_RXDR,
456 .reg_defaults = rockchip_i2s_reg_defaults,
457 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
458 .writeable_reg = rockchip_i2s_wr_reg,
459 .readable_reg = rockchip_i2s_rd_reg,
460 .volatile_reg = rockchip_i2s_volatile_reg,
461 .precious_reg = rockchip_i2s_precious_reg,
462 .cache_type = REGCACHE_FLAT,
465 static int rockchip_i2s_probe(struct platform_device *pdev)
467 struct device_node *node = pdev->dev.of_node;
468 struct rk_i2s_dev *i2s;
469 struct snd_soc_dai_driver *soc_dai;
470 struct resource *res;
475 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
477 dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
481 /* try to prepare related clocks */
482 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
483 if (IS_ERR(i2s->hclk)) {
484 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
485 return PTR_ERR(i2s->hclk);
487 ret = clk_prepare_enable(i2s->hclk);
489 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
493 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
494 if (IS_ERR(i2s->mclk)) {
495 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
496 return PTR_ERR(i2s->mclk);
499 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
500 regs = devm_ioremap_resource(&pdev->dev, res);
502 return PTR_ERR(regs);
504 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
505 &rockchip_i2s_regmap_config);
506 if (IS_ERR(i2s->regmap)) {
508 "Failed to initialise managed register map\n");
509 return PTR_ERR(i2s->regmap);
512 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
513 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
514 i2s->playback_dma_data.maxburst = 4;
516 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
517 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
518 i2s->capture_dma_data.maxburst = 4;
520 i2s->dev = &pdev->dev;
521 dev_set_drvdata(&pdev->dev, i2s);
523 pm_runtime_enable(&pdev->dev);
524 if (!pm_runtime_enabled(&pdev->dev)) {
525 ret = i2s_runtime_resume(&pdev->dev);
530 soc_dai = devm_kzalloc(&pdev->dev,
531 sizeof(*soc_dai), GFP_KERNEL);
535 memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
536 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
537 if (val >= 2 && val <= 8)
538 soc_dai->playback.channels_max = val;
541 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
542 if (val >= 2 && val <= 8)
543 soc_dai->capture.channels_max = val;
546 ret = devm_snd_soc_register_component(&pdev->dev,
547 &rockchip_i2s_component,
551 dev_err(&pdev->dev, "Could not register DAI\n");
555 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
557 dev_err(&pdev->dev, "Could not register PCM\n");
564 if (!pm_runtime_status_suspended(&pdev->dev))
565 i2s_runtime_suspend(&pdev->dev);
567 pm_runtime_disable(&pdev->dev);
572 static int rockchip_i2s_remove(struct platform_device *pdev)
574 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
576 pm_runtime_disable(&pdev->dev);
577 if (!pm_runtime_status_suspended(&pdev->dev))
578 i2s_runtime_suspend(&pdev->dev);
580 clk_disable_unprepare(i2s->mclk);
581 clk_disable_unprepare(i2s->hclk);
586 static const struct of_device_id rockchip_i2s_match[] = {
587 { .compatible = "rockchip,rk3066-i2s", },
588 { .compatible = "rockchip,rk3188-i2s", },
589 { .compatible = "rockchip,rk3288-i2s", },
590 { .compatible = "rockchip,rk3399-i2s", },
594 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
595 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
599 static struct platform_driver rockchip_i2s_driver = {
600 .probe = rockchip_i2s_probe,
601 .remove = rockchip_i2s_remove,
604 .of_match_table = of_match_ptr(rockchip_i2s_match),
605 .pm = &rockchip_i2s_pm_ops,
608 module_platform_driver(rockchip_i2s_driver);
610 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
611 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
612 MODULE_LICENSE("GPL v2");
613 MODULE_ALIAS("platform:" DRV_NAME);
614 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);