2 * Helper routines for R-Car sound ADG.
4 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/sh_clk.h>
20 struct clk *clk[CLKMAX];
22 int rbga_rate_for_441khz_div_6; /* RBGA */
23 int rbgb_rate_for_48khz_div_6; /* RBGB */
27 #define for_each_rsnd_clk(pos, adg, i) \
30 ((pos) = adg->clk[i]); \
32 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
35 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io)
37 struct rsnd_mod *mod = rsnd_io_to_mod_ssi(io);
38 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
39 int id = rsnd_mod_id(mod);
42 if (rsnd_ssi_is_pin_sharing(rsnd_ssi_mod_get(priv, id))) {
57 return (0x6 + ws) << 8;
60 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_dai *rdai,
62 struct rsnd_dai_stream *io)
64 int id = rsnd_mod_id(mod);
65 int shift = (id % 2) ? 16 : 0;
68 val = rsnd_adg_ssi_ws_timing_gen2(io);
71 mask = 0xffff << shift;
73 rsnd_mod_bset(mod, CMDOUT_TIMSEL, mask, val);
78 static int rsnd_adg_set_src_timsel_gen2(struct rsnd_dai *rdai,
80 struct rsnd_dai_stream *io,
83 int is_play = rsnd_io_is_play(io);
84 int id = rsnd_mod_id(mod);
85 int shift = (id % 2) ? 16 : 0;
89 ws = rsnd_adg_ssi_ws_timing_gen2(io);
91 in = (is_play) ? timsel : ws;
92 out = (is_play) ? ws : timsel;
96 mask = 0xffff << shift;
100 rsnd_mod_bset(mod, SRCIN_TIMSEL0, mask, in);
101 rsnd_mod_bset(mod, SRCOUT_TIMSEL0, mask, out);
104 rsnd_mod_bset(mod, SRCIN_TIMSEL1, mask, in);
105 rsnd_mod_bset(mod, SRCOUT_TIMSEL1, mask, out);
108 rsnd_mod_bset(mod, SRCIN_TIMSEL2, mask, in);
109 rsnd_mod_bset(mod, SRCOUT_TIMSEL2, mask, out);
112 rsnd_mod_bset(mod, SRCIN_TIMSEL3, mask, in);
113 rsnd_mod_bset(mod, SRCOUT_TIMSEL3, mask, out);
116 rsnd_mod_bset(mod, SRCIN_TIMSEL4, mask, in);
117 rsnd_mod_bset(mod, SRCOUT_TIMSEL4, mask, out);
124 int rsnd_adg_set_convert_clk_gen2(struct rsnd_mod *mod,
125 struct rsnd_dai *rdai,
126 struct rsnd_dai_stream *io,
127 unsigned int src_rate,
128 unsigned int dst_rate)
130 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
131 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
132 struct device *dev = rsnd_priv_to_dev(priv);
133 int idx, sel, div, step, ret;
135 unsigned int min, diff;
136 unsigned int sel_rate [] = {
137 clk_get_rate(adg->clk[CLKA]), /* 0000: CLKA */
138 clk_get_rate(adg->clk[CLKB]), /* 0001: CLKB */
139 clk_get_rate(adg->clk[CLKC]), /* 0010: CLKC */
140 adg->rbga_rate_for_441khz_div_6,/* 0011: RBGA */
141 adg->rbgb_rate_for_48khz_div_6, /* 0100: RBGB */
147 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
154 for (div = 2; div <= 98304; div += step) {
155 diff = abs(src_rate - sel_rate[sel] / div);
157 val = (sel << 8) | idx;
159 en = 1 << (sel + 1); /* fixme */
163 * step of 0_0000 / 0_0001 / 0_1101
166 if ((idx > 2) && (idx % 2))
177 dev_err(dev, "no Input clock\n");
181 ret = rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
183 dev_err(dev, "timsel error\n");
187 rsnd_mod_bset(mod, DIV_EN, en, en);
192 int rsnd_adg_set_convert_timing_gen2(struct rsnd_mod *mod,
193 struct rsnd_dai *rdai,
194 struct rsnd_dai_stream *io)
196 u32 val = rsnd_adg_ssi_ws_timing_gen2(io);
198 return rsnd_adg_set_src_timsel_gen2(rdai, mod, io, val);
201 int rsnd_adg_set_convert_clk_gen1(struct rsnd_priv *priv,
202 struct rsnd_mod *mod,
203 unsigned int src_rate,
204 unsigned int dst_rate)
206 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
207 struct device *dev = rsnd_priv_to_dev(priv);
208 int idx, sel, div, shift;
210 int id = rsnd_mod_id(mod);
211 unsigned int sel_rate [] = {
212 clk_get_rate(adg->clk[CLKA]), /* 000: CLKA */
213 clk_get_rate(adg->clk[CLKB]), /* 001: CLKB */
214 clk_get_rate(adg->clk[CLKC]), /* 010: CLKC */
215 0, /* 011: MLBCLK (not used) */
216 adg->rbga_rate_for_441khz_div_6,/* 100: RBGA */
217 adg->rbgb_rate_for_48khz_div_6, /* 101: RBGB */
220 /* find div (= 1/128, 1/256, 1/512, 1/1024, 1/2048 */
221 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) {
222 for (div = 128, idx = 0;
225 if (src_rate == sel_rate[sel] / div) {
226 val = (idx << 4) | sel;
231 dev_err(dev, "can't find convert src clk\n");
235 shift = (id % 4) * 8;
236 mask = 0xFF << shift;
239 dev_dbg(dev, "adg convert src clk = %02x\n", val);
243 rsnd_mod_bset(mod, AUDIO_CLK_SEL3, mask, val);
246 rsnd_mod_bset(mod, AUDIO_CLK_SEL4, mask, val);
249 rsnd_mod_bset(mod, AUDIO_CLK_SEL5, mask, val);
254 * Gen1 doesn't need dst_rate settings,
255 * since it uses SSI WS pin.
256 * see also rsnd_src_set_route_if_gen1()
262 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *mod, u32 val)
264 int id = rsnd_mod_id(mod);
265 int shift = (id % 4) * 8;
266 u32 mask = 0xFF << shift;
271 * SSI 8 is not connected to ADG.
272 * it works with SSI 7
279 rsnd_mod_bset(mod, AUDIO_CLK_SEL0, mask, val);
282 rsnd_mod_bset(mod, AUDIO_CLK_SEL1, mask, val);
285 rsnd_mod_bset(mod, AUDIO_CLK_SEL2, mask, val);
290 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *mod)
293 * "mod" = "ssi" here.
294 * we can get "ssi id" from mod
296 rsnd_adg_set_ssi_clk(mod, 0);
301 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *mod, unsigned int rate)
303 struct rsnd_priv *priv = rsnd_mod_to_priv(mod);
304 struct rsnd_adg *adg = rsnd_priv_to_adg(priv);
305 struct device *dev = rsnd_priv_to_dev(priv);
316 dev_dbg(dev, "request clock = %d\n", rate);
319 * find suitable clock from
320 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI.
323 for_each_rsnd_clk(clk, adg, i) {
324 if (rate == clk_get_rate(clk)) {
331 * find 1/6 clock from BRGA/BRGB
333 if (rate == adg->rbga_rate_for_441khz_div_6) {
338 if (rate == adg->rbgb_rate_for_48khz_div_6) {
347 /* see rsnd_adg_ssi_clk_init() */
348 rsnd_mod_bset(mod, SSICKR, 0x00FF0000, adg->ckr);
349 rsnd_mod_write(mod, BRRA, 0x00000002); /* 1/6 */
350 rsnd_mod_write(mod, BRRB, 0x00000002); /* 1/6 */
353 * This "mod" = "ssi" here.
354 * we can get "ssi id" from mod
356 rsnd_adg_set_ssi_clk(mod, data);
358 dev_dbg(dev, "ADG: ssi%d selects clk%d = %d",
359 rsnd_mod_id(mod), i, rate);
364 static void rsnd_adg_ssi_clk_init(struct rsnd_priv *priv, struct rsnd_adg *adg)
378 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC
379 * have 44.1kHz or 48kHz base clocks for now.
381 * SSI itself can divide parent clock by 1/1 - 1/16
382 * So, BRGA outputs 44.1kHz base parent clock 1/32,
383 * and, BRGB outputs 48.0kHz base parent clock 1/32 here.
385 * rsnd_adg_ssi_clk_try_start()
388 adg->rbga_rate_for_441khz_div_6 = 0;
389 adg->rbgb_rate_for_48khz_div_6 = 0;
390 for_each_rsnd_clk(clk, adg, i) {
391 rate = clk_get_rate(clk);
393 if (0 == rate) /* not used */
397 if (!adg->rbga_rate_for_441khz_div_6 && (0 == rate % 44100)) {
398 adg->rbga_rate_for_441khz_div_6 = rate / 6;
399 ckr |= brg_table[i] << 20;
403 if (!adg->rbgb_rate_for_48khz_div_6 && (0 == rate % 48000)) {
404 adg->rbgb_rate_for_48khz_div_6 = rate / 6;
405 ckr |= brg_table[i] << 16;
412 int rsnd_adg_probe(struct platform_device *pdev,
413 const struct rsnd_of_data *of_data,
414 struct rsnd_priv *priv)
416 struct rsnd_adg *adg;
417 struct device *dev = rsnd_priv_to_dev(priv);
421 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL);
423 dev_err(dev, "ADG allocate failed\n");
427 adg->clk[CLKA] = devm_clk_get(dev, "clk_a");
428 adg->clk[CLKB] = devm_clk_get(dev, "clk_b");
429 adg->clk[CLKC] = devm_clk_get(dev, "clk_c");
430 adg->clk[CLKI] = devm_clk_get(dev, "clk_i");
432 for_each_rsnd_clk(clk, adg, i)
433 dev_dbg(dev, "clk %d : %p : %ld\n", i, clk, clk_get_rate(clk));
435 rsnd_adg_ssi_clk_init(priv, adg);
439 dev_dbg(dev, "adg probed\n");