tools/testing/nvdimm/test/nfit.c

   1 /*
   2  * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of version 2 of the GNU General Public License as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/libnvdimm.h>
  17 #include <linux/vmalloc.h>
  18 #include <linux/device.h>
  19 #include <linux/module.h>
  20 #include <linux/mutex.h>
  21 #include <linux/ndctl.h>
  22 #include <linux/sizes.h>
  23 #include <linux/list.h>
  24 #include <linux/slab.h>
  25 #include <nfit.h>
  26 #include <nd.h>
  27 #include "nfit_test.h"
  28
  29 /*
  30  * Generate an NFIT table to describe the following topology:
  31  *
  32  * BUS0: Interleaved PMEM regions, and aliasing with BLK regions
  33  *
  34  *                     (a)                       (b)            DIMM   BLK-REGION
  35  *           +----------+--------------+----------+---------+
  36  * +------+  |  blk2.0  |     pm0.0    |  blk2.1  |  pm1.0  |    0      region2
  37  * | imc0 +--+- - - - - region0 - - - -+----------+         +
  38  * +--+---+  |  blk3.0  |     pm0.0    |  blk3.1  |  pm1.0  |    1      region3
  39  *    |      +----------+--------------v----------v         v
  40  * +--+---+                            |                    |
  41  * | cpu0 |                                    region1
  42  * +--+---+                            |                    |
  43  *    |      +-------------------------^----------^         ^
  44  * +--+---+  |                 blk4.0             |  pm1.0  |    2      region4
  45  * | imc1 +--+-------------------------+----------+         +
  46  * +------+  |                 blk5.0             |  pm1.0  |    3      region5
  47  *           +-------------------------+----------+-+-------+
  48  *
  49  * +--+---+
  50  * | cpu1 |
  51  * +--+---+                   (Hotplug DIMM)
  52  *    |      +----------------------------------------------+
  53  * +--+---+  |                 blk6.0/pm7.0                 |    4      region6/7
  54  * | imc0 +--+----------------------------------------------+
  55  * +------+
  56  *
  57  *
  58  * *) In this layout we have four dimms and two memory controllers in one
  59  *    socket.  Each unique interface (BLK or PMEM) to DPA space
  60  *    is identified by a region device with a dynamically assigned id.
  61  *
  62  * *) The first portion of dimm0 and dimm1 are interleaved as REGION0.
  63  *    A single PMEM namespace "pm0.0" is created using half of the
  64  *    REGION0 SPA-range.  REGION0 spans dimm0 and dimm1.  PMEM namespace
  65  *    allocate from from the bottom of a region.  The unallocated
  66  *    portion of REGION0 aliases with REGION2 and REGION3.  That
  67  *    unallacted capacity is reclaimed as BLK namespaces ("blk2.0" and
  68  *    "blk3.0") starting at the base of each DIMM to offset (a) in those
  69  *    DIMMs.  "pm0.0", "blk2.0" and "blk3.0" are free-form readable
  70  *    names that can be assigned to a namespace.
  71  *
  72  * *) In the last portion of dimm0 and dimm1 we have an interleaved
  73  *    SPA range, REGION1, that spans those two dimms as well as dimm2
  74  *    and dimm3.  Some of REGION1 allocated to a PMEM namespace named
  75  *    "pm1.0" the rest is reclaimed in 4 BLK namespaces (for each
  76  *    dimm in the interleave set), "blk2.1", "blk3.1", "blk4.0", and
  77  *    "blk5.0".
  78  *
  79  * *) The portion of dimm2 and dimm3 that do not participate in the
  80  *    REGION1 interleaved SPA range (i.e. the DPA address below offset
  81  *    (b) are also included in the "blk4.0" and "blk5.0" namespaces.
  82  *    Note, that BLK namespaces need not be contiguous in DPA-space, and
  83  *    can consume aliased capacity from multiple interleave sets.
  84  *
  85  * BUS1: Legacy NVDIMM (single contiguous range)
  86  *
  87  *  region2
  88  * +---------------------+
  89  * |---------------------|
  90  * ||       pm2.0       ||
  91  * |---------------------|
  92  * +---------------------+
  93  *
  94  * *) A NFIT-table may describe a simple system-physical-address range
  95  *    with no BLK aliasing.  This type of region may optionally
  96  *    reference an NVDIMM.
  97  */
  98 enum {
  99         NUM_PM  = 3,
 100         NUM_DCR = 5,
 101         NUM_BDW = NUM_DCR,
 102         NUM_SPA = NUM_PM + NUM_DCR + NUM_BDW,
 103         NUM_MEM = NUM_DCR + NUM_BDW + 2 /* spa0 iset */ + 4 /* spa1 iset */,
 104         DIMM_SIZE = SZ_32M,
 105         LABEL_SIZE = SZ_128K,
 106         SPA0_SIZE = DIMM_SIZE,
 107         SPA1_SIZE = DIMM_SIZE*2,
 108         SPA2_SIZE = DIMM_SIZE,
 109         BDW_SIZE = 64 << 8,
 110         DCR_SIZE = 12,
 111         NUM_NFITS = 2, /* permit testing multiple NFITs per system */
 112 };
 113
 114 struct nfit_test_dcr {
 115         __le64 bdw_addr;
 116         __le32 bdw_status;
 117         __u8 aperature[BDW_SIZE];
 118 };
 119
 120 #define NFIT_DIMM_HANDLE(node, socket, imc, chan, dimm) \
 121         (((node & 0xfff) << 16) | ((socket & 0xf) << 12) \
 122          | ((imc & 0xf) << 8) | ((chan & 0xf) << 4) | (dimm & 0xf))
 123
 124 static u32 handle[NUM_DCR] = {
 125         [0] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 0),
 126         [1] = NFIT_DIMM_HANDLE(0, 0, 0, 0, 1),
 127         [2] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 0),
 128         [3] = NFIT_DIMM_HANDLE(0, 0, 1, 0, 1),
 129         [4] = NFIT_DIMM_HANDLE(0, 1, 0, 0, 0),
 130 };
 131
 132 struct nfit_test {
 133         struct acpi_nfit_desc acpi_desc;
 134         struct platform_device pdev;
 135         struct list_head resources;
 136         void *nfit_buf;
 137         dma_addr_t nfit_dma;
 138         size_t nfit_size;
 139         int num_dcr;
 140         int num_pm;
 141         void **dimm;
 142         dma_addr_t *dimm_dma;
 143         void **flush;
 144         dma_addr_t *flush_dma;
 145         void **label;
 146         dma_addr_t *label_dma;
 147         void **spa_set;
 148         dma_addr_t *spa_set_dma;
 149         struct nfit_test_dcr **dcr;
 150         dma_addr_t *dcr_dma;
 151         int (*alloc)(struct nfit_test *t);
 152         void (*setup)(struct nfit_test *t);
 153         int setup_hotplug;
 154         struct ars_state {
 155                 struct nd_cmd_ars_status *ars_status;
 156                 unsigned long deadline;
 157                 spinlock_t lock;
 158         } ars_state;
 159 };
 160
 161 static struct nfit_test *to_nfit_test(struct device *dev)
 162 {
 163         struct platform_device *pdev = to_platform_device(dev);
 164
 165         return container_of(pdev, struct nfit_test, pdev);
 166 }
 167
 168 static int nfit_test_cmd_get_config_size(struct nd_cmd_get_config_size *nd_cmd,
 169                 unsigned int buf_len)
 170 {
 171         if (buf_len < sizeof(*nd_cmd))
 172                 return -EINVAL;
 173
 174         nd_cmd->status = 0;
 175         nd_cmd->config_size = LABEL_SIZE;
 176         nd_cmd->max_xfer = SZ_4K;
 177
 178         return 0;
 179 }
 180
 181 static int nfit_test_cmd_get_config_data(struct nd_cmd_get_config_data_hdr
 182                 *nd_cmd, unsigned int buf_len, void *label)
 183 {
 184         unsigned int len, offset = nd_cmd->in_offset;
 185         int rc;
 186
 187         if (buf_len < sizeof(*nd_cmd))
 188                 return -EINVAL;
 189         if (offset >= LABEL_SIZE)
 190                 return -EINVAL;
 191         if (nd_cmd->in_length + sizeof(*nd_cmd) > buf_len)
 192                 return -EINVAL;
 193
 194         nd_cmd->status = 0;
 195         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 196         memcpy(nd_cmd->out_buf, label + offset, len);
 197         rc = buf_len - sizeof(*nd_cmd) - len;
 198
 199         return rc;
 200 }
 201
 202 static int nfit_test_cmd_set_config_data(struct nd_cmd_set_config_hdr *nd_cmd,
 203                 unsigned int buf_len, void *label)
 204 {
 205         unsigned int len, offset = nd_cmd->in_offset;
 206         u32 *status;
 207         int rc;
 208
 209         if (buf_len < sizeof(*nd_cmd))
 210                 return -EINVAL;
 211         if (offset >= LABEL_SIZE)
 212                 return -EINVAL;
 213         if (nd_cmd->in_length + sizeof(*nd_cmd) + 4 > buf_len)
 214                 return -EINVAL;
 215
 216         status = (void *)nd_cmd + nd_cmd->in_length + sizeof(*nd_cmd);
 217         *status = 0;
 218         len = min(nd_cmd->in_length, LABEL_SIZE - offset);
 219         memcpy(label + offset, nd_cmd->in_buf, len);
 220         rc = buf_len - sizeof(*nd_cmd) - (len + 4);
 221
 222         return rc;
 223 }
 224
 225 #define NFIT_TEST_ARS_RECORDS 4
 226 #define NFIT_TEST_CLEAR_ERR_UNIT 256
 227
 228 static int nfit_test_cmd_ars_cap(struct nd_cmd_ars_cap *nd_cmd,
 229                 unsigned int buf_len)
 230 {
 231         if (buf_len < sizeof(*nd_cmd))
 232                 return -EINVAL;
 233
 234         nd_cmd->max_ars_out = sizeof(struct nd_cmd_ars_status)
 235                 + NFIT_TEST_ARS_RECORDS * sizeof(struct nd_ars_record);
 236         nd_cmd->status = (ND_ARS_PERSISTENT | ND_ARS_VOLATILE) << 16;
 237         nd_cmd->clear_err_unit = NFIT_TEST_CLEAR_ERR_UNIT;
 238
 239         return 0;
 240 }
 241
 242 /*
 243  * Initialize the ars_state to return an ars_result 1 second in the future with
 244  * a 4K error range in the middle of the requested address range.
 245  */
 246 static void post_ars_status(struct ars_state *ars_state, u64 addr, u64 len)
 247 {
 248         struct nd_cmd_ars_status *ars_status;
 249         struct nd_ars_record *ars_record;
 250
 251         ars_state->deadline = jiffies + 1*HZ;
 252         ars_status = ars_state->ars_status;
 253         ars_status->status = 0;
 254         ars_status->out_length = sizeof(struct nd_cmd_ars_status)
 255                 + sizeof(struct nd_ars_record);
 256         ars_status->address = addr;
 257         ars_status->length = len;
 258         ars_status->type = ND_ARS_PERSISTENT;
 259         ars_status->num_records = 1;
 260         ars_record = &ars_status->records[0];
 261         ars_record->handle = 0;
 262         ars_record->err_address = addr + len / 2;
 263         ars_record->length = SZ_4K;
 264 }
 265
 266 static int nfit_test_cmd_ars_start(struct ars_state *ars_state,
 267                 struct nd_cmd_ars_start *ars_start, unsigned int buf_len,
 268                 int *cmd_rc)
 269 {
 270         if (buf_len < sizeof(*ars_start))
 271                 return -EINVAL;
 272
 273         spin_lock(&ars_state->lock);
 274         if (time_before(jiffies, ars_state->deadline)) {
 275                 ars_start->status = NFIT_ARS_START_BUSY;
 276                 *cmd_rc = -EBUSY;
 277         } else {
 278                 ars_start->status = 0;
 279                 ars_start->scrub_time = 1;
 280                 post_ars_status(ars_state, ars_start->address,
 281                                 ars_start->length);
 282                 *cmd_rc = 0;
 283         }
 284         spin_unlock(&ars_state->lock);
 285
 286         return 0;
 287 }
 288
 289 static int nfit_test_cmd_ars_status(struct ars_state *ars_state,
 290                 struct nd_cmd_ars_status *ars_status, unsigned int buf_len,
 291                 int *cmd_rc)
 292 {
 293         if (buf_len < ars_state->ars_status->out_length)
 294                 return -EINVAL;
 295
 296         spin_lock(&ars_state->lock);
 297         if (time_before(jiffies, ars_state->deadline)) {
 298                 memset(ars_status, 0, buf_len);
 299                 ars_status->status = NFIT_ARS_STATUS_BUSY;
 300                 ars_status->out_length = sizeof(*ars_status);
 301                 *cmd_rc = -EBUSY;
 302         } else {
 303                 memcpy(ars_status, ars_state->ars_status,
 304                                 ars_state->ars_status->out_length);
 305                 *cmd_rc = 0;
 306         }
 307         spin_unlock(&ars_state->lock);
 308         return 0;
 309 }
 310
 311 static int nfit_test_cmd_clear_error(struct nd_cmd_clear_error *clear_err,
 312                 unsigned int buf_len, int *cmd_rc)
 313 {
 314         const u64 mask = NFIT_TEST_CLEAR_ERR_UNIT - 1;
 315         if (buf_len < sizeof(*clear_err))
 316                 return -EINVAL;
 317
 318         if ((clear_err->address & mask) || (clear_err->length & mask))
 319                 return -EINVAL;
 320
 321         /*
 322          * Report 'all clear' success for all commands even though a new
 323          * scrub will find errors again.  This is enough to have the
 324          * error removed from the 'badblocks' tracking in the pmem
 325          * driver.
 326          */
 327         clear_err->status = 0;
 328         clear_err->cleared = clear_err->length;
 329         *cmd_rc = 0;
 330         return 0;
 331 }
 332
 333 static int nfit_test_ctl(struct nvdimm_bus_descriptor *nd_desc,
 334                 struct nvdimm *nvdimm, unsigned int cmd, void *buf,
 335                 unsigned int buf_len, int *cmd_rc)
 336 {
 337         struct acpi_nfit_desc *acpi_desc = to_acpi_desc(nd_desc);
 338         struct nfit_test *t = container_of(acpi_desc, typeof(*t), acpi_desc);
 339         unsigned int func = cmd;
 340         int i, rc = 0, __cmd_rc;
 341
 342         if (!cmd_rc)
 343                 cmd_rc = &__cmd_rc;
 344         *cmd_rc = 0;
 345
 346         if (nvdimm) {
 347                 struct nfit_mem *nfit_mem = nvdimm_provider_data(nvdimm);
 348                 unsigned long cmd_mask = nvdimm_cmd_mask(nvdimm);
 349
 350                 if (!nfit_mem)
 351                         return -ENOTTY;
 352
 353                 if (cmd == ND_CMD_CALL) {
 354                         struct nd_cmd_pkg *call_pkg = buf;
 355
 356                         buf_len = call_pkg->nd_size_in + call_pkg->nd_size_out;
 357                         buf = (void *) call_pkg->nd_payload;
 358                         func = call_pkg->nd_command;
 359                         if (call_pkg->nd_family != nfit_mem->family)
 360                                 return -ENOTTY;
 361                 }
 362
 363                 if (!test_bit(cmd, &cmd_mask)
 364                                 || !test_bit(func, &nfit_mem->dsm_mask))
 365                         return -ENOTTY;
 366
 367                 /* lookup label space for the given dimm */
 368                 for (i = 0; i < ARRAY_SIZE(handle); i++)
 369                         if (__to_nfit_memdev(nfit_mem)->device_handle ==
 370                                         handle[i])
 371                                 break;
 372                 if (i >= ARRAY_SIZE(handle))
 373                         return -ENXIO;
 374
 375                 switch (func) {
 376                 case ND_CMD_GET_CONFIG_SIZE:
 377                         rc = nfit_test_cmd_get_config_size(buf, buf_len);
 378                         break;
 379                 case ND_CMD_GET_CONFIG_DATA:
 380                         rc = nfit_test_cmd_get_config_data(buf, buf_len,
 381                                 t->label[i]);
 382                         break;
 383                 case ND_CMD_SET_CONFIG_DATA:
 384                         rc = nfit_test_cmd_set_config_data(buf, buf_len,
 385                                 t->label[i]);
 386                         break;
 387                 default:
 388                         return -ENOTTY;
 389                 }
 390         } else {
 391                 struct ars_state *ars_state = &t->ars_state;
 392
 393                 if (!nd_desc || !test_bit(cmd, &nd_desc->cmd_mask))
 394                         return -ENOTTY;
 395
 396                 switch (func) {
 397                 case ND_CMD_ARS_CAP:
 398                         rc = nfit_test_cmd_ars_cap(buf, buf_len);
 399                         break;
 400                 case ND_CMD_ARS_START:
 401                         rc = nfit_test_cmd_ars_start(ars_state, buf, buf_len,
 402                                         cmd_rc);
 403                         break;
 404                 case ND_CMD_ARS_STATUS:
 405                         rc = nfit_test_cmd_ars_status(ars_state, buf, buf_len,
 406                                         cmd_rc);
 407                         break;
 408                 case ND_CMD_CLEAR_ERROR:
 409                         rc = nfit_test_cmd_clear_error(buf, buf_len, cmd_rc);
 410                         break;
 411                 default:
 412                         return -ENOTTY;
 413                 }
 414         }
 415
 416         return rc;
 417 }
 418
 419 static DEFINE_SPINLOCK(nfit_test_lock);
 420 static struct nfit_test *instances[NUM_NFITS];
 421
 422 static void release_nfit_res(void *data)
 423 {
 424         struct nfit_test_resource *nfit_res = data;
 425         struct resource *res = nfit_res->res;
 426
 427         spin_lock(&nfit_test_lock);
 428         list_del(&nfit_res->list);
 429         spin_unlock(&nfit_test_lock);
 430
 431         if (is_vmalloc_addr(nfit_res->buf))
 432                 vfree(nfit_res->buf);
 433         else
 434                 dma_free_coherent(nfit_res->dev, resource_size(res),
 435                                 nfit_res->buf, res->start);
 436         kfree(res);
 437         kfree(nfit_res);
 438 }
 439
 440 static void *__test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma,
 441                 void *buf)
 442 {
 443         struct device *dev = &t->pdev.dev;
 444         struct resource *res = kzalloc(sizeof(*res) * 2, GFP_KERNEL);
 445         struct nfit_test_resource *nfit_res = kzalloc(sizeof(*nfit_res),
 446                         GFP_KERNEL);
 447         int rc;
 448
 449         if (!res || !buf || !nfit_res)
 450                 goto err;
 451         rc = devm_add_action(dev, release_nfit_res, nfit_res);
 452         if (rc)
 453                 goto err;
 454         INIT_LIST_HEAD(&nfit_res->list);
 455         memset(buf, 0, size);
 456         nfit_res->dev = dev;
 457         nfit_res->buf = buf;
 458         nfit_res->res = res;
 459         res->start = *dma;
 460         res->end = *dma + size - 1;
 461         res->name = "NFIT";
 462         spin_lock(&nfit_test_lock);
 463         list_add(&nfit_res->list, &t->resources);
 464         spin_unlock(&nfit_test_lock);
 465
 466         return nfit_res->buf;
 467  err:
 468         if (buf && !is_vmalloc_addr(buf))
 469                 dma_free_coherent(dev, size, buf, *dma);
 470         else if (buf)
 471                 vfree(buf);
 472         kfree(res);
 473         kfree(nfit_res);
 474         return NULL;
 475 }
 476
 477 static void *test_alloc(struct nfit_test *t, size_t size, dma_addr_t *dma)
 478 {
 479         void *buf = vmalloc(size);
 480
 481         *dma = (unsigned long) buf;
 482         return __test_alloc(t, size, dma, buf);
 483 }
 484
 485 static void *test_alloc_coherent(struct nfit_test *t, size_t size,
 486                 dma_addr_t *dma)
 487 {
 488         struct device *dev = &t->pdev.dev;
 489         void *buf = dma_alloc_coherent(dev, size, dma, GFP_KERNEL);
 490
 491         return __test_alloc(t, size, dma, buf);
 492 }
 493
 494 static struct nfit_test_resource *nfit_test_lookup(resource_size_t addr)
 495 {
 496         int i;
 497
 498         for (i = 0; i < ARRAY_SIZE(instances); i++) {
 499                 struct nfit_test_resource *n, *nfit_res = NULL;
 500                 struct nfit_test *t = instances[i];
 501
 502                 if (!t)
 503                         continue;
 504                 spin_lock(&nfit_test_lock);
 505                 list_for_each_entry(n, &t->resources, list) {
 506                         if (addr >= n->res->start && (addr < n->res->start
 507                                                 + resource_size(n->res))) {
 508                                 nfit_res = n;
 509                                 break;
 510                         } else if (addr >= (unsigned long) n->buf
 511                                         && (addr < (unsigned long) n->buf
 512                                                 + resource_size(n->res))) {
 513                                 nfit_res = n;
 514                                 break;
 515                         }
 516                 }
 517                 spin_unlock(&nfit_test_lock);
 518                 if (nfit_res)
 519                         return nfit_res;
 520         }
 521
 522         return NULL;
 523 }
 524
 525 static int ars_state_init(struct device *dev, struct ars_state *ars_state)
 526 {
 527         ars_state->ars_status = devm_kzalloc(dev,
 528                         sizeof(struct nd_cmd_ars_status)
 529                         + sizeof(struct nd_ars_record) * NFIT_TEST_ARS_RECORDS,
 530                         GFP_KERNEL);
 531         if (!ars_state->ars_status)
 532                 return -ENOMEM;
 533         spin_lock_init(&ars_state->lock);
 534         return 0;
 535 }
 536
 537 static int nfit_test0_alloc(struct nfit_test *t)
 538 {
 539         size_t nfit_size = sizeof(struct acpi_nfit_system_address) * NUM_SPA
 540                         + sizeof(struct acpi_nfit_memory_map) * NUM_MEM
 541                         + sizeof(struct acpi_nfit_control_region) * NUM_DCR
 542                         + offsetof(struct acpi_nfit_control_region,
 543                                         window_size) * NUM_DCR
 544                         + sizeof(struct acpi_nfit_data_region) * NUM_BDW
 545                         + sizeof(struct acpi_nfit_flush_address) * NUM_DCR;
 546         int i;
 547
 548         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
 549         if (!t->nfit_buf)
 550                 return -ENOMEM;
 551         t->nfit_size = nfit_size;
 552
 553         t->spa_set[0] = test_alloc_coherent(t, SPA0_SIZE, &t->spa_set_dma[0]);
 554         if (!t->spa_set[0])
 555                 return -ENOMEM;
 556
 557         t->spa_set[1] = test_alloc_coherent(t, SPA1_SIZE, &t->spa_set_dma[1]);
 558         if (!t->spa_set[1])
 559                 return -ENOMEM;
 560
 561         t->spa_set[2] = test_alloc_coherent(t, SPA0_SIZE, &t->spa_set_dma[2]);
 562         if (!t->spa_set[2])
 563                 return -ENOMEM;
 564
 565         for (i = 0; i < NUM_DCR; i++) {
 566                 t->dimm[i] = test_alloc(t, DIMM_SIZE, &t->dimm_dma[i]);
 567                 if (!t->dimm[i])
 568                         return -ENOMEM;
 569
 570                 t->label[i] = test_alloc(t, LABEL_SIZE, &t->label_dma[i]);
 571                 if (!t->label[i])
 572                         return -ENOMEM;
 573                 sprintf(t->label[i], "label%d", i);
 574
 575                 t->flush[i] = test_alloc(t, 8, &t->flush_dma[i]);
 576                 if (!t->flush[i])
 577                         return -ENOMEM;
 578         }
 579
 580         for (i = 0; i < NUM_DCR; i++) {
 581                 t->dcr[i] = test_alloc(t, LABEL_SIZE, &t->dcr_dma[i]);
 582                 if (!t->dcr[i])
 583                         return -ENOMEM;
 584         }
 585
 586         return ars_state_init(&t->pdev.dev, &t->ars_state);
 587 }
 588
 589 static int nfit_test1_alloc(struct nfit_test *t)
 590 {
 591         size_t nfit_size = sizeof(struct acpi_nfit_system_address)
 592                 + sizeof(struct acpi_nfit_memory_map)
 593                 + offsetof(struct acpi_nfit_control_region, window_size);
 594
 595         t->nfit_buf = test_alloc(t, nfit_size, &t->nfit_dma);
 596         if (!t->nfit_buf)
 597                 return -ENOMEM;
 598         t->nfit_size = nfit_size;
 599
 600         t->spa_set[0] = test_alloc_coherent(t, SPA2_SIZE, &t->spa_set_dma[0]);
 601         if (!t->spa_set[0])
 602                 return -ENOMEM;
 603
 604         return ars_state_init(&t->pdev.dev, &t->ars_state);
 605 }
 606
 607 static void nfit_test0_setup(struct nfit_test *t)
 608 {
 609         struct acpi_nfit_desc *acpi_desc;
 610         struct acpi_nfit_memory_map *memdev;
 611         void *nfit_buf = t->nfit_buf;
 612         struct acpi_nfit_system_address *spa;
 613         struct acpi_nfit_control_region *dcr;
 614         struct acpi_nfit_data_region *bdw;
 615         struct acpi_nfit_flush_address *flush;
 616         unsigned int offset;
 617
 618         /*
 619          * spa0 (interleave first half of dimm0 and dimm1, note storage
 620          * does not actually alias the related block-data-window
 621          * regions)
 622          */
 623         spa = nfit_buf;
 624         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 625         spa->header.length = sizeof(*spa);
 626         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
 627         spa->range_index = 0+1;
 628         spa->address = t->spa_set_dma[0];
 629         spa->length = SPA0_SIZE;
 630
 631         /*
 632          * spa1 (interleave last half of the 4 DIMMS, note storage
 633          * does not actually alias the related block-data-window
 634          * regions)
 635          */
 636         spa = nfit_buf + sizeof(*spa);
 637         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 638         spa->header.length = sizeof(*spa);
 639         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
 640         spa->range_index = 1+1;
 641         spa->address = t->spa_set_dma[1];
 642         spa->length = SPA1_SIZE;
 643
 644         /* spa2 (dcr0) dimm0 */
 645         spa = nfit_buf + sizeof(*spa) * 2;
 646         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 647         spa->header.length = sizeof(*spa);
 648         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
 649         spa->range_index = 2+1;
 650         spa->address = t->dcr_dma[0];
 651         spa->length = DCR_SIZE;
 652
 653         /* spa3 (dcr1) dimm1 */
 654         spa = nfit_buf + sizeof(*spa) * 3;
 655         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 656         spa->header.length = sizeof(*spa);
 657         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
 658         spa->range_index = 3+1;
 659         spa->address = t->dcr_dma[1];
 660         spa->length = DCR_SIZE;
 661
 662         /* spa4 (dcr2) dimm2 */
 663         spa = nfit_buf + sizeof(*spa) * 4;
 664         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 665         spa->header.length = sizeof(*spa);
 666         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
 667         spa->range_index = 4+1;
 668         spa->address = t->dcr_dma[2];
 669         spa->length = DCR_SIZE;
 670
 671         /* spa5 (dcr3) dimm3 */
 672         spa = nfit_buf + sizeof(*spa) * 5;
 673         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 674         spa->header.length = sizeof(*spa);
 675         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
 676         spa->range_index = 5+1;
 677         spa->address = t->dcr_dma[3];
 678         spa->length = DCR_SIZE;
 679
 680         /* spa6 (bdw for dcr0) dimm0 */
 681         spa = nfit_buf + sizeof(*spa) * 6;
 682         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 683         spa->header.length = sizeof(*spa);
 684         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
 685         spa->range_index = 6+1;
 686         spa->address = t->dimm_dma[0];
 687         spa->length = DIMM_SIZE;
 688
 689         /* spa7 (bdw for dcr1) dimm1 */
 690         spa = nfit_buf + sizeof(*spa) * 7;
 691         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 692         spa->header.length = sizeof(*spa);
 693         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
 694         spa->range_index = 7+1;
 695         spa->address = t->dimm_dma[1];
 696         spa->length = DIMM_SIZE;
 697
 698         /* spa8 (bdw for dcr2) dimm2 */
 699         spa = nfit_buf + sizeof(*spa) * 8;
 700         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 701         spa->header.length = sizeof(*spa);
 702         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
 703         spa->range_index = 8+1;
 704         spa->address = t->dimm_dma[2];
 705         spa->length = DIMM_SIZE;
 706
 707         /* spa9 (bdw for dcr3) dimm3 */
 708         spa = nfit_buf + sizeof(*spa) * 9;
 709         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
 710         spa->header.length = sizeof(*spa);
 711         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
 712         spa->range_index = 9+1;
 713         spa->address = t->dimm_dma[3];
 714         spa->length = DIMM_SIZE;
 715
 716         offset = sizeof(*spa) * 10;
 717         /* mem-region0 (spa0, dimm0) */
 718         memdev = nfit_buf + offset;
 719         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 720         memdev->header.length = sizeof(*memdev);
 721         memdev->device_handle = handle[0];
 722         memdev->physical_id = 0;
 723         memdev->region_id = 0;
 724         memdev->range_index = 0+1;
 725         memdev->region_index = 4+1;
 726         memdev->region_size = SPA0_SIZE/2;
 727         memdev->region_offset = t->spa_set_dma[0];
 728         memdev->address = 0;
 729         memdev->interleave_index = 0;
 730         memdev->interleave_ways = 2;
 731
 732         /* mem-region1 (spa0, dimm1) */
 733         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map);
 734         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 735         memdev->header.length = sizeof(*memdev);
 736         memdev->device_handle = handle[1];
 737         memdev->physical_id = 1;
 738         memdev->region_id = 0;
 739         memdev->range_index = 0+1;
 740         memdev->region_index = 5+1;
 741         memdev->region_size = SPA0_SIZE/2;
 742         memdev->region_offset = t->spa_set_dma[0] + SPA0_SIZE/2;
 743         memdev->address = 0;
 744         memdev->interleave_index = 0;
 745         memdev->interleave_ways = 2;
 746
 747         /* mem-region2 (spa1, dimm0) */
 748         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 2;
 749         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 750         memdev->header.length = sizeof(*memdev);
 751         memdev->device_handle = handle[0];
 752         memdev->physical_id = 0;
 753         memdev->region_id = 1;
 754         memdev->range_index = 1+1;
 755         memdev->region_index = 4+1;
 756         memdev->region_size = SPA1_SIZE/4;
 757         memdev->region_offset = t->spa_set_dma[1];
 758         memdev->address = SPA0_SIZE/2;
 759         memdev->interleave_index = 0;
 760         memdev->interleave_ways = 4;
 761
 762         /* mem-region3 (spa1, dimm1) */
 763         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 3;
 764         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 765         memdev->header.length = sizeof(*memdev);
 766         memdev->device_handle = handle[1];
 767         memdev->physical_id = 1;
 768         memdev->region_id = 1;
 769         memdev->range_index = 1+1;
 770         memdev->region_index = 5+1;
 771         memdev->region_size = SPA1_SIZE/4;
 772         memdev->region_offset = t->spa_set_dma[1] + SPA1_SIZE/4;
 773         memdev->address = SPA0_SIZE/2;
 774         memdev->interleave_index = 0;
 775         memdev->interleave_ways = 4;
 776
 777         /* mem-region4 (spa1, dimm2) */
 778         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 4;
 779         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 780         memdev->header.length = sizeof(*memdev);
 781         memdev->device_handle = handle[2];
 782         memdev->physical_id = 2;
 783         memdev->region_id = 0;
 784         memdev->range_index = 1+1;
 785         memdev->region_index = 6+1;
 786         memdev->region_size = SPA1_SIZE/4;
 787         memdev->region_offset = t->spa_set_dma[1] + 2*SPA1_SIZE/4;
 788         memdev->address = SPA0_SIZE/2;
 789         memdev->interleave_index = 0;
 790         memdev->interleave_ways = 4;
 791
 792         /* mem-region5 (spa1, dimm3) */
 793         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 5;
 794         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 795         memdev->header.length = sizeof(*memdev);
 796         memdev->device_handle = handle[3];
 797         memdev->physical_id = 3;
 798         memdev->region_id = 0;
 799         memdev->range_index = 1+1;
 800         memdev->region_index = 7+1;
 801         memdev->region_size = SPA1_SIZE/4;
 802         memdev->region_offset = t->spa_set_dma[1] + 3*SPA1_SIZE/4;
 803         memdev->address = SPA0_SIZE/2;
 804         memdev->interleave_index = 0;
 805         memdev->interleave_ways = 4;
 806
 807         /* mem-region6 (spa/dcr0, dimm0) */
 808         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 6;
 809         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 810         memdev->header.length = sizeof(*memdev);
 811         memdev->device_handle = handle[0];
 812         memdev->physical_id = 0;
 813         memdev->region_id = 0;
 814         memdev->range_index = 2+1;
 815         memdev->region_index = 0+1;
 816         memdev->region_size = 0;
 817         memdev->region_offset = 0;
 818         memdev->address = 0;
 819         memdev->interleave_index = 0;
 820         memdev->interleave_ways = 1;
 821
 822         /* mem-region7 (spa/dcr1, dimm1) */
 823         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 7;
 824         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 825         memdev->header.length = sizeof(*memdev);
 826         memdev->device_handle = handle[1];
 827         memdev->physical_id = 1;
 828         memdev->region_id = 0;
 829         memdev->range_index = 3+1;
 830         memdev->region_index = 1+1;
 831         memdev->region_size = 0;
 832         memdev->region_offset = 0;
 833         memdev->address = 0;
 834         memdev->interleave_index = 0;
 835         memdev->interleave_ways = 1;
 836
 837         /* mem-region8 (spa/dcr2, dimm2) */
 838         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 8;
 839         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 840         memdev->header.length = sizeof(*memdev);
 841         memdev->device_handle = handle[2];
 842         memdev->physical_id = 2;
 843         memdev->region_id = 0;
 844         memdev->range_index = 4+1;
 845         memdev->region_index = 2+1;
 846         memdev->region_size = 0;
 847         memdev->region_offset = 0;
 848         memdev->address = 0;
 849         memdev->interleave_index = 0;
 850         memdev->interleave_ways = 1;
 851
 852         /* mem-region9 (spa/dcr3, dimm3) */
 853         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 9;
 854         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 855         memdev->header.length = sizeof(*memdev);
 856         memdev->device_handle = handle[3];
 857         memdev->physical_id = 3;
 858         memdev->region_id = 0;
 859         memdev->range_index = 5+1;
 860         memdev->region_index = 3+1;
 861         memdev->region_size = 0;
 862         memdev->region_offset = 0;
 863         memdev->address = 0;
 864         memdev->interleave_index = 0;
 865         memdev->interleave_ways = 1;
 866
 867         /* mem-region10 (spa/bdw0, dimm0) */
 868         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 10;
 869         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 870         memdev->header.length = sizeof(*memdev);
 871         memdev->device_handle = handle[0];
 872         memdev->physical_id = 0;
 873         memdev->region_id = 0;
 874         memdev->range_index = 6+1;
 875         memdev->region_index = 0+1;
 876         memdev->region_size = 0;
 877         memdev->region_offset = 0;
 878         memdev->address = 0;
 879         memdev->interleave_index = 0;
 880         memdev->interleave_ways = 1;
 881
 882         /* mem-region11 (spa/bdw1, dimm1) */
 883         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 11;
 884         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 885         memdev->header.length = sizeof(*memdev);
 886         memdev->device_handle = handle[1];
 887         memdev->physical_id = 1;
 888         memdev->region_id = 0;
 889         memdev->range_index = 7+1;
 890         memdev->region_index = 1+1;
 891         memdev->region_size = 0;
 892         memdev->region_offset = 0;
 893         memdev->address = 0;
 894         memdev->interleave_index = 0;
 895         memdev->interleave_ways = 1;
 896
 897         /* mem-region12 (spa/bdw2, dimm2) */
 898         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 12;
 899         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 900         memdev->header.length = sizeof(*memdev);
 901         memdev->device_handle = handle[2];
 902         memdev->physical_id = 2;
 903         memdev->region_id = 0;
 904         memdev->range_index = 8+1;
 905         memdev->region_index = 2+1;
 906         memdev->region_size = 0;
 907         memdev->region_offset = 0;
 908         memdev->address = 0;
 909         memdev->interleave_index = 0;
 910         memdev->interleave_ways = 1;
 911
 912         /* mem-region13 (spa/dcr3, dimm3) */
 913         memdev = nfit_buf + offset + sizeof(struct acpi_nfit_memory_map) * 13;
 914         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
 915         memdev->header.length = sizeof(*memdev);
 916         memdev->device_handle = handle[3];
 917         memdev->physical_id = 3;
 918         memdev->region_id = 0;
 919         memdev->range_index = 9+1;
 920         memdev->region_index = 3+1;
 921         memdev->region_size = 0;
 922         memdev->region_offset = 0;
 923         memdev->address = 0;
 924         memdev->interleave_index = 0;
 925         memdev->interleave_ways = 1;
 926
 927         offset = offset + sizeof(struct acpi_nfit_memory_map) * 14;
 928         /* dcr-descriptor0: blk */
 929         dcr = nfit_buf + offset;
 930         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
 931         dcr->header.length = sizeof(struct acpi_nfit_control_region);
 932         dcr->region_index = 0+1;
 933         dcr->vendor_id = 0xabcd;
 934         dcr->device_id = 0;
 935         dcr->revision_id = 1;
 936         dcr->serial_number = ~handle[0];
 937         dcr->code = NFIT_FIC_BLK;
 938         dcr->windows = 1;
 939         dcr->window_size = DCR_SIZE;
 940         dcr->command_offset = 0;
 941         dcr->command_size = 8;
 942         dcr->status_offset = 8;
 943         dcr->status_size = 4;
 944
 945         /* dcr-descriptor1: blk */
 946         dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region);
 947         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
 948         dcr->header.length = sizeof(struct acpi_nfit_control_region);
 949         dcr->region_index = 1+1;
 950         dcr->vendor_id = 0xabcd;
 951         dcr->device_id = 0;
 952         dcr->revision_id = 1;
 953         dcr->serial_number = ~handle[1];
 954         dcr->code = NFIT_FIC_BLK;
 955         dcr->windows = 1;
 956         dcr->window_size = DCR_SIZE;
 957         dcr->command_offset = 0;
 958         dcr->command_size = 8;
 959         dcr->status_offset = 8;
 960         dcr->status_size = 4;
 961
 962         /* dcr-descriptor2: blk */
 963         dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region) * 2;
 964         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
 965         dcr->header.length = sizeof(struct acpi_nfit_control_region);
 966         dcr->region_index = 2+1;
 967         dcr->vendor_id = 0xabcd;
 968         dcr->device_id = 0;
 969         dcr->revision_id = 1;
 970         dcr->serial_number = ~handle[2];
 971         dcr->code = NFIT_FIC_BLK;
 972         dcr->windows = 1;
 973         dcr->window_size = DCR_SIZE;
 974         dcr->command_offset = 0;
 975         dcr->command_size = 8;
 976         dcr->status_offset = 8;
 977         dcr->status_size = 4;
 978
 979         /* dcr-descriptor3: blk */
 980         dcr = nfit_buf + offset + sizeof(struct acpi_nfit_control_region) * 3;
 981         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
 982         dcr->header.length = sizeof(struct acpi_nfit_control_region);
 983         dcr->region_index = 3+1;
 984         dcr->vendor_id = 0xabcd;
 985         dcr->device_id = 0;
 986         dcr->revision_id = 1;
 987         dcr->serial_number = ~handle[3];
 988         dcr->code = NFIT_FIC_BLK;
 989         dcr->windows = 1;
 990         dcr->window_size = DCR_SIZE;
 991         dcr->command_offset = 0;
 992         dcr->command_size = 8;
 993         dcr->status_offset = 8;
 994         dcr->status_size = 4;
 995
 996         offset = offset + sizeof(struct acpi_nfit_control_region) * 4;
 997         /* dcr-descriptor0: pmem */
 998         dcr = nfit_buf + offset;
 999         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1000         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1001                         window_size);
1002         dcr->region_index = 4+1;
1003         dcr->vendor_id = 0xabcd;
1004         dcr->device_id = 0;
1005         dcr->revision_id = 1;
1006         dcr->serial_number = ~handle[0];
1007         dcr->code = NFIT_FIC_BYTEN;
1008         dcr->windows = 0;
1009
1010         /* dcr-descriptor1: pmem */
1011         dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1012                         window_size);
1013         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1014         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1015                         window_size);
1016         dcr->region_index = 5+1;
1017         dcr->vendor_id = 0xabcd;
1018         dcr->device_id = 0;
1019         dcr->revision_id = 1;
1020         dcr->serial_number = ~handle[1];
1021         dcr->code = NFIT_FIC_BYTEN;
1022         dcr->windows = 0;
1023
1024         /* dcr-descriptor2: pmem */
1025         dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1026                         window_size) * 2;
1027         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1028         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1029                         window_size);
1030         dcr->region_index = 6+1;
1031         dcr->vendor_id = 0xabcd;
1032         dcr->device_id = 0;
1033         dcr->revision_id = 1;
1034         dcr->serial_number = ~handle[2];
1035         dcr->code = NFIT_FIC_BYTEN;
1036         dcr->windows = 0;
1037
1038         /* dcr-descriptor3: pmem */
1039         dcr = nfit_buf + offset + offsetof(struct acpi_nfit_control_region,
1040                         window_size) * 3;
1041         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1042         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1043                         window_size);
1044         dcr->region_index = 7+1;
1045         dcr->vendor_id = 0xabcd;
1046         dcr->device_id = 0;
1047         dcr->revision_id = 1;
1048         dcr->serial_number = ~handle[3];
1049         dcr->code = NFIT_FIC_BYTEN;
1050         dcr->windows = 0;
1051
1052         offset = offset + offsetof(struct acpi_nfit_control_region,
1053                         window_size) * 4;
1054         /* bdw0 (spa/dcr0, dimm0) */
1055         bdw = nfit_buf + offset;
1056         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1057         bdw->header.length = sizeof(struct acpi_nfit_data_region);
1058         bdw->region_index = 0+1;
1059         bdw->windows = 1;
1060         bdw->offset = 0;
1061         bdw->size = BDW_SIZE;
1062         bdw->capacity = DIMM_SIZE;
1063         bdw->start_address = 0;
1064
1065         /* bdw1 (spa/dcr1, dimm1) */
1066         bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region);
1067         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1068         bdw->header.length = sizeof(struct acpi_nfit_data_region);
1069         bdw->region_index = 1+1;
1070         bdw->windows = 1;
1071         bdw->offset = 0;
1072         bdw->size = BDW_SIZE;
1073         bdw->capacity = DIMM_SIZE;
1074         bdw->start_address = 0;
1075
1076         /* bdw2 (spa/dcr2, dimm2) */
1077         bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region) * 2;
1078         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1079         bdw->header.length = sizeof(struct acpi_nfit_data_region);
1080         bdw->region_index = 2+1;
1081         bdw->windows = 1;
1082         bdw->offset = 0;
1083         bdw->size = BDW_SIZE;
1084         bdw->capacity = DIMM_SIZE;
1085         bdw->start_address = 0;
1086
1087         /* bdw3 (spa/dcr3, dimm3) */
1088         bdw = nfit_buf + offset + sizeof(struct acpi_nfit_data_region) * 3;
1089         bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1090         bdw->header.length = sizeof(struct acpi_nfit_data_region);
1091         bdw->region_index = 3+1;
1092         bdw->windows = 1;
1093         bdw->offset = 0;
1094         bdw->size = BDW_SIZE;
1095         bdw->capacity = DIMM_SIZE;
1096         bdw->start_address = 0;
1097
1098         offset = offset + sizeof(struct acpi_nfit_data_region) * 4;
1099         /* flush0 (dimm0) */
1100         flush = nfit_buf + offset;
1101         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1102         flush->header.length = sizeof(struct acpi_nfit_flush_address);
1103         flush->device_handle = handle[0];
1104         flush->hint_count = 1;
1105         flush->hint_address[0] = t->flush_dma[0];
1106
1107         /* flush1 (dimm1) */
1108         flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 1;
1109         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1110         flush->header.length = sizeof(struct acpi_nfit_flush_address);
1111         flush->device_handle = handle[1];
1112         flush->hint_count = 1;
1113         flush->hint_address[0] = t->flush_dma[1];
1114
1115         /* flush2 (dimm2) */
1116         flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 2;
1117         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1118         flush->header.length = sizeof(struct acpi_nfit_flush_address);
1119         flush->device_handle = handle[2];
1120         flush->hint_count = 1;
1121         flush->hint_address[0] = t->flush_dma[2];
1122
1123         /* flush3 (dimm3) */
1124         flush = nfit_buf + offset + sizeof(struct acpi_nfit_flush_address) * 3;
1125         flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1126         flush->header.length = sizeof(struct acpi_nfit_flush_address);
1127         flush->device_handle = handle[3];
1128         flush->hint_count = 1;
1129         flush->hint_address[0] = t->flush_dma[3];
1130
1131         if (t->setup_hotplug) {
1132                 offset = offset + sizeof(struct acpi_nfit_flush_address) * 4;
1133                 /* dcr-descriptor4: blk */
1134                 dcr = nfit_buf + offset;
1135                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1136                 dcr->header.length = sizeof(struct acpi_nfit_control_region);
1137                 dcr->region_index = 8+1;
1138                 dcr->vendor_id = 0xabcd;
1139                 dcr->device_id = 0;
1140                 dcr->revision_id = 1;
1141                 dcr->serial_number = ~handle[4];
1142                 dcr->code = NFIT_FIC_BLK;
1143                 dcr->windows = 1;
1144                 dcr->window_size = DCR_SIZE;
1145                 dcr->command_offset = 0;
1146                 dcr->command_size = 8;
1147                 dcr->status_offset = 8;
1148                 dcr->status_size = 4;
1149
1150                 offset = offset + sizeof(struct acpi_nfit_control_region);
1151                 /* dcr-descriptor4: pmem */
1152                 dcr = nfit_buf + offset;
1153                 dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1154                 dcr->header.length = offsetof(struct acpi_nfit_control_region,
1155                                 window_size);
1156                 dcr->region_index = 9+1;
1157                 dcr->vendor_id = 0xabcd;
1158                 dcr->device_id = 0;
1159                 dcr->revision_id = 1;
1160                 dcr->serial_number = ~handle[4];
1161                 dcr->code = NFIT_FIC_BYTEN;
1162                 dcr->windows = 0;
1163
1164                 offset = offset + offsetof(struct acpi_nfit_control_region,
1165                                 window_size);
1166                 /* bdw4 (spa/dcr4, dimm4) */
1167                 bdw = nfit_buf + offset;
1168                 bdw->header.type = ACPI_NFIT_TYPE_DATA_REGION;
1169                 bdw->header.length = sizeof(struct acpi_nfit_data_region);
1170                 bdw->region_index = 8+1;
1171                 bdw->windows = 1;
1172                 bdw->offset = 0;
1173                 bdw->size = BDW_SIZE;
1174                 bdw->capacity = DIMM_SIZE;
1175                 bdw->start_address = 0;
1176
1177                 offset = offset + sizeof(struct acpi_nfit_data_region);
1178                 /* spa10 (dcr4) dimm4 */
1179                 spa = nfit_buf + offset;
1180                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1181                 spa->header.length = sizeof(*spa);
1182                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_DCR), 16);
1183                 spa->range_index = 10+1;
1184                 spa->address = t->dcr_dma[4];
1185                 spa->length = DCR_SIZE;
1186
1187                 /*
1188                  * spa11 (single-dimm interleave for hotplug, note storage
1189                  * does not actually alias the related block-data-window
1190                  * regions)
1191                  */
1192                 spa = nfit_buf + offset + sizeof(*spa);
1193                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1194                 spa->header.length = sizeof(*spa);
1195                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1196                 spa->range_index = 11+1;
1197                 spa->address = t->spa_set_dma[2];
1198                 spa->length = SPA0_SIZE;
1199
1200                 /* spa12 (bdw for dcr4) dimm4 */
1201                 spa = nfit_buf + offset + sizeof(*spa) * 2;
1202                 spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1203                 spa->header.length = sizeof(*spa);
1204                 memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_BDW), 16);
1205                 spa->range_index = 12+1;
1206                 spa->address = t->dimm_dma[4];
1207                 spa->length = DIMM_SIZE;
1208
1209                 offset = offset + sizeof(*spa) * 3;
1210                 /* mem-region14 (spa/dcr4, dimm4) */
1211                 memdev = nfit_buf + offset;
1212                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1213                 memdev->header.length = sizeof(*memdev);
1214                 memdev->device_handle = handle[4];
1215                 memdev->physical_id = 4;
1216                 memdev->region_id = 0;
1217                 memdev->range_index = 10+1;
1218                 memdev->region_index = 8+1;
1219                 memdev->region_size = 0;
1220                 memdev->region_offset = 0;
1221                 memdev->address = 0;
1222                 memdev->interleave_index = 0;
1223                 memdev->interleave_ways = 1;
1224
1225                 /* mem-region15 (spa0, dimm4) */
1226                 memdev = nfit_buf + offset +
1227                                 sizeof(struct acpi_nfit_memory_map);
1228                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1229                 memdev->header.length = sizeof(*memdev);
1230                 memdev->device_handle = handle[4];
1231                 memdev->physical_id = 4;
1232                 memdev->region_id = 0;
1233                 memdev->range_index = 11+1;
1234                 memdev->region_index = 9+1;
1235                 memdev->region_size = SPA0_SIZE;
1236                 memdev->region_offset = t->spa_set_dma[2];
1237                 memdev->address = 0;
1238                 memdev->interleave_index = 0;
1239                 memdev->interleave_ways = 1;
1240
1241                 /* mem-region16 (spa/bdw4, dimm4) */
1242                 memdev = nfit_buf + offset +
1243                                 sizeof(struct acpi_nfit_memory_map) * 2;
1244                 memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1245                 memdev->header.length = sizeof(*memdev);
1246                 memdev->device_handle = handle[4];
1247                 memdev->physical_id = 4;
1248                 memdev->region_id = 0;
1249                 memdev->range_index = 12+1;
1250                 memdev->region_index = 8+1;
1251                 memdev->region_size = 0;
1252                 memdev->region_offset = 0;
1253                 memdev->address = 0;
1254                 memdev->interleave_index = 0;
1255                 memdev->interleave_ways = 1;
1256
1257                 offset = offset + sizeof(struct acpi_nfit_memory_map) * 3;
1258                 /* flush3 (dimm4) */
1259                 flush = nfit_buf + offset;
1260                 flush->header.type = ACPI_NFIT_TYPE_FLUSH_ADDRESS;
1261                 flush->header.length = sizeof(struct acpi_nfit_flush_address);
1262                 flush->device_handle = handle[4];
1263                 flush->hint_count = 1;
1264                 flush->hint_address[0] = t->flush_dma[4];
1265         }
1266
1267         post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA0_SIZE);
1268
1269         acpi_desc = &t->acpi_desc;
1270         set_bit(ND_CMD_GET_CONFIG_SIZE, &acpi_desc->dimm_cmd_force_en);
1271         set_bit(ND_CMD_GET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
1272         set_bit(ND_CMD_SET_CONFIG_DATA, &acpi_desc->dimm_cmd_force_en);
1273         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
1274         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
1275         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
1276         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
1277 }
1278
1279 static void nfit_test1_setup(struct nfit_test *t)
1280 {
1281         size_t offset;
1282         void *nfit_buf = t->nfit_buf;
1283         struct acpi_nfit_memory_map *memdev;
1284         struct acpi_nfit_control_region *dcr;
1285         struct acpi_nfit_system_address *spa;
1286         struct acpi_nfit_desc *acpi_desc;
1287
1288         offset = 0;
1289         /* spa0 (flat range with no bdw aliasing) */
1290         spa = nfit_buf + offset;
1291         spa->header.type = ACPI_NFIT_TYPE_SYSTEM_ADDRESS;
1292         spa->header.length = sizeof(*spa);
1293         memcpy(spa->range_guid, to_nfit_uuid(NFIT_SPA_PM), 16);
1294         spa->range_index = 0+1;
1295         spa->address = t->spa_set_dma[0];
1296         spa->length = SPA2_SIZE;
1297
1298         offset += sizeof(*spa);
1299         /* mem-region0 (spa0, dimm0) */
1300         memdev = nfit_buf + offset;
1301         memdev->header.type = ACPI_NFIT_TYPE_MEMORY_MAP;
1302         memdev->header.length = sizeof(*memdev);
1303         memdev->device_handle = 0;
1304         memdev->physical_id = 0;
1305         memdev->region_id = 0;
1306         memdev->range_index = 0+1;
1307         memdev->region_index = 0+1;
1308         memdev->region_size = SPA2_SIZE;
1309         memdev->region_offset = 0;
1310         memdev->address = 0;
1311         memdev->interleave_index = 0;
1312         memdev->interleave_ways = 1;
1313         memdev->flags = ACPI_NFIT_MEM_SAVE_FAILED | ACPI_NFIT_MEM_RESTORE_FAILED
1314                 | ACPI_NFIT_MEM_FLUSH_FAILED | ACPI_NFIT_MEM_HEALTH_OBSERVED
1315                 | ACPI_NFIT_MEM_NOT_ARMED;
1316
1317         offset += sizeof(*memdev);
1318         /* dcr-descriptor0 */
1319         dcr = nfit_buf + offset;
1320         dcr->header.type = ACPI_NFIT_TYPE_CONTROL_REGION;
1321         dcr->header.length = offsetof(struct acpi_nfit_control_region,
1322                         window_size);
1323         dcr->region_index = 0+1;
1324         dcr->vendor_id = 0xabcd;
1325         dcr->device_id = 0;
1326         dcr->revision_id = 1;
1327         dcr->serial_number = ~0;
1328         dcr->code = NFIT_FIC_BYTE;
1329         dcr->windows = 0;
1330
1331         post_ars_status(&t->ars_state, t->spa_set_dma[0], SPA2_SIZE);
1332
1333         acpi_desc = &t->acpi_desc;
1334         set_bit(ND_CMD_ARS_CAP, &acpi_desc->bus_cmd_force_en);
1335         set_bit(ND_CMD_ARS_START, &acpi_desc->bus_cmd_force_en);
1336         set_bit(ND_CMD_ARS_STATUS, &acpi_desc->bus_cmd_force_en);
1337         set_bit(ND_CMD_CLEAR_ERROR, &acpi_desc->bus_cmd_force_en);
1338 }
1339
1340 static int nfit_test_blk_do_io(struct nd_blk_region *ndbr, resource_size_t dpa,
1341                 void *iobuf, u64 len, int rw)
1342 {
1343         struct nfit_blk *nfit_blk = ndbr->blk_provider_data;
1344         struct nfit_blk_mmio *mmio = &nfit_blk->mmio[BDW];
1345         struct nd_region *nd_region = &ndbr->nd_region;
1346         unsigned int lane;
1347
1348         lane = nd_region_acquire_lane(nd_region);
1349         if (rw)
1350                 memcpy(mmio->addr.base + dpa, iobuf, len);
1351         else {
1352                 memcpy(iobuf, mmio->addr.base + dpa, len);
1353
1354                 /* give us some some coverage of the mmio_flush_range() API */
1355                 mmio_flush_range(mmio->addr.base + dpa, len);
1356         }
1357         nd_region_release_lane(nd_region, lane);
1358
1359         return 0;
1360 }
1361
1362 static int nfit_test_probe(struct platform_device *pdev)
1363 {
1364         struct nvdimm_bus_descriptor *nd_desc;
1365         struct acpi_nfit_desc *acpi_desc;
1366         struct device *dev = &pdev->dev;
1367         struct nfit_test *nfit_test;
1368         int rc;
1369
1370         nfit_test = to_nfit_test(&pdev->dev);
1371
1372         /* common alloc */
1373         if (nfit_test->num_dcr) {
1374                 int num = nfit_test->num_dcr;
1375
1376                 nfit_test->dimm = devm_kcalloc(dev, num, sizeof(void *),
1377                                 GFP_KERNEL);
1378                 nfit_test->dimm_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
1379                                 GFP_KERNEL);
1380                 nfit_test->flush = devm_kcalloc(dev, num, sizeof(void *),
1381                                 GFP_KERNEL);
1382                 nfit_test->flush_dma = devm_kcalloc(dev, num, sizeof(dma_addr_t),
1383                                 GFP_KERNEL);
1384                 nfit_test->label = devm_kcalloc(dev, num, sizeof(void *),
1385                                 GFP_KERNEL);
1386                 nfit_test->label_dma = devm_kcalloc(dev, num,
1387                                 sizeof(dma_addr_t), GFP_KERNEL);
1388                 nfit_test->dcr = devm_kcalloc(dev, num,
1389                                 sizeof(struct nfit_test_dcr *), GFP_KERNEL);
1390                 nfit_test->dcr_dma = devm_kcalloc(dev, num,
1391                                 sizeof(dma_addr_t), GFP_KERNEL);
1392                 if (nfit_test->dimm && nfit_test->dimm_dma && nfit_test->label
1393                                 && nfit_test->label_dma && nfit_test->dcr
1394                                 && nfit_test->dcr_dma && nfit_test->flush
1395                                 && nfit_test->flush_dma)
1396                         /* pass */;
1397                 else
1398                         return -ENOMEM;
1399         }
1400
1401         if (nfit_test->num_pm) {
1402                 int num = nfit_test->num_pm;
1403
1404                 nfit_test->spa_set = devm_kcalloc(dev, num, sizeof(void *),
1405                                 GFP_KERNEL);
1406                 nfit_test->spa_set_dma = devm_kcalloc(dev, num,
1407                                 sizeof(dma_addr_t), GFP_KERNEL);
1408                 if (nfit_test->spa_set && nfit_test->spa_set_dma)
1409                         /* pass */;
1410                 else
1411                         return -ENOMEM;
1412         }
1413
1414         /* per-nfit specific alloc */
1415         if (nfit_test->alloc(nfit_test))
1416                 return -ENOMEM;
1417
1418         nfit_test->setup(nfit_test);
1419         acpi_desc = &nfit_test->acpi_desc;
1420         acpi_nfit_desc_init(acpi_desc, &pdev->dev);
1421         acpi_desc->nfit = nfit_test->nfit_buf;
1422         acpi_desc->blk_do_io = nfit_test_blk_do_io;
1423         nd_desc = &acpi_desc->nd_desc;
1424         nd_desc->provider_name = NULL;
1425         nd_desc->ndctl = nfit_test_ctl;
1426         acpi_desc->nvdimm_bus = nvdimm_bus_register(&pdev->dev, nd_desc);
1427         if (!acpi_desc->nvdimm_bus)
1428                 return -ENXIO;
1429
1430         rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_size);
1431         if (rc) {
1432                 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1433                 return rc;
1434         }
1435
1436         if (nfit_test->setup != nfit_test0_setup)
1437                 return 0;
1438
1439         nfit_test->setup_hotplug = 1;
1440         nfit_test->setup(nfit_test);
1441
1442         rc = acpi_nfit_init(acpi_desc, nfit_test->nfit_size);
1443         if (rc) {
1444                 nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1445                 return rc;
1446         }
1447
1448         return 0;
1449 }
1450
1451 static int nfit_test_remove(struct platform_device *pdev)
1452 {
1453         struct nfit_test *nfit_test = to_nfit_test(&pdev->dev);
1454         struct acpi_nfit_desc *acpi_desc = &nfit_test->acpi_desc;
1455
1456         nvdimm_bus_unregister(acpi_desc->nvdimm_bus);
1457
1458         return 0;
1459 }
1460
1461 static void nfit_test_release(struct device *dev)
1462 {
1463         struct nfit_test *nfit_test = to_nfit_test(dev);
1464
1465         kfree(nfit_test);
1466 }
1467
1468 static const struct platform_device_id nfit_test_id[] = {
1469         { KBUILD_MODNAME },
1470         { },
1471 };
1472
1473 static struct platform_driver nfit_test_driver = {
1474         .probe = nfit_test_probe,
1475         .remove = nfit_test_remove,
1476         .driver = {
1477                 .name = KBUILD_MODNAME,
1478         },
1479         .id_table = nfit_test_id,
1480 };
1481
1482 #ifdef CONFIG_CMA_SIZE_MBYTES
1483 #define CMA_SIZE_MBYTES CONFIG_CMA_SIZE_MBYTES
1484 #else
1485 #define CMA_SIZE_MBYTES 0
1486 #endif
1487
1488 static __init int nfit_test_init(void)
1489 {
1490         int rc, i;
1491
1492         nfit_test_setup(nfit_test_lookup);
1493
1494         for (i = 0; i < NUM_NFITS; i++) {
1495                 struct nfit_test *nfit_test;
1496                 struct platform_device *pdev;
1497                 static int once;
1498
1499                 nfit_test = kzalloc(sizeof(*nfit_test), GFP_KERNEL);
1500                 if (!nfit_test) {
1501                         rc = -ENOMEM;
1502                         goto err_register;
1503                 }
1504                 INIT_LIST_HEAD(&nfit_test->resources);
1505                 switch (i) {
1506                 case 0:
1507                         nfit_test->num_pm = NUM_PM;
1508                         nfit_test->num_dcr = NUM_DCR;
1509                         nfit_test->alloc = nfit_test0_alloc;
1510                         nfit_test->setup = nfit_test0_setup;
1511                         break;
1512                 case 1:
1513                         nfit_test->num_pm = 1;
1514                         nfit_test->alloc = nfit_test1_alloc;
1515                         nfit_test->setup = nfit_test1_setup;
1516                         break;
1517                 default:
1518                         rc = -EINVAL;
1519                         goto err_register;
1520                 }
1521                 pdev = &nfit_test->pdev;
1522                 pdev->name = KBUILD_MODNAME;
1523                 pdev->id = i;
1524                 pdev->dev.release = nfit_test_release;
1525                 rc = platform_device_register(pdev);
1526                 if (rc) {
1527                         put_device(&pdev->dev);
1528                         goto err_register;
1529                 }
1530
1531                 rc = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1532                 if (rc)
1533                         goto err_register;
1534
1535                 instances[i] = nfit_test;
1536
1537                 if (!once++) {
1538                         dma_addr_t dma;
1539                         void *buf;
1540
1541                         buf = dma_alloc_coherent(&pdev->dev, SZ_128M, &dma,
1542                                         GFP_KERNEL);
1543                         if (!buf) {
1544                                 rc = -ENOMEM;
1545                                 dev_warn(&pdev->dev, "need 128M of free cma\n");
1546                                 goto err_register;
1547                         }
1548                         dma_free_coherent(&pdev->dev, SZ_128M, buf, dma);
1549                 }
1550         }
1551
1552         rc = platform_driver_register(&nfit_test_driver);
1553         if (rc)
1554                 goto err_register;
1555         return 0;
1556
1557  err_register:
1558         for (i = 0; i < NUM_NFITS; i++)
1559                 if (instances[i])
1560                         platform_device_unregister(&instances[i]->pdev);
1561         nfit_test_teardown();
1562         return rc;
1563 }
1564
1565 static __exit void nfit_test_exit(void)
1566 {
1567         int i;
1568
1569         platform_driver_unregister(&nfit_test_driver);
1570         for (i = 0; i < NUM_NFITS; i++)
1571                 platform_device_unregister(&instances[i]->pdev);
1572         nfit_test_teardown();
1573 }
1574
1575 module_init(nfit_test_init);
1576 module_exit(nfit_test_exit);
1577 MODULE_LICENSE("GPL v2");
1578 MODULE_AUTHOR("Intel Corporation");