2 * VGICv2 MMIO handling functions
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/irqchip/arm-gic.h>
15 #include <linux/kvm.h>
16 #include <linux/kvm_host.h>
17 #include <kvm/iodev.h>
18 #include <kvm/arm_vgic.h>
21 #include "vgic-mmio.h"
23 static unsigned long vgic_mmio_read_v2_misc(struct kvm_vcpu *vcpu,
24 gpa_t addr, unsigned int len)
28 switch (addr & 0x0c) {
30 value = vcpu->kvm->arch.vgic.enabled ? GICD_ENABLE : 0;
33 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
34 value = (value >> 5) - 1;
35 value |= (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
38 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
47 static void vgic_mmio_write_v2_misc(struct kvm_vcpu *vcpu,
48 gpa_t addr, unsigned int len,
51 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
52 bool was_enabled = dist->enabled;
54 switch (addr & 0x0c) {
56 dist->enabled = val & GICD_ENABLE;
57 if (!was_enabled && dist->enabled)
58 vgic_kick_vcpus(vcpu->kvm);
67 static void vgic_mmio_write_sgir(struct kvm_vcpu *source_vcpu,
68 gpa_t addr, unsigned int len,
71 int nr_vcpus = atomic_read(&source_vcpu->kvm->online_vcpus);
72 int intid = val & 0xf;
73 int targets = (val >> 16) & 0xff;
74 int mode = (val >> 24) & 0x03;
76 struct kvm_vcpu *vcpu;
79 case 0x0: /* as specified by targets */
82 targets = (1U << nr_vcpus) - 1; /* all, ... */
83 targets &= ~(1U << source_vcpu->vcpu_id); /* but self */
85 case 0x2: /* this very vCPU only */
86 targets = (1U << source_vcpu->vcpu_id);
88 case 0x3: /* reserved */
92 kvm_for_each_vcpu(c, vcpu, source_vcpu->kvm) {
95 if (!(targets & (1U << c)))
98 irq = vgic_get_irq(source_vcpu->kvm, vcpu, intid);
100 spin_lock(&irq->irq_lock);
102 irq->source |= 1U << source_vcpu->vcpu_id;
104 vgic_queue_irq_unlock(source_vcpu->kvm, irq);
105 vgic_put_irq(source_vcpu->kvm, irq);
109 static unsigned long vgic_mmio_read_target(struct kvm_vcpu *vcpu,
110 gpa_t addr, unsigned int len)
112 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
116 for (i = 0; i < len; i++) {
117 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
119 val |= (u64)irq->targets << (i * 8);
121 vgic_put_irq(vcpu->kvm, irq);
127 static void vgic_mmio_write_target(struct kvm_vcpu *vcpu,
128 gpa_t addr, unsigned int len,
131 u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
134 /* GICD_ITARGETSR[0-7] are read-only */
135 if (intid < VGIC_NR_PRIVATE_IRQS)
138 for (i = 0; i < len; i++) {
139 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid + i);
142 spin_lock(&irq->irq_lock);
144 irq->targets = (val >> (i * 8)) & 0xff;
145 target = irq->targets ? __ffs(irq->targets) : 0;
146 irq->target_vcpu = kvm_get_vcpu(vcpu->kvm, target);
148 spin_unlock(&irq->irq_lock);
149 vgic_put_irq(vcpu->kvm, irq);
153 static unsigned long vgic_mmio_read_sgipend(struct kvm_vcpu *vcpu,
154 gpa_t addr, unsigned int len)
156 u32 intid = addr & 0x0f;
160 for (i = 0; i < len; i++) {
161 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
163 val |= (u64)irq->source << (i * 8);
165 vgic_put_irq(vcpu->kvm, irq);
170 static void vgic_mmio_write_sgipendc(struct kvm_vcpu *vcpu,
171 gpa_t addr, unsigned int len,
174 u32 intid = addr & 0x0f;
177 for (i = 0; i < len; i++) {
178 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
180 spin_lock(&irq->irq_lock);
182 irq->source &= ~((val >> (i * 8)) & 0xff);
184 irq->pending = false;
186 spin_unlock(&irq->irq_lock);
187 vgic_put_irq(vcpu->kvm, irq);
191 static void vgic_mmio_write_sgipends(struct kvm_vcpu *vcpu,
192 gpa_t addr, unsigned int len,
195 u32 intid = addr & 0x0f;
198 for (i = 0; i < len; i++) {
199 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
201 spin_lock(&irq->irq_lock);
203 irq->source |= (val >> (i * 8)) & 0xff;
207 vgic_queue_irq_unlock(vcpu->kvm, irq);
209 spin_unlock(&irq->irq_lock);
211 vgic_put_irq(vcpu->kvm, irq);
215 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
217 if (kvm_vgic_global_state.type == VGIC_V2)
218 vgic_v2_set_vmcr(vcpu, vmcr);
220 vgic_v3_set_vmcr(vcpu, vmcr);
223 static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
225 if (kvm_vgic_global_state.type == VGIC_V2)
226 vgic_v2_get_vmcr(vcpu, vmcr);
228 vgic_v3_get_vmcr(vcpu, vmcr);
231 #define GICC_ARCH_VERSION_V2 0x2
233 /* These are for userland accesses only, there is no guest-facing emulation. */
234 static unsigned long vgic_mmio_read_vcpuif(struct kvm_vcpu *vcpu,
235 gpa_t addr, unsigned int len)
237 struct vgic_vmcr vmcr;
240 vgic_get_vmcr(vcpu, &vmcr);
242 switch (addr & 0xff) {
246 case GIC_CPU_PRIMASK:
249 case GIC_CPU_BINPOINT:
252 case GIC_CPU_ALIAS_BINPOINT:
256 val = ((PRODUCT_ID_KVM << 20) |
257 (GICC_ARCH_VERSION_V2 << 16) |
267 static void vgic_mmio_write_vcpuif(struct kvm_vcpu *vcpu,
268 gpa_t addr, unsigned int len,
271 struct vgic_vmcr vmcr;
273 vgic_get_vmcr(vcpu, &vmcr);
275 switch (addr & 0xff) {
279 case GIC_CPU_PRIMASK:
282 case GIC_CPU_BINPOINT:
285 case GIC_CPU_ALIAS_BINPOINT:
290 vgic_set_vmcr(vcpu, &vmcr);
293 static const struct vgic_register_region vgic_v2_dist_registers[] = {
294 REGISTER_DESC_WITH_LENGTH(GIC_DIST_CTRL,
295 vgic_mmio_read_v2_misc, vgic_mmio_write_v2_misc, 12,
297 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_IGROUP,
298 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
300 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_SET,
301 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
303 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ENABLE_CLEAR,
304 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
306 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_SET,
307 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
309 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PENDING_CLEAR,
310 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
312 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_SET,
313 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
315 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_ACTIVE_CLEAR,
316 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
318 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_PRI,
319 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
320 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
321 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_TARGET,
322 vgic_mmio_read_target, vgic_mmio_write_target, 8,
323 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
324 REGISTER_DESC_WITH_BITS_PER_IRQ(GIC_DIST_CONFIG,
325 vgic_mmio_read_config, vgic_mmio_write_config, 2,
327 REGISTER_DESC_WITH_LENGTH(GIC_DIST_SOFTINT,
328 vgic_mmio_read_raz, vgic_mmio_write_sgir, 4,
330 REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_CLEAR,
331 vgic_mmio_read_sgipend, vgic_mmio_write_sgipendc, 16,
332 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
333 REGISTER_DESC_WITH_LENGTH(GIC_DIST_SGI_PENDING_SET,
334 vgic_mmio_read_sgipend, vgic_mmio_write_sgipends, 16,
335 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
338 static const struct vgic_register_region vgic_v2_cpu_registers[] = {
339 REGISTER_DESC_WITH_LENGTH(GIC_CPU_CTRL,
340 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
342 REGISTER_DESC_WITH_LENGTH(GIC_CPU_PRIMASK,
343 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
345 REGISTER_DESC_WITH_LENGTH(GIC_CPU_BINPOINT,
346 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
348 REGISTER_DESC_WITH_LENGTH(GIC_CPU_ALIAS_BINPOINT,
349 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
351 REGISTER_DESC_WITH_LENGTH(GIC_CPU_ACTIVEPRIO,
352 vgic_mmio_read_raz, vgic_mmio_write_wi, 16,
354 REGISTER_DESC_WITH_LENGTH(GIC_CPU_IDENT,
355 vgic_mmio_read_vcpuif, vgic_mmio_write_vcpuif, 4,
359 unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev)
361 dev->regions = vgic_v2_dist_registers;
362 dev->nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
364 kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
369 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr)
371 int nr_irqs = dev->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
372 const struct vgic_register_region *regions;
374 int nr_regions, i, len;
376 addr = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
378 switch (attr->group) {
379 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
380 regions = vgic_v2_dist_registers;
381 nr_regions = ARRAY_SIZE(vgic_v2_dist_registers);
383 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
384 regions = vgic_v2_cpu_registers;
385 nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers);
391 /* We only support aligned 32-bit accesses. */
395 for (i = 0; i < nr_regions; i++) {
396 if (regions[i].bits_per_irq)
397 len = (regions[i].bits_per_irq * nr_irqs) / 8;
399 len = regions[i].len;
401 if (regions[i].reg_offset <= addr &&
402 regions[i].reg_offset + len > addr)
410 * When userland tries to access the VGIC register handlers, we need to
411 * create a usable struct vgic_io_device to be passed to the handlers and we
412 * have to set up a buffer similar to what would have happened if a guest MMIO
413 * access occurred, including doing endian conversions on BE systems.
415 static int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
416 bool is_write, int offset, u32 *val)
418 unsigned int len = 4;
423 vgic_data_host_to_mmio_bus(buf, len, *val);
424 ret = kvm_io_gic_ops.write(vcpu, &dev->dev, offset, len, buf);
426 ret = kvm_io_gic_ops.read(vcpu, &dev->dev, offset, len, buf);
428 *val = vgic_data_mmio_bus_to_host(buf, len);
434 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
435 int offset, u32 *val)
437 struct vgic_io_device dev = {
438 .regions = vgic_v2_cpu_registers,
439 .nr_regions = ARRAY_SIZE(vgic_v2_cpu_registers),
440 .iodev_type = IODEV_CPUIF,
443 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
446 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
447 int offset, u32 *val)
449 struct vgic_io_device dev = {
450 .regions = vgic_v2_dist_registers,
451 .nr_regions = ARRAY_SIZE(vgic_v2_dist_registers),
452 .iodev_type = IODEV_DIST,
455 return vgic_uaccess(vcpu, &dev, is_write, offset, val);