virt/kvm/arm/vgic/vgic-mmio-v3.c

   1 /*
   2  * VGICv3 MMIO handling functions
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/irqchip/arm-gic-v3.h>
  15 #include <linux/kvm.h>
  16 #include <linux/kvm_host.h>
  17 #include <kvm/iodev.h>
  18 #include <kvm/arm_vgic.h>
  19
  20 #include <asm/kvm_emulate.h>
  21
  22 #include "vgic.h"
  23 #include "vgic-mmio.h"
  24
  25 /* extract @num bytes at @offset bytes offset in data */
  26 static unsigned long extract_bytes(unsigned long data, unsigned int offset,
  27                                    unsigned int num)
  28 {
  29         return (data >> (offset * 8)) & GENMASK_ULL(num * 8 - 1, 0);
  30 }
  31
  32 static unsigned long vgic_mmio_read_v3_misc(struct kvm_vcpu *vcpu,
  33                                             gpa_t addr, unsigned int len)
  34 {
  35         u32 value = 0;
  36
  37         switch (addr & 0x0c) {
  38         case GICD_CTLR:
  39                 if (vcpu->kvm->arch.vgic.enabled)
  40                         value |= GICD_CTLR_ENABLE_SS_G1;
  41                 value |= GICD_CTLR_ARE_NS | GICD_CTLR_DS;
  42                 break;
  43         case GICD_TYPER:
  44                 value = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
  45                 value = (value >> 5) - 1;
  46                 value |= (INTERRUPT_ID_BITS_SPIS - 1) << 19;
  47                 break;
  48         case GICD_IIDR:
  49                 value = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
  50                 break;
  51         default:
  52                 return 0;
  53         }
  54
  55         return value;
  56 }
  57
  58 static void vgic_mmio_write_v3_misc(struct kvm_vcpu *vcpu,
  59                                     gpa_t addr, unsigned int len,
  60                                     unsigned long val)
  61 {
  62         struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
  63         bool was_enabled = dist->enabled;
  64
  65         switch (addr & 0x0c) {
  66         case GICD_CTLR:
  67                 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
  68
  69                 if (!was_enabled && dist->enabled)
  70                         vgic_kick_vcpus(vcpu->kvm);
  71                 break;
  72         case GICD_TYPER:
  73         case GICD_IIDR:
  74                 return;
  75         }
  76 }
  77
  78 static unsigned long vgic_mmio_read_irouter(struct kvm_vcpu *vcpu,
  79                                             gpa_t addr, unsigned int len)
  80 {
  81         int intid = VGIC_ADDR_TO_INTID(addr, 64);
  82         struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, NULL, intid);
  83         unsigned long ret = 0;
  84
  85         if (!irq)
  86                 return 0;
  87
  88         /* The upper word is RAZ for us. */
  89         if (!(addr & 4))
  90                 ret = extract_bytes(READ_ONCE(irq->mpidr), addr & 7, len);
  91
  92         vgic_put_irq(vcpu->kvm, irq);
  93         return ret;
  94 }
  95
  96 static void vgic_mmio_write_irouter(struct kvm_vcpu *vcpu,
  97                                     gpa_t addr, unsigned int len,
  98                                     unsigned long val)
  99 {
 100         int intid = VGIC_ADDR_TO_INTID(addr, 64);
 101         struct vgic_irq *irq;
 102
 103         /* The upper word is WI for us since we don't implement Aff3. */
 104         if (addr & 4)
 105                 return;
 106
 107         irq = vgic_get_irq(vcpu->kvm, NULL, intid);
 108
 109         if (!irq)
 110                 return;
 111
 112         spin_lock(&irq->irq_lock);
 113
 114         /* We only care about and preserve Aff0, Aff1 and Aff2. */
 115         irq->mpidr = val & GENMASK(23, 0);
 116         irq->target_vcpu = kvm_mpidr_to_vcpu(vcpu->kvm, irq->mpidr);
 117
 118         spin_unlock(&irq->irq_lock);
 119         vgic_put_irq(vcpu->kvm, irq);
 120 }
 121
 122 static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu,
 123                                               gpa_t addr, unsigned int len)
 124 {
 125         unsigned long mpidr = kvm_vcpu_get_mpidr_aff(vcpu);
 126         int target_vcpu_id = vcpu->vcpu_id;
 127         u64 value;
 128
 129         value = (mpidr & GENMASK(23, 0)) << 32;
 130         value |= ((target_vcpu_id & 0xffff) << 8);
 131         if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1)
 132                 value |= GICR_TYPER_LAST;
 133
 134         return extract_bytes(value, addr & 7, len);
 135 }
 136
 137 static unsigned long vgic_mmio_read_v3r_iidr(struct kvm_vcpu *vcpu,
 138                                              gpa_t addr, unsigned int len)
 139 {
 140         return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
 141 }
 142
 143 static unsigned long vgic_mmio_read_v3_idregs(struct kvm_vcpu *vcpu,
 144                                               gpa_t addr, unsigned int len)
 145 {
 146         switch (addr & 0xffff) {
 147         case GICD_PIDR2:
 148                 /* report a GICv3 compliant implementation */
 149                 return 0x3b;
 150         }
 151
 152         return 0;
 153 }
 154
 155 /*
 156  * The GICv3 per-IRQ registers are split to control PPIs and SGIs in the
 157  * redistributors, while SPIs are covered by registers in the distributor
 158  * block. Trying to set private IRQs in this block gets ignored.
 159  * We take some special care here to fix the calculation of the register
 160  * offset.
 161  */
 162 #define REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(off, rd, wr, bpi, acc)   \
 163         {                                                               \
 164                 .reg_offset = off,                                      \
 165                 .bits_per_irq = bpi,                                    \
 166                 .len = (bpi * VGIC_NR_PRIVATE_IRQS) / 8,                \
 167                 .access_flags = acc,                                    \
 168                 .read = vgic_mmio_read_raz,                             \
 169                 .write = vgic_mmio_write_wi,                            \
 170         }, {                                                            \
 171                 .reg_offset = off + (bpi * VGIC_NR_PRIVATE_IRQS) / 8,   \
 172                 .bits_per_irq = bpi,                                    \
 173                 .len = (bpi * (1024 - VGIC_NR_PRIVATE_IRQS)) / 8,       \
 174                 .access_flags = acc,                                    \
 175                 .read = rd,                                             \
 176                 .write = wr,                                            \
 177         }
 178
 179 static const struct vgic_register_region vgic_v3_dist_registers[] = {
 180         REGISTER_DESC_WITH_LENGTH(GICD_CTLR,
 181                 vgic_mmio_read_v3_misc, vgic_mmio_write_v3_misc, 16,
 182                 VGIC_ACCESS_32bit),
 183         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGROUPR,
 184                 vgic_mmio_read_rao, vgic_mmio_write_wi, 1,
 185                 VGIC_ACCESS_32bit),
 186         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISENABLER,
 187                 vgic_mmio_read_enable, vgic_mmio_write_senable, 1,
 188                 VGIC_ACCESS_32bit),
 189         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICENABLER,
 190                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 1,
 191                 VGIC_ACCESS_32bit),
 192         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISPENDR,
 193                 vgic_mmio_read_pending, vgic_mmio_write_spending, 1,
 194                 VGIC_ACCESS_32bit),
 195         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICPENDR,
 196                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 1,
 197                 VGIC_ACCESS_32bit),
 198         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ISACTIVER,
 199                 vgic_mmio_read_active, vgic_mmio_write_sactive, 1,
 200                 VGIC_ACCESS_32bit),
 201         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICACTIVER,
 202                 vgic_mmio_read_active, vgic_mmio_write_cactive, 1,
 203                 VGIC_ACCESS_32bit),
 204         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IPRIORITYR,
 205                 vgic_mmio_read_priority, vgic_mmio_write_priority, 8,
 206                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 207         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ITARGETSR,
 208                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 209                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 210         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
 211                 vgic_mmio_read_config, vgic_mmio_write_config, 2,
 212                 VGIC_ACCESS_32bit),
 213         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IGRPMODR,
 214                 vgic_mmio_read_raz, vgic_mmio_write_wi, 1,
 215                 VGIC_ACCESS_32bit),
 216         REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_IROUTER,
 217                 vgic_mmio_read_irouter, vgic_mmio_write_irouter, 64,
 218                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 219         REGISTER_DESC_WITH_LENGTH(GICD_IDREGS,
 220                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 221                 VGIC_ACCESS_32bit),
 222 };
 223
 224 static const struct vgic_register_region vgic_v3_rdbase_registers[] = {
 225         REGISTER_DESC_WITH_LENGTH(GICR_CTLR,
 226                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 227                 VGIC_ACCESS_32bit),
 228         REGISTER_DESC_WITH_LENGTH(GICR_IIDR,
 229                 vgic_mmio_read_v3r_iidr, vgic_mmio_write_wi, 4,
 230                 VGIC_ACCESS_32bit),
 231         REGISTER_DESC_WITH_LENGTH(GICR_TYPER,
 232                 vgic_mmio_read_v3r_typer, vgic_mmio_write_wi, 8,
 233                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 234         REGISTER_DESC_WITH_LENGTH(GICR_PROPBASER,
 235                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 236                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 237         REGISTER_DESC_WITH_LENGTH(GICR_PENDBASER,
 238                 vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
 239                 VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
 240         REGISTER_DESC_WITH_LENGTH(GICR_IDREGS,
 241                 vgic_mmio_read_v3_idregs, vgic_mmio_write_wi, 48,
 242                 VGIC_ACCESS_32bit),
 243 };
 244
 245 static const struct vgic_register_region vgic_v3_sgibase_registers[] = {
 246         REGISTER_DESC_WITH_LENGTH(GICR_IGROUPR0,
 247                 vgic_mmio_read_rao, vgic_mmio_write_wi, 4,
 248                 VGIC_ACCESS_32bit),
 249         REGISTER_DESC_WITH_LENGTH(GICR_ISENABLER0,
 250                 vgic_mmio_read_enable, vgic_mmio_write_senable, 4,
 251                 VGIC_ACCESS_32bit),
 252         REGISTER_DESC_WITH_LENGTH(GICR_ICENABLER0,
 253                 vgic_mmio_read_enable, vgic_mmio_write_cenable, 4,
 254                 VGIC_ACCESS_32bit),
 255         REGISTER_DESC_WITH_LENGTH(GICR_ISPENDR0,
 256                 vgic_mmio_read_pending, vgic_mmio_write_spending, 4,
 257                 VGIC_ACCESS_32bit),
 258         REGISTER_DESC_WITH_LENGTH(GICR_ICPENDR0,
 259                 vgic_mmio_read_pending, vgic_mmio_write_cpending, 4,
 260                 VGIC_ACCESS_32bit),
 261         REGISTER_DESC_WITH_LENGTH(GICR_ISACTIVER0,
 262                 vgic_mmio_read_active, vgic_mmio_write_sactive, 4,
 263                 VGIC_ACCESS_32bit),
 264         REGISTER_DESC_WITH_LENGTH(GICR_ICACTIVER0,
 265                 vgic_mmio_read_active, vgic_mmio_write_cactive, 4,
 266                 VGIC_ACCESS_32bit),
 267         REGISTER_DESC_WITH_LENGTH(GICR_IPRIORITYR0,
 268                 vgic_mmio_read_priority, vgic_mmio_write_priority, 32,
 269                 VGIC_ACCESS_32bit | VGIC_ACCESS_8bit),
 270         REGISTER_DESC_WITH_LENGTH(GICR_ICFGR0,
 271                 vgic_mmio_read_config, vgic_mmio_write_config, 8,
 272                 VGIC_ACCESS_32bit),
 273         REGISTER_DESC_WITH_LENGTH(GICR_IGRPMODR0,
 274                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 275                 VGIC_ACCESS_32bit),
 276         REGISTER_DESC_WITH_LENGTH(GICR_NSACR,
 277                 vgic_mmio_read_raz, vgic_mmio_write_wi, 4,
 278                 VGIC_ACCESS_32bit),
 279 };
 280
 281 unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev)
 282 {
 283         dev->regions = vgic_v3_dist_registers;
 284         dev->nr_regions = ARRAY_SIZE(vgic_v3_dist_registers);
 285
 286         kvm_iodevice_init(&dev->dev, &kvm_io_gic_ops);
 287
 288         return SZ_64K;
 289 }
 290
 291 int vgic_register_redist_iodevs(struct kvm *kvm, gpa_t redist_base_address)
 292 {
 293         struct kvm_vcpu *vcpu;
 294         int c, ret = 0;
 295
 296         kvm_for_each_vcpu(c, vcpu, kvm) {
 297                 gpa_t rd_base = redist_base_address + c * SZ_64K * 2;
 298                 gpa_t sgi_base = rd_base + SZ_64K;
 299                 struct vgic_io_device *rd_dev = &vcpu->arch.vgic_cpu.rd_iodev;
 300                 struct vgic_io_device *sgi_dev = &vcpu->arch.vgic_cpu.sgi_iodev;
 301
 302                 kvm_iodevice_init(&rd_dev->dev, &kvm_io_gic_ops);
 303                 rd_dev->base_addr = rd_base;
 304                 rd_dev->regions = vgic_v3_rdbase_registers;
 305                 rd_dev->nr_regions = ARRAY_SIZE(vgic_v3_rdbase_registers);
 306                 rd_dev->redist_vcpu = vcpu;
 307
 308                 mutex_lock(&kvm->slots_lock);
 309                 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, rd_base,
 310                                               SZ_64K, &rd_dev->dev);
 311                 mutex_unlock(&kvm->slots_lock);
 312
 313                 if (ret)
 314                         break;
 315
 316                 kvm_iodevice_init(&sgi_dev->dev, &kvm_io_gic_ops);
 317                 sgi_dev->base_addr = sgi_base;
 318                 sgi_dev->regions = vgic_v3_sgibase_registers;
 319                 sgi_dev->nr_regions = ARRAY_SIZE(vgic_v3_sgibase_registers);
 320                 sgi_dev->redist_vcpu = vcpu;
 321
 322                 mutex_lock(&kvm->slots_lock);
 323                 ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, sgi_base,
 324                                               SZ_64K, &sgi_dev->dev);
 325                 mutex_unlock(&kvm->slots_lock);
 326                 if (ret) {
 327                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 328                                                   &rd_dev->dev);
 329                         break;
 330                 }
 331         }
 332
 333         if (ret) {
 334                 /* The current c failed, so we start with the previous one. */
 335                 for (c--; c >= 0; c--) {
 336                         struct vgic_cpu *vgic_cpu;
 337
 338                         vcpu = kvm_get_vcpu(kvm, c);
 339                         vgic_cpu = &vcpu->arch.vgic_cpu;
 340                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 341                                                   &vgic_cpu->rd_iodev.dev);
 342                         kvm_io_bus_unregister_dev(kvm, KVM_MMIO_BUS,
 343                                                   &vgic_cpu->sgi_iodev.dev);
 344                 }
 345         }
 346
 347         return ret;
 348 }
 349
 350 /*
 351  * Compare a given affinity (level 1-3 and a level 0 mask, from the SGI
 352  * generation register ICC_SGI1R_EL1) with a given VCPU.
 353  * If the VCPU's MPIDR matches, return the level0 affinity, otherwise
 354  * return -1.
 355  */
 356 static int match_mpidr(u64 sgi_aff, u16 sgi_cpu_mask, struct kvm_vcpu *vcpu)
 357 {
 358         unsigned long affinity;
 359         int level0;
 360
 361         /*
 362          * Split the current VCPU's MPIDR into affinity level 0 and the
 363          * rest as this is what we have to compare against.
 364          */
 365         affinity = kvm_vcpu_get_mpidr_aff(vcpu);
 366         level0 = MPIDR_AFFINITY_LEVEL(affinity, 0);
 367         affinity &= ~MPIDR_LEVEL_MASK;
 368
 369         /* bail out if the upper three levels don't match */
 370         if (sgi_aff != affinity)
 371                 return -1;
 372
 373         /* Is this VCPU's bit set in the mask ? */
 374         if (!(sgi_cpu_mask & BIT(level0)))
 375                 return -1;
 376
 377         return level0;
 378 }
 379
 380 /*
 381  * The ICC_SGI* registers encode the affinity differently from the MPIDR,
 382  * so provide a wrapper to use the existing defines to isolate a certain
 383  * affinity level.
 384  */
 385 #define SGI_AFFINITY_LEVEL(reg, level) \
 386         ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
 387         >> ICC_SGI1R_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
 388
 389 /**
 390  * vgic_v3_dispatch_sgi - handle SGI requests from VCPUs
 391  * @vcpu: The VCPU requesting a SGI
 392  * @reg: The value written into the ICC_SGI1R_EL1 register by that VCPU
 393  *
 394  * With GICv3 (and ARE=1) CPUs trigger SGIs by writing to a system register.
 395  * This will trap in sys_regs.c and call this function.
 396  * This ICC_SGI1R_EL1 register contains the upper three affinity levels of the
 397  * target processors as well as a bitmask of 16 Aff0 CPUs.
 398  * If the interrupt routing mode bit is not set, we iterate over all VCPUs to
 399  * check for matching ones. If this bit is set, we signal all, but not the
 400  * calling VCPU.
 401  */
 402 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg)
 403 {
 404         struct kvm *kvm = vcpu->kvm;
 405         struct kvm_vcpu *c_vcpu;
 406         u16 target_cpus;
 407         u64 mpidr;
 408         int sgi, c;
 409         int vcpu_id = vcpu->vcpu_id;
 410         bool broadcast;
 411
 412         sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
 413         broadcast = reg & BIT(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
 414         target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
 415         mpidr = SGI_AFFINITY_LEVEL(reg, 3);
 416         mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
 417         mpidr |= SGI_AFFINITY_LEVEL(reg, 1);
 418
 419         /*
 420          * We iterate over all VCPUs to find the MPIDRs matching the request.
 421          * If we have handled one CPU, we clear its bit to detect early
 422          * if we are already finished. This avoids iterating through all
 423          * VCPUs when most of the times we just signal a single VCPU.
 424          */
 425         kvm_for_each_vcpu(c, c_vcpu, kvm) {
 426                 struct vgic_irq *irq;
 427
 428                 /* Exit early if we have dealt with all requested CPUs */
 429                 if (!broadcast && target_cpus == 0)
 430                         break;
 431
 432                 /* Don't signal the calling VCPU */
 433                 if (broadcast && c == vcpu_id)
 434                         continue;
 435
 436                 if (!broadcast) {
 437                         int level0;
 438
 439                         level0 = match_mpidr(mpidr, target_cpus, c_vcpu);
 440                         if (level0 == -1)
 441                                 continue;
 442
 443                         /* remove this matching VCPU from the mask */
 444                         target_cpus &= ~BIT(level0);
 445                 }
 446
 447                 irq = vgic_get_irq(vcpu->kvm, c_vcpu, sgi);
 448
 449                 spin_lock(&irq->irq_lock);
 450                 irq->pending = true;
 451
 452                 vgic_queue_irq_unlock(vcpu->kvm, irq);
 453                 vgic_put_irq(vcpu->kvm, irq);
 454         }
 455 }